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Test case to detect recursive unwinding in Python-based unwinders.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
ab548d2d
AK		 12016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
2
3 * arc-dis.h: Wrap around in extern "C".
4
344bde0a
RS		 52016-08-23 Richard Sandiford <richard.sandiford@arm.com>
6
7 * aarch64-tbl.h (V8_2_INSN): New macro.
8 (aarch64_opcode_table): Use it.
9
5ce912d8
RS		 102016-08-23 Richard Sandiford <richard.sandiford@arm.com>
11
12 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
13 CORE_INSN, __FP_INSN and SIMD_INSN.
14
9d30b0bd
RS		 152016-08-23 Richard Sandiford <richard.sandiford@arm.com>
16
17 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
18 (aarch64_opcode_table): Update uses accordingly.
19
dfdaec14
AJ		 202016-07-25 Andrew Jenner <andrew@codesourcery.com>
21 Kwok Cheung Yeung <kcy@codesourcery.com>
22
23 opcodes/
24 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
25 'e_cmplwi' to 'e_cmpli' instead.
26 (OPVUPRT, OPVUPRT_MASK): Define.
27 (powerpc_opcodes): Add E200Z4 insns.
28 (vle_opcodes): Add context save/restore insns.
29
7bd374a4
MR		 302016-07-27 Maciej W. Rozycki <macro@imgtec.com>
31
32 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
33 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
34 "j".
35
db18dbab
GM		 362016-07-27 Graham Markall <graham.markall@embecosm.com>
37
38 * arc-nps400-tbl.h: Change block comments to GNU format.
39 * arc-dis.c: Add new globals addrtypenames,
40 addrtypenames_max, and addtypeunknown.
41 (get_addrtype): New function.
42 (print_insn_arc): Print colons and address types when
43 required.
44 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
45 define insert and extract functions for all address types.
46 (arc_operands): Add operands for colon and all address
47 types.
48 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
49 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
50 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
51 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
52 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
53 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
54
fecd57f9
L		 552016-07-21 H.J. Lu <hongjiu.lu@intel.com>
56
57 * configure: Regenerated.
58
37fd5ef3
CZ		 592016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
60
61 * arc-dis.c (skipclass): New structure.
62 (decodelist): New variable.
63 (is_compatible_p): New function.
64 (new_element): Likewise.
65 (skip_class_p): Likewise.
66 (find_format_from_table): Use skip_class_p function.
67 (find_format): Decode first the extension instructions.
68 (print_insn_arc): Select either ARCEM or ARCHS based on elf
69 e_flags.
70 (parse_option): New function.
71 (parse_disassembler_options): Likewise.
72 (print_arc_disassembler_options): Likewise.
73 (print_insn_arc): Use parse_disassembler_options function. Proper
74 select ARCv2 cpu variant.
75 * disassemble.c (disassembler_usage): Add ARC disassembler
76 options.
77
92281a5b
MR		 782016-07-13 Maciej W. Rozycki <macro@imgtec.com>
79
80 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
81 annotation from the "nal" entry and reorder it beyond "bltzal".
82
6e7ced37
JM		 832016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
84
85 * sparc-opc.c (ldtxa): New macro.
86 (sparc_opcodes): Use the macro defined above to add entries for
87 the LDTXA instructions.
88 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
89 instruction.
90
2f831b9a 912016-07-07 James Bowman <james.bowman@ftdichip.com>
92
93 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
94 and "jmpc".
95
c07315e0
JB		 962016-07-01 Jan Beulich <jbeulich@suse.com>
97
98 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
99 (movzb): Adjust to cover all permitted suffixes.
100 (movzw): New.
101 * i386-tbl.h: Re-generate.
102
9243100a
JB		 1032016-07-01 Jan Beulich <jbeulich@suse.com>
104
105 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
106 (lgdt): Remove Tbyte from non-64-bit variant.
107 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
108 xsaves64, xsavec64): Remove Disp16.
109 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
110 Remove Disp32S from non-64-bit variants. Remove Disp16 from
111 64-bit variants.
112 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
113 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
114 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
115 64-bit variants.
116 * i386-tbl.h: Re-generate.
117
8325cc63
JB		 1182016-07-01 Jan Beulich <jbeulich@suse.com>
119
120 * i386-opc.tbl (xlat): Remove RepPrefixOk.
121 * i386-tbl.h: Re-generate.
122
838441e4
YQ		 1232016-06-30 Yao Qi <yao.qi@linaro.org>
124
125 * arm-dis.c (print_insn): Fix typo in comment.
126
dab26bf4
RS		 1272016-06-28 Richard Sandiford <richard.sandiford@arm.com>
128
129 * aarch64-opc.c (operand_general_constraint_met_p): Check the
130 range of ldst_elemlist operands.
131 (print_register_list): Use PRIi64 to print the index.
132 (aarch64_print_operand): Likewise.
133
5703197e
TS		 1342016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
135
136 * mcore-opc.h: Remove sentinal.
137 * mcore-dis.c (print_insn_mcore): Adjust.
138
ce440d63
GM		 1392016-06-23 Graham Markall <graham.markall@embecosm.com>
140
141 * arc-opc.c: Correct description of availability of NPS400
142 features.
143
6fd3a02d
PB		 1442016-06-22 Peter Bergner <bergner@vnet.ibm.com>
145
146 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
147 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
148 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
149 xor3>: New mnemonics.
150 <setb>: Change to a VX form instruction.
151 (insert_sh6): Add support for rldixor.
152 (extract_sh6): Likewise.
153
6b477896
TS		 1542016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
155
156 * arc-ext.h: Wrap in extern C.
157
bdd582db
GM		 1582016-06-21 Graham Markall <graham.markall@embecosm.com>
159
160 * arc-dis.c (arc_insn_length): Add comment on instruction length.
161 Use same method for determining instruction length on ARC700 and
162 NPS-400.
163 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
164 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
165 with the NPS400 subclass.
166 * arc-opc.c: Likewise.
167
96074adc
JM		 1682016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
169
170 * sparc-opc.c (rdasr): New macro.
171 (wrasr): Likewise.
172 (rdpr): Likewise.
173 (wrpr): Likewise.
174 (rdhpr): Likewise.
175 (wrhpr): Likewise.
176 (sparc_opcodes): Use the macros above to fix and expand the
177 definition of read/write instructions from/to
178 asr/privileged/hyperprivileged instructions.
179 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
180 %hva_mask_nz. Prefer softint_set and softint_clear over
181 set_softint and clear_softint.
182 (print_insn_sparc): Support %ver in Rd.
183
7a10c22f
JM		 1842016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
185
186 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
187 architecture according to the hardware capabilities they require.
188
4f26fb3a
JM		 1892016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
190
191 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
192 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
193 bfd_mach_sparc_v9{c,d,e,v,m}.
194 * sparc-opc.c (MASK_V9C): Define.
195 (MASK_V9D): Likewise.
196 (MASK_V9E): Likewise.
197 (MASK_V9V): Likewise.
198 (MASK_V9M): Likewise.
199 (v6): Add MASK_V9{C,D,E,V,M}.
200 (v6notlet): Likewise.
201 (v7): Likewise.
202 (v8): Likewise.
203 (v9): Likewise.
204 (v9andleon): Likewise.
205 (v9a): Likewise.
206 (v9b): Likewise.
207 (v9c): Define.
208 (v9d): Likewise.
209 (v9e): Likewise.
210 (v9v): Likewise.
211 (v9m): Likewise.
212 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
213
3ee6e4fb
NC		 2142016-06-15 Nick Clifton <nickc@redhat.com>
215
216 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
217 constants to match expected behaviour.
218 (nds32_parse_opcode): Likewise. Also for whitespace.
219
02f3be19
AB		 2202016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
221
222 * arc-opc.c (extract_rhv1): Extract value from insn.
223
6f9f37ed 2242016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 225
226 * arc-nps400-tbl.h: Add ldbit instruction.
227 * arc-opc.c: Add flag classes required for ldbit.
228
6f9f37ed 2292016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 230
231 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
232 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
233 support the above instructions.
234
6f9f37ed 2352016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 236
237 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
238 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
239 csma, cbba, zncv, and hofs.
240 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
241 support the above instructions.
242
2432016-06-06 Graham Markall <graham.markall@embecosm.com>
244
245 * arc-nps400-tbl.h: Add andab and orab instructions.
246
2472016-06-06 Graham Markall <graham.markall@embecosm.com>
248
249 * arc-nps400-tbl.h: Add addl-like instructions.
250
2512016-06-06 Graham Markall <graham.markall@embecosm.com>
252
253 * arc-nps400-tbl.h: Add mxb and imxb instructions.
254
2552016-06-06 Graham Markall <graham.markall@embecosm.com>
256
257 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
258 instructions.
259
b2cc3f6f
AK		 2602016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
261
262 * s390-dis.c (option_use_insn_len_bits_p): New file scope
263 variable.
264 (init_disasm): Handle new command line option "insnlength".
265 (print_s390_disassembler_options): Mention new option in help
266 output.
267 (print_insn_s390): Use the encoded insn length when dumping
268 unknown instructions.
269
1857fe72
DC		 2702016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
271
272 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
273 to the address and set as symbol address for LDS/ STS immediate operands.
274
14b57c7c
AM		 2752016-06-07 Alan Modra <amodra@gmail.com>
276
277 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
278 cpu for "vle" to e500.
279 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
280 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
281 (PPCNONE): Delete, substitute throughout.
282 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
283 except for major opcode 4 and 31.
284 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
285
4d1464f2
MW		 2862016-06-07 Matthew Wahab <matthew.wahab@arm.com>
287
288 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
289 ARM_EXT_RAS in relevant entries.
290
026122a6
PB		 2912016-06-03 Peter Bergner <bergner@vnet.ibm.com>
292
293 PR binutils/20196
294 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
295 opcodes for E6500.
296
07f5af7d
L		 2972016-06-03 H.J. Lu <hongjiu.lu@intel.com>
298
299 PR binutis/18386
300 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
301 (indir_v_mode): New.
302 Add comments for '&'.
303 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
304 (putop): Handle '&'.
305 (intel_operand_size): Handle indir_v_mode.
306 (OP_E_register): Likewise.
307 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
308 64-bit indirect call/jmp for AMD64.
309 * i386-tbl.h: Regenerated
310
4eb6f892
AB		 3112016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
312
313 * arc-dis.c (struct arc_operand_iterator): New structure.
314 (find_format_from_table): All the old content from find_format,
315 with some minor adjustments, and parameter renaming.
316 (find_format_long_instructions): New function.
317 (find_format): Rewritten.
318 (arc_insn_length): Add LSB parameter.
319 (extract_operand_value): New function.
320 (operand_iterator_next): New function.
321 (print_insn_arc): Use new functions to find opcode, and iterator
322 over operands.
323 * arc-opc.c (insert_nps_3bit_dst_short): New function.
324 (extract_nps_3bit_dst_short): New function.
325 (insert_nps_3bit_src2_short): New function.
326 (extract_nps_3bit_src2_short): New function.
327 (insert_nps_bitop1_size): New function.
328 (extract_nps_bitop1_size): New function.
329 (insert_nps_bitop2_size): New function.
330 (extract_nps_bitop2_size): New function.
331 (insert_nps_bitop_mod4_msb): New function.
332 (extract_nps_bitop_mod4_msb): New function.
333 (insert_nps_bitop_mod4_lsb): New function.
334 (extract_nps_bitop_mod4_lsb): New function.
335 (insert_nps_bitop_dst_pos3_pos4): New function.
336 (extract_nps_bitop_dst_pos3_pos4): New function.
337 (insert_nps_bitop_ins_ext): New function.
338 (extract_nps_bitop_ins_ext): New function.
339 (arc_operands): Add new operands.
340 (arc_long_opcodes): New global array.
341 (arc_num_long_opcodes): New global.
342 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
343
1fe0971e
TS		 3442016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
345
346 * nds32-asm.h: Add extern "C".
347 * sh-opc.h: Likewise.
348
315f180f
GM		 3492016-06-01 Graham Markall <graham.markall@embecosm.com>
350
351 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
352 0,b,limm to the rflt instruction.
353
a2b5fccc
TS		 3542016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
355
356 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
357 constant.
358
0cbd0046
L		 3592016-05-29 H.J. Lu <hongjiu.lu@intel.com>
360
361 PR gas/20145
362 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
363 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
364 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
365 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
366 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
367 * i386-init.h: Regenerated.
368
1848e567
L		 3692016-05-27 H.J. Lu <hongjiu.lu@intel.com>
370
371 PR gas/20145
372 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
373 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
374 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
375 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
376 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
377 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
378 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
379 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
380 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
381 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
382 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
383 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
384 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
385 CpuRegMask for AVX512.
386 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
387 and CpuRegMask.
388 (set_bitfield_from_cpu_flag_init): New function.
389 (set_bitfield): Remove const on f. Call
390 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
391 * i386-opc.h (CpuRegMMX): New.
392 (CpuRegXMM): Likewise.
393 (CpuRegYMM): Likewise.
394 (CpuRegZMM): Likewise.
395 (CpuRegMask): Likewise.
396 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
397 and cpuregmask.
398 * i386-init.h: Regenerated.
399 * i386-tbl.h: Likewise.
400
e92bae62
L		 4012016-05-27 H.J. Lu <hongjiu.lu@intel.com>
402
403 PR gas/20154
404 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
405 (opcode_modifiers): Add AMD64 and Intel64.
406 (main): Properly verify CpuMax.
407 * i386-opc.h (CpuAMD64): Removed.
408 (CpuIntel64): Likewise.
409 (CpuMax): Set to CpuNo64.
410 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
411 (AMD64): New.
412 (Intel64): Likewise.
413 (i386_opcode_modifier): Add amd64 and intel64.
414 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
415 on call and jmp.
416 * i386-init.h: Regenerated.
417 * i386-tbl.h: Likewise.
418
e89c5eaa
L		 4192016-05-27 H.J. Lu <hongjiu.lu@intel.com>
420
421 PR gas/20154
422 * i386-gen.c (main): Fail if CpuMax is incorrect.
423 * i386-opc.h (CpuMax): Set to CpuIntel64.
424 * i386-tbl.h: Regenerated.
425
77d66e7b
NC		 4262016-05-27 Nick Clifton <nickc@redhat.com>
427
428 PR target/20150
429 * msp430-dis.c (msp430dis_read_two_bytes): New function.
430 (msp430dis_opcode_unsigned): New function.
431 (msp430dis_opcode_signed): New function.
432 (msp430_singleoperand): Use the new opcode reading functions.
433 Only disassenmble bytes if they were successfully read.
434 (msp430_doubleoperand): Likewise.
435 (msp430_branchinstr): Likewise.
436 (msp430x_callx_instr): Likewise.
437 (print_insn_msp430): Check that it is safe to read bytes before
438 attempting disassembly. Use the new opcode reading functions.
439
19dfcc89
PB		 4402016-05-26 Peter Bergner <bergner@vnet.ibm.com>
441
442 * ppc-opc.c (CY): New define. Document it.
443 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
444
f3ad7637
L		 4452016-05-25 H.J. Lu <hongjiu.lu@intel.com>
446
447 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
448 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
449 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
450 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
451 CPU_ANY_AVX_FLAGS.
452 * i386-init.h: Regenerated.
453
f1360d58
L		 4542016-05-25 H.J. Lu <hongjiu.lu@intel.com>
455
456 PR gas/20141
457 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
458 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
459 * i386-init.h: Regenerated.
460
293f5f65
L		 4612016-05-25 H.J. Lu <hongjiu.lu@intel.com>
462
463 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
464 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
465 * i386-init.h: Regenerated.
466
d9eca1df
CZ		 4672016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
468
469 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
470 information.
471 (print_insn_arc): Set insn_type information.
472 * arc-opc.c (C_CC): Add F_CLASS_COND.
473 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
474 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
475 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
476 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
477 (brne, brne_s, jeq_s, jne_s): Likewise.
478
87789e08
CZ		 4792016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
480
481 * arc-tbl.h (neg): New instruction variant.
482
c810e0b8
CZ		 4832016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
484
485 * arc-dis.c (find_format, find_format, get_auxreg)
486 (print_insn_arc): Changed.
487 * arc-ext.h (INSERT_XOP): Likewise.
488
3d207518
TS		 4892016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
490
491 * tic54x-dis.c (sprint_mmr): Adjust.
492 * tic54x-opc.c: Likewise.
493
514e58b7
AM		 4942016-05-19 Alan Modra <amodra@gmail.com>
495
496 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
497
e43de63c
AM		 4982016-05-19 Alan Modra <amodra@gmail.com>
499
500 * ppc-opc.c: Formatting.
501 (NSISIGNOPT): Define.
502 (powerpc_opcodes <subis>): Use NSISIGNOPT.
503
1401d2fe
MR		 5042016-05-18 Maciej W. Rozycki <macro@imgtec.com>
505
506 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
507 replacing references to `micromips_ase' throughout.
508 (_print_insn_mips): Don't use file-level microMIPS annotation to
509 determine the disassembly mode with the symbol table.
510
1178da44
PB		 5112016-05-13 Peter Bergner <bergner@vnet.ibm.com>
512
513 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
514
8f4f9071
MF		 5152016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
516
517 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
518 mips64r6.
519 * mips-opc.c (D34): New macro.
520 (mips_builtin_opcodes): Define bposge32c for DSPr3.
521
8bc52696
AF		 5222016-05-10 Alexander Fomin <alexander.fomin@intel.com>
523
524 * i386-dis.c (prefix_table): Add RDPID instruction.
525 * i386-gen.c (cpu_flag_init): Add RDPID flag.
526 (cpu_flags): Add RDPID bitfield.
527 * i386-opc.h (enum): Add RDPID element.
528 (i386_cpu_flags): Add RDPID field.
529 * i386-opc.tbl: Add RDPID instruction.
530 * i386-init.h: Regenerate.
531 * i386-tbl.h: Regenerate.
532
39d911fc
TP		 5332016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
534
535 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
536 branch type of a symbol.
537 (print_insn): Likewise.
538
16a1fa25
TP		 5392016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
540
541 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
542 Mainline Security Extensions instructions.
543 (thumb_opcodes): Add entries for narrow ARMv8-M Security
544 Extensions instructions.
545 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
546 instructions.
547 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
548 special registers.
549
d751b79e
JM		 5502016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
551
552 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
553
945e0f82
CZ		 5542016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
555
556 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
557 (arcExtMap_genOpcode): Likewise.
558 * arc-opc.c (arg_32bit_rc): Define new variable.
559 (arg_32bit_u6): Likewise.
560 (arg_32bit_limm): Likewise.
561
20f55f38
SN		 5622016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
563
564 * aarch64-gen.c (VERIFIER): Define.
565 * aarch64-opc.c (VERIFIER): Define.
566 (verify_ldpsw): Use static linkage.
567 * aarch64-opc.h (verify_ldpsw): Remove.
568 * aarch64-tbl.h: Use VERIFIER for verifiers.
569
4bd13cde
NC		 5702016-04-28 Nick Clifton <nickc@redhat.com>
571
572 PR target/19722
573 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
574 * aarch64-opc.c (verify_ldpsw): New function.
575 * aarch64-opc.h (verify_ldpsw): New prototype.
576 * aarch64-tbl.h: Add initialiser for verifier field.
577 (LDPSW): Set verifier to verify_ldpsw.
578
c0f92bf9
L		 5792016-04-23 H.J. Lu <hongjiu.lu@intel.com>
580
581 PR binutils/19983
582 PR binutils/19984
583 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
584 smaller than address size.
585
e6c7cdec
TS		 5862016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
587
588 * alpha-dis.c: Regenerate.
589 * crx-dis.c: Likewise.
590 * disassemble.c: Likewise.
591 * epiphany-opc.c: Likewise.
592 * fr30-opc.c: Likewise.
593 * frv-opc.c: Likewise.
594 * ip2k-opc.c: Likewise.
595 * iq2000-opc.c: Likewise.
596 * lm32-opc.c: Likewise.
597 * lm32-opinst.c: Likewise.
598 * m32c-opc.c: Likewise.
599 * m32r-opc.c: Likewise.
600 * m32r-opinst.c: Likewise.
601 * mep-opc.c: Likewise.
602 * mt-opc.c: Likewise.
603 * or1k-opc.c: Likewise.
604 * or1k-opinst.c: Likewise.
605 * tic80-opc.c: Likewise.
606 * xc16x-opc.c: Likewise.
607 * xstormy16-opc.c: Likewise.
608
537aefaf
AB		 6092016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
610
611 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
612 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
613 calcsd, and calcxd instructions.
614 * arc-opc.c (insert_nps_bitop_size): Delete.
615 (extract_nps_bitop_size): Delete.
616 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
617 (extract_nps_qcmp_m3): Define.
618 (extract_nps_qcmp_m2): Define.
619 (extract_nps_qcmp_m1): Define.
620 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
621 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
622 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
623 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
624 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
625 NPS_QCMP_M3.
626
c8f785f2
AB		 6272016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
628
629 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
630
6fd8e7c2
L		 6312016-04-15 H.J. Lu <hongjiu.lu@intel.com>
632
633 * Makefile.in: Regenerated with automake 1.11.6.
634 * aclocal.m4: Likewise.
635
4b0c052e
AB		 6362016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
637
638 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
639 instructions.
640 * arc-opc.c (insert_nps_cmem_uimm16): New function.
641 (extract_nps_cmem_uimm16): New function.
642 (arc_operands): Add NPS_XLDST_UIMM16 operand.
643
cb040366
AB		 6442016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
645
646 * arc-dis.c (arc_insn_length): New function.
647 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
648 (find_format): Change insnLen parameter to unsigned.
649
accc0180
NC		 6502016-04-13 Nick Clifton <nickc@redhat.com>
651
652 PR target/19937
653 * v850-opc.c (v850_opcodes): Correct masks for long versions of
654 the LD.B and LD.BU instructions.
655
f36e33da
CZ		 6562016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
657
658 * arc-dis.c (find_format): Check for extension flags.
659 (print_flags): New function.
660 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
661 .extAuxRegister.
662 * arc-ext.c (arcExtMap_coreRegName): Use
663 LAST_EXTENSION_CORE_REGISTER.
664 (arcExtMap_coreReadWrite): Likewise.
665 (dump_ARC_extmap): Update printing.
666 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
667 (arc_aux_regs): Add cpu field.
668 * arc-regs.h: Add cpu field, lower case name aux registers.
669
1c2e355e
CZ		 6702016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
671
672 * arc-tbl.h: Add rtsc, sleep with no arguments.
673
b99747ae
CZ		 6742016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
675
676 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
677 Initialize.
678 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
679 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
680 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
681 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
682 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
683 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
684 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
685 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
686 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
687 (arc_opcode arc_opcodes): Null terminate the array.
688 (arc_num_opcodes): Remove.
689 * arc-ext.h (INSERT_XOP): Define.
690 (extInstruction_t): Likewise.
691 (arcExtMap_instName): Delete.
692 (arcExtMap_insn): New function.
693 (arcExtMap_genOpcode): Likewise.
694 * arc-ext.c (ExtInstruction): Remove.
695 (create_map): Zero initialize instruction fields.
696 (arcExtMap_instName): Remove.
697 (arcExtMap_insn): New function.
698 (dump_ARC_extmap): More info while debuging.
699 (arcExtMap_genOpcode): New function.
700 * arc-dis.c (find_format): New function.
701 (print_insn_arc): Use find_format.
702 (arc_get_disassembler): Enable dump_ARC_extmap only when
703 debugging.
704
92708cec
MR		 7052016-04-11 Maciej W. Rozycki <macro@imgtec.com>
706
707 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
708 instruction bits out.
709
a42a4f84
AB		 7102016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
711
712 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
713 * arc-opc.c (arc_flag_operands): Add new flags.
714 (arc_flag_classes): Add new classes.
715
1328504b
AB		 7162016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
717
718 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
719
820f03ff
AB		 7202016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
721
722 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
723 encode1, rflt, crc16, and crc32 instructions.
724 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
725 (arc_flag_classes): Add C_NPS_R.
726 (insert_nps_bitop_size_2b): New function.
727 (extract_nps_bitop_size_2b): Likewise.
728 (insert_nps_bitop_uimm8): Likewise.
729 (extract_nps_bitop_uimm8): Likewise.
730 (arc_operands): Add new operand entries.
731
8ddf6b2a
CZ		 7322016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
733
b99747ae
CZ		 734 * arc-regs.h: Add a new subclass field. Add double assist
735 accumulator register values.
736 * arc-tbl.h: Use DPA subclass to mark the double assist
737 instructions. Use DPX/SPX subclas to mark the FPX instructions.
738 * arc-opc.c (RSP): Define instead of SP.
739 (arc_aux_regs): Add the subclass field.
8ddf6b2a 740
589a7d88
JW		 7412016-04-05 Jiong Wang <jiong.wang@arm.com>
742
743 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
744
0a191de9 7452016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 746
747 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
748 NPS_R_SRC1.
749
0a106562
AB		 7502016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
751
752 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
753 issues. No functional changes.
754
bd05ac5f
CZ		 7552016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
756
b99747ae
CZ		 757 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
758 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
759 (RTT): Remove duplicate.
760 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
761 (PCT_CONFIG*): Remove.
762 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 763
9885948f
CZ		 7642016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
765
b99747ae 766 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 767
f2dd8838
CZ		 7682016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
769
b99747ae
CZ		 770 * arc-tbl.h (invld07): Remove.
771 * arc-ext-tbl.h: New file.
772 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
773 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 774
0d2f91fe
JK		 7752016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
776
777 Fix -Wstack-usage warnings.
778 * aarch64-dis.c (print_operands): Substitute size.
779 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
780
a6b71f42
JM		 7812016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
782
783 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
784 to get a proper diagnostic when an invalid ASR register is used.
785
9780e045
NC		 7862016-03-22 Nick Clifton <nickc@redhat.com>
787
788 * configure: Regenerate.
789
e23e8ebe
AB		 7902016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
791
792 * arc-nps400-tbl.h: New file.
793 * arc-opc.c: Add top level comment.
794 (insert_nps_3bit_dst): New function.
795 (extract_nps_3bit_dst): New function.
796 (insert_nps_3bit_src2): New function.
797 (extract_nps_3bit_src2): New function.
798 (insert_nps_bitop_size): New function.
799 (extract_nps_bitop_size): New function.
800 (arc_flag_operands): Add nps400 entries.
801 (arc_flag_classes): Add nps400 entries.
802 (arc_operands): Add nps400 entries.
803 (arc_opcodes): Add nps400 include.
804
1ae8ab47
AB		 8052016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
806
807 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
808 the new class enum values.
809
8699fc3e
AB		 8102016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
811
812 * arc-dis.c (print_insn_arc): Handle nps400.
813
24740d83
AB		 8142016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
815
816 * arc-opc.c (BASE): Delete.
817
8678914f
NC		 8182016-03-18 Nick Clifton <nickc@redhat.com>
819
820 PR target/19721
821 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
822 of MOV insn that aliases an ORR insn.
823
cc933301
JW		 8242016-03-16 Jiong Wang <jiong.wang@arm.com>
825
826 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
827
f86f5863
TS		 8282016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
829
830 * mcore-opc.h: Add const qualifiers.
831 * microblaze-opc.h (struct op_code_struct): Likewise.
832 * sh-opc.h: Likewise.
833 * tic4x-dis.c (tic4x_print_indirect): Likewise.
834 (tic4x_print_op): Likewise.
835
62de1c63
AM		 8362016-03-02 Alan Modra <amodra@gmail.com>
837
d11698cd 838 * or1k-desc.h: Regenerate.
62de1c63 839 * fr30-ibld.c: Regenerate.
c697cf0b 840 * rl78-decode.c: Regenerate.
62de1c63 841
020efce5
NC		 8422016-03-01 Nick Clifton <nickc@redhat.com>
843
844 PR target/19747
845 * rl78-dis.c (print_insn_rl78_common): Fix typo.
846
b0c11777
RL		 8472016-02-24 Renlin Li <renlin.li@arm.com>
848
849 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
850 (print_insn_coprocessor): Support fp16 instructions.
851
3e309328
RL		 8522016-02-24 Renlin Li <renlin.li@arm.com>
853
854 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
855 vminnm, vrint(mpna).
856
8afc7bea
RL		 8572016-02-24 Renlin Li <renlin.li@arm.com>
858
859 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
860 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
861
4fd7268a
L		 8622016-02-15 H.J. Lu <hongjiu.lu@intel.com>
863
864 * i386-dis.c (print_insn): Parenthesize expression to prevent
865 truncated addresses.
866 (OP_J): Likewise.
867
4670103e
CZ		 8682016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
869 Janek van Oirschot <jvanoirs@synopsys.com>
870
b99747ae
CZ		 871 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
872 variable.
4670103e 873
c1d9289f
NC		 8742016-02-04 Nick Clifton <nickc@redhat.com>
875
876 PR target/19561
877 * msp430-dis.c (print_insn_msp430): Add a special case for
878 decoding an RRC instruction with the ZC bit set in the extension
879 word.
880
a143b004
AB		 8812016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
882
883 * cgen-ibld.in (insert_normal): Rework calculation of shift.
884 * epiphany-ibld.c: Regenerate.
885 * fr30-ibld.c: Regenerate.
886 * frv-ibld.c: Regenerate.
887 * ip2k-ibld.c: Regenerate.
888 * iq2000-ibld.c: Regenerate.
889 * lm32-ibld.c: Regenerate.
890 * m32c-ibld.c: Regenerate.
891 * m32r-ibld.c: Regenerate.
892 * mep-ibld.c: Regenerate.
893 * mt-ibld.c: Regenerate.
894 * or1k-ibld.c: Regenerate.
895 * xc16x-ibld.c: Regenerate.
896 * xstormy16-ibld.c: Regenerate.
897
b89807c6
AB		 8982016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
899
900 * epiphany-dis.c: Regenerated from latest cpu files.
901
d8c823c8
MM		 9022016-02-01 Michael McConville <mmcco@mykolab.com>
903
904 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
905 test bit.
906
5bc5ae88
RL		 9072016-01-25 Renlin Li <renlin.li@arm.com>
908
909 * arm-dis.c (mapping_symbol_for_insn): New function.
910 (find_ifthen_state): Call mapping_symbol_for_insn().
911
0bff6e2d
MW		 9122016-01-20 Matthew Wahab <matthew.wahab@arm.com>
913
914 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
915 of MSR UAO immediate operand.
916
100b4f2e
MR		 9172016-01-18 Maciej W. Rozycki <macro@imgtec.com>
918
919 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
920 instruction support.
921
5c14705f
AM		 9222016-01-17 Alan Modra <amodra@gmail.com>
923
924 * configure: Regenerate.
925
4d82fe66
NC		 9262016-01-14 Nick Clifton <nickc@redhat.com>
927
928 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
929 instructions that can support stack pointer operations.
930 * rl78-decode.c: Regenerate.
931 * rl78-dis.c: Fix display of stack pointer in MOVW based
932 instructions.
933
651657fa
MW		 9342016-01-14 Matthew Wahab <matthew.wahab@arm.com>
935
936 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
937 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
938 erxtatus_el1 and erxaddr_el1.
939
105bde57
MW		 9402016-01-12 Matthew Wahab <matthew.wahab@arm.com>
941
942 * arm-dis.c (arm_opcodes): Add "esb".
943 (thumb_opcodes): Likewise.
944
afa8d405
PB		 9452016-01-11 Peter Bergner <bergner@vnet.ibm.com>
946
947 * ppc-opc.c <xscmpnedp>: Delete.
948 <xvcmpnedp>: Likewise.
949 <xvcmpnedp.>: Likewise.
950 <xvcmpnesp>: Likewise.
951 <xvcmpnesp.>: Likewise.
952
83c3256e
AS		 9532016-01-08 Andreas Schwab <schwab@linux-m68k.org>
954
955 PR gas/13050
956 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
957 addition to ISA_A.
958
6f2750fe
AM		 9592016-01-01 Alan Modra <amodra@gmail.com>
960
961 Update year range in copyright notice of all files.
962
3499769a
AM		 963For older changes see ChangeLog-2015
964\f
965Copyright (C) 2016 Free Software Foundation, Inc.
966
967Copying and distribution of this file, with or without modification,
968are permitted in any medium without royalty provided the copyright
969notice and this notice are preserved.
970
971Local Variables:
972mode: change-log
973left-margin: 8
974fill-column: 74
975version-control: never
976End:
GDB Binutils - Deliverables
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