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ld: aarch64: fix TLS relaxation where TCB_SIZE is used
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
a6a51754
RL		 12016-12-13 Renlin Li <renlin.li@arm.com>
2
3 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
4 qualifier.
5 (operand_general_constraint_met_p): Remove case for CP_REG.
6 (aarch64_print_operand): Print CRn, CRm operand using imm field.
7 * aarch64-tbl.h (QL_SYS): Use CR qualifier.
8 (QL_SYSL): Likewise.
9 (aarch64_opcode_table): Change CRn, CRm operand class and type.
10 * aarch64-opc-2.c : Regenerate.
11 * aarch64-asm-2.c : Likewise.
12 * aarch64-dis-2.c : Likewise.
13
029e9d52
YQ		 142016-12-12 Yao Qi <yao.qi@linaro.org>
15
16 * rx-dis.c: Include <setjmp.h>
17 (struct private): New.
18 (rx_get_byte): Check return value of read_memory_func, and
19 call memory_error_func and OPCODES_SIGLONGJMP on error.
20 (print_insn_rx): Call OPCODES_SIGSETJMP.
21
3a0b8f7d
YQ		 222016-12-12 Yao Qi <yao.qi@linaro.org>
23
24 * rl78-dis.c: Include <setjmp.h>.
25 (struct private): New.
26 (rl78_get_byte): Check return value of read_memory_func, and
27 call memory_error_func and OPCODES_SIGLONGJMP on error.
28 (print_insn_rl78_common): Call OPCODES_SIGJMP.
29
64c11183
MR		 302016-12-09 Maciej W. Rozycki <macro@imgtec.com>
31
32 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
33
f17ecb4b
MR		 342016-12-09 Maciej W. Rozycki <macro@imgtec.com>
35
36 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
37 than UINT.
38
55af4784
MR		 392016-12-09 Maciej W. Rozycki <macro@imgtec.com>
40
41 * mips-dis.c (print_insn_mips16): Use a tab rather than a space
42 to separate `extend' and its uninterpreted argument output.
43 Separate hexadecimal halves of undecoded extended instructions
44 output.
45
39f66f3a
MR		 462016-12-08 Maciej W. Rozycki <macro@imgtec.com>
47
48 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
49 indentation space across.
50
860b03a8
MR		 512016-12-08 Maciej W. Rozycki <macro@imgtec.com>
52
53 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
54 adjustment for PC-relative operations following MIPS16e compact
55 jumps or undefined RR/J(AL)R(C) encodings.
56
329d01f7
MR		 572016-12-08 Maciej W. Rozycki <macro@imgtec.com>
58
59 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
60 variable to `reglane_index'.
61
3a2488dd
LM		 622016-12-08 Luis Machado <lgustavo@codesourcery.com>
63
64 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
65
5f5c6e03
MR		 662016-12-07 Maciej W. Rozycki <macro@imgtec.com>
67
68 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
69
343fa690
MR		 702016-12-07 Maciej W. Rozycki <macro@imgtec.com>
71
72 * mips16-opc.c (mips16_opcodes): Update comment naming structure
73 members.
74
6725647c
MR		 752016-12-07 Maciej W. Rozycki <macro@imgtec.com>
76
77 * mips-dis.c (print_mips_disassembler_options): Reformat output.
78
c28eeff2
SN		 792016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
80
81 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
82 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
83
49e8a725
SN		 842016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
85
86 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
87
a37a2806
NC		 882016-12-01 Nick Clifton <nickc@redhat.com>
89
90 PR binutils/20893
91 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
92 opcode designator.
93
abe7c33b
CZ		 942016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
95
96 * arc-opc.c (insert_ra_chk): New function.
97 (insert_rb_chk): Likewise.
98 (insert_rad): Update text error message.
99 (insert_rcd): Likewise.
100 (insert_rhv2): Likewise.
101 (insert_r0): Likewise.
102 (insert_r1): Likewise.
103 (insert_r2): Likewise.
104 (insert_r3): Likewise.
105 (insert_sp): Likewise.
106 (insert_gp): Likewise.
107 (insert_pcl): Likewise.
108 (insert_blink): Likewise.
109 (insert_ilink1): Likewise.
110 (insert_ilink2): Likewise.
111 (insert_ras): Likewise.
112 (insert_rbs): Likewise.
113 (insert_rcs): Likewise.
114 (insert_simm3s): Likewise.
115 (insert_rrange): Likewise.
116 (insert_fpel): Likewise.
117 (insert_blinkel): Likewise.
118 (insert_pcel): Likewise.
119 (insert_nps_3bit_dst): Likewise.
120 (insert_nps_3bit_dst_short): Likewise.
121 (insert_nps_3bit_src2_short): Likewise.
122 (insert_nps_bitop_size_2b): Likewise.
123 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
124 (RA_CHK): Define.
125 (RB): Adjust.
126 (RB_CHK): Define.
127 (RC): Adjust.
128 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
129 * arc-tbl.h (div, divu): All instructions are DIVREM class.
130 Change first insn argument to check for LP_COUNT usage.
131 (rem): Likewise.
132 (ld, ldd): All instructions are LOAD class. Change first insn
133 argument to check for LP_COUNT usage.
134 (st, std): All instructions are STORE class.
135 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
136 Change first insn argument to check for LP_COUNT usage.
137 (mov): All instructions are MOVE class. Change first insn
138 argument to check for LP_COUNT usage.
139
ee881e5d
CZ		 1402016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
141
142 * arc-dis.c (is_compatible_p): Remove function.
143 (skip_this_opcode): Don't add any decoding class to decode list.
144 Remove warning.
145 (find_format_from_table): Go through all opcodes, and warn if we
146 use a guessed mnemonic.
147
abfcb414
AP		 1482016-11-28 Ramiro Polla <ramiro@hex-rays.com>
149 Amit Pawar <amit.pawar@amd.com>
150
151 PR binutils/20637
152 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
153 instructions.
154
96fe4562
AM		 1552016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
156
157 * configure: Regenerate.
158
6884417a
JM		 1592016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
160
161 * sparc-opc.c (HWS_V8): Definition moved from
162 gas/config/tc-sparc.c.
163 (HWS_V9): Likewise.
164 (HWS_VA): Likewise.
165 (HWS_VB): Likewise.
166 (HWS_VC): Likewise.
167 (HWS_VD): Likewise.
168 (HWS_VE): Likewise.
169 (HWS_VV): Likewise.
170 (HWS_VM): Likewise.
171 (HWS2_VM): Likewise.
172 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
173 existing entries.
174
c4b943d7
CZ		 1752016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
176
177 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
178 instructions.
179
c2c4ff8d
SN		 1802016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
181
182 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
183 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
184 (aarch64_opcode_table): Add fcmla and fcadd.
185 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
186 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
187 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
188 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
189 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
190 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
191 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
192 (operand_general_constraint_met_p): Rotate and index range check.
193 (aarch64_print_operand): Handle rotate operand.
194 * aarch64-asm-2.c: Regenerate.
195 * aarch64-dis-2.c: Likewise.
196 * aarch64-opc-2.c: Likewise.
197
28617675
SN		 1982016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
199
200 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
201 * aarch64-asm-2.c: Regenerate.
202 * aarch64-dis-2.c: Regenerate.
203 * aarch64-opc-2.c: Regenerate.
204
ccfc90a3
SN		 2052016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
206
207 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
208 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
209 * aarch64-asm-2.c: Regenerate.
210 * aarch64-dis-2.c: Regenerate.
211 * aarch64-opc-2.c: Regenerate.
212
3f06e550
SN		 2132016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
214
215 * aarch64-tbl.h (QL_X1NIL): New.
216 (arch64_opcode_table): Add ldraa, ldrab.
217 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
218 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
219 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
220 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
221 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
222 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
223 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
224 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
225 (aarch64_print_operand): Likewise.
226 * aarch64-asm-2.c: Regenerate.
227 * aarch64-dis-2.c: Regenerate.
228 * aarch64-opc-2.c: Regenerate.
229
74f5402d
SN		 2302016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
231
232 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
233 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
234 * aarch64-asm-2.c: Regenerate.
235 * aarch64-dis-2.c: Regenerate.
236 * aarch64-opc-2.c: Regenerate.
237
c84364ec
SN		 2382016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
239
240 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
241 (AARCH64_OPERANDS): Add Rm_SP.
242 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
243 * aarch64-asm-2.c: Regenerate.
244 * aarch64-dis-2.c: Regenerate.
245 * aarch64-opc-2.c: Regenerate.
246
a2cfc830
SN		 2472016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
248
249 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
250 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
251 autdzb, xpaci, xpacd.
252 * aarch64-asm-2.c: Regenerate.
253 * aarch64-dis-2.c: Regenerate.
254 * aarch64-opc-2.c: Regenerate.
255
b0bfa7b5
SN		 2562016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
257
258 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
259 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
260 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
261 (aarch64_sys_reg_supported_p): Add feature test for new registers.
262
8787d804
SN		 2632016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
264
265 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
266 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
267 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
268 autibsp.
269 * aarch64-asm-2.c: Regenerate.
270 * aarch64-dis-2.c: Regenerate.
271
3d731f69
SN		 2722016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
273
274 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
275
60227d64
L		 2762016-11-09 H.J. Lu <hongjiu.lu@intel.com>
277
278 PR binutils/20799
279 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
280 * i386-dis.c (EdqwS): Removed.
281 (dqw_swap_mode): Likewise.
282 (intel_operand_size): Don't check dqw_swap_mode.
283 (OP_E_register): Likewise.
284 (OP_E_memory): Likewise.
285 (OP_G): Likewise.
286 (OP_EX): Likewise.
287 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
288 * i386-tbl.h: Regerated.
289
7efeed17
L		 2902016-11-09 H.J. Lu <hongjiu.lu@intel.com>
291
292 * i386-opc.tbl: Merge AVX512F vmovq.
1032d6eb 293 * i386-tbl.h: Regerated.
7efeed17 294
1f334aeb
L		 2952016-11-08 H.J. Lu <hongjiu.lu@intel.com>
296
297 PR binutils/20701
298 * i386-dis.c (THREE_BYTE_0F7A): Removed.
299 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
300 (three_byte_table): Remove THREE_BYTE_0F7A.
301
48c97fa1
L		 3022016-11-07 H.J. Lu <hongjiu.lu@intel.com>
303
304 PR binutils/20775
305 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
306 (FGRPd9_4): Replace 1 with 2.
307 (FGRPd9_5): Replace 2 with 3.
308 (FGRPd9_6): Replace 3 with 4.
309 (FGRPd9_7): Replace 4 with 5.
310 (FGRPda_5): Replace 5 with 6.
311 (FGRPdb_4): Replace 6 with 7.
312 (FGRPde_3): Replace 7 with 8.
313 (FGRPdf_4): Replace 8 with 9.
314 (fgrps): Add an entry for Bad_Opcode.
315
b437d035
AB		 3162016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
317
318 * arc-opc.c (arc_flag_operands): Add F_DI14.
319 (arc_flag_classes): Add C_DI14.
320 * arc-nps400-tbl.h: Add new exc instructions.
321
5a736821
GM		 3222016-11-03 Graham Markall <graham.markall@embecosm.com>
323
324 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
325 major opcode 0xa.
326 * arc-nps-400-tbl.h: Add dcmac instruction.
327 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
328 (insert_nps_rbdouble_64): Added.
329 (extract_nps_rbdouble_64): Added.
330 (insert_nps_proto_size): Added.
331 (extract_nps_proto_size): Added.
332
bdfe53e3
AB		 3332016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
334
335 * arc-dis.c (struct arc_operand_iterator): Remove all fields
336 relating to long instruction processing, add new limm field.
337 (OPCODE): Rename to...
338 (OPCODE_32BIT_INSN): ...this.
339 (OPCODE_AC): Delete.
340 (skip_this_opcode): Handle different instruction lengths, update
341 macro name.
342 (special_flag_p): Update parameter type.
343 (find_format_from_table): Update for more instruction lengths.
344 (find_format_long_instructions): Delete.
345 (find_format): Update for more instruction lengths.
346 (arc_insn_length): Likewise.
347 (extract_operand_value): Update for more instruction lengths.
348 (operand_iterator_next): Remove code relating to long
349 instructions.
350 (arc_opcode_to_insn_type): New function.
351 (print_insn_arc):Update for more instructions lengths.
352 * arc-ext.c (extInstruction_t): Change argument type.
353 * arc-ext.h (extInstruction_t): Change argument type.
354 * arc-fxi.h: Change type unsigned to unsigned long long
355 extensively throughout.
356 * arc-nps400-tbl.h: Add long instructions taken from
357 arc_long_opcodes table in arc-opc.c.
358 * arc-opc.c: Update parameter types on insert/extract handlers.
359 (arc_long_opcodes): Delete.
360 (arc_num_long_opcodes): Delete.
361 (arc_opcode_len): Update for more instruction lengths.
362
90f61cce
GM		 3632016-11-03 Graham Markall <graham.markall@embecosm.com>
364
365 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
366
06fe285f
GM		 3672016-11-03 Graham Markall <graham.markall@embecosm.com>
368
369 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
370 with arc_opcode_len.
371 (find_format_long_instructions): Likewise.
372 * arc-opc.c (arc_opcode_len): New function.
373
ecf64ec6
AB		 3742016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
375
376 * arc-nps400-tbl.h: Fix some instruction masks.
377
d039fef3
L		 3782016-11-03 H.J. Lu <hongjiu.lu@intel.com>
379
380 * i386-dis.c (REG_82): Removed.
381 (X86_64_82_REG_0): Likewise.
382 (X86_64_82_REG_1): Likewise.
383 (X86_64_82_REG_2): Likewise.
384 (X86_64_82_REG_3): Likewise.
385 (X86_64_82_REG_4): Likewise.
386 (X86_64_82_REG_5): Likewise.
387 (X86_64_82_REG_6): Likewise.
388 (X86_64_82_REG_7): Likewise.
389 (X86_64_82): New.
390 (dis386): Use X86_64_82 instead of REG_82.
391 (reg_table): Remove REG_82.
392 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
393 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
394 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
395 X86_64_82_REG_7.
396
8b89fe14
L		 3972016-11-03 H.J. Lu <hongjiu.lu@intel.com>
398
399 PR binutils/20754
400 * i386-dis.c (REG_82): New.
401 (X86_64_82_REG_0): Likewise.
402 (X86_64_82_REG_1): Likewise.
403 (X86_64_82_REG_2): Likewise.
404 (X86_64_82_REG_3): Likewise.
405 (X86_64_82_REG_4): Likewise.
406 (X86_64_82_REG_5): Likewise.
407 (X86_64_82_REG_6): Likewise.
408 (X86_64_82_REG_7): Likewise.
409 (dis386): Use REG_82.
410 (reg_table): Add REG_82.
411 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
412 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
413 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
414
7148c369
L		 4152016-11-03 H.J. Lu <hongjiu.lu@intel.com>
416
417 * i386-dis.c (REG_82): Renamed to ...
418 (REG_83): This.
419 (dis386): Updated.
420 (reg_table): Likewise.
421
47acf0bd
IT		 4222016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
423
424 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
425 * i386-dis-evex.h (evex_table): Updated.
426 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
427 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
428 (cpu_flags): Add CpuAVX512_4VNNIW.
429 * i386-opc.h (enum): (AVX512_4VNNIW): New.
430 (i386_cpu_flags): Add cpuavx512_4vnniw.
431 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
432 * i386-init.h: Regenerate.
433 * i386-tbl.h: Ditto.
434
920d2ddc
IT		 4352016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
436
437 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
438 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
439 * i386-dis-evex.h (evex_table): Updated.
440 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
441 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
442 (cpu_flags): Add CpuAVX512_4FMAPS.
443 (opcode_modifiers): Add ImplicitQuadGroup modifier.
444 * i386-opc.h (AVX512_4FMAP): New.
445 (i386_cpu_flags): Add cpuavx512_4fmaps.
446 (ImplicitQuadGroup): New.
447 (i386_opcode_modifier): Add implicitquadgroup.
448 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
449 * i386-init.h: Regenerate.
450 * i386-tbl.h: Ditto.
451
e23eba97
NC		 4522016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
453 Andrew Waterman <andrew@sifive.com>
454
455 Add support for RISC-V architecture.
456 * configure.ac: Add entry for bfd_riscv_arch.
457 * configure: Regenerate.
458 * disassemble.c (disassembler): Add support for riscv.
459 (disassembler_usage): Likewise.
460 * riscv-dis.c: New file.
461 * riscv-opc.c: New file.
462
b5cefcca
L		 4632016-10-21 H.J. Lu <hongjiu.lu@intel.com>
464
465 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
466 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
467 (rm_table): Update the RM_0FAE_REG_7 entry.
468 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
469 (cpu_flags): Remove CpuPCOMMIT.
470 * i386-opc.h (CpuPCOMMIT): Removed.
471 (i386_cpu_flags): Remove cpupcommit.
472 * i386-opc.tbl: Remove pcommit.
473 * i386-init.h: Regenerated.
474 * i386-tbl.h: Likewise.
475
9889cbb1
L		 4762016-10-20 H.J. Lu <hongjiu.lu@intel.com>
477
478 PR binutis/20705
479 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
480 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
481 32-bit mode. Don't check vex.register_specifier in 32-bit
482 mode.
483 (OP_VEX): Check for invalid mask registers.
484
28596323
L		 4852016-10-18 H.J. Lu <hongjiu.lu@intel.com>
486
487 PR binutis/20699
488 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
489 sizeflag.
490
da8d7d66
L		 4912016-10-18 H.J. Lu <hongjiu.lu@intel.com>
492
493 PR binutis/20704
494 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
495
eaf02703
MR		 4962016-10-18 Maciej W. Rozycki <macro@imgtec.com>
497
498 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
499 local variable to `index_regno'.
500
decf5bd1
CM		 5012016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
502
503 * arc-tbl.h: Removed any "inv.+" instructions from the table.
504
e5b06ef0
CZ		 5052016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
506
507 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
508 usage on ISA basis.
509
93562a34
JW		 5102016-10-11 Jiong Wang <jiong.wang@arm.com>
511
512 PR target/20666
513 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
514
362c0c4d
JW		 5152016-10-07 Jiong Wang <jiong.wang@arm.com>
516
517 PR target/20667
518 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
519 available.
520
1047201f
AM		 5212016-10-07 Alan Modra <amodra@gmail.com>
522
523 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
524
1a0670f3
AM		 5252016-10-06 Alan Modra <amodra@gmail.com>
526
527 * aarch64-opc.c: Spell fall through comments consistently.
528 * i386-dis.c: Likewise.
529 * aarch64-dis.c: Add missing fall through comments.
530 * aarch64-opc.c: Likewise.
531 * arc-dis.c: Likewise.
532 * arm-dis.c: Likewise.
533 * i386-dis.c: Likewise.
534 * m68k-dis.c: Likewise.
535 * mep-asm.c: Likewise.
536 * ns32k-dis.c: Likewise.
537 * sh-dis.c: Likewise.
538 * tic4x-dis.c: Likewise.
539 * tic6x-dis.c: Likewise.
540 * vax-dis.c: Likewise.
541
2b804145
AM		 5422016-10-06 Alan Modra <amodra@gmail.com>
543
544 * arc-ext.c (create_map): Add missing break.
545 * msp430-decode.opc (encode_as): Likewise.
546 * msp430-decode.c: Regenerate.
547
616ec358
AM		 5482016-10-06 Alan Modra <amodra@gmail.com>
549
550 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
551 * crx-dis.c (print_insn_crx): Likewise.
552
72da393d
L		 5532016-09-30 H.J. Lu <hongjiu.lu@intel.com>
554
555 PR binutils/20657
556 * i386-dis.c (putop): Don't assign alt twice.
557
744ce302
JW		 5582016-09-29 Jiong Wang <jiong.wang@arm.com>
559
560 PR target/20553
561 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
562
a5721ba2
AM		 5632016-09-29 Alan Modra <amodra@gmail.com>
564
565 * ppc-opc.c (L): Make compulsory.
566 (LOPT): New, optional form of L.
567 (HTM_R): Define as LOPT.
568 (L0, L1): Delete.
569 (L32OPT): New, optional for 32-bit L.
570 (L2OPT): New, 2-bit L for dcbf.
571 (SVC_LEC): Update.
572 (L2): Define.
573 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
574 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
575 <dcbf>: Use L2OPT.
576 <tlbiel, tlbie>: Use LOPT.
577 <wclr, wclrall>: Use L2.
578
c5da1932
VZ		 5792016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
580
581 * Makefile.in: Regenerate.
582 * configure: Likewise.
583
2b848ebd
CZ		 5842016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
585
586 * arc-ext-tbl.h (EXTINSN2OPF): Define.
587 (EXTINSN2OP): Use EXTINSN2OPF.
588 (bspeekm, bspop, modapp): New extension instructions.
589 * arc-opc.c (F_DNZ_ND): Define.
590 (F_DNZ_D): Likewise.
591 (F_SIZEB1): Changed.
592 (C_DNZ_D): Define.
593 (C_HARD): Changed.
594 * arc-tbl.h (dbnz): New instruction.
595 (prealloc): Allow it for ARC EM.
596 (xbfu): Likewise.
597
ad43e107
RS		 5982016-09-21 Richard Sandiford <richard.sandiford@arm.com>
599
600 * aarch64-opc.c (print_immediate_offset_address): Print spaces
601 after commas in addresses.
602 (aarch64_print_operand): Likewise.
603
ab3b8fcf
RS		 6042016-09-21 Richard Sandiford <richard.sandiford@arm.com>
605
606 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
607 rather than "should be" or "expected to be" in error messages.
608
bb7eff52
RS		 6092016-09-21 Richard Sandiford <richard.sandiford@arm.com>
610
611 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
612 (print_mnemonic_name): ...here.
613 (print_comment): New function.
614 (print_aarch64_insn): Call it.
615 * aarch64-opc.c (aarch64_conds): Add SVE names.
616 (aarch64_print_operand): Print alternative condition names in
617 a comment.
618
c0890d26
RS		 6192016-09-21 Richard Sandiford <richard.sandiford@arm.com>
620
621 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
622 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
623 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
624 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
625 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
626 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
627 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
628 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
629 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
630 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
631 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
632 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
633 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
634 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
635 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
636 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
637 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
638 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
639 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
640 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
641 (OP_SVE_XWU, OP_SVE_XXU): New macros.
642 (aarch64_feature_sve): New variable.
643 (SVE): New macro.
644 (_SVE_INSN): Likewise.
645 (aarch64_opcode_table): Add SVE instructions.
646 * aarch64-opc.h (extract_fields): Declare.
647 * aarch64-opc-2.c: Regenerate.
648 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
649 * aarch64-asm-2.c: Regenerate.
650 * aarch64-dis.c (extract_fields): Make global.
651 (do_misc_decoding): Handle the new SVE aarch64_ops.
652 * aarch64-dis-2.c: Regenerate.
653
116b6019
RS		 6542016-09-21 Richard Sandiford <richard.sandiford@arm.com>
655
656 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
657 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
658 aarch64_field_kinds.
659 * aarch64-opc.c (fields): Add corresponding entries.
660 * aarch64-asm.c (aarch64_get_variant): New function.
661 (aarch64_encode_variant_using_iclass): Likewise.
662 (aarch64_opcode_encode): Call it.
663 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
664 (aarch64_opcode_decode): Call it.
665
047cd301
RS		 6662016-09-21 Richard Sandiford <richard.sandiford@arm.com>
667
668 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
669 and FP register operands.
670 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
671 (FLD_SVE_Vn): New aarch64_field_kinds.
672 * aarch64-opc.c (fields): Add corresponding entries.
673 (aarch64_print_operand): Handle the new SVE core and FP register
674 operands.
675 * aarch64-opc-2.c: Regenerate.
676 * aarch64-asm-2.c: Likewise.
677 * aarch64-dis-2.c: Likewise.
678
165d4950
RS		 6792016-09-21 Richard Sandiford <richard.sandiford@arm.com>
680
681 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
682 immediate operands.
683 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
684 * aarch64-opc.c (fields): Add corresponding entry.
685 (operand_general_constraint_met_p): Handle the new SVE FP immediate
686 operands.
687 (aarch64_print_operand): Likewise.
688 * aarch64-opc-2.c: Regenerate.
689 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
690 (ins_sve_float_zero_one): New inserters.
691 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
692 (aarch64_ins_sve_float_half_two): Likewise.
693 (aarch64_ins_sve_float_zero_one): Likewise.
694 * aarch64-asm-2.c: Regenerate.
695 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
696 (ext_sve_float_zero_one): New extractors.
697 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
698 (aarch64_ext_sve_float_half_two): Likewise.
699 (aarch64_ext_sve_float_zero_one): Likewise.
700 * aarch64-dis-2.c: Regenerate.
701
e950b345
RS		 7022016-09-21 Richard Sandiford <richard.sandiford@arm.com>
703
704 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
705 integer immediate operands.
706 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
707 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
708 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
709 * aarch64-opc.c (fields): Add corresponding entries.
710 (operand_general_constraint_met_p): Handle the new SVE integer
711 immediate operands.
712 (aarch64_print_operand): Likewise.
713 (aarch64_sve_dupm_mov_immediate_p): New function.
714 * aarch64-opc-2.c: Regenerate.
715 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
716 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
717 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
718 (aarch64_ins_limm): ...here.
719 (aarch64_ins_inv_limm): New function.
720 (aarch64_ins_sve_aimm): Likewise.
721 (aarch64_ins_sve_asimm): Likewise.
722 (aarch64_ins_sve_limm_mov): Likewise.
723 (aarch64_ins_sve_shlimm): Likewise.
724 (aarch64_ins_sve_shrimm): Likewise.
725 * aarch64-asm-2.c: Regenerate.
726 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
727 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
728 * aarch64-dis.c (decode_limm): New function, split out from...
729 (aarch64_ext_limm): ...here.
730 (aarch64_ext_inv_limm): New function.
731 (decode_sve_aimm): Likewise.
732 (aarch64_ext_sve_aimm): Likewise.
733 (aarch64_ext_sve_asimm): Likewise.
734 (aarch64_ext_sve_limm_mov): Likewise.
735 (aarch64_top_bit): Likewise.
736 (aarch64_ext_sve_shlimm): Likewise.
737 (aarch64_ext_sve_shrimm): Likewise.
738 * aarch64-dis-2.c: Regenerate.
739
98907a70
RS		 7402016-09-21 Richard Sandiford <richard.sandiford@arm.com>
741
742 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
743 operands.
744 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
745 the AARCH64_MOD_MUL_VL entry.
746 (value_aligned_p): Cope with non-power-of-two alignments.
747 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
748 (print_immediate_offset_address): Likewise.
749 (aarch64_print_operand): Likewise.
750 * aarch64-opc-2.c: Regenerate.
751 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
752 (ins_sve_addr_ri_s9xvl): New inserters.
753 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
754 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
755 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
756 * aarch64-asm-2.c: Regenerate.
757 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
758 (ext_sve_addr_ri_s9xvl): New extractors.
759 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
760 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
761 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
762 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
763 * aarch64-dis-2.c: Regenerate.
764
4df068de
RS		 7652016-09-21 Richard Sandiford <richard.sandiford@arm.com>
766
767 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
768 address operands.
769 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
770 (FLD_SVE_xs_22): New aarch64_field_kinds.
771 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
772 (get_operand_specific_data): New function.
773 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
774 FLD_SVE_xs_14 and FLD_SVE_xs_22.
775 (operand_general_constraint_met_p): Handle the new SVE address
776 operands.
777 (sve_reg): New array.
778 (get_addr_sve_reg_name): New function.
779 (aarch64_print_operand): Handle the new SVE address operands.
780 * aarch64-opc-2.c: Regenerate.
781 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
782 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
783 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
784 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
785 (aarch64_ins_sve_addr_rr_lsl): Likewise.
786 (aarch64_ins_sve_addr_rz_xtw): Likewise.
787 (aarch64_ins_sve_addr_zi_u5): Likewise.
788 (aarch64_ins_sve_addr_zz): Likewise.
789 (aarch64_ins_sve_addr_zz_lsl): Likewise.
790 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
791 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
792 * aarch64-asm-2.c: Regenerate.
793 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
794 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
795 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
796 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
797 (aarch64_ext_sve_addr_ri_u6): Likewise.
798 (aarch64_ext_sve_addr_rr_lsl): Likewise.
799 (aarch64_ext_sve_addr_rz_xtw): Likewise.
800 (aarch64_ext_sve_addr_zi_u5): Likewise.
801 (aarch64_ext_sve_addr_zz): Likewise.
802 (aarch64_ext_sve_addr_zz_lsl): Likewise.
803 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
804 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
805 * aarch64-dis-2.c: Regenerate.
806
2442d846
RS		 8072016-09-21 Richard Sandiford <richard.sandiford@arm.com>
808
809 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
810 AARCH64_OPND_SVE_PATTERN_SCALED.
811 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
812 * aarch64-opc.c (fields): Add a corresponding entry.
813 (set_multiplier_out_of_range_error): New function.
814 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
815 (operand_general_constraint_met_p): Handle
816 AARCH64_OPND_SVE_PATTERN_SCALED.
817 (print_register_offset_address): Use PRIi64 to print the
818 shift amount.
819 (aarch64_print_operand): Likewise. Handle
820 AARCH64_OPND_SVE_PATTERN_SCALED.
821 * aarch64-opc-2.c: Regenerate.
822 * aarch64-asm.h (ins_sve_scale): New inserter.
823 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
824 * aarch64-asm-2.c: Regenerate.
825 * aarch64-dis.h (ext_sve_scale): New inserter.
826 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
827 * aarch64-dis-2.c: Regenerate.
828
245d2e3f
RS		 8292016-09-21 Richard Sandiford <richard.sandiford@arm.com>
830
831 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
832 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
833 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
834 (FLD_SVE_prfop): Likewise.
835 * aarch64-opc.c: Include libiberty.h.
836 (aarch64_sve_pattern_array): New variable.
837 (aarch64_sve_prfop_array): Likewise.
838 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
839 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
840 AARCH64_OPND_SVE_PRFOP.
841 * aarch64-asm-2.c: Regenerate.
842 * aarch64-dis-2.c: Likewise.
843 * aarch64-opc-2.c: Likewise.
844
d50c751e
RS		 8452016-09-21 Richard Sandiford <richard.sandiford@arm.com>
846
847 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
848 AARCH64_OPND_QLF_P_[ZM].
849 (aarch64_print_operand): Print /z and /m where appropriate.
850
f11ad6bc
RS		 8512016-09-21 Richard Sandiford <richard.sandiford@arm.com>
852
853 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
854 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
855 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
856 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
857 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
858 * aarch64-opc.c (fields): Add corresponding entries here.
859 (operand_general_constraint_met_p): Check that SVE register lists
860 have the correct length. Check the ranges of SVE index registers.
861 Check for cases where p8-p15 are used in 3-bit predicate fields.
862 (aarch64_print_operand): Handle the new SVE operands.
863 * aarch64-opc-2.c: Regenerate.
864 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
865 * aarch64-asm.c (aarch64_ins_sve_index): New function.
866 (aarch64_ins_sve_reglist): Likewise.
867 * aarch64-asm-2.c: Regenerate.
868 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
869 * aarch64-dis.c (aarch64_ext_sve_index): New function.
870 (aarch64_ext_sve_reglist): Likewise.
871 * aarch64-dis-2.c: Regenerate.
872
0c608d6b
RS		 8732016-09-21 Richard Sandiford <richard.sandiford@arm.com>
874
875 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
876 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
877 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
878 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
879 tied operands.
880
01dbfe4c
RS		 8812016-09-21 Richard Sandiford <richard.sandiford@arm.com>
882
883 * aarch64-opc.c (get_offset_int_reg_name): New function.
884 (print_immediate_offset_address): Likewise.
885 (print_register_offset_address): Take the base and offset
886 registers as parameters.
887 (aarch64_print_operand): Update caller accordingly. Use
888 print_immediate_offset_address.
889
72e9f319
RS		 8902016-09-21 Richard Sandiford <richard.sandiford@arm.com>
891
892 * aarch64-opc.c (BANK): New macro.
893 (R32, R64): Take a register number as argument
894 (int_reg): Use BANK.
895
8a7f0c1b
RS		 8962016-09-21 Richard Sandiford <richard.sandiford@arm.com>
897
898 * aarch64-opc.c (print_register_list): Add a prefix parameter.
899 (aarch64_print_operand): Update accordingly.
900
aa2aa4c6
RS		 9012016-09-21 Richard Sandiford <richard.sandiford@arm.com>
902
903 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
904 for FPIMM.
905 * aarch64-asm.h (ins_fpimm): New inserter.
906 * aarch64-asm.c (aarch64_ins_fpimm): New function.
907 * aarch64-asm-2.c: Regenerate.
908 * aarch64-dis.h (ext_fpimm): New extractor.
909 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
910 (aarch64_ext_fpimm): New function.
911 * aarch64-dis-2.c: Regenerate.
912
b5464a68
RS		 9132016-09-21 Richard Sandiford <richard.sandiford@arm.com>
914
915 * aarch64-asm.c: Include libiberty.h.
916 (insert_fields): New function.
917 (aarch64_ins_imm): Use it.
918 * aarch64-dis.c (extract_fields): New function.
919 (aarch64_ext_imm): Use it.
920
42408347
RS		 9212016-09-21 Richard Sandiford <richard.sandiford@arm.com>
922
923 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
924 with an esize parameter.
925 (operand_general_constraint_met_p): Update accordingly.
926 Fix misindented code.
927 * aarch64-asm.c (aarch64_ins_limm): Update call to
928 aarch64_logical_immediate_p.
929
4989adac
RS		 9302016-09-21 Richard Sandiford <richard.sandiford@arm.com>
931
932 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
933
bd11d5d8
RS		 9342016-09-21 Richard Sandiford <richard.sandiford@arm.com>
935
936 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
937
f807f43d
CZ		 9382016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
939
940 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
941
fd486b63
PB		 9422016-09-14 Peter Bergner <bergner@vnet.ibm.com>
943
944 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
945 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
946 xor3>: Delete mnemonics.
947 <cp_abort>: Rename mnemonic from ...
948 <cpabort>: ...to this.
949 <setb>: Change to a X form instruction.
950 <sync>: Change to 1 operand form.
951 <copy>: Delete mnemonic.
952 <copy_first>: Rename mnemonic from ...
953 <copy>: ...to this.
954 <paste, paste.>: Delete mnemonics.
955 <paste_last>: Rename mnemonic from ...
956 <paste.>: ...to this.
957
dce08442
AK		 9582016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
959
960 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
961
952c3f51
AK		 9622016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
963
964 * s390-mkopc.c (main): Support alternate arch strings.
965
8b71537b
PS		 9662016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
967
968 * s390-opc.txt: Fix kmctr instruction type.
969
5b64d091
L		 9702016-09-07 H.J. Lu <hongjiu.lu@intel.com>
971
972 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
973 * i386-init.h: Regenerated.
974
7763838e
CM		 9752016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
976
977 * opcodes/arc-dis.c (print_insn_arc): Changed.
978
1b8b6532
JM		 9792016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
980
981 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
982 camellia_fl.
983
1a336194
TP		 9842016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
985
986 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
987 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
988 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
989
6b40c462
L		 9902016-08-24 H.J. Lu <hongjiu.lu@intel.com>
991
992 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
993 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
994 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
995 PREFIX_MOD_3_0FAE_REG_4.
996 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
997 PREFIX_MOD_3_0FAE_REG_4.
998 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
999 (cpu_flags): Add CpuPTWRITE.
1000 * i386-opc.h (CpuPTWRITE): New.
1001 (i386_cpu_flags): Add cpuptwrite.
1002 * i386-opc.tbl: Add ptwrite instruction.
1003 * i386-init.h: Regenerated.
1004 * i386-tbl.h: Likewise.
1005
ab548d2d
AK		 10062016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
1007
1008 * arc-dis.h: Wrap around in extern "C".
1009
344bde0a
RS		 10102016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1011
1012 * aarch64-tbl.h (V8_2_INSN): New macro.
1013 (aarch64_opcode_table): Use it.
1014
5ce912d8
RS		 10152016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1016
1017 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
1018 CORE_INSN, __FP_INSN and SIMD_INSN.
1019
9d30b0bd
RS		 10202016-08-23 Richard Sandiford <richard.sandiford@arm.com>
1021
1022 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
1023 (aarch64_opcode_table): Update uses accordingly.
1024
dfdaec14
AJ		 10252016-07-25 Andrew Jenner <andrew@codesourcery.com>
1026 Kwok Cheung Yeung <kcy@codesourcery.com>
1027
1028 opcodes/
1029 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
1030 'e_cmplwi' to 'e_cmpli' instead.
1031 (OPVUPRT, OPVUPRT_MASK): Define.
1032 (powerpc_opcodes): Add E200Z4 insns.
1033 (vle_opcodes): Add context save/restore insns.
1034
7bd374a4
MR		 10352016-07-27 Maciej W. Rozycki <macro@imgtec.com>
1036
1037 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
1038 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
1039 "j".
1040
db18dbab
GM		 10412016-07-27 Graham Markall <graham.markall@embecosm.com>
1042
1043 * arc-nps400-tbl.h: Change block comments to GNU format.
1044 * arc-dis.c: Add new globals addrtypenames,
1045 addrtypenames_max, and addtypeunknown.
1046 (get_addrtype): New function.
1047 (print_insn_arc): Print colons and address types when
1048 required.
1049 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1050 define insert and extract functions for all address types.
1051 (arc_operands): Add operands for colon and all address
1052 types.
1053 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1054 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1055 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1056 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1057 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1058 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1059
fecd57f9
L		 10602016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1061
1062 * configure: Regenerated.
1063
37fd5ef3
CZ		 10642016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1065
1066 * arc-dis.c (skipclass): New structure.
1067 (decodelist): New variable.
1068 (is_compatible_p): New function.
1069 (new_element): Likewise.
1070 (skip_class_p): Likewise.
1071 (find_format_from_table): Use skip_class_p function.
1072 (find_format): Decode first the extension instructions.
1073 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1074 e_flags.
1075 (parse_option): New function.
1076 (parse_disassembler_options): Likewise.
1077 (print_arc_disassembler_options): Likewise.
1078 (print_insn_arc): Use parse_disassembler_options function. Proper
1079 select ARCv2 cpu variant.
1080 * disassemble.c (disassembler_usage): Add ARC disassembler
1081 options.
1082
92281a5b
MR		 10832016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1084
1085 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1086 annotation from the "nal" entry and reorder it beyond "bltzal".
1087
6e7ced37
JM		 10882016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1089
1090 * sparc-opc.c (ldtxa): New macro.
1091 (sparc_opcodes): Use the macro defined above to add entries for
1092 the LDTXA instructions.
1093 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1094 instruction.
1095
2f831b9a 10962016-07-07 James Bowman <james.bowman@ftdichip.com>
1097
1098 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1099 and "jmpc".
1100
c07315e0
JB		 11012016-07-01 Jan Beulich <jbeulich@suse.com>
1102
1103 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1104 (movzb): Adjust to cover all permitted suffixes.
1105 (movzw): New.
1106 * i386-tbl.h: Re-generate.
1107
9243100a
JB		 11082016-07-01 Jan Beulich <jbeulich@suse.com>
1109
1110 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1111 (lgdt): Remove Tbyte from non-64-bit variant.
1112 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1113 xsaves64, xsavec64): Remove Disp16.
1114 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1115 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1116 64-bit variants.
1117 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1118 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1119 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1120 64-bit variants.
1121 * i386-tbl.h: Re-generate.
1122
8325cc63
JB		 11232016-07-01 Jan Beulich <jbeulich@suse.com>
1124
1125 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1126 * i386-tbl.h: Re-generate.
1127
838441e4
YQ		 11282016-06-30 Yao Qi <yao.qi@linaro.org>
1129
1130 * arm-dis.c (print_insn): Fix typo in comment.
1131
dab26bf4
RS		 11322016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1133
1134 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1135 range of ldst_elemlist operands.
1136 (print_register_list): Use PRIi64 to print the index.
1137 (aarch64_print_operand): Likewise.
1138
5703197e
TS		 11392016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1140
1141 * mcore-opc.h: Remove sentinal.
1142 * mcore-dis.c (print_insn_mcore): Adjust.
1143
ce440d63
GM		 11442016-06-23 Graham Markall <graham.markall@embecosm.com>
1145
1146 * arc-opc.c: Correct description of availability of NPS400
1147 features.
1148
6fd3a02d
PB		 11492016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1150
1151 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1152 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1153 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1154 xor3>: New mnemonics.
1155 <setb>: Change to a VX form instruction.
1156 (insert_sh6): Add support for rldixor.
1157 (extract_sh6): Likewise.
1158
6b477896
TS		 11592016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1160
1161 * arc-ext.h: Wrap in extern C.
1162
bdd582db
GM		 11632016-06-21 Graham Markall <graham.markall@embecosm.com>
1164
1165 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1166 Use same method for determining instruction length on ARC700 and
1167 NPS-400.
1168 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1169 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1170 with the NPS400 subclass.
1171 * arc-opc.c: Likewise.
1172
96074adc
JM		 11732016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1174
1175 * sparc-opc.c (rdasr): New macro.
1176 (wrasr): Likewise.
1177 (rdpr): Likewise.
1178 (wrpr): Likewise.
1179 (rdhpr): Likewise.
1180 (wrhpr): Likewise.
1181 (sparc_opcodes): Use the macros above to fix and expand the
1182 definition of read/write instructions from/to
1183 asr/privileged/hyperprivileged instructions.
1184 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1185 %hva_mask_nz. Prefer softint_set and softint_clear over
1186 set_softint and clear_softint.
1187 (print_insn_sparc): Support %ver in Rd.
1188
7a10c22f
JM		 11892016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1190
1191 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1192 architecture according to the hardware capabilities they require.
1193
4f26fb3a
JM		 11942016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1195
1196 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1197 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1198 bfd_mach_sparc_v9{c,d,e,v,m}.
1199 * sparc-opc.c (MASK_V9C): Define.
1200 (MASK_V9D): Likewise.
1201 (MASK_V9E): Likewise.
1202 (MASK_V9V): Likewise.
1203 (MASK_V9M): Likewise.
1204 (v6): Add MASK_V9{C,D,E,V,M}.
1205 (v6notlet): Likewise.
1206 (v7): Likewise.
1207 (v8): Likewise.
1208 (v9): Likewise.
1209 (v9andleon): Likewise.
1210 (v9a): Likewise.
1211 (v9b): Likewise.
1212 (v9c): Define.
1213 (v9d): Likewise.
1214 (v9e): Likewise.
1215 (v9v): Likewise.
1216 (v9m): Likewise.
1217 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1218
3ee6e4fb
NC		 12192016-06-15 Nick Clifton <nickc@redhat.com>
1220
1221 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1222 constants to match expected behaviour.
1223 (nds32_parse_opcode): Likewise. Also for whitespace.
1224
02f3be19
AB		 12252016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1226
1227 * arc-opc.c (extract_rhv1): Extract value from insn.
1228
6f9f37ed 12292016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 1230
1231 * arc-nps400-tbl.h: Add ldbit instruction.
1232 * arc-opc.c: Add flag classes required for ldbit.
1233
6f9f37ed 12342016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 1235
1236 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1237 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1238 support the above instructions.
1239
6f9f37ed 12402016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 1241
1242 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1243 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1244 csma, cbba, zncv, and hofs.
1245 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1246 support the above instructions.
1247
12482016-06-06 Graham Markall <graham.markall@embecosm.com>
1249
1250 * arc-nps400-tbl.h: Add andab and orab instructions.
1251
12522016-06-06 Graham Markall <graham.markall@embecosm.com>
1253
1254 * arc-nps400-tbl.h: Add addl-like instructions.
1255
12562016-06-06 Graham Markall <graham.markall@embecosm.com>
1257
1258 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1259
12602016-06-06 Graham Markall <graham.markall@embecosm.com>
1261
1262 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1263 instructions.
1264
b2cc3f6f
AK		 12652016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1266
1267 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1268 variable.
1269 (init_disasm): Handle new command line option "insnlength".
1270 (print_s390_disassembler_options): Mention new option in help
1271 output.
1272 (print_insn_s390): Use the encoded insn length when dumping
1273 unknown instructions.
1274
1857fe72
DC		 12752016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1276
1277 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1278 to the address and set as symbol address for LDS/ STS immediate operands.
1279
14b57c7c
AM		 12802016-06-07 Alan Modra <amodra@gmail.com>
1281
1282 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1283 cpu for "vle" to e500.
1284 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1285 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1286 (PPCNONE): Delete, substitute throughout.
1287 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1288 except for major opcode 4 and 31.
1289 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1290
4d1464f2
MW		 12912016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1292
1293 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1294 ARM_EXT_RAS in relevant entries.
1295
026122a6
PB		 12962016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1297
1298 PR binutils/20196
1299 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1300 opcodes for E6500.
1301
07f5af7d
L		 13022016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1303
1304 PR binutis/18386
1305 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1306 (indir_v_mode): New.
1307 Add comments for '&'.
1308 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1309 (putop): Handle '&'.
1310 (intel_operand_size): Handle indir_v_mode.
1311 (OP_E_register): Likewise.
1312 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1313 64-bit indirect call/jmp for AMD64.
1314 * i386-tbl.h: Regenerated
1315
4eb6f892
AB		 13162016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1317
1318 * arc-dis.c (struct arc_operand_iterator): New structure.
1319 (find_format_from_table): All the old content from find_format,
1320 with some minor adjustments, and parameter renaming.
1321 (find_format_long_instructions): New function.
1322 (find_format): Rewritten.
1323 (arc_insn_length): Add LSB parameter.
1324 (extract_operand_value): New function.
1325 (operand_iterator_next): New function.
1326 (print_insn_arc): Use new functions to find opcode, and iterator
1327 over operands.
1328 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1329 (extract_nps_3bit_dst_short): New function.
1330 (insert_nps_3bit_src2_short): New function.
1331 (extract_nps_3bit_src2_short): New function.
1332 (insert_nps_bitop1_size): New function.
1333 (extract_nps_bitop1_size): New function.
1334 (insert_nps_bitop2_size): New function.
1335 (extract_nps_bitop2_size): New function.
1336 (insert_nps_bitop_mod4_msb): New function.
1337 (extract_nps_bitop_mod4_msb): New function.
1338 (insert_nps_bitop_mod4_lsb): New function.
1339 (extract_nps_bitop_mod4_lsb): New function.
1340 (insert_nps_bitop_dst_pos3_pos4): New function.
1341 (extract_nps_bitop_dst_pos3_pos4): New function.
1342 (insert_nps_bitop_ins_ext): New function.
1343 (extract_nps_bitop_ins_ext): New function.
1344 (arc_operands): Add new operands.
1345 (arc_long_opcodes): New global array.
1346 (arc_num_long_opcodes): New global.
1347 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1348
1fe0971e
TS		 13492016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1350
1351 * nds32-asm.h: Add extern "C".
1352 * sh-opc.h: Likewise.
1353
315f180f
GM		 13542016-06-01 Graham Markall <graham.markall@embecosm.com>
1355
1356 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1357 0,b,limm to the rflt instruction.
1358
a2b5fccc
TS		 13592016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1360
1361 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1362 constant.
1363
0cbd0046
L		 13642016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1365
1366 PR gas/20145
1367 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1368 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1369 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1370 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1371 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1372 * i386-init.h: Regenerated.
1373
1848e567
L		 13742016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1375
1376 PR gas/20145
1377 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1378 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1379 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1380 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1381 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1382 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1383 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1384 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1385 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1386 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1387 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1388 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1389 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1390 CpuRegMask for AVX512.
1391 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1392 and CpuRegMask.
1393 (set_bitfield_from_cpu_flag_init): New function.
1394 (set_bitfield): Remove const on f. Call
1395 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1396 * i386-opc.h (CpuRegMMX): New.
1397 (CpuRegXMM): Likewise.
1398 (CpuRegYMM): Likewise.
1399 (CpuRegZMM): Likewise.
1400 (CpuRegMask): Likewise.
1401 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1402 and cpuregmask.
1403 * i386-init.h: Regenerated.
1404 * i386-tbl.h: Likewise.
1405
e92bae62
L		 14062016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1407
1408 PR gas/20154
1409 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1410 (opcode_modifiers): Add AMD64 and Intel64.
1411 (main): Properly verify CpuMax.
1412 * i386-opc.h (CpuAMD64): Removed.
1413 (CpuIntel64): Likewise.
1414 (CpuMax): Set to CpuNo64.
1415 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1416 (AMD64): New.
1417 (Intel64): Likewise.
1418 (i386_opcode_modifier): Add amd64 and intel64.
1419 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1420 on call and jmp.
1421 * i386-init.h: Regenerated.
1422 * i386-tbl.h: Likewise.
1423
e89c5eaa
L		 14242016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1425
1426 PR gas/20154
1427 * i386-gen.c (main): Fail if CpuMax is incorrect.
1428 * i386-opc.h (CpuMax): Set to CpuIntel64.
1429 * i386-tbl.h: Regenerated.
1430
77d66e7b
NC		 14312016-05-27 Nick Clifton <nickc@redhat.com>
1432
1433 PR target/20150
1434 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1435 (msp430dis_opcode_unsigned): New function.
1436 (msp430dis_opcode_signed): New function.
1437 (msp430_singleoperand): Use the new opcode reading functions.
1438 Only disassenmble bytes if they were successfully read.
1439 (msp430_doubleoperand): Likewise.
1440 (msp430_branchinstr): Likewise.
1441 (msp430x_callx_instr): Likewise.
1442 (print_insn_msp430): Check that it is safe to read bytes before
1443 attempting disassembly. Use the new opcode reading functions.
1444
19dfcc89
PB		 14452016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1446
1447 * ppc-opc.c (CY): New define. Document it.
1448 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1449
f3ad7637
L		 14502016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1451
1452 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1453 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1454 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1455 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1456 CPU_ANY_AVX_FLAGS.
1457 * i386-init.h: Regenerated.
1458
f1360d58
L		 14592016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1460
1461 PR gas/20141
1462 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1463 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1464 * i386-init.h: Regenerated.
1465
293f5f65
L		 14662016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1467
1468 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1469 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1470 * i386-init.h: Regenerated.
1471
d9eca1df
CZ		 14722016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1473
1474 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1475 information.
1476 (print_insn_arc): Set insn_type information.
1477 * arc-opc.c (C_CC): Add F_CLASS_COND.
1478 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1479 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1480 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1481 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1482 (brne, brne_s, jeq_s, jne_s): Likewise.
1483
87789e08
CZ		 14842016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1485
1486 * arc-tbl.h (neg): New instruction variant.
1487
c810e0b8
CZ		 14882016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1489
1490 * arc-dis.c (find_format, find_format, get_auxreg)
1491 (print_insn_arc): Changed.
1492 * arc-ext.h (INSERT_XOP): Likewise.
1493
3d207518
TS		 14942016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1495
1496 * tic54x-dis.c (sprint_mmr): Adjust.
1497 * tic54x-opc.c: Likewise.
1498
514e58b7
AM		 14992016-05-19 Alan Modra <amodra@gmail.com>
1500
1501 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1502
e43de63c
AM		 15032016-05-19 Alan Modra <amodra@gmail.com>
1504
1505 * ppc-opc.c: Formatting.
1506 (NSISIGNOPT): Define.
1507 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1508
1401d2fe
MR		 15092016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1510
1511 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1512 replacing references to `micromips_ase' throughout.
1513 (_print_insn_mips): Don't use file-level microMIPS annotation to
1514 determine the disassembly mode with the symbol table.
1515
1178da44
PB		 15162016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1517
1518 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1519
8f4f9071
MF		 15202016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1521
1522 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1523 mips64r6.
1524 * mips-opc.c (D34): New macro.
1525 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1526
8bc52696
AF		 15272016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1528
1529 * i386-dis.c (prefix_table): Add RDPID instruction.
1530 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1531 (cpu_flags): Add RDPID bitfield.
1532 * i386-opc.h (enum): Add RDPID element.
1533 (i386_cpu_flags): Add RDPID field.
1534 * i386-opc.tbl: Add RDPID instruction.
1535 * i386-init.h: Regenerate.
1536 * i386-tbl.h: Regenerate.
1537
39d911fc
TP		 15382016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1539
1540 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1541 branch type of a symbol.
1542 (print_insn): Likewise.
1543
16a1fa25
TP		 15442016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1545
1546 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1547 Mainline Security Extensions instructions.
1548 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1549 Extensions instructions.
1550 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1551 instructions.
1552 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1553 special registers.
1554
d751b79e
JM		 15552016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1556
1557 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1558
945e0f82
CZ		 15592016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1560
1561 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1562 (arcExtMap_genOpcode): Likewise.
1563 * arc-opc.c (arg_32bit_rc): Define new variable.
1564 (arg_32bit_u6): Likewise.
1565 (arg_32bit_limm): Likewise.
1566
20f55f38
SN		 15672016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1568
1569 * aarch64-gen.c (VERIFIER): Define.
1570 * aarch64-opc.c (VERIFIER): Define.
1571 (verify_ldpsw): Use static linkage.
1572 * aarch64-opc.h (verify_ldpsw): Remove.
1573 * aarch64-tbl.h: Use VERIFIER for verifiers.
1574
4bd13cde
NC		 15752016-04-28 Nick Clifton <nickc@redhat.com>
1576
1577 PR target/19722
1578 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1579 * aarch64-opc.c (verify_ldpsw): New function.
1580 * aarch64-opc.h (verify_ldpsw): New prototype.
1581 * aarch64-tbl.h: Add initialiser for verifier field.
1582 (LDPSW): Set verifier to verify_ldpsw.
1583
c0f92bf9
L		 15842016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1585
1586 PR binutils/19983
1587 PR binutils/19984
1588 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1589 smaller than address size.
1590
e6c7cdec
TS		 15912016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1592
1593 * alpha-dis.c: Regenerate.
1594 * crx-dis.c: Likewise.
1595 * disassemble.c: Likewise.
1596 * epiphany-opc.c: Likewise.
1597 * fr30-opc.c: Likewise.
1598 * frv-opc.c: Likewise.
1599 * ip2k-opc.c: Likewise.
1600 * iq2000-opc.c: Likewise.
1601 * lm32-opc.c: Likewise.
1602 * lm32-opinst.c: Likewise.
1603 * m32c-opc.c: Likewise.
1604 * m32r-opc.c: Likewise.
1605 * m32r-opinst.c: Likewise.
1606 * mep-opc.c: Likewise.
1607 * mt-opc.c: Likewise.
1608 * or1k-opc.c: Likewise.
1609 * or1k-opinst.c: Likewise.
1610 * tic80-opc.c: Likewise.
1611 * xc16x-opc.c: Likewise.
1612 * xstormy16-opc.c: Likewise.
1613
537aefaf
AB		 16142016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1615
1616 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1617 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1618 calcsd, and calcxd instructions.
1619 * arc-opc.c (insert_nps_bitop_size): Delete.
1620 (extract_nps_bitop_size): Delete.
1621 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1622 (extract_nps_qcmp_m3): Define.
1623 (extract_nps_qcmp_m2): Define.
1624 (extract_nps_qcmp_m1): Define.
1625 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1626 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1627 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1628 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1629 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1630 NPS_QCMP_M3.
1631
c8f785f2
AB		 16322016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1633
1634 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1635
6fd8e7c2
L		 16362016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1637
1638 * Makefile.in: Regenerated with automake 1.11.6.
1639 * aclocal.m4: Likewise.
1640
4b0c052e
AB		 16412016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1642
1643 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1644 instructions.
1645 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1646 (extract_nps_cmem_uimm16): New function.
1647 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1648
cb040366
AB		 16492016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1650
1651 * arc-dis.c (arc_insn_length): New function.
1652 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1653 (find_format): Change insnLen parameter to unsigned.
1654
accc0180
NC		 16552016-04-13 Nick Clifton <nickc@redhat.com>
1656
1657 PR target/19937
1658 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1659 the LD.B and LD.BU instructions.
1660
f36e33da
CZ		 16612016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1662
1663 * arc-dis.c (find_format): Check for extension flags.
1664 (print_flags): New function.
1665 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1666 .extAuxRegister.
1667 * arc-ext.c (arcExtMap_coreRegName): Use
1668 LAST_EXTENSION_CORE_REGISTER.
1669 (arcExtMap_coreReadWrite): Likewise.
1670 (dump_ARC_extmap): Update printing.
1671 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1672 (arc_aux_regs): Add cpu field.
1673 * arc-regs.h: Add cpu field, lower case name aux registers.
1674
1c2e355e
CZ		 16752016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1676
1677 * arc-tbl.h: Add rtsc, sleep with no arguments.
1678
b99747ae
CZ		 16792016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1680
1681 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1682 Initialize.
1683 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1684 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1685 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1686 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1687 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1688 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1689 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1690 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1691 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1692 (arc_opcode arc_opcodes): Null terminate the array.
1693 (arc_num_opcodes): Remove.
1694 * arc-ext.h (INSERT_XOP): Define.
1695 (extInstruction_t): Likewise.
1696 (arcExtMap_instName): Delete.
1697 (arcExtMap_insn): New function.
1698 (arcExtMap_genOpcode): Likewise.
1699 * arc-ext.c (ExtInstruction): Remove.
1700 (create_map): Zero initialize instruction fields.
1701 (arcExtMap_instName): Remove.
1702 (arcExtMap_insn): New function.
1703 (dump_ARC_extmap): More info while debuging.
1704 (arcExtMap_genOpcode): New function.
1705 * arc-dis.c (find_format): New function.
1706 (print_insn_arc): Use find_format.
1707 (arc_get_disassembler): Enable dump_ARC_extmap only when
1708 debugging.
1709
92708cec
MR		 17102016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1711
1712 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1713 instruction bits out.
1714
a42a4f84
AB		 17152016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1716
1717 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1718 * arc-opc.c (arc_flag_operands): Add new flags.
1719 (arc_flag_classes): Add new classes.
1720
1328504b
AB		 17212016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1722
1723 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1724
820f03ff
AB		 17252016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1726
1727 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1728 encode1, rflt, crc16, and crc32 instructions.
1729 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1730 (arc_flag_classes): Add C_NPS_R.
1731 (insert_nps_bitop_size_2b): New function.
1732 (extract_nps_bitop_size_2b): Likewise.
1733 (insert_nps_bitop_uimm8): Likewise.
1734 (extract_nps_bitop_uimm8): Likewise.
1735 (arc_operands): Add new operand entries.
1736
8ddf6b2a
CZ		 17372016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1738
b99747ae
CZ		 1739 * arc-regs.h: Add a new subclass field. Add double assist
1740 accumulator register values.
1741 * arc-tbl.h: Use DPA subclass to mark the double assist
1742 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1743 * arc-opc.c (RSP): Define instead of SP.
1744 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1745
589a7d88
JW		 17462016-04-05 Jiong Wang <jiong.wang@arm.com>
1747
1748 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1749
0a191de9 17502016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1751
1752 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1753 NPS_R_SRC1.
1754
0a106562
AB		 17552016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1756
1757 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1758 issues. No functional changes.
1759
bd05ac5f
CZ		 17602016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1761
b99747ae
CZ		 1762 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1763 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1764 (RTT): Remove duplicate.
1765 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1766 (PCT_CONFIG*): Remove.
1767 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1768
9885948f
CZ		 17692016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1770
b99747ae 1771 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1772
f2dd8838
CZ		 17732016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1774
b99747ae
CZ		 1775 * arc-tbl.h (invld07): Remove.
1776 * arc-ext-tbl.h: New file.
1777 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1778 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1779
0d2f91fe
JK		 17802016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1781
1782 Fix -Wstack-usage warnings.
1783 * aarch64-dis.c (print_operands): Substitute size.
1784 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1785
a6b71f42
JM		 17862016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1787
1788 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1789 to get a proper diagnostic when an invalid ASR register is used.
1790
9780e045
NC		 17912016-03-22 Nick Clifton <nickc@redhat.com>
1792
1793 * configure: Regenerate.
1794
e23e8ebe
AB		 17952016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1796
1797 * arc-nps400-tbl.h: New file.
1798 * arc-opc.c: Add top level comment.
1799 (insert_nps_3bit_dst): New function.
1800 (extract_nps_3bit_dst): New function.
1801 (insert_nps_3bit_src2): New function.
1802 (extract_nps_3bit_src2): New function.
1803 (insert_nps_bitop_size): New function.
1804 (extract_nps_bitop_size): New function.
1805 (arc_flag_operands): Add nps400 entries.
1806 (arc_flag_classes): Add nps400 entries.
1807 (arc_operands): Add nps400 entries.
1808 (arc_opcodes): Add nps400 include.
1809
1ae8ab47
AB		 18102016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1811
1812 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1813 the new class enum values.
1814
8699fc3e
AB		 18152016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1816
1817 * arc-dis.c (print_insn_arc): Handle nps400.
1818
24740d83
AB		 18192016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1820
1821 * arc-opc.c (BASE): Delete.
1822
8678914f
NC		 18232016-03-18 Nick Clifton <nickc@redhat.com>
1824
1825 PR target/19721
1826 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1827 of MOV insn that aliases an ORR insn.
1828
cc933301
JW		 18292016-03-16 Jiong Wang <jiong.wang@arm.com>
1830
1831 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1832
f86f5863
TS		 18332016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1834
1835 * mcore-opc.h: Add const qualifiers.
1836 * microblaze-opc.h (struct op_code_struct): Likewise.
1837 * sh-opc.h: Likewise.
1838 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1839 (tic4x_print_op): Likewise.
1840
62de1c63
AM		 18412016-03-02 Alan Modra <amodra@gmail.com>
1842
d11698cd 1843 * or1k-desc.h: Regenerate.
62de1c63 1844 * fr30-ibld.c: Regenerate.
c697cf0b 1845 * rl78-decode.c: Regenerate.
62de1c63 1846
020efce5
NC		 18472016-03-01 Nick Clifton <nickc@redhat.com>
1848
1849 PR target/19747
1850 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1851
b0c11777
RL		 18522016-02-24 Renlin Li <renlin.li@arm.com>
1853
1854 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1855 (print_insn_coprocessor): Support fp16 instructions.
1856
3e309328
RL		 18572016-02-24 Renlin Li <renlin.li@arm.com>
1858
1859 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1860 vminnm, vrint(mpna).
1861
8afc7bea
RL		 18622016-02-24 Renlin Li <renlin.li@arm.com>
1863
1864 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1865 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1866
4fd7268a
L		 18672016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1868
1869 * i386-dis.c (print_insn): Parenthesize expression to prevent
1870 truncated addresses.
1871 (OP_J): Likewise.
1872
4670103e
CZ		 18732016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1874 Janek van Oirschot <jvanoirs@synopsys.com>
1875
b99747ae
CZ		 1876 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1877 variable.
4670103e 1878
c1d9289f
NC		 18792016-02-04 Nick Clifton <nickc@redhat.com>
1880
1881 PR target/19561
1882 * msp430-dis.c (print_insn_msp430): Add a special case for
1883 decoding an RRC instruction with the ZC bit set in the extension
1884 word.
1885
a143b004
AB		 18862016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1887
1888 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1889 * epiphany-ibld.c: Regenerate.
1890 * fr30-ibld.c: Regenerate.
1891 * frv-ibld.c: Regenerate.
1892 * ip2k-ibld.c: Regenerate.
1893 * iq2000-ibld.c: Regenerate.
1894 * lm32-ibld.c: Regenerate.
1895 * m32c-ibld.c: Regenerate.
1896 * m32r-ibld.c: Regenerate.
1897 * mep-ibld.c: Regenerate.
1898 * mt-ibld.c: Regenerate.
1899 * or1k-ibld.c: Regenerate.
1900 * xc16x-ibld.c: Regenerate.
1901 * xstormy16-ibld.c: Regenerate.
1902
b89807c6
AB		 19032016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1904
1905 * epiphany-dis.c: Regenerated from latest cpu files.
1906
d8c823c8
MM		 19072016-02-01 Michael McConville <mmcco@mykolab.com>
1908
1909 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1910 test bit.
1911
5bc5ae88
RL		 19122016-01-25 Renlin Li <renlin.li@arm.com>
1913
1914 * arm-dis.c (mapping_symbol_for_insn): New function.
1915 (find_ifthen_state): Call mapping_symbol_for_insn().
1916
0bff6e2d
MW		 19172016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1918
1919 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1920 of MSR UAO immediate operand.
1921
100b4f2e
MR		 19222016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1923
1924 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1925 instruction support.
1926
5c14705f
AM		 19272016-01-17 Alan Modra <amodra@gmail.com>
1928
1929 * configure: Regenerate.
1930
4d82fe66
NC		 19312016-01-14 Nick Clifton <nickc@redhat.com>
1932
1933 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1934 instructions that can support stack pointer operations.
1935 * rl78-decode.c: Regenerate.
1936 * rl78-dis.c: Fix display of stack pointer in MOVW based
1937 instructions.
1938
651657fa
MW		 19392016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1940
1941 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1942 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1943 erxtatus_el1 and erxaddr_el1.
1944
105bde57
MW		 19452016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1946
1947 * arm-dis.c (arm_opcodes): Add "esb".
1948 (thumb_opcodes): Likewise.
1949
afa8d405
PB		 19502016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1951
1952 * ppc-opc.c <xscmpnedp>: Delete.
1953 <xvcmpnedp>: Likewise.
1954 <xvcmpnedp.>: Likewise.
1955 <xvcmpnesp>: Likewise.
1956 <xvcmpnesp.>: Likewise.
1957
83c3256e
AS		 19582016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1959
1960 PR gas/13050
1961 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1962 addition to ISA_A.
1963
6f2750fe
AM		 19642016-01-01 Alan Modra <amodra@gmail.com>
1965
1966 Update year range in copyright notice of all files.
1967
3499769a
AM		 1968For older changes see ChangeLog-2015
1969\f
1970Copyright (C) 2016 Free Software Foundation, Inc.
1971
1972Copying and distribution of this file, with or without modification,
1973are permitted in any medium without royalty provided the copyright
1974notice and this notice are preserved.
1975
1976Local Variables:
1977mode: change-log
1978left-margin: 8
1979fill-column: 74
1980version-control: never
1981End:
GDB Binutils - Deliverables
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