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aarch64: Fix MOVPRFX markup for bf16 conversions
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
c3036ed0
RS		 12020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2
3 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
4 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
5
0c115f84
AM		 62020-01-30 Alan Modra <amodra@gmail.com>
7
8 * m32c-ibld.c: Regenerate.
9
bd434cc4
JM		 102020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
11
12 * bpf-opc.c: Regenerate.
13
aeab2b26
JB		 142020-01-30 Jan Beulich <jbeulich@suse.com>
15
16 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
17 (dis386): Use them to replace C2/C3 table entries.
18 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
19 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
20 ones. Use Size64 instead of DefaultSize on Intel64 ones.
21 * i386-tbl.h: Re-generate.
22
62b3f548
JB		 232020-01-30 Jan Beulich <jbeulich@suse.com>
24
25 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
26 forms.
27 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
28 DefaultSize.
29 * i386-tbl.h: Re-generate.
30
1bd8ae10
AM		 312020-01-30 Alan Modra <amodra@gmail.com>
32
33 * tic4x-dis.c (tic4x_dp): Make unsigned.
34
bc31405e
L		 352020-01-27 H.J. Lu <hongjiu.lu@intel.com>
36 Jan Beulich <jbeulich@suse.com>
37
38 PR binutils/25445
39 * i386-dis.c (MOVSXD_Fixup): New function.
40 (movsxd_mode): New enum.
41 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
42 (intel_operand_size): Handle movsxd_mode.
43 (OP_E_register): Likewise.
44 (OP_G): Likewise.
45 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
46 register on movsxd. Add movsxd with 16-bit destination register
47 for AMD64 and Intel64 ISAs.
48 * i386-tbl.h: Regenerated.
49
7568c93b
TC		 502020-01-27 Tamar Christina <tamar.christina@arm.com>
51
52 PR 25403
53 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
54 * aarch64-asm-2.c: Regenerate
55 * aarch64-dis-2.c: Likewise.
56 * aarch64-opc-2.c: Likewise.
57
c006a730
JB		 582020-01-21 Jan Beulich <jbeulich@suse.com>
59
60 * i386-opc.tbl (sysret): Drop DefaultSize.
61 * i386-tbl.h: Re-generate.
62
c906a69a
JB		 632020-01-21 Jan Beulich <jbeulich@suse.com>
64
65 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
66 Dword.
67 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
68 * i386-tbl.h: Re-generate.
69
26916852
NC		 702020-01-20 Nick Clifton <nickc@redhat.com>
71
72 * po/de.po: Updated German translation.
73 * po/pt_BR.po: Updated Brazilian Portuguese translation.
74 * po/uk.po: Updated Ukranian translation.
75
4d6cbb64
AM		 762020-01-20 Alan Modra <amodra@gmail.com>
77
78 * hppa-dis.c (fput_const): Remove useless cast.
79
2bddb71a
AM		 802020-01-20 Alan Modra <amodra@gmail.com>
81
82 * arm-dis.c (print_insn_arm): Wrap 'T' value.
83
1b1bb2c6
NC		 842020-01-18 Nick Clifton <nickc@redhat.com>
85
86 * configure: Regenerate.
87 * po/opcodes.pot: Regenerate.
88
ae774686
NC		 892020-01-18 Nick Clifton <nickc@redhat.com>
90
91 Binutils 2.34 branch created.
92
07f1f3aa
CB		 932020-01-17 Christian Biesinger <cbiesinger@google.com>
94
95 * opintl.h: Fix spelling error (seperate).
96
42e04b36
L		 972020-01-17 H.J. Lu <hongjiu.lu@intel.com>
98
99 * i386-opc.tbl: Add {vex} pseudo prefix.
100 * i386-tbl.h: Regenerated.
101
2da2eaf4
AV		 1022020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
103
104 PR 25376
105 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
106 (neon_opcodes): Likewise.
107 (select_arm_features): Make sure we enable MVE bits when selecting
108 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
109 any architecture.
110
d0849eed
JB		 1112020-01-16 Jan Beulich <jbeulich@suse.com>
112
113 * i386-opc.tbl: Drop stale comment from XOP section.
114
9cf70a44
JB		 1152020-01-16 Jan Beulich <jbeulich@suse.com>
116
117 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
118 (extractps): Add VexWIG to SSE2AVX forms.
119 * i386-tbl.h: Re-generate.
120
4814632e
JB		 1212020-01-16 Jan Beulich <jbeulich@suse.com>
122
123 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
124 Size64 from and use VexW1 on SSE2AVX forms.
125 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
126 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
127 * i386-tbl.h: Re-generate.
128
aad09917
AM		 1292020-01-15 Alan Modra <amodra@gmail.com>
130
131 * tic4x-dis.c (tic4x_version): Make unsigned long.
132 (optab, optab_special, registernames): New file scope vars.
133 (tic4x_print_register): Set up registernames rather than
134 malloc'd registertable.
135 (tic4x_disassemble): Delete optable and optable_special. Use
136 optab and optab_special instead. Throw away old optab,
137 optab_special and registernames when info->mach changes.
138
7a6bf3be
SB		 1392020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
140
141 PR 25377
142 * z80-dis.c (suffix): Use .db instruction to generate double
143 prefix.
144
ca1eaac0
AM		 1452020-01-14 Alan Modra <amodra@gmail.com>
146
147 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
148 values to unsigned before shifting.
149
1d67fe3b
TT		 1502020-01-13 Thomas Troeger <tstroege@gmx.de>
151
152 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
153 flow instructions.
154 (print_insn_thumb16, print_insn_thumb32): Likewise.
155 (print_insn): Initialize the insn info.
156 * i386-dis.c (print_insn): Initialize the insn info fields, and
157 detect jumps.
158
5e4f7e05
CZ		 1592012-01-13 Claudiu Zissulescu <claziss@gmail.com>
160
161 * arc-opc.c (C_NE): Make it required.
162
b9fe6b8a
CZ		 1632012-01-13 Claudiu Zissulescu <claziss@gmail.com>
164
165 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
166 reserved register name.
167
90dee485
AM		 1682020-01-13 Alan Modra <amodra@gmail.com>
169
170 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
171 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
172
febda64f
AM		 1732020-01-13 Alan Modra <amodra@gmail.com>
174
175 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
176 result of wasm_read_leb128 in a uint64_t and check that bits
177 are not lost when copying to other locals. Use uint32_t for
178 most locals. Use PRId64 when printing int64_t.
179
df08b588
AM		 1802020-01-13 Alan Modra <amodra@gmail.com>
181
182 * score-dis.c: Formatting.
183 * score7-dis.c: Formatting.
184
b2c759ce
AM		 1852020-01-13 Alan Modra <amodra@gmail.com>
186
187 * score-dis.c (print_insn_score48): Use unsigned variables for
188 unsigned values. Don't left shift negative values.
189 (print_insn_score32): Likewise.
190 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
191
5496abe1
AM		 1922020-01-13 Alan Modra <amodra@gmail.com>
193
194 * tic4x-dis.c (tic4x_print_register): Remove dead code.
195
202e762b
AM		 1962020-01-13 Alan Modra <amodra@gmail.com>
197
198 * fr30-ibld.c: Regenerate.
199
7ef412cf
AM		 2002020-01-13 Alan Modra <amodra@gmail.com>
201
202 * xgate-dis.c (print_insn): Don't left shift signed value.
203 (ripBits): Formatting, use 1u.
204
7f578b95
AM		 2052020-01-10 Alan Modra <amodra@gmail.com>
206
207 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
208 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
209
441af85b
AM		 2102020-01-10 Alan Modra <amodra@gmail.com>
211
212 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
213 and XRREG value earlier to avoid a shift with negative exponent.
214 * m10200-dis.c (disassemble): Similarly.
215
bce58db4
NC		 2162020-01-09 Nick Clifton <nickc@redhat.com>
217
218 PR 25224
219 * z80-dis.c (ld_ii_ii): Use correct cast.
220
40c75bc8
SB		 2212020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
222
223 PR 25224
224 * z80-dis.c (ld_ii_ii): Use character constant when checking
225 opcode byte value.
226
d835a58b
JB		 2272020-01-09 Jan Beulich <jbeulich@suse.com>
228
229 * i386-dis.c (SEP_Fixup): New.
230 (SEP): Define.
231 (dis386_twobyte): Use it for sysenter/sysexit.
232 (enum x86_64_isa): Change amd64 enumerator to value 1.
233 (OP_J): Compare isa64 against intel64 instead of amd64.
234 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
235 forms.
236 * i386-tbl.h: Re-generate.
237
030a2e78
AM		 2382020-01-08 Alan Modra <amodra@gmail.com>
239
240 * z8k-dis.c: Include libiberty.h
241 (instr_data_s): Make max_fetched unsigned.
242 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
243 Don't exceed byte_info bounds.
244 (output_instr): Make num_bytes unsigned.
245 (unpack_instr): Likewise for nibl_count and loop.
246 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
247 idx unsigned.
248 * z8k-opc.h: Regenerate.
249
bb82aefe
SV		 2502020-01-07 Shahab Vahedi <shahab@synopsys.com>
251
252 * arc-tbl.h (llock): Use 'LLOCK' as class.
253 (llockd): Likewise.
254 (scond): Use 'SCOND' as class.
255 (scondd): Likewise.
256 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
257 (scondd): Likewise.
258
cc6aa1a6
AM		 2592020-01-06 Alan Modra <amodra@gmail.com>
260
261 * m32c-ibld.c: Regenerate.
262
660e62b1
AM		 2632020-01-06 Alan Modra <amodra@gmail.com>
264
265 PR 25344
266 * z80-dis.c (suffix): Don't use a local struct buffer copy.
267 Peek at next byte to prevent recursion on repeated prefix bytes.
268 Ensure uninitialised "mybuf" is not accessed.
269 (print_insn_z80): Don't zero n_fetch and n_used here,..
270 (print_insn_z80_buf): ..do it here instead.
271
c9ae58fe
AM		 2722020-01-04 Alan Modra <amodra@gmail.com>
273
274 * m32r-ibld.c: Regenerate.
275
5f57d4ec
AM		 2762020-01-04 Alan Modra <amodra@gmail.com>
277
278 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
279
2c5c1196
AM		 2802020-01-04 Alan Modra <amodra@gmail.com>
281
282 * crx-dis.c (match_opcode): Avoid shift left of signed value.
283
2e98c6c5
AM		 2842020-01-04 Alan Modra <amodra@gmail.com>
285
286 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
287
567dfba2
JB		 2882020-01-03 Jan Beulich <jbeulich@suse.com>
289
5437a02a
JB		 290 * aarch64-tbl.h (aarch64_opcode_table): Use
291 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
292
2932020-01-03 Jan Beulich <jbeulich@suse.com>
294
295 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 296 forms of SUDOT and USDOT.
297
8c45011a
JB		 2982020-01-03 Jan Beulich <jbeulich@suse.com>
299
5437a02a 300 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 301 uzip{1,2}.
302 * opcodes/aarch64-dis-2.c: Re-generate.
303
f4950f76
JB		 3042020-01-03 Jan Beulich <jbeulich@suse.com>
305
5437a02a 306 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 307 FMMLA encoding.
308 * opcodes/aarch64-dis-2.c: Re-generate.
309
6655dba2
SB		 3102020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
311
312 * z80-dis.c: Add support for eZ80 and Z80 instructions.
313
b14ce8bf
AM		 3142020-01-01 Alan Modra <amodra@gmail.com>
315
316 Update year range in copyright notice of all files.
317
0b114740 318For older changes see ChangeLog-2019
3499769a 319\f
0b114740 320Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 321
322Copying and distribution of this file, with or without modification,
323are permitted in any medium without royalty provided the copyright
324notice and this notice are preserved.
325
326Local Variables:
327mode: change-log
328left-margin: 8
329fill-column: 74
330version-control: never
331End:
GDB Binutils - Deliverables
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