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x86: fold VCMP_Fixup() into CMP_Fixup()
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
c4de7606
JB		 12020-07-14 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
4 (simd_cmp_op): Add const.
5 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
6 (CMP_Fixup): Handle VEX case.
7 (prefix_table): Replace VCMP by CMP.
8 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
9
9ab00b61
JB		 102020-07-14 Jan Beulich <jbeulich@suse.com>
11
12 * i386-dis.c (MOVBE_Fixup): Delete.
13 (Mv): Define.
14 (prefix_table): Use Mv for movbe entries.
15
2875b28a
JB		 162020-07-14 Jan Beulich <jbeulich@suse.com>
17
18 * i386-dis.c (CRC32_Fixup): Delete.
19 (prefix_table): Use Eb/Ev for crc32 entries.
20
e184e611
JB		 212020-07-14 Jan Beulich <jbeulich@suse.com>
22
23 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
24 Conditionalize invocations of "USED_REX (0)".
25
e8b5d5f9
JB		 262020-07-14 Jan Beulich <jbeulich@suse.com>
27
28 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
29 CH, DH, BH, AX, DX): Delete.
30 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
31 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
32 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
33
260cd341
LC		 342020-07-10 Lili Cui <lili.cui@intel.com>
35
36 * i386-dis.c (TMM): New.
37 (EXtmm): Likewise.
38 (VexTmm): Likewise.
39 (MVexSIBMEM): Likewise.
40 (tmm_mode): Likewise.
41 (vex_sibmem_mode): Likewise.
42 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
43 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
44 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
45 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
46 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
47 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
48 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
49 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
50 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
51 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
52 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
53 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
54 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
55 (PREFIX_VEX_0F3849_X86_64): Likewise.
56 (PREFIX_VEX_0F384B_X86_64): Likewise.
57 (PREFIX_VEX_0F385C_X86_64): Likewise.
58 (PREFIX_VEX_0F385E_X86_64): Likewise.
59 (X86_64_VEX_0F3849): Likewise.
60 (X86_64_VEX_0F384B): Likewise.
61 (X86_64_VEX_0F385C): Likewise.
62 (X86_64_VEX_0F385E): Likewise.
63 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
64 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
65 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
66 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
67 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
68 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
69 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
70 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
71 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
72 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
73 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
74 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
75 (VEX_W_0F3849_X86_64_P_0): Likewise.
76 (VEX_W_0F3849_X86_64_P_2): Likewise.
77 (VEX_W_0F3849_X86_64_P_3): Likewise.
78 (VEX_W_0F384B_X86_64_P_1): Likewise.
79 (VEX_W_0F384B_X86_64_P_2): Likewise.
80 (VEX_W_0F384B_X86_64_P_3): Likewise.
81 (VEX_W_0F385C_X86_64_P_1): Likewise.
82 (VEX_W_0F385E_X86_64_P_0): Likewise.
83 (VEX_W_0F385E_X86_64_P_1): Likewise.
84 (VEX_W_0F385E_X86_64_P_2): Likewise.
85 (VEX_W_0F385E_X86_64_P_3): Likewise.
86 (names_tmm): Likewise.
87 (att_names_tmm): Likewise.
88 (intel_operand_size): Handle void_mode.
89 (OP_XMM): Handle tmm_mode.
90 (OP_EX): Likewise.
91 (OP_VEX): Likewise.
92 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
93 CpuAMX_BF16 and CpuAMX_TILE.
94 (operand_type_shorthands): Add RegTMM.
95 (operand_type_init): Likewise.
96 (operand_types): Add Tmmword.
97 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
98 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
99 * i386-opc.h (CpuAMX_INT8): New.
100 (CpuAMX_BF16): Likewise.
101 (CpuAMX_TILE): Likewise.
102 (SIBMEM): Likewise.
103 (Tmmword): Likewise.
104 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
105 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
106 (i386_operand_type): Add tmmword.
107 * i386-opc.tbl: Add AMX instructions.
108 * i386-reg.tbl: Add AMX registers.
109 * i386-init.h: Regenerated.
110 * i386-tbl.h: Likewise.
111
467bbef0
JB		 1122020-07-08 Jan Beulich <jbeulich@suse.com>
113
114 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
115 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
116 Rename to ...
117 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
118 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
119 respectively.
120 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
121 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
122 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
123 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
124 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
125 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
126 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
127 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
128 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
129 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
130 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
131 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
132 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
133 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
134 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
135 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
136 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
137 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
138 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
139 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
140 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
141 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
142 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
143 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
144 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
145 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
146 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
147 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
148 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
149 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
150 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
151 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
152 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
153 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
154 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
155 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
156 (reg_table): Re-order XOP entries. Adjust their operands.
157 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
158 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
159 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
160 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
161 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
162 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
163 entries by references ...
164 (vex_len_table): ... to resepctive new entries here. For several
165 new and existing entries reference ...
166 (vex_w_table): ... new entries here.
167 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
168
6384fd9e
JB		 1692020-07-08 Jan Beulich <jbeulich@suse.com>
170
171 * i386-dis.c (XMVexScalarI4): Define.
172 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
173 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
174 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
175 (vex_len_table): Move scalar FMA4 entries ...
176 (prefix_table): ... here.
177 (OP_REG_VexI4): Handle scalar_mode.
178 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
179 * i386-tbl.h: Re-generate.
180
e6123d0c
JB		 1812020-07-08 Jan Beulich <jbeulich@suse.com>
182
183 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
184 Vex_2src_2): Delete.
185 (OP_VexW, VexW): New.
186 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
187 for shifts and rotates by register.
188
93abb146
JB		 1892020-07-08 Jan Beulich <jbeulich@suse.com>
190
191 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
192 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
193 OP_EX_VexReg): Delete.
194 (OP_VexI4, VexI4): New.
195 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
196 (prefix_table): ... here.
197 (print_insn): Drop setting of vex_w_done.
198
b13b1bc0
JB		 1992020-07-08 Jan Beulich <jbeulich@suse.com>
200
201 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
202 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
203 (xop_table): Replace operands of 4-operand insns.
204 (OP_REG_VexI4): Move VEX.W based operand swaping here.
205
f337259f
CZ		 2062020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
207
208 * arc-opc.c (insert_rbd): New function.
209 (RBD): Define.
210 (RBDdup): Likewise.
211 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
212 instructions.
213
931452b6
JB		 2142020-07-07 Jan Beulich <jbeulich@suse.com>
215
216 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
217 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
218 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
219 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
220 Delete.
221 (putop): Handle "BW".
222 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
223 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
224 and 0F3A3F ...
225 * i386-dis-evex-prefix.h: ... here.
226
b5b098c2
JB		 2272020-07-06 Jan Beulich <jbeulich@suse.com>
228
229 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
230 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
231 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
232 VEX_W_0FXOP_09_83): New enumerators.
233 (xop_table): Reference the above.
234 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
235 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
236 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
237 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
238
21a3faeb
JB		 2392020-07-06 Jan Beulich <jbeulich@suse.com>
240
241 * i386-dis.c (EVEX_W_0F3838_P_1,
242 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
243 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
244 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
245 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
246 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
247 (putop): Centralize management of last[]. Delete SAVE_LAST.
248 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
249 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
250 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
251 * i386-dis-evex-prefix.h: here.
252
bc152a17
JB		 2532020-07-06 Jan Beulich <jbeulich@suse.com>
254
255 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
256 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
257 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
258 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
259 enumerators.
260 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
261 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
262 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
263 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
264 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
265 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
266 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
267 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
268 these, respectively.
269 * i386-dis-evex-len.h: Adjust comments.
270 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
271 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
272 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
273 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
274 MOD_EVEX_0F385B_P_2_W_1 table entries.
275 * i386-dis-evex-w.h: Reference mod_table[] for
276 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
277 EVEX_W_0F385B_P_2.
278
c82a99a0
JB		 2792020-07-06 Jan Beulich <jbeulich@suse.com>
280
281 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
282 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
283 EXymm.
284 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
285 Likewise. Mark 256-bit entries invalid.
286
fedfb81e
JB		 2872020-07-06 Jan Beulich <jbeulich@suse.com>
288
289 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
290 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
291 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
292 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
293 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
294 PREFIX_EVEX_0F382B): Delete.
295 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
296 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
297 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
298 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
299 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
300 to ...
301 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
302 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
303 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
304 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
305 respectively.
306 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
307 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
308 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
309 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
310 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
311 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
312 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
313 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
314 PREFIX_EVEX_0F382B): Remove table entries.
315 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
316 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
317 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
318
3a57774c
JB		 3192020-07-06 Jan Beulich <jbeulich@suse.com>
320
321 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
322 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
323 enumerators.
324 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
325 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
326 EVEX_LEN_0F3A01_P_2_W_1 table entries.
327 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
328 entries.
329
e74d9fa9
JB		 3302020-07-06 Jan Beulich <jbeulich@suse.com>
331
332 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
333 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
334 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
335 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
336 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
337 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
338 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
339 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
340 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
341 entries.
342
6431c801
JB		 3432020-07-06 Jan Beulich <jbeulich@suse.com>
344
345 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
346 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
347 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
348 respectively.
349 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
350 entries.
351 * i386-dis-evex.h (evex_table): Reference VEX table entry for
352 opcode 0F3A1D.
353 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
354 entry.
355 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
356
6df22cf6
JB		 3572020-07-06 Jan Beulich <jbeulich@suse.com>
358
359 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
360 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
361 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
362 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
363 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
364 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
365 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
366 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
367 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
368 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
369 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
370 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
371 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
372 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
373 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
374 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
375 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
376 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
377 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
378 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
379 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
380 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
381 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
382 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
383 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
384 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
385 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
386 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
387 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
388 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
389 (prefix_table): Add EXxEVexR to FMA table entries.
390 (OP_Rounding): Move abort() invocation.
391 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
392 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
393 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
394 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
395 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
396 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
397 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
398 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
399 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
400 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
401 0F3ACE, 0F3ACF.
402 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
403 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
404 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
405 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
406 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
407 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
408 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
409 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
410 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
411 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
412 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
413 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
414 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
415 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
416 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
417 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
418 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
419 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
420 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
421 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
422 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
423 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
424 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
425 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
426 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
427 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
428 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
429 Delete table entries.
430 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
431 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
432 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
433 Likewise.
434
39e0f456
JB		 4352020-07-06 Jan Beulich <jbeulich@suse.com>
436
437 * i386-dis.c (EXqScalarS): Delete.
438 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
439 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
440
5b872f7d
JB		 4412020-07-06 Jan Beulich <jbeulich@suse.com>
442
443 * i386-dis.c (safe-ctype.h): Include.
444 (EXdScalar, EXqScalar): Delete.
445 (d_scalar_mode, q_scalar_mode): Delete.
446 (prefix_table, vex_len_table): Use EXxmm_md in place of
447 EXdScalar and EXxmm_mq in place of EXqScalar.
448 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
449 d_scalar_mode and q_scalar_mode.
450 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
451 (vmovsd): Use EXxmm_mq.
452
ddc73fa9
NC		 4532020-07-06 Yuri Chornoivan <yurchor@ukr.net>
454
455 PR 26204
456 * arc-dis.c: Fix spelling mistake.
457 * po/opcodes.pot: Regenerate.
458
17550be7
NC		 4592020-07-06 Nick Clifton <nickc@redhat.com>
460
461 * po/pt_BR.po: Updated Brazilian Portugugese translation.
462 * po/uk.po: Updated Ukranian translation.
463
b19d852d
NC		 4642020-07-04 Nick Clifton <nickc@redhat.com>
465
466 * configure: Regenerate.
467 * po/opcodes.pot: Regenerate.
468
b115b9fd
NC		 4692020-07-04 Nick Clifton <nickc@redhat.com>
470
471 Binutils 2.35 branch created.
472
c2ecccb3
L		 4732020-07-02 H.J. Lu <hongjiu.lu@intel.com>
474
475 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
476 * i386-opc.h (VexSwapSources): New.
477 (i386_opcode_modifier): Add vexswapsources.
478 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
479 with two source operands swapped.
480 * i386-tbl.h: Regenerated.
481
08ccfccf
NC		 4822020-06-30 Nelson Chu <nelson.chu@sifive.com>
483
484 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
485 unprivileged CSR can also be initialized.
486
279edac5
AM		 4872020-06-29 Alan Modra <amodra@gmail.com>
488
489 * arm-dis.c: Use C style comments.
490 * cr16-opc.c: Likewise.
491 * ft32-dis.c: Likewise.
492 * moxie-opc.c: Likewise.
493 * tic54x-dis.c: Likewise.
494 * s12z-opc.c: Remove useless comment.
495 * xgate-dis.c: Likewise.
496
e978ad62
L		 4972020-06-26 H.J. Lu <hongjiu.lu@intel.com>
498
499 * i386-opc.tbl: Add a blank line.
500
63112cd6
L		 5012020-06-26 H.J. Lu <hongjiu.lu@intel.com>
502
503 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
504 (VecSIB128): Renamed to ...
505 (VECSIB128): This.
506 (VecSIB256): Renamed to ...
507 (VECSIB256): This.
508 (VecSIB512): Renamed to ...
509 (VECSIB512): This.
510 (VecSIB): Renamed to ...
511 (SIB): This.
512 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 513 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 514 (VecSIB256): Likewise.
515 (VecSIB512): Likewise.
79b32e73 516 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 517 and VecSIB512, respectively.
518
d1c36125
JB		 5192020-06-26 Jan Beulich <jbeulich@suse.com>
520
521 * i386-dis.c: Adjust description of I macro.
522 (x86_64_table): Drop use of I.
523 (float_mem): Replace use of I.
524 (putop): Remove handling of I. Adjust setting/clearing of "alt".
525
2a1bb84c
JB		 5262020-06-26 Jan Beulich <jbeulich@suse.com>
527
528 * i386-dis.c: (print_insn): Avoid straight assignment to
529 priv.orig_sizeflag when processing -M sub-options.
530
8f570d62
JB		 5312020-06-25 Jan Beulich <jbeulich@suse.com>
532
533 * i386-dis.c: Adjust description of J macro.
534 (dis386, x86_64_table, mod_table): Replace J.
535 (putop): Remove handling of J.
536
464dc4af
JB		 5372020-06-25 Jan Beulich <jbeulich@suse.com>
538
539 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
540
589958d6
JB		 5412020-06-25 Jan Beulich <jbeulich@suse.com>
542
543 * i386-dis.c: Adjust description of "LQ" macro.
544 (dis386_twobyte): Use LQ for sysret.
545 (putop): Adjust handling of LQ.
546
39ff0b81
NC		 5472020-06-22 Nelson Chu <nelson.chu@sifive.com>
548
549 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
550 * riscv-dis.c: Include elfxx-riscv.h.
551
d27c357a
JB		 5522020-06-18 H.J. Lu <hongjiu.lu@intel.com>
553
554 * i386-dis.c (prefix_table): Revert the last vmgexit change.
555
6fde587f
CL		 5562020-06-17 Lili Cui <lili.cui@intel.com>
557
558 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
559
efe30057
L		 5602020-06-14 H.J. Lu <hongjiu.lu@intel.com>
561
562 PR gas/26115
563 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
564 * i386-opc.tbl: Likewise.
565 * i386-tbl.h: Regenerated.
566
d8af286f
NC		 5672020-06-12 Nelson Chu <nelson.chu@sifive.com>
568
569 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
570
14962256
AC		 5712020-06-11 Alex Coplan <alex.coplan@arm.com>
572
573 * aarch64-opc.c (SYSREG): New macro for describing system registers.
574 (SR_CORE): Likewise.
575 (SR_FEAT): Likewise.
576 (SR_RNG): Likewise.
577 (SR_V8_1): Likewise.
578 (SR_V8_2): Likewise.
579 (SR_V8_3): Likewise.
580 (SR_V8_4): Likewise.
581 (SR_PAN): Likewise.
582 (SR_RAS): Likewise.
583 (SR_SSBS): Likewise.
584 (SR_SVE): Likewise.
585 (SR_ID_PFR2): Likewise.
586 (SR_PROFILE): Likewise.
587 (SR_MEMTAG): Likewise.
588 (SR_SCXTNUM): Likewise.
589 (aarch64_sys_regs): Refactor to store feature information in the table.
590 (aarch64_sys_reg_supported_p): Collapse logic for system registers
591 that now describe their own features.
592 (aarch64_pstatefield_supported_p): Likewise.
593
f9630fa6
L		 5942020-06-09 H.J. Lu <hongjiu.lu@intel.com>
595
596 * i386-dis.c (prefix_table): Fix a typo in comments.
597
73239888
JB		 5982020-06-09 Jan Beulich <jbeulich@suse.com>
599
600 * i386-dis.c (rex_ignored): Delete.
601 (ckprefix): Drop rex_ignored initialization.
602 (get_valid_dis386): Drop setting of rex_ignored.
603 (print_insn): Drop checking of rex_ignored. Don't record data
604 size prefix as used with VEX-and-alike encodings.
605
18897deb
JB		 6062020-06-09 Jan Beulich <jbeulich@suse.com>
607
608 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
609 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
610 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
611 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
612 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
613 VEX_0F12, and VEX_0F16.
614 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
615 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
616 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
617 from movlps and movhlps. New MOD_0F12_PREFIX_2,
618 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
619 MOD_VEX_0F16_PREFIX_2 entries.
620
97e6786a
JB		 6212020-06-09 Jan Beulich <jbeulich@suse.com>
622
623 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
624 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
625 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
626 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
627 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
628 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
629 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
630 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
631 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
632 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
633 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
634 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
635 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
636 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
637 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
638 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
639 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
640 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
641 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
642 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
643 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
644 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
645 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
646 EVEX_W_0FC6_P_2): Delete.
647 (print_insn): Add EVEX.W vs embedded prefix consistency check
648 to prefix validation.
649 * i386-dis-evex.h (evex_table): Don't further descend for
650 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
651 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
652 and 0F2B.
653 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
654 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
655 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
656 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
657 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
658 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
659 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
660 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
661 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
662 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
663 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
664 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
665 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
666 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
667 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
668 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
669 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
670 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
671 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
672 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
673 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
674 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
675 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
676 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
677 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
678 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
679 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
680
bf926894
JB		 6812020-06-09 Jan Beulich <jbeulich@suse.com>
682
683 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
684 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
685 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
686 vmovmskpX.
687 (print_insn): Drop pointless check against bad_opcode. Split
688 prefix validation into legacy and VEX-and-alike parts.
689 (putop): Re-work 'X' macro handling.
690
a5aaedb9
JB		 6912020-06-09 Jan Beulich <jbeulich@suse.com>
692
693 * i386-dis.c (MOD_0F51): Rename to ...
694 (MOD_0F50): ... this.
695
26417f19
AC		 6962020-06-08 Alex Coplan <alex.coplan@arm.com>
697
698 * arm-dis.c (arm_opcodes): Add dfb.
699 (thumb32_opcodes): Add dfb.
700
8a6fb3f9
JB		 7012020-06-08 Jan Beulich <jbeulich@suse.com>
702
703 * i386-opc.h (reg_entry): Const-qualify reg_name field.
704
1424c35d
AM		 7052020-06-06 Alan Modra <amodra@gmail.com>
706
707 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
708
d3d1cc7b
AM		 7092020-06-05 Alan Modra <amodra@gmail.com>
710
711 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
712 size is large enough.
713
d8740be1
JM		 7142020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
715
716 * disassemble.c (disassemble_init_for_target): Set endian_code for
717 bpf targets.
718 * bpf-desc.c: Regenerate.
719 * bpf-opc.c: Likewise.
720 * bpf-dis.c: Likewise.
721
e9bffec9
JM		 7222020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
723
724 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
725 (cgen_put_insn_value): Likewise.
726 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
727 * cgen-dis.in (print_insn): Likewise.
728 * cgen-ibld.in (insert_1): Likewise.
729 (insert_1): Likewise.
730 (insert_insn_normal): Likewise.
731 (extract_1): Likewise.
732 * bpf-dis.c: Regenerate.
733 * bpf-ibld.c: Likewise.
734 * bpf-ibld.c: Likewise.
735 * cgen-dis.in: Likewise.
736 * cgen-ibld.in: Likewise.
737 * cgen-opc.c: Likewise.
738 * epiphany-dis.c: Likewise.
739 * epiphany-ibld.c: Likewise.
740 * fr30-dis.c: Likewise.
741 * fr30-ibld.c: Likewise.
742 * frv-dis.c: Likewise.
743 * frv-ibld.c: Likewise.
744 * ip2k-dis.c: Likewise.
745 * ip2k-ibld.c: Likewise.
746 * iq2000-dis.c: Likewise.
747 * iq2000-ibld.c: Likewise.
748 * lm32-dis.c: Likewise.
749 * lm32-ibld.c: Likewise.
750 * m32c-dis.c: Likewise.
751 * m32c-ibld.c: Likewise.
752 * m32r-dis.c: Likewise.
753 * m32r-ibld.c: Likewise.
754 * mep-dis.c: Likewise.
755 * mep-ibld.c: Likewise.
756 * mt-dis.c: Likewise.
757 * mt-ibld.c: Likewise.
758 * or1k-dis.c: Likewise.
759 * or1k-ibld.c: Likewise.
760 * xc16x-dis.c: Likewise.
761 * xc16x-ibld.c: Likewise.
762 * xstormy16-dis.c: Likewise.
763 * xstormy16-ibld.c: Likewise.
764
b3db6d07
JM		 7652020-06-04 Jose E. Marchesi <jemarch@gnu.org>
766
767 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
768 (print_insn_): Handle instruction endian.
769 * bpf-dis.c: Regenerate.
770 * bpf-desc.c: Regenerate.
771 * epiphany-dis.c: Likewise.
772 * epiphany-desc.c: Likewise.
773 * fr30-dis.c: Likewise.
774 * fr30-desc.c: Likewise.
775 * frv-dis.c: Likewise.
776 * frv-desc.c: Likewise.
777 * ip2k-dis.c: Likewise.
778 * ip2k-desc.c: Likewise.
779 * iq2000-dis.c: Likewise.
780 * iq2000-desc.c: Likewise.
781 * lm32-dis.c: Likewise.
782 * lm32-desc.c: Likewise.
783 * m32c-dis.c: Likewise.
784 * m32c-desc.c: Likewise.
785 * m32r-dis.c: Likewise.
786 * m32r-desc.c: Likewise.
787 * mep-dis.c: Likewise.
788 * mep-desc.c: Likewise.
789 * mt-dis.c: Likewise.
790 * mt-desc.c: Likewise.
791 * or1k-dis.c: Likewise.
792 * or1k-desc.c: Likewise.
793 * xc16x-dis.c: Likewise.
794 * xc16x-desc.c: Likewise.
795 * xstormy16-dis.c: Likewise.
796 * xstormy16-desc.c: Likewise.
797
4ee4189f
NC		 7982020-06-03 Nick Clifton <nickc@redhat.com>
799
800 * po/sr.po: Updated Serbian translation.
801
44730156
NC		 8022020-06-03 Nelson Chu <nelson.chu@sifive.com>
803
804 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
805 (riscv_get_priv_spec_class): Likewise.
806
3c3d0376
AM		 8072020-06-01 Alan Modra <amodra@gmail.com>
808
809 * bpf-desc.c: Regenerate.
810
78c1c354
JM		 8112020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
812 David Faust <david.faust@oracle.com>
813
814 * bpf-desc.c: Regenerate.
815 * bpf-opc.h: Likewise.
816 * bpf-opc.c: Likewise.
817 * bpf-dis.c: Likewise.
818
efcf5fb5
AM		 8192020-05-28 Alan Modra <amodra@gmail.com>
820
821 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
822 values.
823
ab382d64
AM		 8242020-05-28 Alan Modra <amodra@gmail.com>
825
826 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
827 immediates.
828 (print_insn_ns32k): Revert last change.
829
151f5de4
NC		 8302020-05-28 Nick Clifton <nickc@redhat.com>
831
832 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
833 static.
834
25e1eca8
SL		 8352020-05-26 Sandra Loosemore <sandra@codesourcery.com>
836
837 Fix extraction of signed constants in nios2 disassembler (again).
838
839 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
840 extractions of signed fields.
841
57b17940
SSF		 8422020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
843
844 * s390-opc.txt: Relocate vector load/store instructions with
845 additional alignment parameter and change architecture level
846 constraint from z14 to z13.
847
d96bf37b
AM		 8482020-05-21 Alan Modra <amodra@gmail.com>
849
850 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
851 * sparc-dis.c: Likewise.
852 * tic4x-dis.c: Likewise.
853 * xtensa-dis.c: Likewise.
854 * bpf-desc.c: Regenerate.
855 * epiphany-desc.c: Regenerate.
856 * fr30-desc.c: Regenerate.
857 * frv-desc.c: Regenerate.
858 * ip2k-desc.c: Regenerate.
859 * iq2000-desc.c: Regenerate.
860 * lm32-desc.c: Regenerate.
861 * m32c-desc.c: Regenerate.
862 * m32r-desc.c: Regenerate.
863 * mep-asm.c: Regenerate.
864 * mep-desc.c: Regenerate.
865 * mt-desc.c: Regenerate.
866 * or1k-desc.c: Regenerate.
867 * xc16x-desc.c: Regenerate.
868 * xstormy16-desc.c: Regenerate.
869
8f595e9b
NC		 8702020-05-20 Nelson Chu <nelson.chu@sifive.com>
871
872 * riscv-opc.c (riscv_ext_version_table): The table used to store
873 all information about the supported spec and the corresponding ISA
874 versions. Currently, only Zicsr is supported to verify the
875 correctness of Z sub extension settings. Others will be supported
876 in the future patches.
877 (struct isa_spec_t, isa_specs): List for all supported ISA spec
878 classes and the corresponding strings.
879 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
880 spec class by giving a ISA spec string.
881 * riscv-opc.c (struct priv_spec_t): New structure.
882 (struct priv_spec_t priv_specs): List for all supported privilege spec
883 classes and the corresponding strings.
884 (riscv_get_priv_spec_class): New function. Get the corresponding
885 privilege spec class by giving a spec string.
886 (riscv_get_priv_spec_name): New function. Get the corresponding
887 privilege spec string by giving a CSR version class.
888 * riscv-dis.c: Updated since DECLARE_CSR is changed.
889 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
890 according to the chosen version. Build a hash table riscv_csr_hash to
891 store the valid CSR for the chosen pirv verison. Dump the direct
892 CSR address rather than it's name if it is invalid.
893 (parse_riscv_dis_option_without_args): New function. Parse the options
894 without arguments.
895 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
896 parse the options without arguments first, and then handle the options
897 with arguments. Add the new option -Mpriv-spec, which has argument.
898 * riscv-dis.c (print_riscv_disassembler_options): Add description
899 about the new OBJDUMP option.
900
3d205eb4
PB		 9012020-05-19 Peter Bergner <bergner@linux.ibm.com>
902
903 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
904 WC values on POWER10 sync, dcbf and wait instructions.
905 (insert_pl, extract_pl): New functions.
906 (L2OPT, LS, WC): Use insert_ls and extract_ls.
907 (LS3): New , 3-bit L for sync.
908 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
909 (SC2, PL): New, 2-bit SC and PL for sync and wait.
910 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
911 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
912 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
913 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
914 <wait>: Enable PL operand on POWER10.
915 <dcbf>: Enable L3OPT operand on POWER10.
916 <sync>: Enable SC2 operand on POWER10.
917
a501eb44
SH		 9182020-05-19 Stafford Horne <shorne@gmail.com>
919
920 PR 25184
921 * or1k-asm.c: Regenerate.
922 * or1k-desc.c: Regenerate.
923 * or1k-desc.h: Regenerate.
924 * or1k-dis.c: Regenerate.
925 * or1k-ibld.c: Regenerate.
926 * or1k-opc.c: Regenerate.
927 * or1k-opc.h: Regenerate.
928 * or1k-opinst.c: Regenerate.
929
3b646889
AM		 9302020-05-11 Alan Modra <amodra@gmail.com>
931
932 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
933 xsmaxcqp, xsmincqp.
934
9cc4ce88
AM		 9352020-05-11 Alan Modra <amodra@gmail.com>
936
937 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
938 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
939
5d57bc3f
AM		 9402020-05-11 Alan Modra <amodra@gmail.com>
941
942 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
943
66ef5847
AM		 9442020-05-11 Alan Modra <amodra@gmail.com>
945
946 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
947 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
948
4f3e9537
PB		 9492020-05-11 Peter Bergner <bergner@linux.ibm.com>
950
951 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
952 mnemonics.
953
ec40e91c
AM		 9542020-05-11 Alan Modra <amodra@gmail.com>
955
956 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
957 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
958 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
959 (prefix_opcodes): Add xxeval.
960
d7e97a76
AM		 9612020-05-11 Alan Modra <amodra@gmail.com>
962
963 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
964 xxgenpcvwm, xxgenpcvdm.
965
fdefed7c
AM		 9662020-05-11 Alan Modra <amodra@gmail.com>
967
968 * ppc-opc.c (MP, VXVAM_MASK): Define.
969 (VXVAPS_MASK): Use VXVA_MASK.
970 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
971 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
972 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
973 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
974
aa3c112f
AM		 9752020-05-11 Alan Modra <amodra@gmail.com>
976 Peter Bergner <bergner@linux.ibm.com>
977
978 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
979 New functions.
980 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
981 YMSK2, XA6a, XA6ap, XB6a entries.
982 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
983 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
984 (PPCVSX4): Define.
985 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
986 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
987 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
988 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
989 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
990 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
991 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
992 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
993 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
994 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
995 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
996 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
997 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
998 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
999
6edbfd3b
AM		 10002020-05-11 Alan Modra <amodra@gmail.com>
1001
1002 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1003 (insert_xts, extract_xts): New functions.
1004 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1005 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1006 (VXRC_MASK, VXSH_MASK): Define.
1007 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1008 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1009 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1010 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1011 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1012 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1013 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1014
c7d7aea2
AM		 10152020-05-11 Alan Modra <amodra@gmail.com>
1016
1017 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1018 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1019 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1020 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1021 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1022
94ba9882
AM		 10232020-05-11 Alan Modra <amodra@gmail.com>
1024
1025 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1026 (XTP, DQXP, DQXP_MASK): Define.
1027 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1028 (prefix_opcodes): Add plxvp and pstxvp.
1029
f4791f1a
AM		 10302020-05-11 Alan Modra <amodra@gmail.com>
1031
1032 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1033 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1034 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1035
3ff0a5ba
PB		 10362020-05-11 Peter Bergner <bergner@linux.ibm.com>
1037
1038 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1039
afef4fe9
PB		 10402020-05-11 Peter Bergner <bergner@linux.ibm.com>
1041
1042 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1043 (L1OPT): Define.
1044 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1045
1224c05d
PB		 10462020-05-11 Peter Bergner <bergner@linux.ibm.com>
1047
1048 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1049
6bbb0c05
AM		 10502020-05-11 Alan Modra <amodra@gmail.com>
1051
1052 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1053
7c1f4227
AM		 10542020-05-11 Alan Modra <amodra@gmail.com>
1055
1056 * ppc-dis.c (ppc_opts): Add "power10" entry.
1057 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1058 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1059
73199c2b
NC		 10602020-05-11 Nick Clifton <nickc@redhat.com>
1061
1062 * po/fr.po: Updated French translation.
1063
09c1e68a
AC		 10642020-04-30 Alex Coplan <alex.coplan@arm.com>
1065
1066 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1067 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1068 (operand_general_constraint_met_p): validate
1069 AARCH64_OPND_UNDEFINED.
1070 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1071 for FLD_imm16_2.
1072 * aarch64-asm-2.c: Regenerated.
1073 * aarch64-dis-2.c: Regenerated.
1074 * aarch64-opc-2.c: Regenerated.
1075
9654d51a
NC		 10762020-04-29 Nick Clifton <nickc@redhat.com>
1077
1078 PR 22699
1079 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1080 and SETRC insns.
1081
c2e71e57
NC		 10822020-04-29 Nick Clifton <nickc@redhat.com>
1083
1084 * po/sv.po: Updated Swedish translation.
1085
5c936ef5
NC		 10862020-04-29 Nick Clifton <nickc@redhat.com>
1087
1088 PR 22699
1089 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1090 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1091 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1092 IMM0_8U case.
1093
bb2a1453
AS		 10942020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1095
1096 PR 25848
1097 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1098 cmpi only on m68020up and cpu32.
1099
c2e5c986
SD		 11002020-04-20 Sudakshina Das <sudi.das@arm.com>
1101
1102 * aarch64-asm.c (aarch64_ins_none): New.
1103 * aarch64-asm.h (ins_none): New declaration.
1104 * aarch64-dis.c (aarch64_ext_none): New.
1105 * aarch64-dis.h (ext_none): New declaration.
1106 * aarch64-opc.c (aarch64_print_operand): Update case for
1107 AARCH64_OPND_BARRIER_PSB.
1108 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1109 (AARCH64_OPERANDS): Update inserter/extracter for
1110 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1111 * aarch64-asm-2.c: Regenerated.
1112 * aarch64-dis-2.c: Regenerated.
1113 * aarch64-opc-2.c: Regenerated.
1114
8a6e1d1d
SD		 11152020-04-20 Sudakshina Das <sudi.das@arm.com>
1116
1117 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1118 (aarch64_feature_ras, RAS): Likewise.
1119 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1120 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1121 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1122 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1123 * aarch64-asm-2.c: Regenerated.
1124 * aarch64-dis-2.c: Regenerated.
1125 * aarch64-opc-2.c: Regenerated.
1126
e409955d
FS		 11272020-04-17 Fredrik Strupe <fredrik@strupe.net>
1128
1129 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1130 (print_insn_neon): Support disassembly of conditional
1131 instructions.
1132
c54a9b56
DF		 11332020-02-16 David Faust <david.faust@oracle.com>
1134
1135 * bpf-desc.c: Regenerate.
1136 * bpf-desc.h: Likewise.
1137 * bpf-opc.c: Regenerate.
1138 * bpf-opc.h: Likewise.
1139
bb651e8b
CL		 11402020-04-07 Lili Cui <lili.cui@intel.com>
1141
1142 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1143 (prefix_table): New instructions (see prefixes above).
1144 (rm_table): Likewise
1145 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1146 CPU_ANY_TSXLDTRK_FLAGS.
1147 (cpu_flags): Add CpuTSXLDTRK.
1148 * i386-opc.h (enum): Add CpuTSXLDTRK.
1149 (i386_cpu_flags): Add cputsxldtrk.
1150 * i386-opc.tbl: Add XSUSPLDTRK insns.
1151 * i386-init.h: Regenerate.
1152 * i386-tbl.h: Likewise.
1153
4b27d27c
L		 11542020-04-02 Lili Cui <lili.cui@intel.com>
1155
1156 * i386-dis.c (prefix_table): New instructions serialize.
1157 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1158 CPU_ANY_SERIALIZE_FLAGS.
1159 (cpu_flags): Add CpuSERIALIZE.
1160 * i386-opc.h (enum): Add CpuSERIALIZE.
1161 (i386_cpu_flags): Add cpuserialize.
1162 * i386-opc.tbl: Add SERIALIZE insns.
1163 * i386-init.h: Regenerate.
1164 * i386-tbl.h: Likewise.
1165
832a5807
AM		 11662020-03-26 Alan Modra <amodra@gmail.com>
1167
1168 * disassemble.h (opcodes_assert): Declare.
1169 (OPCODES_ASSERT): Define.
1170 * disassemble.c: Don't include assert.h. Include opintl.h.
1171 (opcodes_assert): New function.
1172 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1173 (bfd_h8_disassemble): Reduce size of data array. Correctly
1174 calculate maxlen. Omit insn decoding when insn length exceeds
1175 maxlen. Exit from nibble loop when looking for E, before
1176 accessing next data byte. Move processing of E outside loop.
1177 Replace tests of maxlen in loop with assertions.
1178
4c4addbe
AM		 11792020-03-26 Alan Modra <amodra@gmail.com>
1180
1181 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1182
a18cd0ca
AM		 11832020-03-25 Alan Modra <amodra@gmail.com>
1184
1185 * z80-dis.c (suffix): Init mybuf.
1186
57cb32b3
AM		 11872020-03-22 Alan Modra <amodra@gmail.com>
1188
1189 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1190 successflly read from section.
1191
beea5cc1
AM		 11922020-03-22 Alan Modra <amodra@gmail.com>
1193
1194 * arc-dis.c (find_format): Use ISO C string concatenation rather
1195 than line continuation within a string. Don't access needs_limm
1196 before testing opcode != NULL.
1197
03704c77
AM		 11982020-03-22 Alan Modra <amodra@gmail.com>
1199
1200 * ns32k-dis.c (print_insn_arg): Update comment.
1201 (print_insn_ns32k): Reduce size of index_offset array, and
1202 initialize, passing -1 to print_insn_arg for args that are not
1203 an index. Don't exit arg loop early. Abort on bad arg number.
1204
d1023b5d
AM		 12052020-03-22 Alan Modra <amodra@gmail.com>
1206
1207 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1208 * s12z-opc.c: Formatting.
1209 (operands_f): Return an int.
1210 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1211 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1212 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1213 (exg_sex_discrim): Likewise.
1214 (create_immediate_operand, create_bitfield_operand),
1215 (create_register_operand_with_size, create_register_all_operand),
1216 (create_register_all16_operand, create_simple_memory_operand),
1217 (create_memory_operand, create_memory_auto_operand): Don't
1218 segfault on malloc failure.
1219 (z_ext24_decode): Return an int status, negative on fail, zero
1220 on success.
1221 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1222 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1223 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1224 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1225 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1226 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1227 (loop_primitive_decode, shift_decode, psh_pul_decode),
1228 (bit_field_decode): Similarly.
1229 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1230 to return value, update callers.
1231 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1232 Don't segfault on NULL operand.
1233 (decode_operation): Return OP_INVALID on first fail.
1234 (decode_s12z): Check all reads, returning -1 on fail.
1235
340f3ac8
AM		 12362020-03-20 Alan Modra <amodra@gmail.com>
1237
1238 * metag-dis.c (print_insn_metag): Don't ignore status from
1239 read_memory_func.
1240
fe90ae8a
AM		 12412020-03-20 Alan Modra <amodra@gmail.com>
1242
1243 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1244 Initialize parts of buffer not written when handling a possible
1245 2-byte insn at end of section. Don't attempt decoding of such
1246 an insn by the 4-byte machinery.
1247
833d919c
AM		 12482020-03-20 Alan Modra <amodra@gmail.com>
1249
1250 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1251 partially filled buffer. Prevent lookup of 4-byte insns when
1252 only VLE 2-byte insns are possible due to section size. Print
1253 ".word" rather than ".long" for 2-byte leftovers.
1254
327ef784
NC		 12552020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1256
1257 PR 25641
1258 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1259
1673df32
JB		 12602020-03-13 Jan Beulich <jbeulich@suse.com>
1261
1262 * i386-dis.c (X86_64_0D): Rename to ...
1263 (X86_64_0E): ... this.
1264
384f3689
L		 12652020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1266
1267 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1268 * Makefile.in: Regenerated.
1269
865e2027
JB		 12702020-03-09 Jan Beulich <jbeulich@suse.com>
1271
1272 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1273 3-operand pseudos.
1274 * i386-tbl.h: Re-generate.
1275
2f13234b
JB		 12762020-03-09 Jan Beulich <jbeulich@suse.com>
1277
1278 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1279 vprot*, vpsha*, and vpshl*.
1280 * i386-tbl.h: Re-generate.
1281
3fabc179
JB		 12822020-03-09 Jan Beulich <jbeulich@suse.com>
1283
1284 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1285 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1286 * i386-tbl.h: Re-generate.
1287
3677e4c1
JB		 12882020-03-09 Jan Beulich <jbeulich@suse.com>
1289
1290 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1291 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1292 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1293 * i386-tbl.h: Re-generate.
1294
4c4898e8
JB		 12952020-03-09 Jan Beulich <jbeulich@suse.com>
1296
1297 * i386-gen.c (struct template_arg, struct template_instance,
1298 struct template_param, struct template, templates,
1299 parse_template, expand_templates): New.
1300 (process_i386_opcodes): Various local variables moved to
1301 expand_templates. Call parse_template and expand_templates.
1302 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1303 * i386-tbl.h: Re-generate.
1304
bc49bfd8
JB		 13052020-03-06 Jan Beulich <jbeulich@suse.com>
1306
1307 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1308 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1309 register and memory source templates. Replace VexW= by VexW*
1310 where applicable.
1311 * i386-tbl.h: Re-generate.
1312
4873e243
JB		 13132020-03-06 Jan Beulich <jbeulich@suse.com>
1314
1315 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1316 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1317 * i386-tbl.h: Re-generate.
1318
672a349b
JB		 13192020-03-06 Jan Beulich <jbeulich@suse.com>
1320
1321 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1322 * i386-tbl.h: Re-generate.
1323
4ed21b58
JB		 13242020-03-06 Jan Beulich <jbeulich@suse.com>
1325
1326 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1327 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1328 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1329 VexW0 on SSE2AVX variants.
1330 (vmovq): Drop NoRex64 from XMM/XMM variants.
1331 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1332 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1333 applicable use VexW0.
1334 * i386-tbl.h: Re-generate.
1335
643bb870
JB		 13362020-03-06 Jan Beulich <jbeulich@suse.com>
1337
1338 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1339 * i386-opc.h (Rex64): Delete.
1340 (struct i386_opcode_modifier): Remove rex64 field.
1341 * i386-opc.tbl (crc32): Drop Rex64.
1342 Replace Rex64 with Size64 everywhere else.
1343 * i386-tbl.h: Re-generate.
1344
a23b33b3
JB		 13452020-03-06 Jan Beulich <jbeulich@suse.com>
1346
1347 * i386-dis.c (OP_E_memory): Exclude recording of used address
1348 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1349 addressed memory operands for MPX insns.
1350
a0497384
JB		 13512020-03-06 Jan Beulich <jbeulich@suse.com>
1352
1353 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1354 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1355 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1356 (ptwrite): Split into non-64-bit and 64-bit forms.
1357 * i386-tbl.h: Re-generate.
1358
b630c145
JB		 13592020-03-06 Jan Beulich <jbeulich@suse.com>
1360
1361 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1362 template.
1363 * i386-tbl.h: Re-generate.
1364
a847e322
JB		 13652020-03-04 Jan Beulich <jbeulich@suse.com>
1366
1367 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1368 (prefix_table): Move vmmcall here. Add vmgexit.
1369 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1370 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1371 (cpu_flags): Add CpuSEV_ES entry.
1372 * i386-opc.h (CpuSEV_ES): New.
1373 (union i386_cpu_flags): Add cpusev_es field.
1374 * i386-opc.tbl (vmgexit): New.
1375 * i386-init.h, i386-tbl.h: Re-generate.
1376
3cd7f3e3
L		 13772020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1378
1379 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1380 with MnemonicSize.
1381 * i386-opc.h (IGNORESIZE): New.
1382 (DEFAULTSIZE): Likewise.
1383 (IgnoreSize): Removed.
1384 (DefaultSize): Likewise.
1385 (MnemonicSize): New.
1386 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1387 mnemonicsize.
1388 * i386-opc.tbl (IgnoreSize): New.
1389 (DefaultSize): Likewise.
1390 * i386-tbl.h: Regenerated.
1391
b8ba1385
SB		 13922020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1393
1394 PR 25627
1395 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1396 instructions.
1397
10d97a0f
L		 13982020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1399
1400 PR gas/25622
1401 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1402 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1403 * i386-tbl.h: Regenerated.
1404
dc1e8a47
AM		 14052020-02-26 Alan Modra <amodra@gmail.com>
1406
1407 * aarch64-asm.c: Indent labels correctly.
1408 * aarch64-dis.c: Likewise.
1409 * aarch64-gen.c: Likewise.
1410 * aarch64-opc.c: Likewise.
1411 * alpha-dis.c: Likewise.
1412 * i386-dis.c: Likewise.
1413 * nds32-asm.c: Likewise.
1414 * nfp-dis.c: Likewise.
1415 * visium-dis.c: Likewise.
1416
265b4673
CZ		 14172020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1418
1419 * arc-regs.h (int_vector_base): Make it available for all ARC
1420 CPUs.
1421
bd0cf5a6
NC		 14222020-02-20 Nelson Chu <nelson.chu@sifive.com>
1423
1424 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1425 changed.
1426
fa164239
JW		 14272020-02-19 Nelson Chu <nelson.chu@sifive.com>
1428
1429 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1430 c.mv/c.li if rs1 is zero.
1431
272a84b1
L		 14322020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1433
1434 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1435 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1436 CPU_POPCNT_FLAGS.
1437 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1438 * i386-opc.h (CpuABM): Removed.
1439 (CpuPOPCNT): New.
1440 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1441 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1442 popcnt. Remove CpuABM from lzcnt.
1443 * i386-init.h: Regenerated.
1444 * i386-tbl.h: Likewise.
1445
1f730c46
JB		 14462020-02-17 Jan Beulich <jbeulich@suse.com>
1447
1448 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1449 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1450 VexW1 instead of open-coding them.
1451 * i386-tbl.h: Re-generate.
1452
c8f8eebc
JB		 14532020-02-17 Jan Beulich <jbeulich@suse.com>
1454
1455 * i386-opc.tbl (AddrPrefixOpReg): Define.
1456 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1457 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1458 templates. Drop NoRex64.
1459 * i386-tbl.h: Re-generate.
1460
b9915cbc
JB		 14612020-02-17 Jan Beulich <jbeulich@suse.com>
1462
1463 PR gas/6518
1464 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1465 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1466 into Intel syntax instance (with Unpsecified) and AT&T one
1467 (without).
1468 (vcvtneps2bf16): Likewise, along with folding the two so far
1469 separate ones.
1470 * i386-tbl.h: Re-generate.
1471
ce504911
L		 14722020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1473
1474 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1475 CPU_ANY_SSE4A_FLAGS.
1476
dabec65d
AM		 14772020-02-17 Alan Modra <amodra@gmail.com>
1478
1479 * i386-gen.c (cpu_flag_init): Correct last change.
1480
af5c13b0
L		 14812020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1482
1483 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1484 CPU_ANY_SSE4_FLAGS.
1485
6867aac0
L		 14862020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1487
1488 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1489 (movzx): Likewise.
1490
65fca059
JB		 14912020-02-14 Jan Beulich <jbeulich@suse.com>
1492
1493 PR gas/25438
1494 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1495 destination for Cpu64-only variant.
1496 (movzx): Fold patterns.
1497 * i386-tbl.h: Re-generate.
1498
7deea9aa
JB		 14992020-02-13 Jan Beulich <jbeulich@suse.com>
1500
1501 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1502 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1503 CPU_ANY_SSE4_FLAGS entry.
1504 * i386-init.h: Re-generate.
1505
6c0946d0
JB		 15062020-02-12 Jan Beulich <jbeulich@suse.com>
1507
1508 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1509 with Unspecified, making the present one AT&T syntax only.
1510 * i386-tbl.h: Re-generate.
1511
ddb56fe6
JB		 15122020-02-12 Jan Beulich <jbeulich@suse.com>
1513
1514 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1515 * i386-tbl.h: Re-generate.
1516
5990e377
JB		 15172020-02-12 Jan Beulich <jbeulich@suse.com>
1518
1519 PR gas/24546
1520 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1521 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1522 Amd64 and Intel64 templates.
1523 (call, jmp): Likewise for far indirect variants. Dro
1524 Unspecified.
1525 * i386-tbl.h: Re-generate.
1526
50128d0c
JB		 15272020-02-11 Jan Beulich <jbeulich@suse.com>
1528
1529 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1530 * i386-opc.h (ShortForm): Delete.
1531 (struct i386_opcode_modifier): Remove shortform field.
1532 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1533 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1534 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1535 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1536 Drop ShortForm.
1537 * i386-tbl.h: Re-generate.
1538
1e05b5c4
JB		 15392020-02-11 Jan Beulich <jbeulich@suse.com>
1540
1541 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1542 fucompi): Drop ShortForm from operand-less templates.
1543 * i386-tbl.h: Re-generate.
1544
2f5dd314
AM		 15452020-02-11 Alan Modra <amodra@gmail.com>
1546
1547 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1548 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1549 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1550 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1551 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1552
5aae9ae9
MM		 15532020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1554
1555 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1556 (cde_opcodes): Add VCX* instructions.
1557
4934a27c
MM		 15582020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1559 Matthew Malcomson <matthew.malcomson@arm.com>
1560
1561 * arm-dis.c (struct cdeopcode32): New.
1562 (CDE_OPCODE): New macro.
1563 (cde_opcodes): New disassembly table.
1564 (regnames): New option to table.
1565 (cde_coprocs): New global variable.
1566 (print_insn_cde): New
1567 (print_insn_thumb32): Use print_insn_cde.
1568 (parse_arm_disassembler_options): Parse coprocN args.
1569
4b5aaf5f
L		 15702020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1571
1572 PR gas/25516
1573 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1574 with ISA64.
1575 * i386-opc.h (AMD64): Removed.
1576 (Intel64): Likewose.
1577 (AMD64): New.
1578 (INTEL64): Likewise.
1579 (INTEL64ONLY): Likewise.
1580 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1581 * i386-opc.tbl (Amd64): New.
1582 (Intel64): Likewise.
1583 (Intel64Only): Likewise.
1584 Replace AMD64 with Amd64. Update sysenter/sysenter with
1585 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1586 * i386-tbl.h: Regenerated.
1587
9fc0b501
SB		 15882020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1589
1590 PR 25469
1591 * z80-dis.c: Add support for GBZ80 opcodes.
1592
c5d7be0c
AM		 15932020-02-04 Alan Modra <amodra@gmail.com>
1594
1595 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1596
44e4546f
AM		 15972020-02-03 Alan Modra <amodra@gmail.com>
1598
1599 * m32c-ibld.c: Regenerate.
1600
b2b1453a
AM		 16012020-02-01 Alan Modra <amodra@gmail.com>
1602
1603 * frv-ibld.c: Regenerate.
1604
4102be5c
JB		 16052020-01-31 Jan Beulich <jbeulich@suse.com>
1606
1607 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1608 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1609 (OP_E_memory): Replace xmm_mdq_mode case label by
1610 vex_scalar_w_dq_mode one.
1611 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1612
825bd36c
JB		 16132020-01-31 Jan Beulich <jbeulich@suse.com>
1614
1615 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1616 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1617 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1618 (intel_operand_size): Drop vex_w_dq_mode case label.
1619
c3036ed0
RS		 16202020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1621
1622 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1623 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1624
0c115f84
AM		 16252020-01-30 Alan Modra <amodra@gmail.com>
1626
1627 * m32c-ibld.c: Regenerate.
1628
bd434cc4
JM		 16292020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1630
1631 * bpf-opc.c: Regenerate.
1632
aeab2b26
JB		 16332020-01-30 Jan Beulich <jbeulich@suse.com>
1634
1635 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1636 (dis386): Use them to replace C2/C3 table entries.
1637 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1638 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1639 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1640 * i386-tbl.h: Re-generate.
1641
62b3f548
JB		 16422020-01-30 Jan Beulich <jbeulich@suse.com>
1643
1644 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1645 forms.
1646 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1647 DefaultSize.
1648 * i386-tbl.h: Re-generate.
1649
1bd8ae10
AM		 16502020-01-30 Alan Modra <amodra@gmail.com>
1651
1652 * tic4x-dis.c (tic4x_dp): Make unsigned.
1653
bc31405e
L		 16542020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1655 Jan Beulich <jbeulich@suse.com>
1656
1657 PR binutils/25445
1658 * i386-dis.c (MOVSXD_Fixup): New function.
1659 (movsxd_mode): New enum.
1660 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1661 (intel_operand_size): Handle movsxd_mode.
1662 (OP_E_register): Likewise.
1663 (OP_G): Likewise.
1664 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1665 register on movsxd. Add movsxd with 16-bit destination register
1666 for AMD64 and Intel64 ISAs.
1667 * i386-tbl.h: Regenerated.
1668
7568c93b
TC		 16692020-01-27 Tamar Christina <tamar.christina@arm.com>
1670
1671 PR 25403
1672 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1673 * aarch64-asm-2.c: Regenerate
1674 * aarch64-dis-2.c: Likewise.
1675 * aarch64-opc-2.c: Likewise.
1676
c006a730
JB		 16772020-01-21 Jan Beulich <jbeulich@suse.com>
1678
1679 * i386-opc.tbl (sysret): Drop DefaultSize.
1680 * i386-tbl.h: Re-generate.
1681
c906a69a
JB		 16822020-01-21 Jan Beulich <jbeulich@suse.com>
1683
1684 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1685 Dword.
1686 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1687 * i386-tbl.h: Re-generate.
1688
26916852
NC		 16892020-01-20 Nick Clifton <nickc@redhat.com>
1690
1691 * po/de.po: Updated German translation.
1692 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1693 * po/uk.po: Updated Ukranian translation.
1694
4d6cbb64
AM		 16952020-01-20 Alan Modra <amodra@gmail.com>
1696
1697 * hppa-dis.c (fput_const): Remove useless cast.
1698
2bddb71a
AM		 16992020-01-20 Alan Modra <amodra@gmail.com>
1700
1701 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1702
1b1bb2c6
NC		 17032020-01-18 Nick Clifton <nickc@redhat.com>
1704
1705 * configure: Regenerate.
1706 * po/opcodes.pot: Regenerate.
1707
ae774686
NC		 17082020-01-18 Nick Clifton <nickc@redhat.com>
1709
1710 Binutils 2.34 branch created.
1711
07f1f3aa
CB		 17122020-01-17 Christian Biesinger <cbiesinger@google.com>
1713
1714 * opintl.h: Fix spelling error (seperate).
1715
42e04b36
L		 17162020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1717
1718 * i386-opc.tbl: Add {vex} pseudo prefix.
1719 * i386-tbl.h: Regenerated.
1720
2da2eaf4
AV		 17212020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1722
1723 PR 25376
1724 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1725 (neon_opcodes): Likewise.
1726 (select_arm_features): Make sure we enable MVE bits when selecting
1727 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1728 any architecture.
1729
d0849eed
JB		 17302020-01-16 Jan Beulich <jbeulich@suse.com>
1731
1732 * i386-opc.tbl: Drop stale comment from XOP section.
1733
9cf70a44
JB		 17342020-01-16 Jan Beulich <jbeulich@suse.com>
1735
1736 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1737 (extractps): Add VexWIG to SSE2AVX forms.
1738 * i386-tbl.h: Re-generate.
1739
4814632e
JB		 17402020-01-16 Jan Beulich <jbeulich@suse.com>
1741
1742 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1743 Size64 from and use VexW1 on SSE2AVX forms.
1744 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1745 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1746 * i386-tbl.h: Re-generate.
1747
aad09917
AM		 17482020-01-15 Alan Modra <amodra@gmail.com>
1749
1750 * tic4x-dis.c (tic4x_version): Make unsigned long.
1751 (optab, optab_special, registernames): New file scope vars.
1752 (tic4x_print_register): Set up registernames rather than
1753 malloc'd registertable.
1754 (tic4x_disassemble): Delete optable and optable_special. Use
1755 optab and optab_special instead. Throw away old optab,
1756 optab_special and registernames when info->mach changes.
1757
7a6bf3be
SB		 17582020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1759
1760 PR 25377
1761 * z80-dis.c (suffix): Use .db instruction to generate double
1762 prefix.
1763
ca1eaac0
AM		 17642020-01-14 Alan Modra <amodra@gmail.com>
1765
1766 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1767 values to unsigned before shifting.
1768
1d67fe3b
TT		 17692020-01-13 Thomas Troeger <tstroege@gmx.de>
1770
1771 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1772 flow instructions.
1773 (print_insn_thumb16, print_insn_thumb32): Likewise.
1774 (print_insn): Initialize the insn info.
1775 * i386-dis.c (print_insn): Initialize the insn info fields, and
1776 detect jumps.
1777
5e4f7e05
CZ		 17782012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1779
1780 * arc-opc.c (C_NE): Make it required.
1781
b9fe6b8a
CZ		 17822012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1783
1784 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1785 reserved register name.
1786
90dee485
AM		 17872020-01-13 Alan Modra <amodra@gmail.com>
1788
1789 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1790 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1791
febda64f
AM		 17922020-01-13 Alan Modra <amodra@gmail.com>
1793
1794 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1795 result of wasm_read_leb128 in a uint64_t and check that bits
1796 are not lost when copying to other locals. Use uint32_t for
1797 most locals. Use PRId64 when printing int64_t.
1798
df08b588
AM		 17992020-01-13 Alan Modra <amodra@gmail.com>
1800
1801 * score-dis.c: Formatting.
1802 * score7-dis.c: Formatting.
1803
b2c759ce
AM		 18042020-01-13 Alan Modra <amodra@gmail.com>
1805
1806 * score-dis.c (print_insn_score48): Use unsigned variables for
1807 unsigned values. Don't left shift negative values.
1808 (print_insn_score32): Likewise.
1809 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1810
5496abe1
AM		 18112020-01-13 Alan Modra <amodra@gmail.com>
1812
1813 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1814
202e762b
AM		 18152020-01-13 Alan Modra <amodra@gmail.com>
1816
1817 * fr30-ibld.c: Regenerate.
1818
7ef412cf
AM		 18192020-01-13 Alan Modra <amodra@gmail.com>
1820
1821 * xgate-dis.c (print_insn): Don't left shift signed value.
1822 (ripBits): Formatting, use 1u.
1823
7f578b95
AM		 18242020-01-10 Alan Modra <amodra@gmail.com>
1825
1826 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1827 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1828
441af85b
AM		 18292020-01-10 Alan Modra <amodra@gmail.com>
1830
1831 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1832 and XRREG value earlier to avoid a shift with negative exponent.
1833 * m10200-dis.c (disassemble): Similarly.
1834
bce58db4
NC		 18352020-01-09 Nick Clifton <nickc@redhat.com>
1836
1837 PR 25224
1838 * z80-dis.c (ld_ii_ii): Use correct cast.
1839
40c75bc8
SB		 18402020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1841
1842 PR 25224
1843 * z80-dis.c (ld_ii_ii): Use character constant when checking
1844 opcode byte value.
1845
d835a58b
JB		 18462020-01-09 Jan Beulich <jbeulich@suse.com>
1847
1848 * i386-dis.c (SEP_Fixup): New.
1849 (SEP): Define.
1850 (dis386_twobyte): Use it for sysenter/sysexit.
1851 (enum x86_64_isa): Change amd64 enumerator to value 1.
1852 (OP_J): Compare isa64 against intel64 instead of amd64.
1853 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1854 forms.
1855 * i386-tbl.h: Re-generate.
1856
030a2e78
AM		 18572020-01-08 Alan Modra <amodra@gmail.com>
1858
1859 * z8k-dis.c: Include libiberty.h
1860 (instr_data_s): Make max_fetched unsigned.
1861 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1862 Don't exceed byte_info bounds.
1863 (output_instr): Make num_bytes unsigned.
1864 (unpack_instr): Likewise for nibl_count and loop.
1865 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1866 idx unsigned.
1867 * z8k-opc.h: Regenerate.
1868
bb82aefe
SV		 18692020-01-07 Shahab Vahedi <shahab@synopsys.com>
1870
1871 * arc-tbl.h (llock): Use 'LLOCK' as class.
1872 (llockd): Likewise.
1873 (scond): Use 'SCOND' as class.
1874 (scondd): Likewise.
1875 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1876 (scondd): Likewise.
1877
cc6aa1a6
AM		 18782020-01-06 Alan Modra <amodra@gmail.com>
1879
1880 * m32c-ibld.c: Regenerate.
1881
660e62b1
AM		 18822020-01-06 Alan Modra <amodra@gmail.com>
1883
1884 PR 25344
1885 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1886 Peek at next byte to prevent recursion on repeated prefix bytes.
1887 Ensure uninitialised "mybuf" is not accessed.
1888 (print_insn_z80): Don't zero n_fetch and n_used here,..
1889 (print_insn_z80_buf): ..do it here instead.
1890
c9ae58fe
AM		 18912020-01-04 Alan Modra <amodra@gmail.com>
1892
1893 * m32r-ibld.c: Regenerate.
1894
5f57d4ec
AM		 18952020-01-04 Alan Modra <amodra@gmail.com>
1896
1897 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1898
2c5c1196
AM		 18992020-01-04 Alan Modra <amodra@gmail.com>
1900
1901 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1902
2e98c6c5
AM		 19032020-01-04 Alan Modra <amodra@gmail.com>
1904
1905 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1906
567dfba2
JB		 19072020-01-03 Jan Beulich <jbeulich@suse.com>
1908
5437a02a
JB		 1909 * aarch64-tbl.h (aarch64_opcode_table): Use
1910 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1911
19122020-01-03 Jan Beulich <jbeulich@suse.com>
1913
1914 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1915 forms of SUDOT and USDOT.
1916
8c45011a
JB		 19172020-01-03 Jan Beulich <jbeulich@suse.com>
1918
5437a02a 1919 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1920 uzip{1,2}.
1921 * opcodes/aarch64-dis-2.c: Re-generate.
1922
f4950f76
JB		 19232020-01-03 Jan Beulich <jbeulich@suse.com>
1924
5437a02a 1925 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1926 FMMLA encoding.
1927 * opcodes/aarch64-dis-2.c: Re-generate.
1928
6655dba2
SB		 19292020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1930
1931 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1932
b14ce8bf
AM		 19332020-01-01 Alan Modra <amodra@gmail.com>
1934
1935 Update year range in copyright notice of all files.
1936
0b114740 1937For older changes see ChangeLog-2019
3499769a 1938\f
0b114740 1939Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1940
1941Copying and distribution of this file, with or without modification,
1942are permitted in any medium without royalty provided the copyright
1943notice and this notice are preserved.
1944
1945Local Variables:
1946mode: change-log
1947left-margin: 8
1948fill-column: 74
1949version-control: never
1950End:
GDB Binutils - Deliverables
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