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2008-09-30 H.J. Lu <hongjiu.lu@intel.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
c587b3f9
L		 12008-09-30 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-gen.c: Include "hashtab.h".
4 (next_field): Take a new argument, last. Check last.
5 (process_i386_cpu_flag): Updated.
6 (process_i386_opcode_modifier): Likewise.
7 (process_i386_operand_type): Likewise.
8 (process_i386_registers): Likewise.
9 (output_i386_opcode): New.
10 (opcode_hash_entry): Likewise.
11 (opcode_hash_table): Likewise.
12 (opcode_hash_hash): Likewise.
13 (opcode_hash_eq): Likewise.
14 (process_i386_opcodes): Use opcode hash table and opcode array.
15
34b23dab
AK		 162008-09-30 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
17
18 * s390-opc.txt (stdy, stey): Fix description
19
782e11fd
AM		 202008-09-30 Alan Modra <amodra@bigpond.net.au>
21
22 * Makefile.am: Run "make dep-am".
23 * Makefile.in: Regenerate.
24
1927a18f
L		 252008-09-29 H.J. Lu <hongjiu.lu@intel.com>
26
27 * aclocal.m4: Regenerated.
28 * configure: Likewise.
29 * Makefile.in: Likewise.
30
afac680a
NC		 312008-09-29 Nick Clifton <nickc@redhat.com>
32
33 * po/vi.po: Updated Vietnamese translation.
34 * po/fr.po: Updated French translation.
35
b40d5eb9
AK		 362008-09-26 Florian Krohm <fkrohm@us.ibm.com>
37
38 * s390-opc.txt (thder, thdr): Change RRE_RR to RRE_FF.
39 (cfxr, cfdr, cfer, clclu): Add esa flag.
40 (sqd): Instruction added.
41 (qadtr, qaxtr): Change RRF_FFFU to RRF_FUFF.
42 * s390-opc.c: (INSTR_RRF_FFFU, MASK_RRF_FFFU): Removed.
43
d0411736
AM		 442008-09-14 Arnold Metselaar <arnold.metselaar@planet.nl>
45
46 * z80-dis.c (prt_rr_nn): Fix register pair for two byte opcodes.
47 (tab_elt opc_ed): Add "ld r,a" and "ld r,a" instructions.
48
3e126784
L		 492008-09-11 H.J. Lu <hongjiu.lu@intel.com>
50
51 * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd].
52 * i386-tbl.h: Regenerated.
53
ddab3d59
JB		 542008-08-28 Jan Beulich <jbeulich@novell.com>
55
56 * i386-dis.c (dis386): Adjust far return mnemonics.
57 * i386-opc.tbl: Add retf.
58 * i386-tbl.h: Re-generate.
59
b19d5385
JB		 602008-08-28 Jan Beulich <jbeulich@novell.com>
61
62 * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics.
63
1ca35711
L		 642008-08-28 H.J. Lu <hongjiu.lu@intel.com>
65
66 * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1.
67 * ia64-gen.c (lookup_specifier): Likewise.
68
69 * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1.
70 * ia64-raw.tbl: Likewise.
71 * ia64-waw.tbl: Likewise.
72 * ia64-asmtab.c: Regenerated.
73
515c56e7
L		 742008-08-27 H.J. Lu <hongjiu.lu@intel.com>
75
76 * i386-opc.tbl: Correct fidivr operand size.
77
78 * i386-tbl.h: Regenerated.
79
da594c4a
AM		 802008-08-24 Alan Modra <amodra@bigpond.net.au>
81
82 * configure.in: Update a number of obsolete autoconf macros.
83 * aclocal.m4: Regenerate.
84
a5ff0eb2
L		 852008-08-20 H.J. Lu <hongjiu.lu@intel.com>
86
87 AVX Programming Reference (August, 2008)
88 * i386-dis.c (PREFIX_VEX_38DB): New.
89 (PREFIX_VEX_38DC): Likewise.
90 (PREFIX_VEX_38DD): Likewise.
91 (PREFIX_VEX_38DE): Likewise.
92 (PREFIX_VEX_38DF): Likewise.
93 (PREFIX_VEX_3ADF): Likewise.
94 (VEX_LEN_38DB_P_2): Likewise.
95 (VEX_LEN_38DC_P_2): Likewise.
96 (VEX_LEN_38DD_P_2): Likewise.
97 (VEX_LEN_38DE_P_2): Likewise.
98 (VEX_LEN_38DF_P_2): Likewise.
99 (VEX_LEN_3ADF_P_2): Likewise.
100 (PREFIX_VEX_3A04): Updated.
101 (VEX_LEN_3A06_P_2): Likewise.
102 (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC,
103 PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF.
104 (x86_64_table): Likewise.
105 (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2,
106 VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and
107 VEX_LEN_3ADF_P_2.
108
109 * i386-opc.tbl: Add AES + AVX instructions.
110 * i386-init.h: Regenerated.
111 * i386-tbl.h: Likewise.
112
7dc6076f
AK		 1132008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
114
115 * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
116 * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.
117
7357c5b6
AM		 1182008-08-15 Alan Modra <amodra@bigpond.net.au>
119
120 PR 6526
121 * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
122 * Makefile.in: Regenerate.
123 * aclocal.m4: Regenerate.
124 * config.in: Regenerate.
125 * configure: Regenerate.
126
899d85be
AM		 1272008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
128
129 PR 6825
130 * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
131
dfb07592
L		 1322008-08-12 H.J. Lu <hongjiu.lu@intel.com>
133
134 * i386-opc.tbl: Add syscall and sysret for Cpu64.
135
136 * i386-tbl.h: Regenerated.
137
323ee3f4
AM		 1382008-08-04 Alan Modra <amodra@bigpond.net.au>
139
140 * Makefile.am (POTFILES.in): Set LC_ALL=C.
141 * Makefile.in: Regenerate.
142 * po/POTFILES.in: Regenerate.
143
9b4e5766
PB		 1442008-08-01 Peter Bergner <bergner@vnet.ibm.com>
145
146 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
147 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
148 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
149 * ppc-opc.c (insert_xt6): New static function.
150 (extract_xt6): Likewise.
151 (insert_xa6): Likewise.
152 (extract_xa6: Likewise.
153 (insert_xb6): Likewise.
154 (extract_xb6): Likewise.
155 (insert_xb6s): Likewise.
156 (extract_xb6s): Likewise.
157 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
158 XX3DM_MASK, PPCVSX): New.
159 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
160 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
161
20fd6e2e
PA		 1622008-08-01 Pedro Alves <pedro@codesourcery.com>
163
164 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
165 * Makefile.in: Regenerate.
166
a656ed5b
L		 1672008-08-01 H.J. Lu <hongjiu.lu@intel.com>
168
169 * i386-reg.tbl: Use Dw2Inval on AVX registers.
170 * i386-tbl.h: Regenerated.
171
081ba1b3
AM		 1722008-07-30 Michael J. Eager <eager@eagercon.com>
173
174 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
175 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
176 (insert_sprg, PPC405): Use PPC_OPCODE_405.
177 (powerpc_opcodes): Add Xilinx APU related opcodes.
178
0af1713e
AM		 1792008-07-30 Alan Modra <amodra@bigpond.net.au>
180
181 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
182
30c09090
RS		 1832008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
184
185 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
186
c27e721e
AN		 1872008-07-07 Adam Nemet <anemet@caviumnetworks.com>
188
189 * mips-opc.c (CP): New macro.
190 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
191 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
192 dmtc2 Octeon instructions.
193
bd2e2557
SS		 1942008-07-07 Stan Shebs <stan@codesourcery.com>
195
196 * dis-init.c (init_disassemble_info): Init endian_code field.
197 * arm-dis.c (print_insn): Disassemble code according to
198 setting of endian_code.
199 (print_insn_big_arm): Detect when BE8 extension flag has been set.
200
6ba2a415
RS		 2012008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
202
203 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
204 for ELF symbols.
205
c8187e15
PB		 2062008-06-25 Peter Bergner <bergner@vnet.ibm.com>
207
208 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
209 (print_ppc_disassembler_options): Likewise.
210 * ppc-opc.c (PPC464): Define.
211 (powerpc_opcodes): Add mfdcrux and mtdcrux.
212
7a283e07
RW		 2132008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
214
215 * configure: Regenerate.
216
fa452fa6
PB		 2172008-06-13 Peter Bergner <bergner@vnet.ibm.com>
218
219 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
220 ppc_cpu_t typedef.
221 (struct dis_private): New.
222 (POWERPC_DIALECT): New define.
223 (powerpc_dialect): Renamed to...
224 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
225 struct dis_private.
226 (print_insn_big_powerpc): Update for using structure in
227 info->private_data.
228 (print_insn_little_powerpc): Likewise.
229 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
230 (skip_optional_operands): Likewise.
231 (print_insn_powerpc): Likewise. Remove initialization of dialect.
232 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
233 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
234 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
235 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
236 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
237 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
238 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
239 param to be of type ppc_cpu_t. Update prototype.
240
bb35fb24
NC		 2412008-06-12 Adam Nemet <anemet@caviumnetworks.com>
242
243 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
244 +s, +S.
245 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
246 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
247 syncw, syncws, vm3mulu, vm0 and vmulu.
248
dd3cbb7e
NC		 249 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
250 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
251 seqi, sne and snei.
252
a5dabbb0
L		 2532008-05-30 H.J. Lu <hongjiu.lu@intel.com>
254
255 * i386-opc.tbl: Add vmovd with 64bit operand.
256 * i386-tbl.h: Regenerated.
257
725a9891
MS		 2582008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
259
260 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
261
cbc80391
L		 2622008-05-22 H.J. Lu <hongjiu.lu@intel.com>
263
264 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
265 * i386-tbl.h: Regenerated.
266
116615c5
L		 2672008-05-22 H.J. Lu <hongjiu.lu@intel.com>
268
269 PR gas/6517
270 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
271 into 32bit and 64bit. Remove Reg64|Qword and add
272 IgnoreSize|No_qSuf on 32bit version.
273 * i386-tbl.h: Regenerated.
274
d9479f2d
L		 2752008-05-21 H.J. Lu <hongjiu.lu@intel.com>
276
277 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
278 * i386-tbl.h: Regenerated.
279
3ce6fddb
NC		 2802008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
281
282 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
283
8944f3c2
AM		 2842008-05-14 Alan Modra <amodra@bigpond.net.au>
285
286 * Makefile.am: Run "make dep-am".
287 * Makefile.in: Regenerate.
288
f1f8f695
L		 2892008-05-02 H.J. Lu <hongjiu.lu@intel.com>
290
291 * i386-dis.c (MOVBE_Fixup): New.
292 (Mo): Likewise.
293 (PREFIX_0F3880): Likewise.
294 (PREFIX_0F3881): Likewise.
295 (PREFIX_0F38F0): Updated.
296 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
297 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
298 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
299
300 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
301 CPU_EPT_FLAGS.
302 (cpu_flags): Add CpuMovbe and CpuEPT.
303
304 * i386-opc.h (CpuMovbe): New.
305 (CpuEPT): Likewise.
306 (CpuLM): Updated.
307 (i386_cpu_flags): Add cpumovbe and cpuept.
308
309 * i386-opc.tbl: Add entries for movbe and EPT instructions.
310 * i386-init.h: Regenerated.
311 * i386-tbl.h: Likewise.
312
89aa3097
AN		 3132008-04-29 Adam Nemet <anemet@caviumnetworks.com>
314
315 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
316 the two drem and the two dremu macros.
317
39c5c168
AN		 3182008-04-28 Adam Nemet <anemet@caviumnetworks.com>
319
320 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
321 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
322 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
323 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
324
f04d18b7
DM		 3252008-04-25 David S. Miller <davem@davemloft.net>
326
327 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
328 instead of %sys_tick_cmpr, as suggested in architecture manuals.
329
6194aaab
L		 3302008-04-23 Paolo Bonzini <bonzini@gnu.org>
331
332 * aclocal.m4: Regenerate.
333 * configure: Regenerate.
334
1a6b486f
DM		 3352008-04-23 David S. Miller <davem@davemloft.net>
336
337 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
338 extended values.
339 (prefetch_table): Add missing values.
340
81f8a913
L		 3412008-04-22 H.J. Lu <hongjiu.lu@intel.com>
342
343 * i386-gen.c (opcode_modifiers): Add NoAVX.
344
345 * i386-opc.h (NoAVX): New.
346 (OldGcc): Updated.
347 (i386_opcode_modifier): Add noavx.
348
349 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
350 instructions which don't have AVX equivalent.
351 * i386-tbl.h: Regenerated.
352
dae39acc
L		 3532008-04-18 H.J. Lu <hongjiu.lu@intel.com>
354
355 * i386-dis.c (OP_VEX_FMA): New.
356 (OP_EX_VexImmW): Likewise.
357 (VexFMA): Likewise.
358 (Vex128FMA): Likewise.
359 (EXVexImmW): Likewise.
360 (get_vex_imm8): Likewise.
361 (OP_EX_VexReg): Likewise.
362 (vex_i4_done): Renamed to ...
363 (vex_w_done): This.
364 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
365 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
366 FMA instructions.
367 (print_insn): Updated.
368 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
369 (OP_REG_VexI4): Check invalid high registers.
370
ce886ab1
DR		 3712008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
372 Michael Meissner <michael.meissner@amd.com>
373
374 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
375 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 376
19a6653c
AM		 3772008-04-14 Edmar Wienskoski <edmar@freescale.com>
378
379 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
380 accept Power E500MC instructions.
381 (print_ppc_disassembler_options): Document -Me500mc.
382 * ppc-opc.c (DUIS, DUI, T): New.
383 (XRT, XRTRA): Likewise.
384 (E500MC): Likewise.
385 (powerpc_opcodes): Add new Power E500MC instructions.
386
112b7c50
AK		 3872008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
388
389 * s390-dis.c (init_disasm): Evaluate disassembler_options.
390 (print_s390_disassembler_options): New function.
391 * disassemble.c (disassembler_usage): Invoke
392 print_s390_disassembler_options.
393
7ff42648
AK		 3942008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
395
396 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
397 of local variables used for mnemonic parsing: prefix, suffix and
398 number.
399
45a5551e
AK		 4002008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
401
402 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
403 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
404 (s390_crb_extensions): New extensions table.
405 (insertExpandedMnemonic): Handle '$' tag.
406 * s390-opc.txt: Remove conditional jump variants which can now
407 be expanded automatically.
408 Replace '*' tag with '$' in the compare and branch instructions.
409
06c8514a
L		 4102008-04-07 H.J. Lu <hongjiu.lu@intel.com>
411
412 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
413 (PREFIX_VEX_3AXX): Likewis.
414
b122c285
L		 4152008-04-07 H.J. Lu <hongjiu.lu@intel.com>
416
417 * i386-opc.tbl: Remove 4 extra blank lines.
418
594ab6a3
L		 4192008-04-04 H.J. Lu <hongjiu.lu@intel.com>
420
421 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
422 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
423 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
424 * i386-opc.tbl: Likewise.
425
426 * i386-opc.h (CpuCLMUL): Renamed to ...
427 (CpuPCLMUL): This.
428 (CpuFMA): Updated.
429 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
430
431 * i386-init.h: Regenerated.
432
c0f3af97
L		 4332008-04-03 H.J. Lu <hongjiu.lu@intel.com>
434
435 * i386-dis.c (OP_E_register): New.
436 (OP_E_memory): Likewise.
437 (OP_VEX): Likewise.
438 (OP_EX_Vex): Likewise.
439 (OP_EX_VexW): Likewise.
440 (OP_XMM_Vex): Likewise.
441 (OP_XMM_VexW): Likewise.
442 (OP_REG_VexI4): Likewise.
443 (PCLMUL_Fixup): Likewise.
444 (VEXI4_Fixup): Likewise.
445 (VZERO_Fixup): Likewise.
446 (VCMP_Fixup): Likewise.
447 (VPERMIL2_Fixup): Likewise.
448 (rex_original): Likewise.
449 (rex_ignored): Likewise.
450 (Mxmm): Likewise.
451 (XMM): Likewise.
452 (EXxmm): Likewise.
453 (EXxmmq): Likewise.
454 (EXymmq): Likewise.
455 (Vex): Likewise.
456 (Vex128): Likewise.
457 (Vex256): Likewise.
458 (VexI4): Likewise.
459 (EXdVex): Likewise.
460 (EXqVex): Likewise.
461 (EXVexW): Likewise.
462 (EXdVexW): Likewise.
463 (EXqVexW): Likewise.
464 (XMVex): Likewise.
465 (XMVexW): Likewise.
466 (XMVexI4): Likewise.
467 (PCLMUL): Likewise.
468 (VZERO): Likewise.
469 (VCMP): Likewise.
470 (VPERMIL2): Likewise.
471 (xmm_mode): Likewise.
472 (xmmq_mode): Likewise.
473 (ymmq_mode): Likewise.
474 (vex_mode): Likewise.
475 (vex128_mode): Likewise.
476 (vex256_mode): Likewise.
477 (USE_VEX_C4_TABLE): Likewise.
478 (USE_VEX_C5_TABLE): Likewise.
479 (USE_VEX_LEN_TABLE): Likewise.
480 (VEX_C4_TABLE): Likewise.
481 (VEX_C5_TABLE): Likewise.
482 (VEX_LEN_TABLE): Likewise.
483 (REG_VEX_XX): Likewise.
484 (MOD_VEX_XXX): Likewise.
485 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
486 (PREFIX_0F3A44): Likewise.
487 (PREFIX_0F3ADF): Likewise.
488 (PREFIX_VEX_XXX): Likewise.
489 (VEX_OF): Likewise.
490 (VEX_OF38): Likewise.
491 (VEX_OF3A): Likewise.
492 (VEX_LEN_XXX): Likewise.
493 (vex): Likewise.
494 (need_vex): Likewise.
495 (need_vex_reg): Likewise.
496 (vex_i4_done): Likewise.
497 (vex_table): Likewise.
498 (vex_len_table): Likewise.
499 (OP_REG_VexI4): Likewise.
500 (vex_cmp_op): Likewise.
501 (pclmul_op): Likewise.
502 (vpermil2_op): Likewise.
503 (m_mode): Updated.
504 (es_reg): Likewise.
505 (PREFIX_0F38F0): Likewise.
506 (PREFIX_0F3A60): Likewise.
507 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
508 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
509 and PREFIX_VEX_XXX entries.
510 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
511 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
512 PREFIX_0F3ADF.
513 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
514 Add MOD_VEX_XXX entries.
515 (ckprefix): Initialize rex_original and rex_ignored. Store the
516 REX byte in rex_original.
517 (get_valid_dis386): Handle the implicit prefix in VEX prefix
518 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
519 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
520 calling get_valid_dis386. Use rex_original and rex_ignored when
521 printing out REX.
522 (putop): Handle "XY".
523 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
524 ymmq_mode.
525 (OP_E_extended): Updated to use OP_E_register and
526 OP_E_memory.
527 (OP_XMM): Handle VEX.
528 (OP_EX): Likewise.
529 (XMM_Fixup): Likewise.
530 (CMP_Fixup): Use ARRAY_SIZE.
531
532 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
533 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
534 (operand_type_init): Add OPERAND_TYPE_REGYMM and
535 OPERAND_TYPE_VEX_IMM4.
536 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
537 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
538 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
539 VexImmExt and SSE2AVX.
540 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
541
542 * i386-opc.h (CpuAVX): New.
543 (CpuAES): Likewise.
544 (CpuCLMUL): Likewise.
545 (CpuFMA): Likewise.
546 (Vex): Likewise.
547 (Vex256): Likewise.
548 (VexNDS): Likewise.
549 (VexNDD): Likewise.
550 (VexW0): Likewise.
551 (VexW1): Likewise.
552 (Vex0F): Likewise.
553 (Vex0F38): Likewise.
554 (Vex0F3A): Likewise.
555 (Vex3Sources): Likewise.
556 (VexImmExt): Likewise.
557 (SSE2AVX): Likewise.
558 (RegYMM): Likewise.
559 (Ymmword): Likewise.
560 (Vex_Imm4): Likewise.
561 (Implicit1stXmm0): Likewise.
562 (CpuXsave): Updated.
563 (CpuLM): Likewise.
564 (ByteOkIntel): Likewise.
565 (OldGcc): Likewise.
566 (Control): Likewise.
567 (Unspecified): Likewise.
568 (OTMax): Likewise.
569 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
570 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
571 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
572 vex3sources, veximmext and sse2avx.
573 (i386_operand_type): Add regymm, ymmword and vex_imm4.
574
575 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
576
577 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
578
579 * i386-init.h: Regenerated.
580 * i386-tbl.h: Likewise.
581
b21c9cb4
BS		 5822008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
583
584 From Robin Getz <robin.getz@analog.com>
585 * bfin-dis.c (bu32): Typedef.
586 (enum const_forms_t): Add c_uimm32 and c_huimm32.
587 (constant_formats[]): Add uimm32 and huimm16.
588 (fmtconst_val): New.
589 (uimm32): Define.
590 (huimm32): Define.
591 (imm16_val): Define.
592 (luimm16_val): Define.
593 (struct saved_state): Define.
594 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
595 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
596 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
597 (get_allreg): New.
598 (decode_LDIMMhalf_0): Print out the whole register value.
599
ee171c8f
BS		 600 From Jie Zhang <jie.zhang@analog.com>
601 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
602 multiply and multiply-accumulate to data register instruction.
603
086134ec
BS		 604 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
605 c_imm32, c_huimm32e): Define.
606 (constant_formats): Add flags for printing decimal, leading spaces, and
607 exact symbols.
608 (comment, parallel): Add global flags in all disassembly.
609 (fmtconst): Take advantage of new flags, and print default in hex.
610 (fmtconst_val): Likewise.
611 (decode_macfunc): Be consistant with spaces, tabs, comments,
612 capitalization in disassembly, fix minor coding style issues.
613 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
614 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
615 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
616 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
617 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
618 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
619 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
620 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
621 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
622 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
623 _print_insn_bfin, print_insn_bfin): Likewise.
624
58c85be7
RW		 6252008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
626
627 * aclocal.m4: Regenerate.
628 * configure: Likewise.
629 * Makefile.in: Likewise.
630
50e7d84b
AM		 6312008-03-13 Alan Modra <amodra@bigpond.net.au>
632
633 * Makefile.am: Run "make dep-am".
634 * Makefile.in: Regenerate.
635 * configure: Regenerate.
636
de866fcc
AM		 6372008-03-07 Alan Modra <amodra@bigpond.net.au>
638
639 * ppc-opc.c (powerpc_opcodes): Order and format.
640
28dbc079
L		 6412008-03-01 H.J. Lu <hongjiu.lu@intel.com>
642
643 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
644 * i386-tbl.h: Regenerated.
645
849830bd
L		 6462008-02-23 H.J. Lu <hongjiu.lu@intel.com>
647
648 * i386-opc.tbl: Disallow 16-bit near indirect branches for
649 x86-64.
650 * i386-tbl.h: Regenerated.
651
743ddb6b
JB		 6522008-02-21 Jan Beulich <jbeulich@novell.com>
653
654 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
655 and Fword for far indirect jmp. Allow Reg16 and Word for near
656 indirect jmp on x86-64. Disallow Fword for lcall.
657 * i386-tbl.h: Re-generate.
658
796d5313
NC		 6592008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
660
661 * cr16-opc.c (cr16_num_optab): Defined
662
65da13b5
L		 6632008-02-16 H.J. Lu <hongjiu.lu@intel.com>
664
665 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
666 * i386-init.h: Regenerated.
667
0e336180
NC		 6682008-02-14 Nick Clifton <nickc@redhat.com>
669
670 PR binutils/5524
671 * configure.in (SHARED_LIBADD): Select the correct host specific
672 file extension for shared libraries.
673 * configure: Regenerate.
674
b7240065
JB		 6752008-02-13 Jan Beulich <jbeulich@novell.com>
676
677 * i386-opc.h (RegFlat): New.
678 * i386-reg.tbl (flat): Add.
679 * i386-tbl.h: Re-generate.
680
34b772a6
JB		 6812008-02-13 Jan Beulich <jbeulich@novell.com>
682
683 * i386-dis.c (a_mode): New.
684 (cond_jump_mode): Adjust.
685 (Ma): Change to a_mode.
686 (intel_operand_size): Handle a_mode.
687 * i386-opc.tbl: Allow Dword and Qword for bound.
688 * i386-tbl.h: Re-generate.
689
a60de03c
JB		 6902008-02-13 Jan Beulich <jbeulich@novell.com>
691
692 * i386-gen.c (process_i386_registers): Process new fields.
693 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
694 unsigned char. Add dw2_regnum and Dw2Inval.
695 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
696 register names.
697 * i386-tbl.h: Re-generate.
698
f03fe4c1
L		 6992008-02-11 H.J. Lu <hongjiu.lu@intel.com>
700
4b6bc8eb 701 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 702 * i386-init.h: Updated.
703
475a2301
L		 7042008-02-11 H.J. Lu <hongjiu.lu@intel.com>
705
706 * i386-gen.c (cpu_flags): Add CpuXsave.
707
708 * i386-opc.h (CpuXsave): New.
4b6bc8eb 709 (CpuLM): Updated.
475a2301
L		 710 (i386_cpu_flags): Add cpuxsave.
711
712 * i386-dis.c (MOD_0FAE_REG_4): New.
713 (RM_0F01_REG_2): Likewise.
714 (MOD_0FAE_REG_5): Updated.
715 (RM_0F01_REG_3): Likewise.
716 (reg_table): Use MOD_0FAE_REG_4.
717 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
718 for xrstor.
719 (rm_table): Add RM_0F01_REG_2.
720
721 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
722 * i386-init.h: Regenerated.
723 * i386-tbl.h: Likewise.
724
595785c6 7252008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 726
595785c6
JB		 727 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
728 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
729 * i386-tbl.h: Re-generate.
730
bb8541b9
L		 7312008-02-04 H.J. Lu <hongjiu.lu@intel.com>
732
733 PR 5715
734 * configure: Regenerated.
735
57b592a3
AN		 7362008-02-04 Adam Nemet <anemet@caviumnetworks.com>
737
738 * mips-dis.c: Update copyright.
739 (mips_arch_choices): Add Octeon.
740 * mips-opc.c: Update copyright.
741 (IOCT): New macro.
742 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
743
930bb4cf
AM		 7442008-01-29 Alan Modra <amodra@bigpond.net.au>
745
746 * ppc-opc.c: Support optional L form mtmsr.
747
82c18208
L		 7482008-01-24 H.J. Lu <hongjiu.lu@intel.com>
749
750 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
751
599121aa
L		 7522008-01-23 H.J. Lu <hongjiu.lu@intel.com>
753
754 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
755 * i386-init.h: Regenerated.
756
80098f51
TG		 7572008-01-23 Tristan Gingold <gingold@adacore.com>
758
759 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
760 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
761
115c7c25
L		 7622008-01-22 H.J. Lu <hongjiu.lu@intel.com>
763
764 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
765 (cpu_flags): Likewise.
766
767 * i386-opc.h (CpuMMX2): Removed.
768 (CpuSSE): Updated.
769
770 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
771 * i386-init.h: Regenerated.
772 * i386-tbl.h: Likewise.
773
6305a203
L		 7742008-01-22 H.J. Lu <hongjiu.lu@intel.com>
775
776 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
777 CPU_SMX_FLAGS.
778 * i386-init.h: Regenerated.
779
fd07a1c8
L		 7802008-01-15 H.J. Lu <hongjiu.lu@intel.com>
781
782 * i386-opc.tbl: Use Qword on movddup.
783 * i386-tbl.h: Regenerated.
784
321fd21e
L		 7852008-01-15 H.J. Lu <hongjiu.lu@intel.com>
786
787 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
788 * i386-tbl.h: Regenerated.
789
4ee52178
L		 7902008-01-15 H.J. Lu <hongjiu.lu@intel.com>
791
792 * i386-dis.c (Mx): New.
793 (PREFIX_0FC3): Likewise.
794 (PREFIX_0FC7_REG_6): Updated.
795 (dis386_twobyte): Use PREFIX_0FC3.
796 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
797 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
798 movntss.
799
5c07affc
L		 8002008-01-14 H.J. Lu <hongjiu.lu@intel.com>
801
802 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
803 (operand_types): Add Mem.
804
805 * i386-opc.h (IntelSyntax): New.
806 * i386-opc.h (Mem): New.
807 (Byte): Updated.
808 (Opcode_Modifier_Max): Updated.
809 (i386_opcode_modifier): Add intelsyntax.
810 (i386_operand_type): Add mem.
811
812 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
813 instructions.
814
815 * i386-reg.tbl: Add size for accumulator.
816
817 * i386-init.h: Regenerated.
818 * i386-tbl.h: Likewise.
819
0d6a2f58
L		 8202008-01-13 H.J. Lu <hongjiu.lu@intel.com>
821
822 * i386-opc.h (Byte): Fix a typo.
823
7d5e4556
L		 8242008-01-12 H.J. Lu <hongjiu.lu@intel.com>
825
826 PR gas/5534
827 * i386-gen.c (operand_type_init): Add Dword to
828 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
829 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
830 Qword and Xmmword.
831 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
832 Xmmword, Unspecified and Anysize.
833 (set_bitfield): Make Mmword an alias of Qword. Make Oword
834 an alias of Xmmword.
835
836 * i386-opc.h (CheckSize): Removed.
837 (Byte): Updated.
838 (Word): Likewise.
839 (Dword): Likewise.
840 (Qword): Likewise.
841 (Xmmword): Likewise.
842 (FWait): Updated.
843 (OTMax): Likewise.
844 (i386_opcode_modifier): Remove checksize, byte, word, dword,
845 qword and xmmword.
846 (Fword): New.
847 (TBYTE): Likewise.
848 (Unspecified): Likewise.
849 (Anysize): Likewise.
850 (i386_operand_type): Add byte, word, dword, fword, qword,
851 tbyte xmmword, unspecified and anysize.
852
853 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
854 Tbyte, Xmmword, Unspecified and Anysize.
855
856 * i386-reg.tbl: Add size for accumulator.
857
858 * i386-init.h: Regenerated.
859 * i386-tbl.h: Likewise.
860
b5b1fc4f
L		 8612008-01-10 H.J. Lu <hongjiu.lu@intel.com>
862
863 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
864 (REG_0F18): Updated.
865 (reg_table): Updated.
866 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
867 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
868
50e8458f
L		 8692008-01-08 H.J. Lu <hongjiu.lu@intel.com>
870
871 * i386-gen.c (set_bitfield): Use fail () on error.
872
3d4d5afa
L		 8732008-01-08 H.J. Lu <hongjiu.lu@intel.com>
874
875 * i386-gen.c (lineno): New.
876 (filename): Likewise.
877 (set_bitfield): Report filename and line numer on error.
878 (process_i386_opcodes): Set filename and update lineno.
879 (process_i386_registers): Likewise.
880
e1d4d893
L		 8812008-01-05 H.J. Lu <hongjiu.lu@intel.com>
882
883 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
884 ATTSyntax.
885
886 * i386-opc.h (IntelMnemonic): Renamed to ..
887 (ATTSyntax): This
888 (Opcode_Modifier_Max): Updated.
889 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
890 and intelsyntax.
891
8944f3c2 892 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 893 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
894 * i386-tbl.h: Regenerated.
895
6f143e4d
L		 8962008-01-04 H.J. Lu <hongjiu.lu@intel.com>
897
898 * i386-gen.c: Update copyright to 2008.
899 * i386-opc.h: Likewise.
900 * i386-opc.tbl: Likewise.
901
902 * i386-init.h: Regenerated.
903 * i386-tbl.h: Likewise.
904
c6add537
L		 9052008-01-04 H.J. Lu <hongjiu.lu@intel.com>
906
907 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
908 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
909 * i386-tbl.h: Regenerated.
910
3629bb00
L		 9112008-01-03 H.J. Lu <hongjiu.lu@intel.com>
912
913 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
914 CpuSSE4_2_Or_ABM.
915 (cpu_flags): Likewise.
916
917 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
918 (CpuSSE4_2_Or_ABM): Likewise.
919 (CpuLM): Updated.
920 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
921
922 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
923 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
924 and CpuPadLock, respectively.
925 * i386-init.h: Regenerated.
926 * i386-tbl.h: Likewise.
927
24995bd6
L		 9282008-01-03 H.J. Lu <hongjiu.lu@intel.com>
929
930 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
931
932 * i386-opc.h (No_xSuf): Removed.
933 (CheckSize): Updated.
934
935 * i386-tbl.h: Regenerated.
936
e0329a22
L		 9372008-01-02 H.J. Lu <hongjiu.lu@intel.com>
938
939 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
940 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
941 CPU_SSE5_FLAGS.
942 (cpu_flags): Add CpuSSE4_2_Or_ABM.
943
944 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
945 (CpuLM): Updated.
946 (i386_cpu_flags): Add cpusse4_2_or_abm.
947
948 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
949 CpuABM|CpuSSE4_2 on popcnt.
950 * i386-init.h: Regenerated.
951 * i386-tbl.h: Likewise.
952
f2a9c676
L		 9532008-01-02 H.J. Lu <hongjiu.lu@intel.com>
954
955 * i386-opc.h: Update comments.
956
d978b5be
L		 9572008-01-02 H.J. Lu <hongjiu.lu@intel.com>
958
959 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
960 * i386-opc.h: Likewise.
961 * i386-opc.tbl: Likewise.
962
582d5edd
L		 9632008-01-02 H.J. Lu <hongjiu.lu@intel.com>
964
965 PR gas/5534
966 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
967 Byte, Word, Dword, QWord and Xmmword.
968
969 * i386-opc.h (No_xSuf): New.
970 (CheckSize): Likewise.
971 (Byte): Likewise.
972 (Word): Likewise.
973 (Dword): Likewise.
974 (QWord): Likewise.
975 (Xmmword): Likewise.
976 (FWait): Updated.
977 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
978 Dword, QWord and Xmmword.
979
980 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
981 used.
982 * i386-tbl.h: Regenerated.
983
3fe15143
MK		 9842008-01-02 Mark Kettenis <kettenis@gnu.org>
985
986 * m88k-dis.c (instructions): Fix fcvt.* instructions.
987 From Miod Vallat.
988
6c7ac64e 989For older changes see ChangeLog-2007
252b5132
RH		 990\f
991Local Variables:
2f6d2f85
NC		 992mode: change-log
993left-margin: 8
994fill-column: 74
252b5132
RH		 995version-control: never
996End:
GDB Binutils - Deliverables
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