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MIPS16: Add R_MIPS16_PC16_S1 branch relocation support
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
5703197e
TS		 12016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
2
3 * mcore-opc.h: Remove sentinal.
4 * mcore-dis.c (print_insn_mcore): Adjust.
5
ce440d63
GM		 62016-06-23 Graham Markall <graham.markall@embecosm.com>
7
8 * arc-opc.c: Correct description of availability of NPS400
9 features.
10
6fd3a02d
PB		 112016-06-22 Peter Bergner <bergner@vnet.ibm.com>
12
13 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
14 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
15 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
16 xor3>: New mnemonics.
17 <setb>: Change to a VX form instruction.
18 (insert_sh6): Add support for rldixor.
19 (extract_sh6): Likewise.
20
6b477896
TS		 212016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
22
23 * arc-ext.h: Wrap in extern C.
24
bdd582db
GM		 252016-06-21 Graham Markall <graham.markall@embecosm.com>
26
27 * arc-dis.c (arc_insn_length): Add comment on instruction length.
28 Use same method for determining instruction length on ARC700 and
29 NPS-400.
30 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
31 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
32 with the NPS400 subclass.
33 * arc-opc.c: Likewise.
34
96074adc
JM		 352016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
36
37 * sparc-opc.c (rdasr): New macro.
38 (wrasr): Likewise.
39 (rdpr): Likewise.
40 (wrpr): Likewise.
41 (rdhpr): Likewise.
42 (wrhpr): Likewise.
43 (sparc_opcodes): Use the macros above to fix and expand the
44 definition of read/write instructions from/to
45 asr/privileged/hyperprivileged instructions.
46 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
47 %hva_mask_nz. Prefer softint_set and softint_clear over
48 set_softint and clear_softint.
49 (print_insn_sparc): Support %ver in Rd.
50
7a10c22f
JM		 512016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
52
53 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
54 architecture according to the hardware capabilities they require.
55
4f26fb3a
JM		 562016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
57
58 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
59 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
60 bfd_mach_sparc_v9{c,d,e,v,m}.
61 * sparc-opc.c (MASK_V9C): Define.
62 (MASK_V9D): Likewise.
63 (MASK_V9E): Likewise.
64 (MASK_V9V): Likewise.
65 (MASK_V9M): Likewise.
66 (v6): Add MASK_V9{C,D,E,V,M}.
67 (v6notlet): Likewise.
68 (v7): Likewise.
69 (v8): Likewise.
70 (v9): Likewise.
71 (v9andleon): Likewise.
72 (v9a): Likewise.
73 (v9b): Likewise.
74 (v9c): Define.
75 (v9d): Likewise.
76 (v9e): Likewise.
77 (v9v): Likewise.
78 (v9m): Likewise.
79 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
80
3ee6e4fb
NC		 812016-06-15 Nick Clifton <nickc@redhat.com>
82
83 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
84 constants to match expected behaviour.
85 (nds32_parse_opcode): Likewise. Also for whitespace.
86
02f3be19
AB		 872016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
88
89 * arc-opc.c (extract_rhv1): Extract value from insn.
90
6f9f37ed 912016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 92
93 * arc-nps400-tbl.h: Add ldbit instruction.
94 * arc-opc.c: Add flag classes required for ldbit.
95
6f9f37ed 962016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 97
98 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
99 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
100 support the above instructions.
101
6f9f37ed 1022016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 103
104 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
105 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
106 csma, cbba, zncv, and hofs.
107 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
108 support the above instructions.
109
1102016-06-06 Graham Markall <graham.markall@embecosm.com>
111
112 * arc-nps400-tbl.h: Add andab and orab instructions.
113
1142016-06-06 Graham Markall <graham.markall@embecosm.com>
115
116 * arc-nps400-tbl.h: Add addl-like instructions.
117
1182016-06-06 Graham Markall <graham.markall@embecosm.com>
119
120 * arc-nps400-tbl.h: Add mxb and imxb instructions.
121
1222016-06-06 Graham Markall <graham.markall@embecosm.com>
123
124 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
125 instructions.
126
b2cc3f6f
AK		 1272016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
128
129 * s390-dis.c (option_use_insn_len_bits_p): New file scope
130 variable.
131 (init_disasm): Handle new command line option "insnlength".
132 (print_s390_disassembler_options): Mention new option in help
133 output.
134 (print_insn_s390): Use the encoded insn length when dumping
135 unknown instructions.
136
1857fe72
DC		 1372016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
138
139 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
140 to the address and set as symbol address for LDS/ STS immediate operands.
141
14b57c7c
AM		 1422016-06-07 Alan Modra <amodra@gmail.com>
143
144 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
145 cpu for "vle" to e500.
146 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
147 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
148 (PPCNONE): Delete, substitute throughout.
149 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
150 except for major opcode 4 and 31.
151 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
152
4d1464f2
MW		 1532016-06-07 Matthew Wahab <matthew.wahab@arm.com>
154
155 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
156 ARM_EXT_RAS in relevant entries.
157
026122a6
PB		 1582016-06-03 Peter Bergner <bergner@vnet.ibm.com>
159
160 PR binutils/20196
161 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
162 opcodes for E6500.
163
07f5af7d
L		 1642016-06-03 H.J. Lu <hongjiu.lu@intel.com>
165
166 PR binutis/18386
167 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
168 (indir_v_mode): New.
169 Add comments for '&'.
170 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
171 (putop): Handle '&'.
172 (intel_operand_size): Handle indir_v_mode.
173 (OP_E_register): Likewise.
174 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
175 64-bit indirect call/jmp for AMD64.
176 * i386-tbl.h: Regenerated
177
4eb6f892
AB		 1782016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
179
180 * arc-dis.c (struct arc_operand_iterator): New structure.
181 (find_format_from_table): All the old content from find_format,
182 with some minor adjustments, and parameter renaming.
183 (find_format_long_instructions): New function.
184 (find_format): Rewritten.
185 (arc_insn_length): Add LSB parameter.
186 (extract_operand_value): New function.
187 (operand_iterator_next): New function.
188 (print_insn_arc): Use new functions to find opcode, and iterator
189 over operands.
190 * arc-opc.c (insert_nps_3bit_dst_short): New function.
191 (extract_nps_3bit_dst_short): New function.
192 (insert_nps_3bit_src2_short): New function.
193 (extract_nps_3bit_src2_short): New function.
194 (insert_nps_bitop1_size): New function.
195 (extract_nps_bitop1_size): New function.
196 (insert_nps_bitop2_size): New function.
197 (extract_nps_bitop2_size): New function.
198 (insert_nps_bitop_mod4_msb): New function.
199 (extract_nps_bitop_mod4_msb): New function.
200 (insert_nps_bitop_mod4_lsb): New function.
201 (extract_nps_bitop_mod4_lsb): New function.
202 (insert_nps_bitop_dst_pos3_pos4): New function.
203 (extract_nps_bitop_dst_pos3_pos4): New function.
204 (insert_nps_bitop_ins_ext): New function.
205 (extract_nps_bitop_ins_ext): New function.
206 (arc_operands): Add new operands.
207 (arc_long_opcodes): New global array.
208 (arc_num_long_opcodes): New global.
209 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
210
1fe0971e
TS		 2112016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
212
213 * nds32-asm.h: Add extern "C".
214 * sh-opc.h: Likewise.
215
315f180f
GM		 2162016-06-01 Graham Markall <graham.markall@embecosm.com>
217
218 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
219 0,b,limm to the rflt instruction.
220
a2b5fccc
TS		 2212016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
222
223 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
224 constant.
225
0cbd0046
L		 2262016-05-29 H.J. Lu <hongjiu.lu@intel.com>
227
228 PR gas/20145
229 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
230 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
231 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
232 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
233 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
234 * i386-init.h: Regenerated.
235
1848e567
L		 2362016-05-27 H.J. Lu <hongjiu.lu@intel.com>
237
238 PR gas/20145
239 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
240 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
241 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
242 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
243 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
244 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
245 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
246 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
247 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
248 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
249 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
250 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
251 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
252 CpuRegMask for AVX512.
253 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
254 and CpuRegMask.
255 (set_bitfield_from_cpu_flag_init): New function.
256 (set_bitfield): Remove const on f. Call
257 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
258 * i386-opc.h (CpuRegMMX): New.
259 (CpuRegXMM): Likewise.
260 (CpuRegYMM): Likewise.
261 (CpuRegZMM): Likewise.
262 (CpuRegMask): Likewise.
263 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
264 and cpuregmask.
265 * i386-init.h: Regenerated.
266 * i386-tbl.h: Likewise.
267
e92bae62
L		 2682016-05-27 H.J. Lu <hongjiu.lu@intel.com>
269
270 PR gas/20154
271 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
272 (opcode_modifiers): Add AMD64 and Intel64.
273 (main): Properly verify CpuMax.
274 * i386-opc.h (CpuAMD64): Removed.
275 (CpuIntel64): Likewise.
276 (CpuMax): Set to CpuNo64.
277 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
278 (AMD64): New.
279 (Intel64): Likewise.
280 (i386_opcode_modifier): Add amd64 and intel64.
281 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
282 on call and jmp.
283 * i386-init.h: Regenerated.
284 * i386-tbl.h: Likewise.
285
e89c5eaa
L		 2862016-05-27 H.J. Lu <hongjiu.lu@intel.com>
287
288 PR gas/20154
289 * i386-gen.c (main): Fail if CpuMax is incorrect.
290 * i386-opc.h (CpuMax): Set to CpuIntel64.
291 * i386-tbl.h: Regenerated.
292
77d66e7b
NC		 2932016-05-27 Nick Clifton <nickc@redhat.com>
294
295 PR target/20150
296 * msp430-dis.c (msp430dis_read_two_bytes): New function.
297 (msp430dis_opcode_unsigned): New function.
298 (msp430dis_opcode_signed): New function.
299 (msp430_singleoperand): Use the new opcode reading functions.
300 Only disassenmble bytes if they were successfully read.
301 (msp430_doubleoperand): Likewise.
302 (msp430_branchinstr): Likewise.
303 (msp430x_callx_instr): Likewise.
304 (print_insn_msp430): Check that it is safe to read bytes before
305 attempting disassembly. Use the new opcode reading functions.
306
19dfcc89
PB		 3072016-05-26 Peter Bergner <bergner@vnet.ibm.com>
308
309 * ppc-opc.c (CY): New define. Document it.
310 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
311
f3ad7637
L		 3122016-05-25 H.J. Lu <hongjiu.lu@intel.com>
313
314 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
315 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
316 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
317 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
318 CPU_ANY_AVX_FLAGS.
319 * i386-init.h: Regenerated.
320
f1360d58
L		 3212016-05-25 H.J. Lu <hongjiu.lu@intel.com>
322
323 PR gas/20141
324 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
325 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
326 * i386-init.h: Regenerated.
327
293f5f65
L		 3282016-05-25 H.J. Lu <hongjiu.lu@intel.com>
329
330 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
331 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
332 * i386-init.h: Regenerated.
333
d9eca1df
CZ		 3342016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
335
336 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
337 information.
338 (print_insn_arc): Set insn_type information.
339 * arc-opc.c (C_CC): Add F_CLASS_COND.
340 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
341 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
342 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
343 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
344 (brne, brne_s, jeq_s, jne_s): Likewise.
345
87789e08
CZ		 3462016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
347
348 * arc-tbl.h (neg): New instruction variant.
349
c810e0b8
CZ		 3502016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
351
352 * arc-dis.c (find_format, find_format, get_auxreg)
353 (print_insn_arc): Changed.
354 * arc-ext.h (INSERT_XOP): Likewise.
355
3d207518
TS		 3562016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
357
358 * tic54x-dis.c (sprint_mmr): Adjust.
359 * tic54x-opc.c: Likewise.
360
514e58b7
AM		 3612016-05-19 Alan Modra <amodra@gmail.com>
362
363 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
364
e43de63c
AM		 3652016-05-19 Alan Modra <amodra@gmail.com>
366
367 * ppc-opc.c: Formatting.
368 (NSISIGNOPT): Define.
369 (powerpc_opcodes <subis>): Use NSISIGNOPT.
370
1401d2fe
MR		 3712016-05-18 Maciej W. Rozycki <macro@imgtec.com>
372
373 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
374 replacing references to `micromips_ase' throughout.
375 (_print_insn_mips): Don't use file-level microMIPS annotation to
376 determine the disassembly mode with the symbol table.
377
1178da44
PB		 3782016-05-13 Peter Bergner <bergner@vnet.ibm.com>
379
380 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
381
8f4f9071
MF		 3822016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
383
384 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
385 mips64r6.
386 * mips-opc.c (D34): New macro.
387 (mips_builtin_opcodes): Define bposge32c for DSPr3.
388
8bc52696
AF		 3892016-05-10 Alexander Fomin <alexander.fomin@intel.com>
390
391 * i386-dis.c (prefix_table): Add RDPID instruction.
392 * i386-gen.c (cpu_flag_init): Add RDPID flag.
393 (cpu_flags): Add RDPID bitfield.
394 * i386-opc.h (enum): Add RDPID element.
395 (i386_cpu_flags): Add RDPID field.
396 * i386-opc.tbl: Add RDPID instruction.
397 * i386-init.h: Regenerate.
398 * i386-tbl.h: Regenerate.
399
39d911fc
TP		 4002016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
401
402 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
403 branch type of a symbol.
404 (print_insn): Likewise.
405
16a1fa25
TP		 4062016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
407
408 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
409 Mainline Security Extensions instructions.
410 (thumb_opcodes): Add entries for narrow ARMv8-M Security
411 Extensions instructions.
412 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
413 instructions.
414 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
415 special registers.
416
d751b79e
JM		 4172016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
418
419 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
420
945e0f82
CZ		 4212016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
422
423 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
424 (arcExtMap_genOpcode): Likewise.
425 * arc-opc.c (arg_32bit_rc): Define new variable.
426 (arg_32bit_u6): Likewise.
427 (arg_32bit_limm): Likewise.
428
20f55f38
SN		 4292016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
430
431 * aarch64-gen.c (VERIFIER): Define.
432 * aarch64-opc.c (VERIFIER): Define.
433 (verify_ldpsw): Use static linkage.
434 * aarch64-opc.h (verify_ldpsw): Remove.
435 * aarch64-tbl.h: Use VERIFIER for verifiers.
436
4bd13cde
NC		 4372016-04-28 Nick Clifton <nickc@redhat.com>
438
439 PR target/19722
440 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
441 * aarch64-opc.c (verify_ldpsw): New function.
442 * aarch64-opc.h (verify_ldpsw): New prototype.
443 * aarch64-tbl.h: Add initialiser for verifier field.
444 (LDPSW): Set verifier to verify_ldpsw.
445
c0f92bf9
L		 4462016-04-23 H.J. Lu <hongjiu.lu@intel.com>
447
448 PR binutils/19983
449 PR binutils/19984
450 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
451 smaller than address size.
452
e6c7cdec
TS		 4532016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
454
455 * alpha-dis.c: Regenerate.
456 * crx-dis.c: Likewise.
457 * disassemble.c: Likewise.
458 * epiphany-opc.c: Likewise.
459 * fr30-opc.c: Likewise.
460 * frv-opc.c: Likewise.
461 * ip2k-opc.c: Likewise.
462 * iq2000-opc.c: Likewise.
463 * lm32-opc.c: Likewise.
464 * lm32-opinst.c: Likewise.
465 * m32c-opc.c: Likewise.
466 * m32r-opc.c: Likewise.
467 * m32r-opinst.c: Likewise.
468 * mep-opc.c: Likewise.
469 * mt-opc.c: Likewise.
470 * or1k-opc.c: Likewise.
471 * or1k-opinst.c: Likewise.
472 * tic80-opc.c: Likewise.
473 * xc16x-opc.c: Likewise.
474 * xstormy16-opc.c: Likewise.
475
537aefaf
AB		 4762016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
477
478 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
479 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
480 calcsd, and calcxd instructions.
481 * arc-opc.c (insert_nps_bitop_size): Delete.
482 (extract_nps_bitop_size): Delete.
483 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
484 (extract_nps_qcmp_m3): Define.
485 (extract_nps_qcmp_m2): Define.
486 (extract_nps_qcmp_m1): Define.
487 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
488 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
489 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
490 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
491 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
492 NPS_QCMP_M3.
493
c8f785f2
AB		 4942016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
495
496 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
497
6fd8e7c2
L		 4982016-04-15 H.J. Lu <hongjiu.lu@intel.com>
499
500 * Makefile.in: Regenerated with automake 1.11.6.
501 * aclocal.m4: Likewise.
502
4b0c052e
AB		 5032016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
504
505 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
506 instructions.
507 * arc-opc.c (insert_nps_cmem_uimm16): New function.
508 (extract_nps_cmem_uimm16): New function.
509 (arc_operands): Add NPS_XLDST_UIMM16 operand.
510
cb040366
AB		 5112016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
512
513 * arc-dis.c (arc_insn_length): New function.
514 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
515 (find_format): Change insnLen parameter to unsigned.
516
accc0180
NC		 5172016-04-13 Nick Clifton <nickc@redhat.com>
518
519 PR target/19937
520 * v850-opc.c (v850_opcodes): Correct masks for long versions of
521 the LD.B and LD.BU instructions.
522
f36e33da
CZ		 5232016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
524
525 * arc-dis.c (find_format): Check for extension flags.
526 (print_flags): New function.
527 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
528 .extAuxRegister.
529 * arc-ext.c (arcExtMap_coreRegName): Use
530 LAST_EXTENSION_CORE_REGISTER.
531 (arcExtMap_coreReadWrite): Likewise.
532 (dump_ARC_extmap): Update printing.
533 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
534 (arc_aux_regs): Add cpu field.
535 * arc-regs.h: Add cpu field, lower case name aux registers.
536
1c2e355e
CZ		 5372016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
538
539 * arc-tbl.h: Add rtsc, sleep with no arguments.
540
b99747ae
CZ		 5412016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
542
543 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
544 Initialize.
545 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
546 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
547 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
548 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
549 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
550 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
551 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
552 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
553 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
554 (arc_opcode arc_opcodes): Null terminate the array.
555 (arc_num_opcodes): Remove.
556 * arc-ext.h (INSERT_XOP): Define.
557 (extInstruction_t): Likewise.
558 (arcExtMap_instName): Delete.
559 (arcExtMap_insn): New function.
560 (arcExtMap_genOpcode): Likewise.
561 * arc-ext.c (ExtInstruction): Remove.
562 (create_map): Zero initialize instruction fields.
563 (arcExtMap_instName): Remove.
564 (arcExtMap_insn): New function.
565 (dump_ARC_extmap): More info while debuging.
566 (arcExtMap_genOpcode): New function.
567 * arc-dis.c (find_format): New function.
568 (print_insn_arc): Use find_format.
569 (arc_get_disassembler): Enable dump_ARC_extmap only when
570 debugging.
571
92708cec
MR		 5722016-04-11 Maciej W. Rozycki <macro@imgtec.com>
573
574 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
575 instruction bits out.
576
a42a4f84
AB		 5772016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
578
579 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
580 * arc-opc.c (arc_flag_operands): Add new flags.
581 (arc_flag_classes): Add new classes.
582
1328504b
AB		 5832016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
584
585 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
586
820f03ff
AB		 5872016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
588
589 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
590 encode1, rflt, crc16, and crc32 instructions.
591 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
592 (arc_flag_classes): Add C_NPS_R.
593 (insert_nps_bitop_size_2b): New function.
594 (extract_nps_bitop_size_2b): Likewise.
595 (insert_nps_bitop_uimm8): Likewise.
596 (extract_nps_bitop_uimm8): Likewise.
597 (arc_operands): Add new operand entries.
598
8ddf6b2a
CZ		 5992016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
600
b99747ae
CZ		 601 * arc-regs.h: Add a new subclass field. Add double assist
602 accumulator register values.
603 * arc-tbl.h: Use DPA subclass to mark the double assist
604 instructions. Use DPX/SPX subclas to mark the FPX instructions.
605 * arc-opc.c (RSP): Define instead of SP.
606 (arc_aux_regs): Add the subclass field.
8ddf6b2a 607
589a7d88
JW		 6082016-04-05 Jiong Wang <jiong.wang@arm.com>
609
610 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
611
0a191de9 6122016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 613
614 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
615 NPS_R_SRC1.
616
0a106562
AB		 6172016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
618
619 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
620 issues. No functional changes.
621
bd05ac5f
CZ		 6222016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
623
b99747ae
CZ		 624 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
625 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
626 (RTT): Remove duplicate.
627 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
628 (PCT_CONFIG*): Remove.
629 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 630
9885948f
CZ		 6312016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
632
b99747ae 633 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 634
f2dd8838
CZ		 6352016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
636
b99747ae
CZ		 637 * arc-tbl.h (invld07): Remove.
638 * arc-ext-tbl.h: New file.
639 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
640 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 641
0d2f91fe
JK		 6422016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
643
644 Fix -Wstack-usage warnings.
645 * aarch64-dis.c (print_operands): Substitute size.
646 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
647
a6b71f42
JM		 6482016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
649
650 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
651 to get a proper diagnostic when an invalid ASR register is used.
652
9780e045
NC		 6532016-03-22 Nick Clifton <nickc@redhat.com>
654
655 * configure: Regenerate.
656
e23e8ebe
AB		 6572016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
658
659 * arc-nps400-tbl.h: New file.
660 * arc-opc.c: Add top level comment.
661 (insert_nps_3bit_dst): New function.
662 (extract_nps_3bit_dst): New function.
663 (insert_nps_3bit_src2): New function.
664 (extract_nps_3bit_src2): New function.
665 (insert_nps_bitop_size): New function.
666 (extract_nps_bitop_size): New function.
667 (arc_flag_operands): Add nps400 entries.
668 (arc_flag_classes): Add nps400 entries.
669 (arc_operands): Add nps400 entries.
670 (arc_opcodes): Add nps400 include.
671
1ae8ab47
AB		 6722016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
673
674 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
675 the new class enum values.
676
8699fc3e
AB		 6772016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
678
679 * arc-dis.c (print_insn_arc): Handle nps400.
680
24740d83
AB		 6812016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
682
683 * arc-opc.c (BASE): Delete.
684
8678914f
NC		 6852016-03-18 Nick Clifton <nickc@redhat.com>
686
687 PR target/19721
688 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
689 of MOV insn that aliases an ORR insn.
690
cc933301
JW		 6912016-03-16 Jiong Wang <jiong.wang@arm.com>
692
693 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
694
f86f5863
TS		 6952016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
696
697 * mcore-opc.h: Add const qualifiers.
698 * microblaze-opc.h (struct op_code_struct): Likewise.
699 * sh-opc.h: Likewise.
700 * tic4x-dis.c (tic4x_print_indirect): Likewise.
701 (tic4x_print_op): Likewise.
702
62de1c63
AM		 7032016-03-02 Alan Modra <amodra@gmail.com>
704
d11698cd 705 * or1k-desc.h: Regenerate.
62de1c63 706 * fr30-ibld.c: Regenerate.
c697cf0b 707 * rl78-decode.c: Regenerate.
62de1c63 708
020efce5
NC		 7092016-03-01 Nick Clifton <nickc@redhat.com>
710
711 PR target/19747
712 * rl78-dis.c (print_insn_rl78_common): Fix typo.
713
b0c11777
RL		 7142016-02-24 Renlin Li <renlin.li@arm.com>
715
716 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
717 (print_insn_coprocessor): Support fp16 instructions.
718
3e309328
RL		 7192016-02-24 Renlin Li <renlin.li@arm.com>
720
721 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
722 vminnm, vrint(mpna).
723
8afc7bea
RL		 7242016-02-24 Renlin Li <renlin.li@arm.com>
725
726 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
727 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
728
4fd7268a
L		 7292016-02-15 H.J. Lu <hongjiu.lu@intel.com>
730
731 * i386-dis.c (print_insn): Parenthesize expression to prevent
732 truncated addresses.
733 (OP_J): Likewise.
734
4670103e
CZ		 7352016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
736 Janek van Oirschot <jvanoirs@synopsys.com>
737
b99747ae
CZ		 738 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
739 variable.
4670103e 740
c1d9289f
NC		 7412016-02-04 Nick Clifton <nickc@redhat.com>
742
743 PR target/19561
744 * msp430-dis.c (print_insn_msp430): Add a special case for
745 decoding an RRC instruction with the ZC bit set in the extension
746 word.
747
a143b004
AB		 7482016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
749
750 * cgen-ibld.in (insert_normal): Rework calculation of shift.
751 * epiphany-ibld.c: Regenerate.
752 * fr30-ibld.c: Regenerate.
753 * frv-ibld.c: Regenerate.
754 * ip2k-ibld.c: Regenerate.
755 * iq2000-ibld.c: Regenerate.
756 * lm32-ibld.c: Regenerate.
757 * m32c-ibld.c: Regenerate.
758 * m32r-ibld.c: Regenerate.
759 * mep-ibld.c: Regenerate.
760 * mt-ibld.c: Regenerate.
761 * or1k-ibld.c: Regenerate.
762 * xc16x-ibld.c: Regenerate.
763 * xstormy16-ibld.c: Regenerate.
764
b89807c6
AB		 7652016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
766
767 * epiphany-dis.c: Regenerated from latest cpu files.
768
d8c823c8
MM		 7692016-02-01 Michael McConville <mmcco@mykolab.com>
770
771 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
772 test bit.
773
5bc5ae88
RL		 7742016-01-25 Renlin Li <renlin.li@arm.com>
775
776 * arm-dis.c (mapping_symbol_for_insn): New function.
777 (find_ifthen_state): Call mapping_symbol_for_insn().
778
0bff6e2d
MW		 7792016-01-20 Matthew Wahab <matthew.wahab@arm.com>
780
781 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
782 of MSR UAO immediate operand.
783
100b4f2e
MR		 7842016-01-18 Maciej W. Rozycki <macro@imgtec.com>
785
786 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
787 instruction support.
788
5c14705f
AM		 7892016-01-17 Alan Modra <amodra@gmail.com>
790
791 * configure: Regenerate.
792
4d82fe66
NC		 7932016-01-14 Nick Clifton <nickc@redhat.com>
794
795 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
796 instructions that can support stack pointer operations.
797 * rl78-decode.c: Regenerate.
798 * rl78-dis.c: Fix display of stack pointer in MOVW based
799 instructions.
800
651657fa
MW		 8012016-01-14 Matthew Wahab <matthew.wahab@arm.com>
802
803 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
804 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
805 erxtatus_el1 and erxaddr_el1.
806
105bde57
MW		 8072016-01-12 Matthew Wahab <matthew.wahab@arm.com>
808
809 * arm-dis.c (arm_opcodes): Add "esb".
810 (thumb_opcodes): Likewise.
811
afa8d405
PB		 8122016-01-11 Peter Bergner <bergner@vnet.ibm.com>
813
814 * ppc-opc.c <xscmpnedp>: Delete.
815 <xvcmpnedp>: Likewise.
816 <xvcmpnedp.>: Likewise.
817 <xvcmpnesp>: Likewise.
818 <xvcmpnesp.>: Likewise.
819
83c3256e
AS		 8202016-01-08 Andreas Schwab <schwab@linux-m68k.org>
821
822 PR gas/13050
823 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
824 addition to ISA_A.
825
6f2750fe
AM		 8262016-01-01 Alan Modra <amodra@gmail.com>
827
828 Update year range in copyright notice of all files.
829
3499769a
AM		 830For older changes see ChangeLog-2015
831\f
832Copyright (C) 2016 Free Software Foundation, Inc.
833
834Copying and distribution of this file, with or without modification,
835are permitted in any medium without royalty provided the copyright
836notice and this notice are preserved.
837
838Local Variables:
839mode: change-log
840left-margin: 8
841fill-column: 74
842version-control: never
843End:
GDB Binutils - Deliverables
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