[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2013-04-03  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
	destination address by subtracting the operand from the current
	address.
	* v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
	a positive value in the insn.
	(extract_u16_loop): Do not negate the returned value.
	(D16_LOOP): Add V850_INVERSE_PCREL flag.

	(ceilf.sw): Remove duplicate entry.
	(cvtf.hs): New entry.
	(cvtf.sh): Likewise.
	(fmaf.s): Likewise.
	(fmsf.s): Likewise.
	(fnmaf.s): Likewise.
	(fnmsf.s): Likewise.
	(maddf.s): Restrict to E3V5 architectures.
	(msubf.s): Likewise.
	(nmaddf.s): Likewise.
	(nmsubf.s): Likewise.

2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (get_sib): Add the sizeflag argument.  Properly
	check address mode.
	(print_insn): Pass sizeflag to get_sib.

2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>

	PR binutils/15068
	* tic6x-dis.c: Add support for displaying 16-bit insns.

2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>

	PR gas/15095
	* tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
	individual msb and lsb halves in src1 & src2 fields.  Discard the
	src1 (lsb) value and only use src2 (msb), discarding bit 0, to
	follow what Ti SDK does in that case as any value in the src1
	field yields the same output with SDK disassembler.

2013-03-12  Michael Eager <eager@eagercon.com>

	* opcodes/mips-dis.c (print_insn_args): Modify def of reg.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.

2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
	(thumb32_opcodes): Likewise.
	(print_insn_thumb32): Handle 'S' control char.

2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>

	* lm32-desc.c: Regenerate.

2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-reg.tbl (riz): Add RegRex64.
	* i386-tbl.h: Regenerated.

2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	(aarch64_feature_crc): New static.
	(CRC): New macro.
	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Ditto.
	* aarch64-opc-2.c: Ditto.

2013-02-27  Alan Modra  <amodra@gmail.com>

	* rl78-decode.opc (rl78_decode_opcode): Fix typo.
	* rl78-decode.c: Regenerate.

2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>

	* rl78-decode.opc: Fix encoding of DIVWU insn.
	* rl78-decode.c: Regenerate.

2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/15159
	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.

	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	(cpu_flags): Add CpuSMAP.

	* i386-opc.h (CpuSMAP): New.
	(i386_cpu_flags): Add cpusmap.

	* i386-opc.tbl: Add clac and stac.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>

	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	which also makes the disassembler output be in little
	endian like it should be.

2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	fields to NULL.
	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.

2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	section disassembled.

2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c: Update strht pattern.

2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>

	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	single-float.  Disable ll, lld, sc and scd for EE.  Disable the
	trunc.w.s macro for EE.

2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
            Andrew Jenner <andrew@codesourcery.com>

	Based on patches from Altera Corporation.

	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	nios2-opc.c.
	* Makefile.in: Regenerated.
	* configure.in: Add case for bfd_nios2_arch.
	* configure: Regenerated.
	* disassemble.c (ARCH_nios2): Define.
	(disassembler): Add case for bfd_arch_nios2.
	* nios2-dis.c: New file.
	* nios2-opc.c: New file.

2013-02-04  Alan Modra  <amodra@gmail.com>

	* po/POTFILES.in: Regenerate.
	* rl78-decode.c: Regenerate.
	* rx-decode.c: Regenerate.

2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
	* aarch64-asm.c (convert_xtl_to_shll): New function.
	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_xtl_to_shll.
	* aarch64-dis.c (convert_shll_to_xtl): New function.
	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_shll_to_xtl.
	* aarch64-gen.c: Update copyright year.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Re-generate.
	* aarch64-opc-2.c: Re-generate.

2013-01-24  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c: Add support for e3v5 architecture.
	* v850-opc.c: Likewise.

2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): For
	AARCH64_MOD_LSL, move the range check on the shift amount before the
	alignment check; change to call set_sft_amount_out_of_range_error
	instead of set_imm_out_of_range_error.
	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	SIMD_IMM_SFT.

2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-01-15  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	values.
	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.

2013-01-14  Will Newton <will.newton@imgtec.com>

	* metag-dis.c (REG_WIDTH): Increase to 64.

2013-01-10  Peter Bergner <bergner@vnet.ibm.com>

	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	(SH6): Update.
	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.

2013-01-10  Will Newton <will.newton@imgtec.com>

	* Makefile.am: Add Meta.
	* configure.in: Add Meta.
	* disassemble.c: Add Meta support.
	* metag-dis.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.

2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	(match_opcode): Rename to cr16_match_opcode.

2013-01-04  Juergen Urban <JuergenUrban@gmx.de>

	* mips-dis.c: Add names for CP0 registers of r5900.
	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	instructions sq and lq.
	Add support for MIPS r5900 CPU.
	Add support for 128 bit MMI (Multimedia Instructions).
	Add support for EE instructions (Emotion Engine).
	Disable unsupported floating point instructions (64 bit and
	undefined compare operations).
	Enable instructions of MIPS ISA IV which are supported by r5900.
	Disable 64 bit co processor instructions.
	Disable 64 bit multiplication and division instructions.
	Disable instructions for co-processor 2 and 3, because these are
	not supported (preparation for later VU0 support (Vector Unit)).
	Disable cvt.w.s because this behaves like trunc.w.s and the
	correct execution can't be ensured on r5900.
	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	will confuse less developers and compilers.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Change to print
	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	in comment.
	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	OP_MOV_IMM_WIDE.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.

2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (process_copyright): Update copyright year to 2013.

2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (match_opcode,make_instruction): Remove static
	declaration.
	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.

For older changes see ChangeLog-2012
\f
Copyright (C) 2013 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
41702d50 NC	1	2013-04-03 Nick Clifton <nickc@redhat.com>
	2
	3	* v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
	4	destination address by subtracting the operand from the current
	5	address.
	6	* v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
	7	a positive value in the insn.
	8	(extract_u16_loop): Do not negate the returned value.
	9	(D16_LOOP): Add V850_INVERSE_PCREL flag.
	10
	11	(ceilf.sw): Remove duplicate entry.
	12	(cvtf.hs): New entry.
	13	(cvtf.sh): Likewise.
	14	(fmaf.s): Likewise.
	15	(fmsf.s): Likewise.
	16	(fnmaf.s): Likewise.
	17	(fnmsf.s): Likewise.
	18	(maddf.s): Restrict to E3V5 architectures.
	19	(msubf.s): Likewise.
	20	(nmaddf.s): Likewise.
	21	(nmsubf.s): Likewise.
	22
55cf16e1 L	23	2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
	24
	25	* i386-dis.c (get_sib): Add the sizeflag argument. Properly
	26	check address mode.
	27	(print_insn): Pass sizeflag to get_sib.
	28
51dcdd4d NC	29	2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
	30
	31	PR binutils/15068
	32	* tic6x-dis.c: Add support for displaying 16-bit insns.
	33
795b8e6b NC	34	2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
	35
	36	PR gas/15095
	37	* tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
	38	individual msb and lsb halves in src1 & src2 fields. Discard the
	39	src1 (lsb) value and only use src2 (msb), discarding bit 0, to
	40	follow what Ti SDK does in that case as any value in the src1
	41	field yields the same output with SDK disassembler.
	42
314d60dd ME	43	2013-03-12 Michael Eager <eager@eagercon.com>
314d60dd ME	44
795b8e6b	45	* opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd	46
dad60f8e SL	47	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	48
	49	* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
	50
f5cb796a SL	51	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	52
	53	* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
	54
21fde85c SL	55	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	56
	57	* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
	58
dd5181d5 KT	59	2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	60
	61	* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
	62	(thumb32_opcodes): Likewise.
	63	(print_insn_thumb32): Handle 'S' control char.
	64
87a8d6cb NC	65	2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
	66
	67	* lm32-desc.c: Regenerate.
	68
99dce992 L	69	2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
	70
	71	* i386-reg.tbl (riz): Add RegRex64.
	72	* i386-tbl.h: Regenerated.
	73
e60bb1dd YZ	74	2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
	75
	76	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	77	(aarch64_feature_crc): New static.
	78	(CRC): New macro.
	79	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	80	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	81	* aarch64-asm-2.c: Re-generate.
	82	* aarch64-dis-2.c: Ditto.
	83	* aarch64-opc-2.c: Ditto.
	84
c7570fcd AM	85	2013-02-27 Alan Modra <amodra@gmail.com>
	86
	87	* rl78-decode.opc (rl78_decode_opcode): Fix typo.
	88	* rl78-decode.c: Regenerate.
	89
151fa98f NC	90	2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
	91
	92	* rl78-decode.opc: Fix encoding of DIVWU insn.
	93	* rl78-decode.c: Regenerate.
	94
5c111e37 L	95	2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
	96
	97	PR gas/15159
	98	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
	99
	100	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	101	(cpu_flags): Add CpuSMAP.
	102
	103	* i386-opc.h (CpuSMAP): New.
	104	(i386_cpu_flags): Add cpusmap.
	105
	106	* i386-opc.tbl: Add clac and stac.
	107
	108	* i386-init.h: Regenerated.
	109	* i386-tbl.h: Likewise.
	110
9d1df426 NC	111	2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
	112
	113	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	114	which also makes the disassembler output be in little
	115	endian like it should be.
	116
a1ccaec9 YZ	117	2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
	118
	119	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	120	fields to NULL.
	121	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
	122
ef068ef4	123	2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e MR	124
	125	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	126	section disassembled.
	127
6fe6ded9 RE	128	2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	129
	130	* arm-dis.c: Update strht pattern.
	131
0aa27725 RS	132	2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
	133
	134	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	135	single-float. Disable ll, lld, sc and scd for EE. Disable the
	136	trunc.w.s macro for EE.
	137
36591ba1 SL	138	2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
	139	Andrew Jenner <andrew@codesourcery.com>
	140
	141	Based on patches from Altera Corporation.
	142
	143	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	144	nios2-opc.c.
	145	* Makefile.in: Regenerated.
	146	* configure.in: Add case for bfd_nios2_arch.
	147	* configure: Regenerated.
	148	* disassemble.c (ARCH_nios2): Define.
	149	(disassembler): Add case for bfd_arch_nios2.
	150	* nios2-dis.c: New file.
	151	* nios2-opc.c: New file.
	152
545093a4 AM	153	2013-02-04 Alan Modra <amodra@gmail.com>
	154
	155	* po/POTFILES.in: Regenerate.
	156	* rl78-decode.c: Regenerate.
	157	* rx-decode.c: Regenerate.
	158
e30181a5 YZ	159	2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
	160
	161	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	162	ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
	163	* aarch64-asm.c (convert_xtl_to_shll): New function.
	164	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	165	calling convert_xtl_to_shll.
	166	* aarch64-dis.c (convert_shll_to_xtl): New function.
	167	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	168	calling convert_shll_to_xtl.
	169	* aarch64-gen.c: Update copyright year.
	170	* aarch64-asm-2.c: Re-generate.
	171	* aarch64-dis-2.c: Re-generate.
	172	* aarch64-opc-2.c: Re-generate.
	173
78c8d46c NC	174	2013-01-24 Nick Clifton <nickc@redhat.com>
	175
	176	* v850-dis.c: Add support for e3v5 architecture.
	177	* v850-opc.c: Likewise.
	178
f5555712 YZ	179	2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
	180
	181	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	182	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	183	* aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c	184	AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712 YZ	185	alignment check; change to call set_sft_amount_out_of_range_error
	186	instead of set_imm_out_of_range_error.
	187	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	188	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	189	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	190	SIMD_IMM_SFT.
	191
2f81ff92 L	192	2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
	193
	194	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
	195
	196	* i386-init.h: Regenerated.
	197	* i386-tbl.h: Likewise.
	198
dd42f060 NC	199	2013-01-15 Nick Clifton <nickc@redhat.com>
	200
	201	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	202	values.
	203	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
	204
a4533ed8 NC	205	2013-01-14 Will Newton <will.newton@imgtec.com>
	206
	207	* metag-dis.c (REG_WIDTH): Increase to 64.
	208
5817ffd1 PB	209	2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
	210
	211	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	212	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	213	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	214	(SH6): Update.
	215	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	216	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	217	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	218	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
	219
a3c62988 NC	220	2013-01-10 Will Newton <will.newton@imgtec.com>
	221
	222	* Makefile.am: Add Meta.
	223	* configure.in: Add Meta.
	224	* disassemble.c: Add Meta support.
	225	* metag-dis.c: New file.
	226	* Makefile.in: Regenerate.
	227	* configure: Regenerate.
	228
73335eae NC	229	2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
	230
	231	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	232	(match_opcode): Rename to cr16_match_opcode.
	233
e407c74b NC	234	2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
	235
	236	* mips-dis.c: Add names for CP0 registers of r5900.
	237	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	238	instructions sq and lq.
	239	Add support for MIPS r5900 CPU.
	240	Add support for 128 bit MMI (Multimedia Instructions).
	241	Add support for EE instructions (Emotion Engine).
	242	Disable unsupported floating point instructions (64 bit and
	243	undefined compare operations).
	244	Enable instructions of MIPS ISA IV which are supported by r5900.
	245	Disable 64 bit co processor instructions.
	246	Disable 64 bit multiplication and division instructions.
	247	Disable instructions for co-processor 2 and 3, because these are
	248	not supported (preparation for later VU0 support (Vector Unit)).
	249	Disable cvt.w.s because this behaves like trunc.w.s and the
	250	correct execution can't be ensured on r5900.
	251	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	252	will confuse less developers and compilers.
	253
a32c3ff8 NC	254	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
a32c3ff8 NC	255
fb098a1e YZ	256	* aarch64-opc.c (aarch64_print_operand): Change to print
	257	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	258	in comment.
	259	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	260	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	261	OP_MOV_IMM_WIDE.
	262
	263	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
	264
	265	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	266	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8	267
62658407 L	268	2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
	269
	270	* i386-gen.c (process_copyright): Update copyright year to 2013.
	271
bab4becb	272	2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7	273
bab4becb NC	274	* cr16-dis.c (match_opcode,make_instruction): Remove static
	275	declaration.
	276	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	277	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7	278
bab4becb	279	For older changes see ChangeLog-2012
252b5132	280	\f
bab4becb	281	Copyright (C) 2013 Free Software Foundation, Inc.
752937aa NC	282
	283	Copying and distribution of this file, with or without modification,
	284	are permitted in any medium without royalty provided the copyright
	285	notice and this notice are preserved.
	286
252b5132	287	Local Variables:
2f6d2f85 NC	288	mode: change-log
	289	left-margin: 8
	290	fill-column: 74
252b5132 RH	291	version-control: never
252b5132 RH	292	End: