[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>

	* mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.

2013-05-20  Peter Bergner <bergner@vnet.ibm.com>

	* ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
	* ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
	XLS_MASK, PPCVSX2): New defines.
	(powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
	fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
	mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
	mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
	mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
	vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
	vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
	vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
	vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
	vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
	vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
	vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
	vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
	vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
	xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
	xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
	xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
	xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
	<lxvx, stxvx>: New extended mnemonics.

2013-05-17  Alan Modra  <amodra@gmail.com>

	* ia64-raw.tbl: Replace non-ASCII char.
	* ia64-waw.tbl: Likewise.
	* ia64-asmtab.c: Regenerate.

2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>

	* i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
	* i386-init.h: Regenerated.

2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
	* aarch64-opc.c (operand_general_constraint_met_p): Relax the range
	check from [0, 255] to [-128, 255].

2013-05-09  Andrew Pinski  <apinski@cavium.com>

	* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
	Add INSN_VIRT and INSN_VIRT64 to mips64r2.
	(parse_mips_dis_option): Handle the virt option.
	(print_insn_args): Handle "+J".
	(print_mips_disassembler_options): Print out message about virt64.
	* mips-opc.c (IVIRT): New define.
	(IVIRT64): New define.
	(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
	tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
	Move rfe to the bottom as it conflicts with tlbgp.

2013-05-09  Alan Modra  <amodra@gmail.com>

	* ppc-opc.c (extract_vlesi): Properly sign extend.
	(extract_vlensi): Likewise.  Comment reason for setting invalid.

2013-05-02  Nick Clifton  <nickc@redhat.com>

	* msp430-dis.c: Add support for MSP430X instructions.

2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>

	* nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
	to "eccinj".

2013-04-17  Wei-chen Wang  <cole945@gmail.com>

	PR binutils/15369
	* cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
	of CGEN_CPU_ENDIAN.
	(hash_insns_list): Likewise.

2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>

	* rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
	warning workaround.

2013-04-08  Jan Beulich <jbeulich@suse.com>

	* i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
	* i386-tbl.h: Re-generate.

2013-04-06  David S. Miller  <davem@davemloft.net>

	* sparc-dis.c (compare_opcodes): When encountering multiple aliases
	of an opcode, prefer the one with F_PREFERRED set.
	* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
	lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
	ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
	mark existing mnenomics as aliases.  Add "cc" suffix to edge
	instructions generating condition codes, mark existing mnenomics
	as aliases.  Add "fp" prefix to VIS compare instructions, mark
	existing mnenomics as aliases.

2013-04-03  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
	destination address by subtracting the operand from the current
	address.
	* v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
	a positive value in the insn.
	(extract_u16_loop): Do not negate the returned value.
	(D16_LOOP): Add V850_INVERSE_PCREL flag.

	(ceilf.sw): Remove duplicate entry.
	(cvtf.hs): New entry.
	(cvtf.sh): Likewise.
	(fmaf.s): Likewise.
	(fmsf.s): Likewise.
	(fnmaf.s): Likewise.
	(fnmsf.s): Likewise.
	(maddf.s): Restrict to E3V5 architectures.
	(msubf.s): Likewise.
	(nmaddf.s): Likewise.
	(nmsubf.s): Likewise.

2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (get_sib): Add the sizeflag argument.  Properly
	check address mode.
	(print_insn): Pass sizeflag to get_sib.

2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>

	PR binutils/15068
	* tic6x-dis.c: Add support for displaying 16-bit insns.

2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>

	PR gas/15095
	* tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
	individual msb and lsb halves in src1 & src2 fields.  Discard the
	src1 (lsb) value and only use src2 (msb), discarding bit 0, to
	follow what Ti SDK does in that case as any value in the src1
	field yields the same output with SDK disassembler.

2013-03-12  Michael Eager <eager@eagercon.com>

	* opcodes/mips-dis.c (print_insn_args): Modify def of reg.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.

2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>

	* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.

2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
	(thumb32_opcodes): Likewise.
	(print_insn_thumb32): Handle 'S' control char.

2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>

	* lm32-desc.c: Regenerate.

2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-reg.tbl (riz): Add RegRex64.
	* i386-tbl.h: Regenerated.

2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	(aarch64_feature_crc): New static.
	(CRC): New macro.
	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Ditto.
	* aarch64-opc-2.c: Ditto.

2013-02-27  Alan Modra  <amodra@gmail.com>

	* rl78-decode.opc (rl78_decode_opcode): Fix typo.
	* rl78-decode.c: Regenerate.

2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>

	* rl78-decode.opc: Fix encoding of DIVWU insn.
	* rl78-decode.c: Regenerate.

2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/15159
	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.

	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	(cpu_flags): Add CpuSMAP.

	* i386-opc.h (CpuSMAP): New.
	(i386_cpu_flags): Add cpusmap.

	* i386-opc.tbl: Add clac and stac.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>

	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	which also makes the disassembler output be in little
	endian like it should be.

2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	fields to NULL.
	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.

2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	section disassembled.

2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* arm-dis.c: Update strht pattern.

2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>

	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	single-float.  Disable ll, lld, sc and scd for EE.  Disable the
	trunc.w.s macro for EE.

2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
            Andrew Jenner <andrew@codesourcery.com>

	Based on patches from Altera Corporation.

	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	nios2-opc.c.
	* Makefile.in: Regenerated.
	* configure.in: Add case for bfd_nios2_arch.
	* configure: Regenerated.
	* disassemble.c (ARCH_nios2): Define.
	(disassembler): Add case for bfd_arch_nios2.
	* nios2-dis.c: New file.
	* nios2-opc.c: New file.

2013-02-04  Alan Modra  <amodra@gmail.com>

	* po/POTFILES.in: Regenerate.
	* rl78-decode.c: Regenerate.
	* rx-decode.c: Regenerate.

2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
	* aarch64-asm.c (convert_xtl_to_shll): New function.
	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_xtl_to_shll.
	* aarch64-dis.c (convert_shll_to_xtl): New function.
	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	calling convert_shll_to_xtl.
	* aarch64-gen.c: Update copyright year.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Re-generate.
	* aarch64-opc-2.c: Re-generate.

2013-01-24  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c: Add support for e3v5 architecture.
	* v850-opc.c: Likewise.

2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): For
	AARCH64_MOD_LSL, move the range check on the shift amount before the
	alignment check; change to call set_sft_amount_out_of_range_error
	instead of set_imm_out_of_range_error.
	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	SIMD_IMM_SFT.

2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2013-01-15  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	values.
	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.

2013-01-14  Will Newton <will.newton@imgtec.com>

	* metag-dis.c (REG_WIDTH): Increase to 64.

2013-01-10  Peter Bergner <bergner@vnet.ibm.com>

	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	(SH6): Update.
	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.

2013-01-10  Will Newton <will.newton@imgtec.com>

	* Makefile.am: Add Meta.
	* configure.in: Add Meta.
	* disassemble.c: Add Meta support.
	* metag-dis.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.

2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	(match_opcode): Rename to cr16_match_opcode.

2013-01-04  Juergen Urban <JuergenUrban@gmx.de>

	* mips-dis.c: Add names for CP0 registers of r5900.
	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	instructions sq and lq.
	Add support for MIPS r5900 CPU.
	Add support for 128 bit MMI (Multimedia Instructions).
	Add support for EE instructions (Emotion Engine).
	Disable unsupported floating point instructions (64 bit and
	undefined compare operations).
	Enable instructions of MIPS ISA IV which are supported by r5900.
	Disable 64 bit co processor instructions.
	Disable 64 bit multiplication and division instructions.
	Disable instructions for co-processor 2 and 3, because these are
	not supported (preparation for later VU0 support (Vector Unit)).
	Disable cvt.w.s because this behaves like trunc.w.s and the
	correct execution can't be ensured on r5900.
	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	will confuse less developers and compilers.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_print_operand): Change to print
	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	in comment.
	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	OP_MOV_IMM_WIDE.

2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>

	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.

2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (process_copyright): Update copyright year to 2013.

2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>

	* cr16-dis.c (match_opcode,make_instruction): Remove static
	declaration.
	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.

For older changes see ChangeLog-2012
\f
Copyright (C) 2013 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
c77c0862 RS	1	2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
	2
	3	* mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
	4
c0637f3a PB	5	2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
	6
	7	* ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
	8	* ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
	9	XLS_MASK, PPCVSX2): New defines.
	10	(powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
	11	fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
	12	mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
	13	mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
	14	mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
	15	vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
	16	vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
	17	vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
	18	vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
	19	vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
	20	vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
	21	vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
	22	vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
	23	vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
	24	xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
	25	xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
	26	xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
	27	xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
	28	<lxvx, stxvx>: New extended mnemonics.
	29
4934fdaf AM	30	2013-05-17 Alan Modra <amodra@gmail.com>
	31
	32	* ia64-raw.tbl: Replace non-ASCII char.
	33	* ia64-waw.tbl: Likewise.
	34	* ia64-asmtab.c: Regenerate.
	35
6091d651 SE	36	2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
	37
	38	* i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
	39	* i386-init.h: Regenerated.
	40
d2865ed3 YZ	41	2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
	42
	43	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
	44	* aarch64-opc.c (operand_general_constraint_met_p): Relax the range
	45	check from [0, 255] to [-128, 255].
	46
b015e599 AP	47	2013-05-09 Andrew Pinski <apinski@cavium.com>
	48
	49	* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
	50	Add INSN_VIRT and INSN_VIRT64 to mips64r2.
	51	(parse_mips_dis_option): Handle the virt option.
	52	(print_insn_args): Handle "+J".
	53	(print_mips_disassembler_options): Print out message about virt64.
	54	* mips-opc.c (IVIRT): New define.
	55	(IVIRT64): New define.
	56	(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
	57	tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
	58	Move rfe to the bottom as it conflicts with tlbgp.
	59
9f0682fe AM	60	2013-05-09 Alan Modra <amodra@gmail.com>
	61
	62	* ppc-opc.c (extract_vlesi): Properly sign extend.
	63	(extract_vlensi): Likewise. Comment reason for setting invalid.
	64
13761a11 NC	65	2013-05-02 Nick Clifton <nickc@redhat.com>
	66
	67	* msp430-dis.c: Add support for MSP430X instructions.
	68
e3031850 SL	69	2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
	70
	71	* nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
	72	to "eccinj".
	73
17310e56 NC	74	2013-04-17 Wei-chen Wang <cole945@gmail.com>
	75
	76	PR binutils/15369
	77	* cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
	78	of CGEN_CPU_ENDIAN.
	79	(hash_insns_list): Likewise.
	80
731df338 JK	81	2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
	82
	83	* rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
	84	warning workaround.
	85
5f77db52 JB	86	2013-04-08 Jan Beulich <jbeulich@suse.com>
	87
	88	* i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
	89	* i386-tbl.h: Re-generate.
	90
0afd1215 DM	91	2013-04-06 David S. Miller <davem@davemloft.net>
	92
	93	* sparc-dis.c (compare_opcodes): When encountering multiple aliases
	94	of an opcode, prefer the one with F_PREFERRED set.
	95	* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
	96	lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
	97	ops. Make 64-bit VIS logical ops have "d" suffix in their names,
	98	mark existing mnenomics as aliases. Add "cc" suffix to edge
	99	instructions generating condition codes, mark existing mnenomics
	100	as aliases. Add "fp" prefix to VIS compare instructions, mark
	101	existing mnenomics as aliases.
	102
41702d50 NC	103	2013-04-03 Nick Clifton <nickc@redhat.com>
	104
	105	* v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
	106	destination address by subtracting the operand from the current
	107	address.
	108	* v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
	109	a positive value in the insn.
	110	(extract_u16_loop): Do not negate the returned value.
	111	(D16_LOOP): Add V850_INVERSE_PCREL flag.
	112
	113	(ceilf.sw): Remove duplicate entry.
	114	(cvtf.hs): New entry.
	115	(cvtf.sh): Likewise.
	116	(fmaf.s): Likewise.
	117	(fmsf.s): Likewise.
	118	(fnmaf.s): Likewise.
	119	(fnmsf.s): Likewise.
	120	(maddf.s): Restrict to E3V5 architectures.
	121	(msubf.s): Likewise.
	122	(nmaddf.s): Likewise.
	123	(nmsubf.s): Likewise.
	124
55cf16e1 L	125	2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
	126
	127	* i386-dis.c (get_sib): Add the sizeflag argument. Properly
	128	check address mode.
	129	(print_insn): Pass sizeflag to get_sib.
	130
51dcdd4d NC	131	2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
	132
	133	PR binutils/15068
	134	* tic6x-dis.c: Add support for displaying 16-bit insns.
	135
795b8e6b NC	136	2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
	137
	138	PR gas/15095
	139	* tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
	140	individual msb and lsb halves in src1 & src2 fields. Discard the
	141	src1 (lsb) value and only use src2 (msb), discarding bit 0, to
	142	follow what Ti SDK does in that case as any value in the src1
	143	field yields the same output with SDK disassembler.
	144
314d60dd ME	145	2013-03-12 Michael Eager <eager@eagercon.com>
314d60dd ME	146
795b8e6b	147	* opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd	148
dad60f8e SL	149	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	150
	151	* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
	152
f5cb796a SL	153	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	154
	155	* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
	156
21fde85c SL	157	2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
	158
	159	* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
	160
dd5181d5 KT	161	2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	162
	163	* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
	164	(thumb32_opcodes): Likewise.
	165	(print_insn_thumb32): Handle 'S' control char.
	166
87a8d6cb NC	167	2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
	168
	169	* lm32-desc.c: Regenerate.
	170
99dce992 L	171	2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
	172
	173	* i386-reg.tbl (riz): Add RegRex64.
	174	* i386-tbl.h: Regenerated.
	175
e60bb1dd YZ	176	2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
	177
	178	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	179	(aarch64_feature_crc): New static.
	180	(CRC): New macro.
	181	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	182	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	183	* aarch64-asm-2.c: Re-generate.
	184	* aarch64-dis-2.c: Ditto.
	185	* aarch64-opc-2.c: Ditto.
	186
c7570fcd AM	187	2013-02-27 Alan Modra <amodra@gmail.com>
	188
	189	* rl78-decode.opc (rl78_decode_opcode): Fix typo.
	190	* rl78-decode.c: Regenerate.
	191
151fa98f NC	192	2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
	193
	194	* rl78-decode.opc: Fix encoding of DIVWU insn.
	195	* rl78-decode.c: Regenerate.
	196
5c111e37 L	197	2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
	198
	199	PR gas/15159
	200	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
	201
	202	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
	203	(cpu_flags): Add CpuSMAP.
	204
	205	* i386-opc.h (CpuSMAP): New.
	206	(i386_cpu_flags): Add cpusmap.
	207
	208	* i386-opc.tbl: Add clac and stac.
	209
	210	* i386-init.h: Regenerated.
	211	* i386-tbl.h: Likewise.
	212
9d1df426 NC	213	2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
	214
	215	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
	216	which also makes the disassembler output be in little
	217	endian like it should be.
	218
a1ccaec9 YZ	219	2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
	220
	221	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
	222	fields to NULL.
	223	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
	224
ef068ef4	225	2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e MR	226
	227	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
	228	section disassembled.
	229
6fe6ded9 RE	230	2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
	231
	232	* arm-dis.c: Update strht pattern.
	233
0aa27725 RS	234	2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
	235
	236	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	237	single-float. Disable ll, lld, sc and scd for EE. Disable the
	238	trunc.w.s macro for EE.
	239
36591ba1 SL	240	2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
	241	Andrew Jenner <andrew@codesourcery.com>
	242
	243	Based on patches from Altera Corporation.
	244
	245	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
	246	nios2-opc.c.
	247	* Makefile.in: Regenerated.
	248	* configure.in: Add case for bfd_nios2_arch.
	249	* configure: Regenerated.
	250	* disassemble.c (ARCH_nios2): Define.
	251	(disassembler): Add case for bfd_arch_nios2.
	252	* nios2-dis.c: New file.
	253	* nios2-opc.c: New file.
	254
545093a4 AM	255	2013-02-04 Alan Modra <amodra@gmail.com>
	256
	257	* po/POTFILES.in: Regenerate.
	258	* rl78-decode.c: Regenerate.
	259	* rx-decode.c: Regenerate.
	260
e30181a5 YZ	261	2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
	262
	263	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
	264	ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
	265	* aarch64-asm.c (convert_xtl_to_shll): New function.
	266	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	267	calling convert_xtl_to_shll.
	268	* aarch64-dis.c (convert_shll_to_xtl): New function.
	269	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
	270	calling convert_shll_to_xtl.
	271	* aarch64-gen.c: Update copyright year.
	272	* aarch64-asm-2.c: Re-generate.
	273	* aarch64-dis-2.c: Re-generate.
	274	* aarch64-opc-2.c: Re-generate.
	275
78c8d46c NC	276	2013-01-24 Nick Clifton <nickc@redhat.com>
	277
	278	* v850-dis.c: Add support for e3v5 architecture.
	279	* v850-opc.c: Likewise.
	280
f5555712 YZ	281	2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
	282
	283	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
	284	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
	285	* aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c	286	AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712 YZ	287	alignment check; change to call set_sft_amount_out_of_range_error
	288	instead of set_imm_out_of_range_error.
	289	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
	290	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
	291	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
	292	SIMD_IMM_SFT.
	293
2f81ff92 L	294	2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
	295
	296	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
	297
	298	* i386-init.h: Regenerated.
	299	* i386-tbl.h: Likewise.
	300
dd42f060 NC	301	2013-01-15 Nick Clifton <nickc@redhat.com>
	302
	303	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	304	values.
	305	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
	306
a4533ed8 NC	307	2013-01-14 Will Newton <will.newton@imgtec.com>
	308
	309	* metag-dis.c (REG_WIDTH): Increase to 64.
	310
5817ffd1 PB	311	2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
	312
	313	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	314	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	315	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	316	(SH6): Update.
	317	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	318	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	319	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	320	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
	321
a3c62988 NC	322	2013-01-10 Will Newton <will.newton@imgtec.com>
	323
	324	* Makefile.am: Add Meta.
	325	* configure.in: Add Meta.
	326	* disassemble.c: Add Meta support.
	327	* metag-dis.c: New file.
	328	* Makefile.in: Regenerate.
	329	* configure: Regenerate.
	330
73335eae NC	331	2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
	332
	333	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
	334	(match_opcode): Rename to cr16_match_opcode.
	335
e407c74b NC	336	2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
	337
	338	* mips-dis.c: Add names for CP0 registers of r5900.
	339	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
	340	instructions sq and lq.
	341	Add support for MIPS r5900 CPU.
	342	Add support for 128 bit MMI (Multimedia Instructions).
	343	Add support for EE instructions (Emotion Engine).
	344	Disable unsupported floating point instructions (64 bit and
	345	undefined compare operations).
	346	Enable instructions of MIPS ISA IV which are supported by r5900.
	347	Disable 64 bit co processor instructions.
	348	Disable 64 bit multiplication and division instructions.
	349	Disable instructions for co-processor 2 and 3, because these are
	350	not supported (preparation for later VU0 support (Vector Unit)).
	351	Disable cvt.w.s because this behaves like trunc.w.s and the
	352	correct execution can't be ensured on r5900.
	353	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
	354	will confuse less developers and compilers.
	355
a32c3ff8 NC	356	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
a32c3ff8 NC	357
fb098a1e YZ	358	* aarch64-opc.c (aarch64_print_operand): Change to print
	359	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
	360	in comment.
	361	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
	362	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
	363	OP_MOV_IMM_WIDE.
	364
	365	2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
	366
	367	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
	368	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8	369
62658407 L	370	2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
	371
	372	* i386-gen.c (process_copyright): Update copyright year to 2013.
	373
bab4becb	374	2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7	375
bab4becb NC	376	* cr16-dis.c (match_opcode,make_instruction): Remove static
	377	declaration.
	378	(dwordU,wordU): Moved typedefs to opcode/cr16.h
	379	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7	380
bab4becb	381	For older changes see ChangeLog-2012
252b5132	382	\f
bab4becb	383	Copyright (C) 2013 Free Software Foundation, Inc.
752937aa NC	384
	385	Copying and distribution of this file, with or without modification,
	386	are permitted in any medium without royalty provided the copyright
	387	notice and this notice are preserved.
	388
252b5132	389	Local Variables:
2f6d2f85 NC	390	mode: change-log
	391	left-margin: 8
	392	fill-column: 74
252b5132 RH	393	version-control: never
252b5132 RH	394	End: