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Remove some unused variables
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
8095d2f7
CX		 12018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
2 Maciej W. Rozycki <macro@mips.com>
3
4 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
5 loongson3a descriptors.
6 (parse_mips_ase_option): Handle -M loongson-mmi option.
7 (print_mips_disassembler_options): Document -M loongson-mmi.
8 * mips-opc.c (LMMI): New macro.
9 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
10 instructions.
11
5f32791e
JB		 122018-07-19 Jan Beulich <jbeulich@suse.com>
13
14 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
15 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
16 IgnoreSize and [XYZ]MMword where applicable.
17 * i386-tbl.h: Re-generate.
18
625cbd7a
JB		 192018-07-19 Jan Beulich <jbeulich@suse.com>
20
21 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
22 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
23 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
24 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
25 * i386-tbl.h: Re-generate.
26
86b15c32
JB		 272018-07-19 Jan Beulich <jbeulich@suse.com>
28
29 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
30 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
31 VPCLMULQDQ templates into their respective AVX512VL counterparts
32 where possible, using Disp8ShiftVL and CheckRegSize instead of
33 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
34 * i386-tbl.h: Re-generate.
35
cf769ed5
JB		 362018-07-19 Jan Beulich <jbeulich@suse.com>
37
38 * i386-opc.tbl: Fold AVX512DQ templates into their respective
39 AVX512VL counterparts where possible, using Disp8ShiftVL and
40 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
41 IgnoreSize) as appropriate.
42 * i386-tbl.h: Re-generate.
43
8282b7ad
JB		 442018-07-19 Jan Beulich <jbeulich@suse.com>
45
46 * i386-opc.tbl: Fold AVX512BW templates into their respective
47 AVX512VL counterparts where possible, using Disp8ShiftVL and
48 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
49 IgnoreSize) as appropriate.
50 * i386-tbl.h: Re-generate.
51
755908cc
JB		 522018-07-19 Jan Beulich <jbeulich@suse.com>
53
54 * i386-opc.tbl: Fold AVX512CD templates into their respective
55 AVX512VL counterparts where possible, using Disp8ShiftVL and
56 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
57 IgnoreSize) as appropriate.
58 * i386-tbl.h: Re-generate.
59
7091c612
JB		 602018-07-19 Jan Beulich <jbeulich@suse.com>
61
62 * i386-opc.h (DISP8_SHIFT_VL): New.
63 * i386-opc.tbl (Disp8ShiftVL): Define.
64 (various): Fold AVX512VL templates into their respective
65 AVX512F counterparts where possible, using Disp8ShiftVL and
66 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
67 IgnoreSize) as appropriate.
68 * i386-tbl.h: Re-generate.
69
c30be56e
JB		 702018-07-19 Jan Beulich <jbeulich@suse.com>
71
72 * Makefile.am: Change dependencies and rule for
73 $(srcdir)/i386-init.h.
74 * Makefile.in: Re-generate.
75 * i386-gen.c (process_i386_opcodes): New local variable
76 "marker". Drop opening of input file. Recognize marker and line
77 number directives.
78 * i386-opc.tbl (OPCODE_I386_H): Define.
79 (i386-opc.h): Include it.
80 (None): Undefine.
81
11a322db
L		 822018-07-18 H.J. Lu <hongjiu.lu@intel.com>
83
84 PR gas/23418
85 * i386-opc.h (Byte): Update comments.
86 (Word): Likewise.
87 (Dword): Likewise.
88 (Fword): Likewise.
89 (Qword): Likewise.
90 (Tbyte): Likewise.
91 (Xmmword): Likewise.
92 (Ymmword): Likewise.
93 (Zmmword): Likewise.
94 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
95 vcvttps2uqq.
96 * i386-tbl.h: Regenerated.
97
cde3679e
NC		 982018-07-12 Sudakshina Das <sudi.das@arm.com>
99
100 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
101 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
102 * aarch64-asm-2.c: Regenerate.
103 * aarch64-dis-2.c: Regenerate.
104 * aarch64-opc-2.c: Regenerate.
105
45a28947
TC		 1062018-07-12 Tamar Christina <tamar.christina@arm.com>
107
108 PR binutils/23192
109 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
110 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
111 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
112 sqdmulh, sqrdmulh): Use Em16.
113
c597cc3d
SD		 1142018-07-11 Sudakshina Das <sudi.das@arm.com>
115
116 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
117 csdb together with them.
118 (thumb32_opcodes): Likewise.
119
a79eaed6
JB		 1202018-07-11 Jan Beulich <jbeulich@suse.com>
121
122 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
123 requiring 32-bit registers as operands 2 and 3. Improve
124 comments.
125 (mwait, mwaitx): Fold templates. Improve comments.
126 OPERAND_TYPE_INOUTPORTREG.
127 * i386-tbl.h: Re-generate.
128
2fb5be8d
JB		 1292018-07-11 Jan Beulich <jbeulich@suse.com>
130
131 * i386-gen.c (operand_type_init): Remove
132 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
133 OPERAND_TYPE_INOUTPORTREG.
134 * i386-init.h: Re-generate.
135
7f5cad30
JB		 1362018-07-11 Jan Beulich <jbeulich@suse.com>
137
138 * i386-opc.tbl (wrssd, wrussd): Add Dword.
139 (wrssq, wrussq): Add Qword.
140 * i386-tbl.h: Re-generate.
141
f0a85b07
JB		 1422018-07-11 Jan Beulich <jbeulich@suse.com>
143
144 * i386-opc.h: Rename OTMax to OTNum.
145 (OTNumOfUints): Adjust calculation.
146 (OTUnused): Directly alias to OTNum.
147
9dcb0ba4
MR		 1482018-07-09 Maciej W. Rozycki <macro@mips.com>
149
150 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
151 `reg_xys'.
152 (lea_reg_xys): Likewise.
153 (print_insn_loop_primitive): Rename `reg' local variable to
154 `reg_dxy'.
155
f311ba7e
TC		 1562018-07-06 Tamar Christina <tamar.christina@arm.com>
157
158 PR binutils/23242
159 * aarch64-tbl.h (ldarh): Fix disassembly mask.
160
cba05feb
TC		 1612018-07-06 Tamar Christina <tamar.christina@arm.com>
162
163 PR binutils/23369
164 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
165 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
166
471b9d15
MR		 1672018-07-02 Maciej W. Rozycki <macro@mips.com>
168
169 PR tdep/8282
170 * mips-dis.c (mips_option_arg_t): New enumeration.
171 (mips_options): New variable.
172 (disassembler_options_mips): New function.
173 (print_mips_disassembler_options): Reimplement in terms of
174 `disassembler_options_mips'.
175 * arm-dis.c (disassembler_options_arm): Adapt to using the
176 `disasm_options_and_args_t' structure.
177 * ppc-dis.c (disassembler_options_powerpc): Likewise.
178 * s390-dis.c (disassembler_options_s390): Likewise.
179
c0c468d5
TP		 1802018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
181
182 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
183 expected result.
184 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
185 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
186 * testsuite/ld-arm/tls-longplt.d: Likewise.
187
369c9167
TC		 1882018-06-29 Tamar Christina <tamar.christina@arm.com>
189
190 PR binutils/23192
191 * aarch64-asm-2.c: Regenerate.
192 * aarch64-dis-2.c: Likewise.
193 * aarch64-opc-2.c: Likewise.
194 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
195 * aarch64-opc.c (operand_general_constraint_met_p,
196 aarch64_print_operand): Likewise.
197 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
198 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
199 fmlal2, fmlsl2.
200 (AARCH64_OPERANDS): Add Em2.
201
30aa1306
NC		 2022018-06-26 Nick Clifton <nickc@redhat.com>
203
204 * po/uk.po: Updated Ukranian translation.
205 * po/de.po: Updated German translation.
206 * po/pt_BR.po: Updated Brazilian Portuguese translation.
207
eca4b721
NC		 2082018-06-26 Nick Clifton <nickc@redhat.com>
209
210 * nfp-dis.c: Fix spelling mistake.
211
71300e2c
NC		 2122018-06-24 Nick Clifton <nickc@redhat.com>
213
214 * configure: Regenerate.
215 * po/opcodes.pot: Regenerate.
216
719d8288
NC		 2172018-06-24 Nick Clifton <nickc@redhat.com>
218
219 2.31 branch created.
220
514cd3a0
TC		 2212018-06-19 Tamar Christina <tamar.christina@arm.com>
222
223 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
224 * aarch64-asm-2.c: Regenerate.
225 * aarch64-dis-2.c: Likewise.
226
385e4d0f
MR		 2272018-06-21 Maciej W. Rozycki <macro@mips.com>
228
229 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
230 `-M ginv' option description.
231
160d1b3d
SH		 2322018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
233
234 PR gas/23305
235 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
236 la and lla.
237
d0ac1c44
SM		 2382018-06-19 Simon Marchi <simon.marchi@ericsson.com>
239
240 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
241 * configure.ac: Remove AC_PREREQ.
242 * Makefile.in: Re-generate.
243 * aclocal.m4: Re-generate.
244 * configure: Re-generate.
245
6f20c942
FS		 2462018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
247
248 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
249 mips64r6 descriptors.
250 (parse_mips_ase_option): Handle -Mginv option.
251 (print_mips_disassembler_options): Document -Mginv.
252 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
253 (GINV): New macro.
254 (mips_opcodes): Define ginvi and ginvt.
255
730c3174
SE		 2562018-06-13 Scott Egerton <scott.egerton@imgtec.com>
257 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
258
259 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
260 * mips-opc.c (CRC, CRC64): New macros.
261 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
262 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
263 crc32cd for CRC64.
264
cb366992
EB		 2652018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
266
267 PR 20319
268 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
269 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
270
ce72cd46
AM		 2712018-06-06 Alan Modra <amodra@gmail.com>
272
273 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
274 setjmp. Move init for some other vars later too.
275
4b8e28c7
MF		 2762018-06-04 Max Filippov <jcmvbkbc@gmail.com>
277
278 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
279 (dis_private): Add new fields for property section tracking.
280 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
281 (xtensa_instruction_fits): New functions.
282 (fetch_data): Bump minimal fetch size to 4.
283 (print_insn_xtensa): Make struct dis_private static.
284 Load and prepare property table on section change.
285 Don't disassemble literals. Don't disassemble instructions that
286 cross property table boundaries.
287
55e99962
L		 2882018-06-01 H.J. Lu <hongjiu.lu@intel.com>
289
290 * configure: Regenerated.
291
733bd0ab
JB		 2922018-06-01 Jan Beulich <jbeulich@suse.com>
293
294 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
295 * i386-tbl.h: Re-generate.
296
dfd27d41
JB		 2972018-06-01 Jan Beulich <jbeulich@suse.com>
298
299 * i386-opc.tbl (sldt, str): Add NoRex64.
300 * i386-tbl.h: Re-generate.
301
64795710
JB		 3022018-06-01 Jan Beulich <jbeulich@suse.com>
303
304 * i386-opc.tbl (invpcid): Add Oword.
305 * i386-tbl.h: Re-generate.
306
030157d8
AM		 3072018-06-01 Alan Modra <amodra@gmail.com>
308
309 * sysdep.h (_bfd_error_handler): Don't declare.
310 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
311 * rl78-decode.opc: Likewise.
312 * msp430-decode.c: Regenerate.
313 * rl78-decode.c: Regenerate.
314
a9660a6f
AP		 3152018-05-30 Amit Pawar <Amit.Pawar@amd.com>
316
317 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
318 * i386-init.h : Regenerated.
319
277eb7f6
AM		 3202018-05-25 Alan Modra <amodra@gmail.com>
321
322 * Makefile.in: Regenerate.
323 * po/POTFILES.in: Regenerate.
324
98553ad3
PB		 3252018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
326
327 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
328 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
329 (insert_bab, extract_bab, insert_btab, extract_btab,
330 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
331 (BAT, BBA VBA RBS XB6S): Delete macros.
332 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
333 (BB, BD, RBX, XC6): Update for new macros.
334 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
335 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
336 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
337 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
338
7b4ae824
JD		 3392018-05-18 John Darrington <john@darrington.wattle.id.au>
340
341 * Makefile.am: Add support for s12z architecture.
342 * configure.ac: Likewise.
343 * disassemble.c: Likewise.
344 * disassemble.h: Likewise.
345 * Makefile.in: Regenerate.
346 * configure: Regenerate.
347 * s12z-dis.c: New file.
348 * s12z.h: New file.
349
29e0f0a1
AM		 3502018-05-18 Alan Modra <amodra@gmail.com>
351
352 * nfp-dis.c: Don't #include libbfd.h.
353 (init_nfp3200_priv): Use bfd_get_section_contents.
354 (nit_nfp6000_mecsr_sec): Likewise.
355
809276d2
NC		 3562018-05-17 Nick Clifton <nickc@redhat.com>
357
358 * po/zh_CN.po: Updated simplified Chinese translation.
359
ff329288
TC		 3602018-05-16 Tamar Christina <tamar.christina@arm.com>
361
362 PR binutils/23109
363 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
364 * aarch64-dis-2.c: Regenerate.
365
f9830ec1
TC		 3662018-05-15 Tamar Christina <tamar.christina@arm.com>
367
368 PR binutils/21446
369 * aarch64-asm.c (opintl.h): Include.
370 (aarch64_ins_sysreg): Enforce read/write constraints.
371 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
372 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
373 (F_REG_READ, F_REG_WRITE): New.
374 * aarch64-opc.c (aarch64_print_operand): Generate notes for
375 AARCH64_OPND_SYSREG.
376 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
377 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
378 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
379 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
380 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
381 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
382 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
383 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
384 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
385 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
386 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
387 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
388 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
389 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
390 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
391 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
392 msr (F_SYS_WRITE), mrs (F_SYS_READ).
393
7d02540a
TC		 3942018-05-15 Tamar Christina <tamar.christina@arm.com>
395
396 PR binutils/21446
397 * aarch64-dis.c (no_notes: New.
398 (parse_aarch64_dis_option): Support notes.
399 (aarch64_decode_insn, print_operands): Likewise.
400 (print_aarch64_disassembler_options): Document notes.
401 * aarch64-opc.c (aarch64_print_operand): Support notes.
402
561a72d4
TC		 4032018-05-15 Tamar Christina <tamar.christina@arm.com>
404
405 PR binutils/21446
406 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
407 and take error struct.
408 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
409 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
410 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
411 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
412 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
413 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
414 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
415 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
416 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
417 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
418 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
419 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
420 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
421 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
422 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
423 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
424 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
425 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
426 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
427 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
428 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
429 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
430 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
431 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
432 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
433 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
434 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
435 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
436 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
437 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
438 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
439 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
440 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
441 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
442 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
443 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
444 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
445 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
446 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
447 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
448 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
449 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
450 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
451 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
452 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
453 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
454 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
455 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
456 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
457 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
458 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
459 (determine_disassembling_preference, aarch64_decode_insn,
460 print_insn_aarch64_word, print_insn_data): Take errors struct.
461 (print_insn_aarch64): Use errors.
462 * aarch64-asm-2.c: Regenerate.
463 * aarch64-dis-2.c: Regenerate.
464 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
465 boolean in aarch64_insert_operan.
466 (print_operand_extractor): Likewise.
467 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
468
1678bd35
FT		 4692018-05-15 Francois H. Theron <francois.theron@netronome.com>
470
471 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
472
06cfb1c8
L		 4732018-05-09 H.J. Lu <hongjiu.lu@intel.com>
474
475 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
476
84f9f8c3
AM		 4772018-05-09 Sebastian Rasmussen <sebras@gmail.com>
478
479 * cr16-opc.c (cr16_instruction): Comment typo fix.
480 * hppa-dis.c (print_insn_hppa): Likewise.
481
e6f372ba
JW		 4822018-05-08 Jim Wilson <jimw@sifive.com>
483
484 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
485 (match_c_slli64, match_srxi_as_c_srxi): New.
486 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
487 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
488 <c.slli, c.srli, c.srai>: Use match_s_slli.
489 <c.slli64, c.srli64, c.srai64>: New.
490
f413a913
AM		 4912018-05-08 Alan Modra <amodra@gmail.com>
492
493 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
494 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
495 partition opcode space for index lookup.
496
a87a6478
PB		 4972018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
498
499 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
500 <insn_length>: ...with this. Update usage.
501 Remove duplicate call to *info->memory_error_func.
502
c0a30a9f
L		 5032018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
504 H.J. Lu <hongjiu.lu@intel.com>
505
506 * i386-dis.c (Gva): New.
507 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
508 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
509 (prefix_table): New instructions (see prefix above).
510 (mod_table): New instructions (see prefix above).
511 (OP_G): Handle va_mode.
512 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
513 CPU_MOVDIR64B_FLAGS.
514 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
515 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
516 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
517 * i386-opc.tbl: Add movidir{i,64b}.
518 * i386-init.h: Regenerated.
519 * i386-tbl.h: Likewise.
520
75c0a438
L		 5212018-05-07 H.J. Lu <hongjiu.lu@intel.com>
522
523 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
524 AddrPrefixOpReg.
525 * i386-opc.h (AddrPrefixOp0): Renamed to ...
526 (AddrPrefixOpReg): This.
527 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
528 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
529
2ceb7719
PB		 5302018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
531
532 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
533 (vle_num_opcodes): Likewise.
534 (spe2_num_opcodes): Likewise.
535 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
536 initialization loop.
537 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
538 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
539 only once.
540
b3ac5c6c
TC		 5412018-05-01 Tamar Christina <tamar.christina@arm.com>
542
543 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
544
fe944acf
FT		 5452018-04-30 Francois H. Theron <francois.theron@netronome.com>
546
547 Makefile.am: Added nfp-dis.c.
548 configure.ac: Added bfd_nfp_arch.
549 disassemble.h: Added print_insn_nfp prototype.
550 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
551 nfp-dis.c: New, for NFP support.
552 po/POTFILES.in: Added nfp-dis.c to the list.
553 Makefile.in: Regenerate.
554 configure: Regenerate.
555
e2195274
JB		 5562018-04-26 Jan Beulich <jbeulich@suse.com>
557
558 * i386-opc.tbl: Fold various non-memory operand AVX512VL
559 templates into their base ones.
560 * i386-tlb.h: Re-generate.
561
59ef5df4
JB		 5622018-04-26 Jan Beulich <jbeulich@suse.com>
563
564 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
565 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
566 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
567 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
568 * i386-init.h: Re-generate.
569
6e041cf4
JB		 5702018-04-26 Jan Beulich <jbeulich@suse.com>
571
572 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
573 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
574 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
575 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
576 comment.
577 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
578 and CpuRegMask.
579 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
580 CpuRegMask: Delete.
581 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
582 cpuregzmm, and cpuregmask.
583 * i386-init.h: Re-generate.
584 * i386-tbl.h: Re-generate.
585
0e0eea78
JB		 5862018-04-26 Jan Beulich <jbeulich@suse.com>
587
588 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
589 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
590 * i386-init.h: Re-generate.
591
2f1bada2
JB		 5922018-04-26 Jan Beulich <jbeulich@suse.com>
593
594 * i386-gen.c (VexImmExt): Delete.
595 * i386-opc.h (VexImmExt, veximmext): Delete.
596 * i386-opc.tbl: Drop all VexImmExt uses.
597 * i386-tlb.h: Re-generate.
598
bacd1457
JB		 5992018-04-25 Jan Beulich <jbeulich@suse.com>
600
601 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
602 register-only forms.
603 * i386-tlb.h: Re-generate.
604
10bba94b
TC		 6052018-04-25 Tamar Christina <tamar.christina@arm.com>
606
607 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
608
c48935d7
IT		 6092018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
610
611 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
612 PREFIX_0F1C.
613 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
614 (cpu_flags): Add CpuCLDEMOTE.
615 * i386-init.h: Regenerate.
616 * i386-opc.h (enum): Add CpuCLDEMOTE,
617 (i386_cpu_flags): Add cpucldemote.
618 * i386-opc.tbl: Add cldemote.
619 * i386-tbl.h: Regenerate.
620
211dc24b
AM		 6212018-04-16 Alan Modra <amodra@gmail.com>
622
623 * Makefile.am: Remove sh5 and sh64 support.
624 * configure.ac: Likewise.
625 * disassemble.c: Likewise.
626 * disassemble.h: Likewise.
627 * sh-dis.c: Likewise.
628 * sh64-dis.c: Delete.
629 * sh64-opc.c: Delete.
630 * sh64-opc.h: Delete.
631 * Makefile.in: Regenerate.
632 * configure: Regenerate.
633 * po/POTFILES.in: Regenerate.
634
a9a4b302
AM		 6352018-04-16 Alan Modra <amodra@gmail.com>
636
637 * Makefile.am: Remove w65 support.
638 * configure.ac: Likewise.
639 * disassemble.c: Likewise.
640 * disassemble.h: Likewise.
641 * w65-dis.c: Delete.
642 * w65-opc.h: Delete.
643 * Makefile.in: Regenerate.
644 * configure: Regenerate.
645 * po/POTFILES.in: Regenerate.
646
04cb01fd
AM		 6472018-04-16 Alan Modra <amodra@gmail.com>
648
649 * configure.ac: Remove we32k support.
650 * configure: Regenerate.
651
c2bf1eec
AM		 6522018-04-16 Alan Modra <amodra@gmail.com>
653
654 * Makefile.am: Remove m88k support.
655 * configure.ac: Likewise.
656 * disassemble.c: Likewise.
657 * disassemble.h: Likewise.
658 * m88k-dis.c: Delete.
659 * Makefile.in: Regenerate.
660 * configure: Regenerate.
661 * po/POTFILES.in: Regenerate.
662
6793974d
AM		 6632018-04-16 Alan Modra <amodra@gmail.com>
664
665 * Makefile.am: Remove i370 support.
666 * configure.ac: Likewise.
667 * disassemble.c: Likewise.
668 * disassemble.h: Likewise.
669 * i370-dis.c: Delete.
670 * i370-opc.c: Delete.
671 * Makefile.in: Regenerate.
672 * configure: Regenerate.
673 * po/POTFILES.in: Regenerate.
674
e82aa794
AM		 6752018-04-16 Alan Modra <amodra@gmail.com>
676
677 * Makefile.am: Remove h8500 support.
678 * configure.ac: Likewise.
679 * disassemble.c: Likewise.
680 * disassemble.h: Likewise.
681 * h8500-dis.c: Delete.
682 * h8500-opc.h: Delete.
683 * Makefile.in: Regenerate.
684 * configure: Regenerate.
685 * po/POTFILES.in: Regenerate.
686
fceadf09
AM		 6872018-04-16 Alan Modra <amodra@gmail.com>
688
689 * configure.ac: Remove tahoe support.
690 * configure: Regenerate.
691
ae1d3843
L		 6922018-04-15 H.J. Lu <hongjiu.lu@intel.com>
693
694 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
695 umwait.
696 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
697 64-bit mode.
698 * i386-tbl.h: Regenerated.
699
de89d0a3
IT		 7002018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
701
702 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
703 PREFIX_MOD_1_0FAE_REG_6.
704 (va_mode): New.
705 (OP_E_register): Use va_mode.
706 * i386-dis-evex.h (prefix_table):
707 New instructions (see prefixes above).
708 * i386-gen.c (cpu_flag_init): Add WAITPKG.
709 (cpu_flags): Likewise.
710 * i386-opc.h (enum): Likewise.
711 (i386_cpu_flags): Likewise.
712 * i386-opc.tbl: Add umonitor, umwait, tpause.
713 * i386-init.h: Regenerate.
714 * i386-tbl.h: Likewise.
715
a8eb42a8
AM		 7162018-04-11 Alan Modra <amodra@gmail.com>
717
718 * opcodes/i860-dis.c: Delete.
719 * opcodes/i960-dis.c: Delete.
720 * Makefile.am: Remove i860 and i960 support.
721 * configure.ac: Likewise.
722 * disassemble.c: Likewise.
723 * disassemble.h: Likewise.
724 * Makefile.in: Regenerate.
725 * configure: Regenerate.
726 * po/POTFILES.in: Regenerate.
727
caf0678c
L		 7282018-04-04 H.J. Lu <hongjiu.lu@intel.com>
729
730 PR binutils/23025
731 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
732 to 0.
733 (print_insn): Clear vex instead of vex.evex.
734
4fb0d2b9
NC		 7352018-04-04 Nick Clifton <nickc@redhat.com>
736
737 * po/es.po: Updated Spanish translation.
738
c39e5b26
JB		 7392018-03-28 Jan Beulich <jbeulich@suse.com>
740
741 * i386-gen.c (opcode_modifiers): Delete VecESize.
742 * i386-opc.h (VecESize): Delete.
743 (struct i386_opcode_modifier): Delete vecesize.
744 * i386-opc.tbl: Drop VecESize.
745 * i386-tlb.h: Re-generate.
746
8e6e0792
JB		 7472018-03-28 Jan Beulich <jbeulich@suse.com>
748
749 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
750 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
751 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
752 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
753 * i386-tlb.h: Re-generate.
754
9f123b91
JB		 7552018-03-28 Jan Beulich <jbeulich@suse.com>
756
757 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
758 Fold AVX512 forms
759 * i386-tlb.h: Re-generate.
760
9646c87b
JB		 7612018-03-28 Jan Beulich <jbeulich@suse.com>
762
763 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
764 (vex_len_table): Drop Y for vcvt*2si.
765 (putop): Replace plain 'Y' handling by abort().
766
c8d59609
NC		 7672018-03-28 Nick Clifton <nickc@redhat.com>
768
769 PR 22988
770 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
771 instructions with only a base address register.
772 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
773 handle AARHC64_OPND_SVE_ADDR_R.
774 (aarch64_print_operand): Likewise.
775 * aarch64-asm-2.c: Regenerate.
776 * aarch64_dis-2.c: Regenerate.
777 * aarch64-opc-2.c: Regenerate.
778
b8c169f3
JB		 7792018-03-22 Jan Beulich <jbeulich@suse.com>
780
781 * i386-opc.tbl: Drop VecESize from register only insn forms and
782 memory forms not allowing broadcast.
783 * i386-tlb.h: Re-generate.
784
96bc132a
JB		 7852018-03-22 Jan Beulich <jbeulich@suse.com>
786
787 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
788 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
789 sha256*): Drop Disp<N>.
790
9f79e886
JB		 7912018-03-22 Jan Beulich <jbeulich@suse.com>
792
793 * i386-dis.c (EbndS, bnd_swap_mode): New.
794 (prefix_table): Use EbndS.
795 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
796 * i386-opc.tbl (bndmov): Move misplaced Load.
797 * i386-tlb.h: Re-generate.
798
d6793fa1
JB		 7992018-03-22 Jan Beulich <jbeulich@suse.com>
800
801 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
802 templates allowing memory operands and folded ones for register
803 only flavors.
804 * i386-tlb.h: Re-generate.
805
f7768225
JB		 8062018-03-22 Jan Beulich <jbeulich@suse.com>
807
808 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
809 256-bit templates. Drop redundant leftover Disp<N>.
810 * i386-tlb.h: Re-generate.
811
0e35537d
JW		 8122018-03-14 Kito Cheng <kito.cheng@gmail.com>
813
814 * riscv-opc.c (riscv_insn_types): New.
815
b4a3689a
NC		 8162018-03-13 Nick Clifton <nickc@redhat.com>
817
818 * po/pt_BR.po: Updated Brazilian Portuguese translation.
819
d3d50934
L		 8202018-03-08 H.J. Lu <hongjiu.lu@intel.com>
821
822 * i386-opc.tbl: Add Optimize to clr.
823 * i386-tbl.h: Regenerated.
824
bd5dea88
L		 8252018-03-08 H.J. Lu <hongjiu.lu@intel.com>
826
827 * i386-gen.c (opcode_modifiers): Remove OldGcc.
828 * i386-opc.h (OldGcc): Removed.
829 (i386_opcode_modifier): Remove oldgcc.
830 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
831 instructions for old (<= 2.8.1) versions of gcc.
832 * i386-tbl.h: Regenerated.
833
e771e7c9
JB		 8342018-03-08 Jan Beulich <jbeulich@suse.com>
835
836 * i386-opc.h (EVEXDYN): New.
837 * i386-opc.tbl: Fold various AVX512VL templates.
838 * i386-tlb.h: Re-generate.
839
ed438a93
JB		 8402018-03-08 Jan Beulich <jbeulich@suse.com>
841
842 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
843 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
844 vpexpandd, vpexpandq): Fold AFX512VF templates.
845 * i386-tlb.h: Re-generate.
846
454172a9
JB		 8472018-03-08 Jan Beulich <jbeulich@suse.com>
848
849 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
850 Fold 128- and 256-bit VEX-encoded templates.
851 * i386-tlb.h: Re-generate.
852
36824150
JB		 8532018-03-08 Jan Beulich <jbeulich@suse.com>
854
855 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
856 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
857 vpexpandd, vpexpandq): Fold AVX512F templates.
858 * i386-tlb.h: Re-generate.
859
e7f5c0a9
JB		 8602018-03-08 Jan Beulich <jbeulich@suse.com>
861
862 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
863 64-bit templates. Drop Disp<N>.
864 * i386-tlb.h: Re-generate.
865
25a4277f
JB		 8662018-03-08 Jan Beulich <jbeulich@suse.com>
867
868 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
869 and 256-bit templates.
870 * i386-tlb.h: Re-generate.
871
d2224064
JB		 8722018-03-08 Jan Beulich <jbeulich@suse.com>
873
874 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
875 * i386-tlb.h: Re-generate.
876
1b193f0b
JB		 8772018-03-08 Jan Beulich <jbeulich@suse.com>
878
879 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
880 Drop NoAVX.
881 * i386-tlb.h: Re-generate.
882
f2f6a710
JB		 8832018-03-08 Jan Beulich <jbeulich@suse.com>
884
885 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
886 * i386-tlb.h: Re-generate.
887
38e314eb
JB		 8882018-03-08 Jan Beulich <jbeulich@suse.com>
889
890 * i386-gen.c (opcode_modifiers): Delete FloatD.
891 * i386-opc.h (FloatD): Delete.
892 (struct i386_opcode_modifier): Delete floatd.
893 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
894 FloatD by D.
895 * i386-tlb.h: Re-generate.
896
d53e6b98
JB		 8972018-03-08 Jan Beulich <jbeulich@suse.com>
898
899 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
900
2907c2f5
JB		 9012018-03-08 Jan Beulich <jbeulich@suse.com>
902
903 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
904 * i386-tlb.h: Re-generate.
905
73053c1f
JB		 9062018-03-08 Jan Beulich <jbeulich@suse.com>
907
908 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
909 forms.
910 * i386-tlb.h: Re-generate.
911
52fe4420
AM		 9122018-03-07 Alan Modra <amodra@gmail.com>
913
914 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
915 bfd_arch_rs6000.
916 * disassemble.h (print_insn_rs6000): Delete.
917 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
918 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
919 (print_insn_rs6000): Delete.
920
a6743a54
AM		 9212018-03-03 Alan Modra <amodra@gmail.com>
922
923 * sysdep.h (opcodes_error_handler): Define.
924 (_bfd_error_handler): Declare.
925 * Makefile.am: Remove stray #.
926 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
927 EDIT" comment.
928 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
929 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
930 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
931 opcodes_error_handler to print errors. Standardize error messages.
932 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
933 and include opintl.h.
934 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
935 * i386-gen.c: Standardize error messages.
936 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
937 * Makefile.in: Regenerate.
938 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
939 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
940 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
941 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
942 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
943 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
944 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
945 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
946 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
947 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
948 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
949 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
950 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
951
8305403a
L		 9522018-03-01 H.J. Lu <hongjiu.lu@intel.com>
953
954 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
955 vpsub[bwdq] instructions.
956 * i386-tbl.h: Regenerated.
957
e184813f
AM		 9582018-03-01 Alan Modra <amodra@gmail.com>
959
960 * configure.ac (ALL_LINGUAS): Sort.
961 * configure: Regenerate.
962
5b616bef
TP		 9632018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
964
965 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
966 macro by assignements.
967
b6f8c7c4
L		 9682018-02-27 H.J. Lu <hongjiu.lu@intel.com>
969
970 PR gas/22871
971 * i386-gen.c (opcode_modifiers): Add Optimize.
972 * i386-opc.h (Optimize): New enum.
973 (i386_opcode_modifier): Add optimize.
974 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
975 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
976 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
977 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
978 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
979 vpxord and vpxorq.
980 * i386-tbl.h: Regenerated.
981
e95b887f
AM		 9822018-02-26 Alan Modra <amodra@gmail.com>
983
984 * crx-dis.c (getregliststring): Allocate a large enough buffer
985 to silence false positive gcc8 warning.
986
0bccfb29
JW		 9872018-02-22 Shea Levy <shea@shealevy.com>
988
989 * disassemble.c (ARCH_riscv): Define if ARCH_all.
990
6b6b6807
L		 9912018-02-22 H.J. Lu <hongjiu.lu@intel.com>
992
993 * i386-opc.tbl: Add {rex},
994 * i386-tbl.h: Regenerated.
995
75f31665
MR		 9962018-02-20 Maciej W. Rozycki <macro@mips.com>
997
998 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
999 (mips16_opcodes): Replace `M' with `m' for "restore".
1000
e207bc53
TP		 10012018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1002
1003 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1004
87993319
MR		 10052018-02-13 Maciej W. Rozycki <macro@mips.com>
1006
1007 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1008 variable to `function_index'.
1009
68d20676
NC		 10102018-02-13 Nick Clifton <nickc@redhat.com>
1011
1012 PR 22823
1013 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1014 about truncation of printing.
1015
d2159fdc
HW		 10162018-02-12 Henry Wong <henry@stuffedcow.net>
1017
1018 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1019
f174ef9f
NC		 10202018-02-05 Nick Clifton <nickc@redhat.com>
1021
1022 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1023
be3a8dca
IT		 10242018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1025
1026 * i386-dis.c (enum): Add pconfig.
1027 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1028 (cpu_flags): Add CpuPCONFIG.
1029 * i386-opc.h (enum): Add CpuPCONFIG.
1030 (i386_cpu_flags): Add cpupconfig.
1031 * i386-opc.tbl: Add PCONFIG instruction.
1032 * i386-init.h: Regenerate.
1033 * i386-tbl.h: Likewise.
1034
3233d7d0
IT		 10352018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1036
1037 * i386-dis.c (enum): Add PREFIX_0F09.
1038 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1039 (cpu_flags): Add CpuWBNOINVD.
1040 * i386-opc.h (enum): Add CpuWBNOINVD.
1041 (i386_cpu_flags): Add cpuwbnoinvd.
1042 * i386-opc.tbl: Add WBNOINVD instruction.
1043 * i386-init.h: Regenerate.
1044 * i386-tbl.h: Likewise.
1045
e925c834
JW		 10462018-01-17 Jim Wilson <jimw@sifive.com>
1047
1048 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1049
d777820b
IT		 10502018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1051
1052 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1053 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1054 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1055 (cpu_flags): Add CpuIBT, CpuSHSTK.
1056 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1057 (i386_cpu_flags): Add cpuibt, cpushstk.
1058 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1059 * i386-init.h: Regenerate.
1060 * i386-tbl.h: Likewise.
1061
f6efed01
NC		 10622018-01-16 Nick Clifton <nickc@redhat.com>
1063
1064 * po/pt_BR.po: Updated Brazilian Portugese translation.
1065 * po/de.po: Updated German translation.
1066
2721d702
JW		 10672018-01-15 Jim Wilson <jimw@sifive.com>
1068
1069 * riscv-opc.c (match_c_nop): New.
1070 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1071
616dcb87
NC		 10722018-01-15 Nick Clifton <nickc@redhat.com>
1073
1074 * po/uk.po: Updated Ukranian translation.
1075
3957a496
NC		 10762018-01-13 Nick Clifton <nickc@redhat.com>
1077
1078 * po/opcodes.pot: Regenerated.
1079
769c7ea5
NC		 10802018-01-13 Nick Clifton <nickc@redhat.com>
1081
1082 * configure: Regenerate.
1083
faf766e3
NC		 10842018-01-13 Nick Clifton <nickc@redhat.com>
1085
1086 2.30 branch created.
1087
888a89da
IT		 10882018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1089
1090 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1091 * i386-tbl.h: Regenerate.
1092
cbda583a
JB		 10932018-01-10 Jan Beulich <jbeulich@suse.com>
1094
1095 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1096 * i386-tbl.h: Re-generate.
1097
c9e92278
JB		 10982018-01-10 Jan Beulich <jbeulich@suse.com>
1099
1100 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1101 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1102 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1103 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1104 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1105 Disp8MemShift of AVX512VL forms.
1106 * i386-tbl.h: Re-generate.
1107
35fd2b2b
JW		 11082018-01-09 Jim Wilson <jimw@sifive.com>
1109
1110 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1111 then the hi_addr value is zero.
1112
91d8b670
JG		 11132018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1114
1115 * arm-dis.c (arm_opcodes): Add csdb.
1116 (thumb32_opcodes): Add csdb.
1117
be2e7d95
JG		 11182018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1119
1120 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1121 * aarch64-asm-2.c: Regenerate.
1122 * aarch64-dis-2.c: Regenerate.
1123 * aarch64-opc-2.c: Regenerate.
1124
704a705d
L		 11252018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1126
1127 PR gas/22681
1128 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1129 Remove AVX512 vmovd with 64-bit operands.
1130 * i386-tbl.h: Regenerated.
1131
35eeb78f
JW		 11322018-01-05 Jim Wilson <jimw@sifive.com>
1133
1134 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1135 jalr.
1136
219d1afa
AM		 11372018-01-03 Alan Modra <amodra@gmail.com>
1138
1139 Update year range in copyright notice of all files.
1140
1508bbf5
JB		 11412018-01-02 Jan Beulich <jbeulich@suse.com>
1142
1143 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1144 and OPERAND_TYPE_REGZMM entries.
1145
1e563868 1146For older changes see ChangeLog-2017
3499769a 1147\f
1e563868 1148Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1149
1150Copying and distribution of this file, with or without modification,
1151are permitted in any medium without royalty provided the copyright
1152notice and this notice are preserved.
1153
1154Local Variables:
1155mode: change-log
1156left-margin: 8
1157fill-column: 74
1158version-control: never
1159End:
GDB Binutils - Deliverables
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