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[AArch64][PATCH 2/3] Adjust a utility function for floating point values.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
cf86120b
MW		 12015-11-27 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64-opc.c (half_conv_t): New.
4 (expand_fp_imm): Replace is_dp flag with the parameter size to
5 specify the number of bytes for the required expansion. Treat
6 a 16-bit expansion like a 32-bit expansion. Add check for an
7 unsupported size request. Update comment.
8 (aarch64_print_operand): Update to support 16-bit floating point
9 values. Update for changes to expand_fp_imm.
10
3bd894a7
MW		 112015-11-27 Matthew Wahab <matthew.wahab@arm.com>
12
13 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
14 (FP_F16): New.
15
64357d2e
MW		 162015-11-27 Matthew Wahab <matthew.wahab@arm.com>
17
18 * aarch64-asm-2.c: Regenerate.
19 * aarch64-dis-2.c: Regenerate.
20 * aarch64-opc-2.c: Regenerate.
21 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
22 "rev64".
23
d685192a
MW		 242015-11-27 Matthew Wahab <matthew.wahab@arm.com>
25
26 * aarch64-asm-2.c: Regenerate.
27 * aarch64-asm.c (convert_bfc_to_bfm): New.
28 (convert_to_real): Add case for OP_BFC.
29 * aarch64-dis-2.c: Regenerate.
30 * aarch64-dis.c: (convert_bfm_to_bfc): New.
31 (convert_to_alias): Add case for OP_BFC.
32 * aarch64-opc-2.c: Regenerate.
33 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
34 to allow width operand in three-operand instructions.
35 * aarch64-tbl.h (QL_BF1): New.
36 (aarch64_feature_v8_2): New.
37 (ARMV8_2): New.
38 (aarch64_opcode_table): Add "bfc".
39
35822b38
MW		 402015-11-27 Matthew Wahab <matthew.wahab@arm.com>
41
42 * aarch64-asm-2.c: Regenerate.
43 * aarch64-dis-2.c: Regenerate.
44 * aarch64-dis.c: Weaken assert.
45 * aarch64-gen.c: Include the instruction in the list of its
46 possible aliases.
47
1a04d1a7
MW		 482015-11-27 Matthew Wahab <matthew.wahab@arm.com>
49
50 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
51 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
52 feature test.
53
e49d43ff
TG		 542015-11-23 Tristan Gingold <gingold@adacore.com>
55
56 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
57
250aafa4
MW		 582015-11-20 Matthew Wahab <matthew.wahab@arm.com>
59
60 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
61 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
62 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
63 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
64 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
65 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
66 cnthv_ctl_el2, cnthv_cval_el2.
67 (aarch64_sys_reg_supported_p): Update for the new system
68 registers.
69
a915c10f
NC		 702015-11-20 Nick Clifton <nickc@redhat.com>
71
72 PR binutils/19224
73 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
74
f8c2a965
NC		 752015-11-20 Nick Clifton <nickc@redhat.com>
76
77 * po/zh_CN.po: Updated simplified Chinese translation.
78
c2825638
MW		 792015-11-19 Matthew Wahab <matthew.wahab@arm.com>
80
81 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
82 of MSR PAN immediate operand.
83
e7286c56
NC		 842015-11-16 Nick Clifton <nickc@redhat.com>
85
86 * rx-dis.c (condition_names): Replace always and never with
87 invalid, since the always/never conditions can never be legal.
88
d8bd95ef
TG		 892015-11-13 Tristan Gingold <gingold@adacore.com>
90
91 * configure: Regenerate.
92
a680de9a
PB		 932015-11-11 Alan Modra <amodra@gmail.com>
94 Peter Bergner <bergner@vnet.ibm.com>
95
96 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
97 Add PPC_OPCODE_VSX3 to the vsx entry.
98 (powerpc_init_dialect): Set default dialect to power9.
99 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
100 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
101 extract_l1 insert_xtq6, extract_xtq6): New static functions.
102 (insert_esync): Test for illegal L operand value.
103 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
104 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
105 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
106 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
107 PPCVSX3): New defines.
108 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
109 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
110 <mcrxr>: Use XBFRARB_MASK.
111 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
112 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
113 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
114 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
115 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
116 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
117 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
118 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
119 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
120 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
121 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
122 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
123 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
124 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
125 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
126 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
127 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
128 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
129 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
130 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
131 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
132 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
133 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
134 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
135 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
136 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
137 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
138 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
139 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
140 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
141 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
142 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
143
854eb72b
NC		 1442015-11-02 Nick Clifton <nickc@redhat.com>
145
146 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
147 instructions.
148 * rx-decode.c: Regenerate.
149
e292aa7a
NC		 1502015-11-02 Nick Clifton <nickc@redhat.com>
151
152 * rx-decode.opc (rx_disp): If the displacement is zero, set the
153 type to RX_Operand_Zero_Indirect.
154 * rx-decode.c: Regenerate.
155 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
156
43cdf5ae
YQ		 1572015-10-28 Yao Qi <yao.qi@linaro.org>
158
159 * aarch64-dis.c (aarch64_decode_insn): Add one argument
160 noaliases_p. Update comments. Pass noaliases_p rather than
161 no_aliases to aarch64_opcode_decode.
162 (print_insn_aarch64_word): Pass no_aliases to
163 aarch64_decode_insn.
164
c2f28758
VK		 1652015-10-27 Vinay <Vinay.G@kpit.com>
166
167 PR binutils/19159
168 * rl78-decode.opc (MOV): Added offset to DE register in index
169 addressing mode.
170 * rl78-decode.c: Regenerate.
171
46662804
VK		 1722015-10-27 Vinay Kumar <vinay.g@kpit.com>
173
174 PR binutils/19158
175 * rl78-decode.opc: Add 's' print operator to instructions that
176 access system registers.
177 * rl78-decode.c: Regenerate.
178 * rl78-dis.c (print_insn_rl78_common): Decode all system
179 registers.
180
02f12cd4
VK		 1812015-10-27 Vinay Kumar <vinay.g@kpit.com>
182
183 PR binutils/19157
184 * rl78-decode.opc: Add 'a' print operator to mov instructions
185 using stack pointer plus index addressing.
186 * rl78-decode.c: Regenerate.
187
485f23cf
AK		 1882015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
189
190 * s390-opc.c: Fix comment.
191 * s390-opc.txt: Change instruction type for troo, trot, trto, and
192 trtt to RRF_U0RER since the second parameter does not need to be a
193 register pair.
194
3f94e60d
NC		 1952015-10-08 Nick Clifton <nickc@redhat.com>
196
197 * arc-dis.c (print_insn_arc): Initiallise insn array.
198
875880c6
YQ		 1992015-10-07 Yao Qi <yao.qi@linaro.org>
200
201 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
202 'name' rather than 'template'.
203 * aarch64-opc.c (aarch64_print_operand): Likewise.
204
886a2506
NC		 2052015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
206
207 * arc-dis.c: Revamped file for ARC support
208 * arc-dis.h: Likewise.
209 * arc-ext.c: Likewise.
210 * arc-ext.h: Likewise.
211 * arc-opc.c: Likewise.
212 * arc-fxi.h: New file.
213 * arc-regs.h: Likewise.
214 * arc-tbl.h: Likewise.
215
36f4aab1
YQ		 2162015-10-02 Yao Qi <yao.qi@linaro.org>
217
218 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
219 argument insn type to aarch64_insn. Rename to ...
220 (aarch64_decode_insn): ... it.
221 (print_insn_aarch64_word): Caller updated.
222
7232d389
YQ		 2232015-10-02 Yao Qi <yao.qi@linaro.org>
224
225 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
226 (print_insn_aarch64_word): Caller updated.
227
7ecc513a
DV		 2282015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
229
230 * s390-mkopc.c (main): Parse htm and vx flag.
231 * s390-opc.txt: Mark instructions from the hardware transactional
232 memory and vector facilities with the "htm"/"vx" flag.
233
b08b78e7
NC		 2342015-09-28 Nick Clifton <nickc@redhat.com>
235
236 * po/de.po: Updated German translation.
237
36f7a941
TR		 2382015-09-28 Tom Rix <tom@bumblecow.com>
239
240 * ppc-opc.c (PPC500): Mark some opcodes as invalid
241
b6518b38
NC		 2422015-09-23 Nick Clifton <nickc@redhat.com>
243
244 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
245 function.
246 * tic30-dis.c (print_branch): Likewise.
247 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
248 value before left shifting.
249 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
250 * hppa-dis.c (print_insn_hppa): Likewise.
251 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
252 array.
253 * msp430-dis.c (msp430_singleoperand): Likewise.
254 (msp430_doubleoperand): Likewise.
255 (print_insn_msp430): Likewise.
256 * nds32-asm.c (parse_operand): Likewise.
257 * sh-opc.h (MASK): Likewise.
258 * v850-dis.c (get_operand_value): Likewise.
259
f04265ec
NC		 2602015-09-22 Nick Clifton <nickc@redhat.com>
261
262 * rx-decode.opc (bwl): Use RX_Bad_Size.
263 (sbwl): Likewise.
264 (ubwl): Likewise. Rename to ubw.
265 (uBWL): Rename to uBW.
266 Replace all references to uBWL with uBW.
267 * rx-decode.c: Regenerate.
268 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
269 (opsize_names): Likewise.
270 (print_insn_rx): Detect and report RX_Bad_Size.
271
6dca4fd1
AB		 2722015-09-22 Anton Blanchard <anton@samba.org>
273
274 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
275
38074311
JM		 2762015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
277
278 * sparc-dis.c (print_insn_sparc): Handle the privileged register
279 %pmcdper.
280
5f40e14d
JS		 2812015-08-24 Jan Stancek <jstancek@redhat.com>
282
283 * i386-dis.c (print_insn): Fix decoding of three byte operands.
284
ab4e4ed5
AF		 2852015-08-21 Alexander Fomin <alexander.fomin@intel.com>
286
287 PR binutils/18257
288 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
289 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
290 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
291 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
292 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
293 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
294 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
295 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
296 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
297 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
298 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
299 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
300 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
301 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
302 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
303 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
304 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
305 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
306 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
307 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
308 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
309 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
310 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
311 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
312 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
313 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
314 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
315 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
316 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
317 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
318 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
319 (vex_w_table): Replace terminals with MOD_TABLE entries for
320 most of mask instructions.
321
919b75f7
AM		 3222015-08-17 Alan Modra <amodra@gmail.com>
323
324 * cgen.sh: Trim trailing space from cgen output.
325 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
326 (print_dis_table): Likewise.
327 * opc2c.c (dump_lines): Likewise.
328 (orig_filename): Warning fix.
329 * ia64-asmtab.c: Regenerate.
330
4ab90a7a
AV		 3312015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
332
333 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
334 and higher with ARM instruction set will now mark the 26-bit
335 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
336 (arm_opcodes): Fix for unpredictable nop being recognized as a
337 teq.
338
40fc1451
SD		 3392015-08-12 Simon Dardis <simon.dardis@imgtec.com>
340
341 * micromips-opc.c (micromips_opcodes): Re-order table so that move
342 based on 'or' is first.
343 * mips-opc.c (mips_builtin_opcodes): Ditto.
344
922c5db5
NC		 3452015-08-11 Nick Clifton <nickc@redhat.com>
346
347 PR 18800
348 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
349 instruction.
350
75fb7498
RS		 3512015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
352
353 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
354
36aed29d
AP		 3552015-08-07 Amit Pawar <Amit.Pawar@amd.com>
356
357 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
358 * i386-init.h: Regenerated.
359
a8484f96
L		 3602015-07-30 H.J. Lu <hongjiu.lu@intel.com>
361
362 PR binutils/13571
363 * i386-dis.c (MOD_0FC3): New.
364 (PREFIX_0FC3): Renamed to ...
365 (PREFIX_MOD_0_0FC3): This.
366 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
367 (prefix_table): Replace Ma with Ev on movntiS.
368 (mod_table): Add MOD_0FC3.
369
37a42ee9
L		 3702015-07-27 H.J. Lu <hongjiu.lu@intel.com>
371
372 * configure: Regenerated.
373
070fe95d
AM		 3742015-07-23 Alan Modra <amodra@gmail.com>
375
376 PR 18708
377 * i386-dis.c (get64): Avoid signed integer overflow.
378
20c2a615
L		 3792015-07-22 Alexander Fomin <alexander.fomin@intel.com>
380
381 PR binutils/18631
382 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
383 "EXEvexHalfBcstXmmq" for the second operand.
384 (EVEX_W_0F79_P_2): Likewise.
385 (EVEX_W_0F7A_P_2): Likewise.
386 (EVEX_W_0F7B_P_2): Likewise.
387
6f1c2142
AM		 3882015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
389
390 * arm-dis.c (print_insn_coprocessor): Added support for quarter
391 float bitfield format.
392 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
393 quarter float bitfield format.
394
8a643cc3
L		 3952015-07-14 H.J. Lu <hongjiu.lu@intel.com>
396
397 * configure: Regenerated.
398
ef5a96d5
AM		 3992015-07-03 Alan Modra <amodra@gmail.com>
400
401 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
402 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
403 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
404
c8c8175b
SL		 4052015-07-01 Sandra Loosemore <sandra@codesourcery.com>
406 Cesar Philippidis <cesar@codesourcery.com>
407
408 * nios2-dis.c (nios2_extract_opcode): New.
409 (nios2_disassembler_state): New.
410 (nios2_find_opcode_hash): Use mach parameter to select correct
411 disassembler state.
412 (nios2_print_insn_arg): Extend to support new R2 argument letters
413 and formats.
414 (print_insn_nios2): Check for 16-bit instruction at end of memory.
415 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
416 (NIOS2_NUM_OPCODES): Rename to...
417 (NIOS2_NUM_R1_OPCODES): This.
418 (nios2_r2_opcodes): New.
419 (NIOS2_NUM_R2_OPCODES): New.
420 (nios2_num_r2_opcodes): New.
421 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
422 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
423 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
424 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
425 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
426
9916071f
AP		 4272015-06-30 Amit Pawar <Amit.Pawar@amd.com>
428
429 * i386-dis.c (OP_Mwaitx): New.
430 (rm_table): Add monitorx/mwaitx.
431 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
432 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
433 (operand_type_init): Add CpuMWAITX.
434 * i386-opc.h (CpuMWAITX): New.
435 (i386_cpu_flags): Add cpumwaitx.
436 * i386-opc.tbl: Add monitorx and mwaitx.
437 * i386-init.h: Regenerated.
438 * i386-tbl.h: Likewise.
439
7b934113
PB		 4402015-06-22 Peter Bergner <bergner@vnet.ibm.com>
441
442 * ppc-opc.c (insert_ls): Test for invalid LS operands.
443 (insert_esync): New function.
444 (LS, WC): Use insert_ls.
445 (ESYNC): Use insert_esync.
446
bdc4de1b
NC		 4472015-06-22 Nick Clifton <nickc@redhat.com>
448
449 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
450 requested region lies beyond it.
451 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
452 looking for 32-bit insns.
453 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
454 data.
455 * sh-dis.c (print_insn_sh): Likewise.
456 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
457 blocks of instructions.
458 * vax-dis.c (print_insn_vax): Check that the requested address
459 does not clash with the stop_vma.
460
11a0cf2e
PB		 4612015-06-19 Peter Bergner <bergner@vnet.ibm.com>
462
070fe95d 463 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 464 * ppc-opc.c (FXM4): Add non-zero optional value.
465 (TBR): Likewise.
466 (SXL): Likewise.
467 (insert_fxm): Handle new default operand value.
468 (extract_fxm): Likewise.
469 (insert_tbr): Likewise.
470 (extract_tbr): Likewise.
471
bdfa8b95
MW		 4722015-06-16 Matthew Wahab <matthew.wahab@arm.com>
473
474 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
475
24b4cf66
SN		 4762015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
477
478 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
479
99a2c561
PB		 4802015-06-12 Peter Bergner <bergner@vnet.ibm.com>
481
482 * ppc-opc.c: Add comment accidentally removed by old commit.
483 (MTMSRD_L): Delete.
484
40f77f82
AM		 4852015-06-04 Peter Bergner <bergner@vnet.ibm.com>
486
487 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
488
13be46a2
NC		 4892015-06-04 Nick Clifton <nickc@redhat.com>
490
491 PR 18474
492 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
493
ddfded2f
MW		 4942015-06-02 Matthew Wahab <matthew.wahab@arm.com>
495
496 * arm-dis.c (arm_opcodes): Add "setpan".
497 (thumb_opcodes): Add "setpan".
498
1af1dd51
MW		 4992015-06-02 Matthew Wahab <matthew.wahab@arm.com>
500
501 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
502 macros.
503
9e1f0fa7
MW		 5042015-06-02 Matthew Wahab <matthew.wahab@arm.com>
505
506 * aarch64-tbl.h (aarch64_feature_rdma): New.
507 (RDMA): New.
508 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
509 * aarch64-asm-2.c: Regenerate.
510 * aarch64-dis-2.c: Regenerate.
511 * aarch64-opc-2.c: Regenerate.
512
290806fd
MW		 5132015-06-02 Matthew Wahab <matthew.wahab@arm.com>
514
515 * aarch64-tbl.h (aarch64_feature_lor): New.
516 (LOR): New.
517 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
518 "stllrb", "stllrh".
519 * aarch64-asm-2.c: Regenerate.
520 * aarch64-dis-2.c: Regenerate.
521 * aarch64-opc-2.c: Regenerate.
522
f21cce2c
MW		 5232015-06-01 Matthew Wahab <matthew.wahab@arm.com>
524
525 * aarch64-opc.c (F_ARCHEXT): New.
526 (aarch64_sys_regs): Add "pan".
527 (aarch64_sys_reg_supported_p): New.
528 (aarch64_pstatefields): Add "pan".
529 (aarch64_pstatefield_supported_p): New.
530
d194d186
JB		 5312015-06-01 Jan Beulich <jbeulich@suse.com>
532
533 * i386-tbl.h: Regenerate.
534
3a8547d2
JB		 5352015-06-01 Jan Beulich <jbeulich@suse.com>
536
537 * i386-dis.c (print_insn): Swap rounding mode specifier and
538 general purpose register in Intel mode.
539
015c54d5
JB		 5402015-06-01 Jan Beulich <jbeulich@suse.com>
541
542 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
543 * i386-tbl.h: Regenerate.
544
071f0063
L		 5452015-05-18 H.J. Lu <hongjiu.lu@intel.com>
546
547 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
548 * i386-init.h: Regenerated.
549
5db04b09
L		 5502015-05-15 H.J. Lu <hongjiu.lu@intel.com>
551
552 PR binutis/18386
553 * i386-dis.c: Add comments for '@'.
554 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
555 (enum x86_64_isa): New.
556 (isa64): Likewise.
557 (print_i386_disassembler_options): Add amd64 and intel64.
558 (print_insn): Handle amd64 and intel64.
559 (putop): Handle '@'.
560 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
561 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
562 * i386-opc.h (AMD64): New.
563 (CpuIntel64): Likewise.
564 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
565 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
566 Mark direct call/jmp without Disp16|Disp32 as Intel64.
567 * i386-init.h: Regenerated.
568 * i386-tbl.h: Likewise.
569
4bc0608a
PB		 5702015-05-14 Peter Bergner <bergner@vnet.ibm.com>
571
572 * ppc-opc.c (IH) New define.
573 (powerpc_opcodes) <wait>: Do not enable for POWER7.
574 <tlbie>: Add RS operand for POWER7.
575 <slbia>: Add IH operand for POWER6.
576
70cead07
L		 5772015-05-11 H.J. Lu <hongjiu.lu@intel.com>
578
579 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
580 direct branch.
581 (jmp): Likewise.
582 * i386-tbl.h: Regenerated.
583
7b6d09fb
L		 5842015-05-11 H.J. Lu <hongjiu.lu@intel.com>
585
586 * configure.ac: Support bfd_iamcu_arch.
587 * disassemble.c (disassembler): Support bfd_iamcu_arch.
588 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
589 CPU_IAMCU_COMPAT_FLAGS.
590 (cpu_flags): Add CpuIAMCU.
591 * i386-opc.h (CpuIAMCU): New.
592 (i386_cpu_flags): Add cpuiamcu.
593 * configure: Regenerated.
594 * i386-init.h: Likewise.
595 * i386-tbl.h: Likewise.
596
31955f99
L		 5972015-05-08 H.J. Lu <hongjiu.lu@intel.com>
598
599 PR binutis/18386
600 * i386-dis.c (X86_64_E8): New.
601 (X86_64_E9): Likewise.
602 Update comments on 'T', 'U', 'V'. Add comments for '^'.
603 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
604 (x86_64_table): Add X86_64_E8 and X86_64_E9.
605 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
606 (putop): Handle '^'.
607 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
608 REX_W.
609
0952813b
DD		 6102015-04-30 DJ Delorie <dj@redhat.com>
611
612 * disassemble.c (disassembler): Choose suitable disassembler based
613 on E_ABI.
614 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
615 it to decode mul/div insns.
616 * rl78-decode.c: Regenerate.
617 * rl78-dis.c (print_insn_rl78): Rename to...
618 (print_insn_rl78_common): ...this, take ISA parameter.
619 (print_insn_rl78): New.
620 (print_insn_rl78_g10): New.
621 (print_insn_rl78_g13): New.
622 (print_insn_rl78_g14): New.
623 (rl78_get_disassembler): New.
624
f9d3ecaa
NC		 6252015-04-29 Nick Clifton <nickc@redhat.com>
626
627 * po/fr.po: Updated French translation.
628
4fff86c5
PB		 6292015-04-27 Peter Bergner <bergner@vnet.ibm.com>
630
631 * ppc-opc.c (DCBT_EO): New define.
632 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
633 <lharx>: Likewise.
634 <stbcx.>: Likewise.
635 <sthcx.>: Likewise.
636 <waitrsv>: Do not enable for POWER7 and later.
637 <waitimpl>: Likewise.
638 <dcbt>: Default to the two operand form of the instruction for all
639 "old" cpus. For "new" cpus, use the operand ordering that matches
640 whether the cpu is server or embedded.
641 <dcbtst>: Likewise.
642
3b78cfe1
AK		 6432015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
644
645 * s390-opc.c: New instruction type VV0UU2.
646 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
647 and WFC.
648
04d824a4
JB		 6492015-04-23 Jan Beulich <jbeulich@suse.com>
650
651 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
652 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
653 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
654 (vfpclasspd, vfpclassps): Add %XZ.
655
09708981
L		 6562015-04-15 H.J. Lu <hongjiu.lu@intel.com>
657
658 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
659 (PREFIX_UD_REPZ): Likewise.
660 (PREFIX_UD_REPNZ): Likewise.
661 (PREFIX_UD_DATA): Likewise.
662 (PREFIX_UD_ADDR): Likewise.
663 (PREFIX_UD_LOCK): Likewise.
664
3888916d
L		 6652015-04-15 H.J. Lu <hongjiu.lu@intel.com>
666
667 * i386-dis.c (prefix_requirement): Removed.
668 (print_insn): Don't set prefix_requirement. Check
669 dp->prefix_requirement instead of prefix_requirement.
670
f24bcbaa
L		 6712015-04-15 H.J. Lu <hongjiu.lu@intel.com>
672
673 PR binutils/17898
674 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
675 (PREFIX_MOD_0_0FC7_REG_6): This.
676 (PREFIX_MOD_3_0FC7_REG_6): New.
677 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
678 (prefix_table): Replace PREFIX_0FC7_REG_6 with
679 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
680 PREFIX_MOD_3_0FC7_REG_7.
681 (mod_table): Replace PREFIX_0FC7_REG_6 with
682 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
683 PREFIX_MOD_3_0FC7_REG_7.
684
507bd325
L		 6852015-04-15 H.J. Lu <hongjiu.lu@intel.com>
686
687 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
688 (PREFIX_MANDATORY_REPNZ): Likewise.
689 (PREFIX_MANDATORY_DATA): Likewise.
690 (PREFIX_MANDATORY_ADDR): Likewise.
691 (PREFIX_MANDATORY_LOCK): Likewise.
692 (PREFIX_MANDATORY): Likewise.
693 (PREFIX_UD_SHIFT): Set to 8
694 (PREFIX_UD_REPZ): Updated.
695 (PREFIX_UD_REPNZ): Likewise.
696 (PREFIX_UD_DATA): Likewise.
697 (PREFIX_UD_ADDR): Likewise.
698 (PREFIX_UD_LOCK): Likewise.
699 (PREFIX_IGNORED_SHIFT): New.
700 (PREFIX_IGNORED_REPZ): Likewise.
701 (PREFIX_IGNORED_REPNZ): Likewise.
702 (PREFIX_IGNORED_DATA): Likewise.
703 (PREFIX_IGNORED_ADDR): Likewise.
704 (PREFIX_IGNORED_LOCK): Likewise.
705 (PREFIX_OPCODE): Likewise.
706 (PREFIX_IGNORED): Likewise.
707 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
708 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
709 (three_byte_table): Likewise.
710 (mod_table): Likewise.
711 (mandatory_prefix): Renamed to ...
712 (prefix_requirement): This.
713 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
714 Update PREFIX_90 entry.
715 (get_valid_dis386): Check prefix_requirement to see if a prefix
716 should be ignored.
717 (print_insn): Replace mandatory_prefix with prefix_requirement.
718
f0fba320
RL		 7192015-04-15 Renlin Li <renlin.li@arm.com>
720
721 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
722 use it for ssat and ssat16.
723 (print_insn_thumb32): Add handle case for 'D' control code.
724
bf890a93
IT		 7252015-04-06 Ilya Tocar <ilya.tocar@intel.com>
726 H.J. Lu <hongjiu.lu@intel.com>
727
728 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
729 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
730 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
731 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
732 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
733 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
734 Fill prefix_requirement field.
735 (struct dis386): Add prefix_requirement field.
736 (dis386): Fill prefix_requirement field.
737 (dis386_twobyte): Ditto.
738 (twobyte_has_mandatory_prefix_: Remove.
739 (reg_table): Fill prefix_requirement field.
740 (prefix_table): Ditto.
741 (x86_64_table): Ditto.
742 (three_byte_table): Ditto.
743 (xop_table): Ditto.
744 (vex_table): Ditto.
745 (vex_len_table): Ditto.
746 (vex_w_table): Ditto.
747 (mod_table): Ditto.
748 (bad_opcode): Ditto.
749 (print_insn): Use prefix_requirement.
750 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
751 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
752 (float_reg): Ditto.
753
2f783c1f
MF		 7542015-03-30 Mike Frysinger <vapier@gentoo.org>
755
756 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
757
b9d94d62
L		 7582015-03-29 H.J. Lu <hongjiu.lu@intel.com>
759
760 * Makefile.in: Regenerated.
761
27c49e9a
AB		 7622015-03-25 Anton Blanchard <anton@samba.org>
763
764 * ppc-dis.c (disassemble_init_powerpc): Only initialise
765 powerpc_opcd_indices and vle_opcd_indices once.
766
c4e676f1
AB		 7672015-03-25 Anton Blanchard <anton@samba.org>
768
769 * ppc-opc.c (powerpc_opcodes): Add slbfee.
770
823d2571
TG		 7712015-03-24 Terry Guo <terry.guo@arm.com>
772
773 * arm-dis.c (opcode32): Updated to use new arm feature struct.
774 (opcode16): Likewise.
775 (coprocessor_opcodes): Replace bit with feature struct.
776 (neon_opcodes): Likewise.
777 (arm_opcodes): Likewise.
778 (thumb_opcodes): Likewise.
779 (thumb32_opcodes): Likewise.
780 (print_insn_coprocessor): Likewise.
781 (print_insn_arm): Likewise.
782 (select_arm_features): Follow new feature struct.
783
029f3522
GG		 7842015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
785
786 * i386-dis.c (rm_table): Add clzero.
787 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
788 Add CPU_CLZERO_FLAGS.
789 (cpu_flags): Add CpuCLZERO.
790 * i386-opc.h: Add CpuCLZERO.
791 * i386-opc.tbl: Add clzero.
792 * i386-init.h: Re-generated.
793 * i386-tbl.h: Re-generated.
794
6914869a
AB		 7952015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
796
797 * mips-opc.c (decode_mips_operand): Fix constraint issues
798 with u and y operands.
799
21e20815
AB		 8002015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
801
802 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
803
6b1d7593
AK		 8042015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
805
806 * s390-opc.c: Add new IBM z13 instructions.
807 * s390-opc.txt: Likewise.
808
c8f89a34
JW		 8092015-03-10 Renlin Li <renlin.li@arm.com>
810
811 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
812 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
813 related alias.
814 * aarch64-asm-2.c: Regenerate.
815 * aarch64-dis-2.c: Likewise.
816 * aarch64-opc-2.c: Likewise.
817
d8282f0e
JW		 8182015-03-03 Jiong Wang <jiong.wang@arm.com>
819
820 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
821
ac994365
OE		 8222015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
823
824 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
825 arch_sh_up.
826 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
827 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
828
fd63f640
V		 8292015-02-23 Vinay <Vinay.G@kpit.com>
830
831 * rl78-decode.opc (MOV): Added space between two operands for
832 'mov' instruction in index addressing mode.
833 * rl78-decode.c: Regenerate.
834
f63c1776
PA		 8352015-02-19 Pedro Alves <palves@redhat.com>
836
837 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
838
07774fcc
PA		 8392015-02-10 Pedro Alves <palves@redhat.com>
840 Tom Tromey <tromey@redhat.com>
841
842 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
843 microblaze_and, microblaze_xor.
844 * microblaze-opc.h (opcodes): Adjust.
845
3f8107ab
AM		 8462015-01-28 James Bowman <james.bowman@ftdichip.com>
847
848 * Makefile.am: Add FT32 files.
849 * configure.ac: Handle FT32.
850 * disassemble.c (disassembler): Call print_insn_ft32.
851 * ft32-dis.c: New file.
852 * ft32-opc.c: New file.
853 * Makefile.in: Regenerate.
854 * configure: Regenerate.
855 * po/POTFILES.in: Regenerate.
856
e5fe4957
KLC		 8572015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
858
859 * nds32-asm.c (keyword_sr): Add new system registers.
860
1e2e8c52
AK		 8612015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
862
863 * s390-dis.c (s390_extract_operand): Support vector register
864 operands.
865 (s390_print_insn_with_opcode): Support new operands types and add
866 new handling of optional operands.
867 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
868 and include opcode/s390.h instead.
869 (struct op_struct): New field `flags'.
870 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
871 (dumpTable): Dump flags.
872 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
873 string.
874 * s390-opc.c: Add new operands types, instruction formats, and
875 instruction masks.
876 (s390_opformats): Add new formats for .insn.
877 * s390-opc.txt: Add new instructions.
878
b90efa5b 8792015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 880
b90efa5b 881 Update year range in copyright notice of all files.
bffb6004 882
b90efa5b 883For older changes see ChangeLog-2014
252b5132 884\f
b90efa5b 885Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 886
887Copying and distribution of this file, with or without modification,
888are permitted in any medium without royalty provided the copyright
889notice and this notice are preserved.
890
252b5132 891Local Variables:
2f6d2f85
NC		 892mode: change-log
893left-margin: 8
894fill-column: 74
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RH		 895version-control: never
896End:
GDB Binutils - Deliverables
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