Commit | Line | Data |
---|---|---|
d241b910 JB |
1 | 2019-10-07 Jan Beulich <jbeulich@suse.com> |
2 | ||
3 | * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize. | |
4 | (cmpsd): Likewise. Move EsSeg to other operand. | |
5 | * opcodes/i386-tbl.h: Re-generate. | |
6 | ||
f5c5b7c1 AM |
7 | 2019-09-23 Alan Modra <amodra@gmail.com> |
8 | ||
9 | * m68k-dis.c: Include cpu-m68k.h | |
10 | ||
7beeaeb8 AM |
11 | 2019-09-23 Alan Modra <amodra@gmail.com> |
12 | ||
13 | * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and | |
14 | "elf/mips.h" earlier. | |
15 | ||
3f9aad11 JB |
16 | 2018-09-20 Jan Beulich <jbeulich@suse.com> |
17 | ||
18 | PR gas/25012 | |
19 | * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates | |
20 | with SReg operand. | |
21 | * i386-tbl.h: Re-generate. | |
22 | ||
fd361982 AM |
23 | 2019-09-18 Alan Modra <amodra@gmail.com> |
24 | ||
25 | * arc-ext.c: Update throughout for bfd section macro changes. | |
26 | ||
e0b2a78c SM |
27 | 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca> |
28 | ||
29 | * Makefile.in: Re-generate. | |
30 | * configure: Re-generate. | |
31 | ||
7e9ad3a3 JW |
32 | 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com> |
33 | ||
34 | * riscv-opc.c (riscv_opcodes): Change subset field | |
35 | to insn_class field for all instructions. | |
36 | (riscv_insn_types): Likewise. | |
37 | ||
bb695960 PB |
38 | 2019-09-16 Phil Blundell <pb@pbcl.net> |
39 | ||
40 | * configure: Regenerated. | |
41 | ||
8063ab7e MV |
42 | 2019-09-10 Miod Vallat <miod@online.fr> |
43 | ||
44 | PR 24982 | |
45 | * m68k-opc.c: Correct aliases for tdivsl and tdivul. | |
46 | ||
60391a25 PB |
47 | 2019-09-09 Phil Blundell <pb@pbcl.net> |
48 | ||
49 | binutils 2.33 branch created. | |
50 | ||
f44b758d NC |
51 | 2019-09-03 Nick Clifton <nickc@redhat.com> |
52 | ||
53 | PR 24961 | |
54 | * tic30-dis.c (get_indirect_operand): Check for bufcnt being | |
55 | greater than zero before indexing via (bufcnt -1). | |
56 | ||
1e4b5e7d NC |
57 | 2019-09-03 Nick Clifton <nickc@redhat.com> |
58 | ||
59 | PR 24958 | |
60 | * mmix-dis.c (MAX_REG_NAME_LEN): Define. | |
61 | (MAX_SPEC_REG_NAME_LEN): Define. | |
62 | (struct mmix_dis_info): Use defined constants for array lengths. | |
63 | (get_reg_name): New function. | |
64 | (get_sprec_reg_name): New function. | |
65 | (print_insn_mmix): Use new functions. | |
66 | ||
c4a23bf8 SP |
67 | 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com> |
68 | ||
69 | * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC. | |
70 | (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC. | |
71 | (print_insn_mve): Add condition to check Qm==Qn of VORR instruction. | |
72 | ||
a051e2f3 KT |
73 | 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com> |
74 | ||
75 | * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1, | |
76 | tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12. | |
77 | (aarch64_sys_reg_supported_p): Update checks for the above. | |
78 | ||
08132bdd SP |
79 | 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com> |
80 | ||
81 | * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for | |
82 | cases MVE_SQRSHRL and MVE_UQRSHLL. | |
83 | (print_insn_mve): Add case for specifier 'k' to check | |
84 | specific bit of the instruction. | |
85 | ||
d88bdcb4 PA |
86 | 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr> |
87 | ||
88 | PR 24854 | |
89 | * arc-dis.c (arc_insn_length): Return 0 rather than aborting when | |
90 | encountering an unknown machine type. | |
91 | (print_insn_arc): Handle arc_insn_length returning 0. In error | |
92 | cases return -1 rather than calling abort. | |
93 | ||
bc750500 JB |
94 | 2019-08-07 Jan Beulich <jbeulich@suse.com> |
95 | ||
96 | * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms. | |
97 | (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by | |
98 | IgnoreSize. | |
99 | * i386-tbl.h: Re-generate. | |
100 | ||
23d188c7 BW |
101 | 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com> |
102 | ||
103 | * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH | |
104 | instructions. | |
105 | ||
c0d6f62f JW |
106 | 2019-07-30 Mel Chen <mel.chen@sifive.com> |
107 | ||
108 | * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm, | |
109 | fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions. | |
110 | ||
111 | * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr, | |
112 | fscsr. | |
113 | ||
0f3f7167 CZ |
114 | 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com> |
115 | ||
116 | * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes, | |
117 | and MPY class instructions. | |
118 | (parse_option): Add nps400 option. | |
119 | (print_arc_disassembler_options): Add nps400 info. | |
120 | ||
7e126ba3 CZ |
121 | 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com> |
122 | ||
123 | * arc-ext-tbl.h (bspeek): Remove it, added to main table. | |
124 | (bspop): Likewise. | |
125 | (modapp): Likewise. | |
126 | * arc-opc.c (RAD_CHK): Add. | |
127 | * arc-tbl.h: Regenerate. | |
128 | ||
a028026d KT |
129 | 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com> |
130 | ||
131 | * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry. | |
132 | (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding. | |
133 | ||
ac79ff9e NC |
134 | 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com> |
135 | ||
136 | * arm-dis.c (is_mve_unpredictable): Stop marking some MVE | |
137 | instructions as UNPREDICTABLE. | |
138 | ||
231097b0 JM |
139 | 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> |
140 | ||
141 | * bpf-desc.c: Regenerated. | |
142 | ||
1d942ae9 JB |
143 | 2019-07-17 Jan Beulich <jbeulich@suse.com> |
144 | ||
145 | * i386-gen.c (static_assert): Define. | |
146 | (main): Use it. | |
147 | * i386-opc.h (Opcode_Modifier_Max): Rename to ... | |
148 | (Opcode_Modifier_Num): ... this. | |
149 | (Mem): Delete. | |
150 | ||
dfd69174 JB |
151 | 2019-07-16 Jan Beulich <jbeulich@suse.com> |
152 | ||
153 | * i386-gen.c (operand_types): Move RegMem ... | |
154 | (opcode_modifiers): ... here. | |
155 | * i386-opc.h (RegMem): Move to opcode modifer enum. | |
156 | (union i386_operand_type): Move regmem field ... | |
157 | (struct i386_opcode_modifier): ... here. | |
158 | * i386-opc.tbl (RegMem): Define. | |
159 | (mov, movq): Move RegMem on segment, control, debug, and test | |
160 | register flavors. | |
161 | (pextrb): Move RegMem on register only flavors. Add IgnoreSize | |
162 | to non-SSE2AVX flavor. | |
163 | (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw): | |
164 | Move RegMem on register only flavors. Drop IgnoreSize from | |
165 | legacy encoding flavors. | |
166 | (movss, movsd, vmovss, vmovsd): Drop RegMem from register only | |
167 | flavors. | |
168 | (vpinsrb, vpinsrw): Drop IgnoreSize where still present on | |
169 | register only flavors. | |
170 | (vmovd): Move RegMem and drop IgnoreSize on register only | |
171 | flavor. Change opcode and operand order to store form. | |
172 | * opcodes/i386-init.h, i386-tbl.h: Re-generate. | |
173 | ||
21df382b JB |
174 | 2019-07-16 Jan Beulich <jbeulich@suse.com> |
175 | ||
176 | * i386-gen.c (operand_type_init, operand_types): Replace SReg | |
177 | entries. | |
178 | * i386-opc.h (SReg2, SReg3): Replace by ... | |
179 | (SReg): ... this. | |
180 | (union i386_operand_type): Replace sreg fields. | |
181 | * i386-opc.tbl (mov, ): Use SReg. | |
182 | (push, pop): Likewies. Drop i386 and x86-64 specific segment | |
183 | register flavors. | |
184 | * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg. | |
185 | * opcodes/i386-init.h, i386-tbl.h: Re-generate. | |
186 | ||
3719fd55 JM |
187 | 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com> |
188 | ||
189 | * bpf-desc.c: Regenerate. | |
190 | * bpf-opc.c: Likewise. | |
191 | * bpf-opc.h: Likewise. | |
192 | ||
92434a14 JM |
193 | 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com> |
194 | ||
195 | * bpf-desc.c: Regenerate. | |
196 | * bpf-opc.c: Likewise. | |
197 | ||
43dd7626 HPN |
198 | 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com> |
199 | ||
200 | * arm-dis.c (print_insn_coprocessor): Rename index to | |
201 | index_operand. | |
202 | ||
98602811 JW |
203 | 2019-07-05 Kito Cheng <kito.cheng@sifive.com> |
204 | ||
205 | * riscv-opc.c (riscv_insn_types): Add r4 type. | |
206 | ||
207 | * riscv-opc.c (riscv_insn_types): Add b and j type. | |
208 | ||
209 | * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect | |
210 | format for sb type and correct s type. | |
211 | ||
01c1ee4a RS |
212 | 2019-07-02 Richard Sandiford <richard.sandiford@arm.com> |
213 | ||
214 | * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the | |
215 | SVE FMOV alias of FCPY. | |
216 | ||
83adff69 RS |
217 | 2019-07-02 Richard Sandiford <richard.sandiford@arm.com> |
218 | ||
219 | * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags | |
220 | to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries. | |
221 | ||
89418844 RS |
222 | 2019-07-02 Richard Sandiford <richard.sandiford@arm.com> |
223 | ||
224 | * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the | |
225 | registers in an instruction prefixed by MOVPRFX. | |
226 | ||
41be57ca MM |
227 | 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> |
228 | ||
229 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new | |
230 | sve_size_13 icode to account for variant behaviour of | |
231 | pmull{t,b}. | |
232 | * aarch64-dis-2.c: Regenerate. | |
233 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new | |
234 | sve_size_13 icode to account for variant behaviour of | |
235 | pmull{t,b}. | |
236 | * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier. | |
237 | (OP_SVE_VVV_Q_D): Add new qualifier. | |
238 | (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier. | |
239 | (struct aarch64_opcode): Split pmull{t,b} into those requiring | |
240 | AES and those not. | |
241 | ||
9d3bf266 JB |
242 | 2019-07-01 Jan Beulich <jbeulich@suse.com> |
243 | ||
244 | * opcodes/i386-gen.c (operand_type_init): Remove | |
245 | OPERAND_TYPE_VEC_IMM4 entry. | |
246 | (operand_types): Remove Vec_Imm4. | |
247 | * opcodes/i386-opc.h (Vec_Imm4): Delete. | |
248 | (union i386_operand_type): Remove vec_imm4. | |
249 | * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4. | |
250 | * opcodes/i386-init.h, i386-tbl.h: Re-generate. | |
251 | ||
c3949f43 JB |
252 | 2019-07-01 Jan Beulich <jbeulich@suse.com> |
253 | ||
254 | * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall, | |
255 | vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs, | |
256 | rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun, | |
257 | vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb, | |
258 | xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac, | |
259 | monitorx, mwaitx): Drop ImmExt from operand-less forms. | |
260 | * i386-tbl.h: Re-generate. | |
261 | ||
5641ec01 JB |
262 | 2019-07-01 Jan Beulich <jbeulich@suse.com> |
263 | ||
264 | * i386-opc.tbl (and, or): Add Optimize to forms allowing two | |
265 | register operands. | |
266 | * i386-tbl.h: Re-generate. | |
267 | ||
79dec6b7 JB |
268 | 2019-07-01 Jan Beulich <jbeulich@suse.com> |
269 | ||
270 | * i386-opc.tbl (C): New. | |
271 | (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw, | |
272 | pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw, | |
273 | por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss, | |
274 | cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw, | |
275 | pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd, | |
276 | cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd, | |
277 | cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd, | |
278 | vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps, | |
279 | vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd, | |
280 | vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd, | |
281 | vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd, | |
282 | vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd, | |
283 | vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd, | |
284 | vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd, | |
285 | vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss, | |
286 | vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss, | |
287 | vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps, | |
288 | vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps, | |
289 | vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps, | |
290 | vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps, | |
291 | vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss, | |
292 | vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw, | |
293 | vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand, | |
294 | vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd, | |
295 | vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw, | |
296 | vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded | |
297 | flavors. | |
298 | * i386-tbl.h: Re-generate. | |
299 | ||
a0a1771e JB |
300 | 2019-07-01 Jan Beulich <jbeulich@suse.com> |
301 | ||
302 | * i386-opc.tbl (and, or): Add Optimize to forms allowing two | |
303 | register operands. | |
304 | * i386-tbl.h: Re-generate. | |
305 | ||
cd546e7b JB |
306 | 2019-07-01 Jan Beulich <jbeulich@suse.com> |
307 | ||
308 | * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq. | |
309 | * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq, | |
310 | vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors. | |
311 | * i386-tbl.h: Re-generate. | |
312 | ||
e3bba3fc JB |
313 | 2019-07-01 Jan Beulich <jbeulich@suse.com> |
314 | ||
315 | * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove | |
316 | Disp8MemShift from register only templates. | |
317 | * i386-tbl.h: Re-generate. | |
318 | ||
36cc073e JB |
319 | 2019-07-01 Jan Beulich <jbeulich@suse.com> |
320 | ||
321 | * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1, | |
322 | MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, | |
323 | MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0, | |
324 | EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, | |
325 | EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0, | |
326 | EVEX_W_0F11_P_3_M_1): Delete. | |
327 | (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1, | |
328 | EVEX_W_0F11_P_3): New. | |
329 | * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1, | |
330 | MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and | |
331 | MOD_EVEX_0F11_PREFIX_3 table entries. | |
332 | * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and | |
333 | PREFIX_EVEX_0F11 table entries. | |
334 | * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1}, | |
335 | EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and | |
336 | EVEX_W_0F11_P_3_M_{0,1} table entries. | |
337 | ||
219920a7 JB |
338 | 2019-07-01 Jan Beulich <jbeulich@suse.com> |
339 | ||
340 | * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex): | |
341 | Delete. | |
342 | ||
e395f487 L |
343 | 2019-06-27 H.J. Lu <hongjiu.lu@intel.com> |
344 | ||
345 | PR binutils/24719 | |
346 | * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2, | |
347 | EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2, | |
348 | EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0, | |
349 | EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0, | |
350 | EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0, | |
351 | EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and | |
352 | EVEX_LEN_0F38C7_R_6_P_2_W_1. | |
353 | * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1, | |
354 | PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and | |
355 | PREFIX_EVEX_0F38C6_REG_6 entries. | |
356 | * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2, | |
357 | EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and | |
358 | EVEX_W_0F38C7_R_6_P_2 entries. | |
359 | * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2, | |
360 | EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2, | |
361 | EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0, | |
362 | EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0, | |
363 | EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0, | |
364 | EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and | |
365 | EVEX_LEN_0F38C7_R_6_P_2_W_1 enums. | |
366 | ||
2b7bcc87 JB |
367 | 2019-06-27 Jan Beulich <jbeulich@suse.com> |
368 | ||
369 | * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3, | |
370 | VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1, | |
371 | VEX_LEN_0F2D_P_3): Delete. | |
372 | (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si, | |
373 | vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ... | |
374 | (prefix_table): ... here. | |
375 | ||
c1dc7af5 JB |
376 | 2019-06-27 Jan Beulich <jbeulich@suse.com> |
377 | ||
378 | * i386-dis.c (Iq): Delete. | |
379 | (Id): New. | |
380 | (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for | |
381 | TBM insns. | |
382 | (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for | |
383 | vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si. | |
384 | (OP_E_memory): Also honor needindex when deciding whether an | |
385 | address size prefix needs printing. | |
386 | (OP_I): Remove handling of q_mode. Add handling of d_mode. | |
387 | ||
d7560e2d JW |
388 | 2019-06-26 Jim Wilson <jimw@sifive.com> |
389 | ||
390 | PR binutils/24739 | |
391 | * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code. | |
392 | Set info->display_endian to info->endian_code. | |
393 | ||
2c703856 JB |
394 | 2019-06-25 Jan Beulich <jbeulich@suse.com> |
395 | ||
396 | * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG | |
397 | entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and | |
398 | OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and | |
399 | OPERAND_TYPE_ACC64 entries. | |
400 | * i386-init.h: Re-generate. | |
401 | ||
54fbadc0 JB |
402 | 2019-06-25 Jan Beulich <jbeulich@suse.com> |
403 | ||
404 | * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1): | |
405 | Delete. | |
406 | (intel_operand_size, OP_E_register, OP_E_memory): Drop handling | |
407 | of dqa_mode. | |
408 | * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf | |
409 | entries here. | |
410 | * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1 | |
411 | entries. Use Edq for vcvtsi2sd and vcvtusi2sd. | |
412 | ||
a280ab8e JB |
413 | 2019-06-25 Jan Beulich <jbeulich@suse.com> |
414 | ||
415 | * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local | |
416 | variables. | |
417 | ||
e1a1babd JB |
418 | 2019-06-25 Jan Beulich <jbeulich@suse.com> |
419 | ||
420 | * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd. | |
421 | Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and | |
422 | movnti. | |
d7560e2d | 423 | * i386-opc.tbl (movnti): Add IgnoreSize. |
e1a1babd JB |
424 | * i386-tbl.h: Re-generate. |
425 | ||
b8364fa7 JB |
426 | 2019-06-25 Jan Beulich <jbeulich@suse.com> |
427 | ||
428 | * i386-opc.tbl (and): Mark Imm8S form for optimization. | |
429 | * i386-tbl.h: Re-generate. | |
430 | ||
ad692897 L |
431 | 2019-06-21 H.J. Lu <hongjiu.lu@intel.com> |
432 | ||
433 | * i386-dis-evex.h: Break into ... | |
434 | * i386-dis-evex-len.h: New file. | |
435 | * i386-dis-evex-mod.h: Likewise. | |
436 | * i386-dis-evex-prefix.h: Likewise. | |
437 | * i386-dis-evex-reg.h: Likewise. | |
438 | * i386-dis-evex-w.h: Likewise. | |
439 | * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h, | |
440 | i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and | |
441 | i386-dis-evex-mod.h. | |
442 | ||
f0a6222e L |
443 | 2019-06-19 H.J. Lu <hongjiu.lu@intel.com> |
444 | ||
445 | PR binutils/24700 | |
446 | * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2, | |
447 | EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and | |
448 | EVEX_W_0F385B_P_2. | |
449 | (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0, | |
450 | EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0, | |
451 | EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0, | |
452 | EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0, | |
453 | EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and | |
454 | EVEX_LEN_0F385B_P_2_W_1. | |
455 | * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum. | |
456 | (EVEX_LEN_0F3819_P_2_W_1): Likewise. | |
457 | (EVEX_LEN_0F381A_P_2_W_0): Likewise. | |
458 | (EVEX_LEN_0F381A_P_2_W_1): Likewise. | |
459 | (EVEX_LEN_0F381B_P_2_W_0): Likewise. | |
460 | (EVEX_LEN_0F381B_P_2_W_1): Likewise. | |
461 | (EVEX_LEN_0F385A_P_2_W_0): Likewise. | |
462 | (EVEX_LEN_0F385A_P_2_W_1): Likewise. | |
463 | (EVEX_LEN_0F385B_P_2_W_0): Likewise. | |
464 | (EVEX_LEN_0F385B_P_2_W_1): Likewise. | |
465 | ||
6e1c90b7 L |
466 | 2019-06-17 H.J. Lu <hongjiu.lu@intel.com> |
467 | ||
468 | PR binutils/24691 | |
469 | * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2, | |
470 | EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, | |
471 | EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2. | |
472 | (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0, | |
473 | EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0, | |
474 | EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0, | |
475 | EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0, | |
476 | EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0, | |
477 | EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and | |
478 | EVEX_LEN_0F3A43_P_2_W_1. | |
479 | * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum. | |
480 | (EVEX_LEN_0F3A23_P_2_W_1): Likewise. | |
481 | (EVEX_LEN_0F3A38_P_2_W_0): Likewise. | |
482 | (EVEX_LEN_0F3A38_P_2_W_1): Likewise. | |
483 | (EVEX_LEN_0F3A39_P_2_W_0): Likewise. | |
484 | (EVEX_LEN_0F3A39_P_2_W_1): Likewise. | |
485 | (EVEX_LEN_0F3A3A_P_2_W_0): Likewise. | |
486 | (EVEX_LEN_0F3A3A_P_2_W_1): Likewise. | |
487 | (EVEX_LEN_0F3A3B_P_2_W_0): Likewise. | |
488 | (EVEX_LEN_0F3A3B_P_2_W_1): Likewise. | |
489 | (EVEX_LEN_0F3A43_P_2_W_0): Likewise. | |
490 | (EVEX_LEN_0F3A43_P_2_W_1): Likewise. | |
491 | ||
bcc5a6eb NC |
492 | 2019-06-14 Nick Clifton <nickc@redhat.com> |
493 | ||
494 | * po/fr.po; Updated French translation. | |
495 | ||
e4c4ac46 SH |
496 | 2019-06-13 Stafford Horne <shorne@gmail.com> |
497 | ||
498 | * or1k-asm.c: Regenerated. | |
499 | * or1k-desc.c: Regenerated. | |
500 | * or1k-desc.h: Regenerated. | |
501 | * or1k-dis.c: Regenerated. | |
502 | * or1k-ibld.c: Regenerated. | |
503 | * or1k-opc.c: Regenerated. | |
504 | * or1k-opc.h: Regenerated. | |
505 | * or1k-opinst.c: Regenerated. | |
506 | ||
a0e44ef5 PB |
507 | 2019-06-12 Peter Bergner <bergner@linux.ibm.com> |
508 | ||
509 | * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic. | |
510 | ||
12efd68d L |
511 | 2019-06-05 H.J. Lu <hongjiu.lu@intel.com> |
512 | ||
513 | PR binutils/24633 | |
514 | * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2, | |
515 | EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2. | |
516 | (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0, | |
517 | EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0, | |
518 | EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0, | |
519 | EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0, | |
520 | EVEX_LEN_0F3A1B_P_2_W_1. | |
521 | * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum. | |
522 | (EVEX_LEN_0F3A18_P_2_W_1): Likewise. | |
523 | (EVEX_LEN_0F3A19_P_2_W_0): Likewise. | |
524 | (EVEX_LEN_0F3A19_P_2_W_1): Likewise. | |
525 | (EVEX_LEN_0F3A1A_P_2_W_0): Likewise. | |
526 | (EVEX_LEN_0F3A1A_P_2_W_1): Likewise. | |
527 | (EVEX_LEN_0F3A1B_P_2_W_0): Likewise. | |
528 | (EVEX_LEN_0F3A1B_P_2_W_1): Likewise. | |
529 | ||
63c6fc6c L |
530 | 2019-06-04 H.J. Lu <hongjiu.lu@intel.com> |
531 | ||
532 | PR binutils/24626 | |
533 | * i386-dis.c (print_insn): Check for unused VEX.vvvv and | |
534 | EVEX.vvvv when disassembling VEX and EVEX instructions. | |
535 | (OP_VEX): Set vex.register_specifier to 0 after readding | |
536 | vex.register_specifier. | |
537 | (OP_Vex_2src_1): Likewise. | |
538 | (OP_Vex_2src_2): Likewise. | |
539 | (OP_LWP_E): Likewise. | |
540 | (OP_EX_Vex): Don't check vex.register_specifier. | |
541 | (OP_XMM_Vex): Likewise. | |
542 | ||
9186c494 L |
543 | 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
544 | Lili Cui <lili.cui@intel.com> | |
545 | ||
546 | * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3. | |
547 | * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT | |
548 | instructions. | |
549 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS, | |
550 | CPU_ANY_AVX512_VP2INTERSECT_FLAGS. | |
551 | (cpu_flags): Add CpuAVX512_VP2INTERSECT. | |
552 | * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT. | |
553 | (i386_cpu_flags): Add cpuavx512_vp2intersect. | |
554 | * i386-opc.tbl: Add AVX512_VP2INTERSECT insns. | |
555 | * i386-init.h: Regenerated. | |
556 | * i386-tbl.h: Likewise. | |
557 | ||
5d79adc4 L |
558 | 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> |
559 | Lili Cui <lili.cui@intel.com> | |
560 | ||
561 | * doc/c-i386.texi: Document enqcmd. | |
562 | * testsuite/gas/i386/enqcmd-intel.d: New file. | |
563 | * testsuite/gas/i386/enqcmd-inval.l: Likewise. | |
564 | * testsuite/gas/i386/enqcmd-inval.s: Likewise. | |
565 | * testsuite/gas/i386/enqcmd.d: Likewise. | |
566 | * testsuite/gas/i386/enqcmd.s: Likewise. | |
567 | * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise. | |
568 | * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise. | |
569 | * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise. | |
570 | * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. | |
571 | * testsuite/gas/i386/x86-64-enqcmd.s: Likewise. | |
572 | * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval, | |
573 | enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval, | |
574 | and x86-64-enqcmd. | |
575 | ||
a9d96ab9 AH |
576 | 2019-06-04 Alan Hayward <alan.hayward@arm.com> |
577 | ||
578 | * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis. | |
579 | ||
4f6d070a AM |
580 | 2019-06-03 Alan Modra <amodra@gmail.com> |
581 | ||
582 | * ppc-dis.c (prefix_opcd_indices): Correct size. | |
583 | ||
a2f4b66c L |
584 | 2019-05-28 H.J. Lu <hongjiu.lu@intel.com> |
585 | ||
586 | PR gas/24625 | |
587 | * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with | |
588 | Disp8ShiftVL. | |
589 | * i386-tbl.h: Regenerated. | |
590 | ||
405b5bd8 AM |
591 | 2019-05-24 Alan Modra <amodra@gmail.com> |
592 | ||
593 | * po/POTFILES.in: Regenerate. | |
594 | ||
8acf1435 PB |
595 | 2019-05-24 Peter Bergner <bergner@linux.ibm.com> |
596 | Alan Modra <amodra@gmail.com> | |
597 | ||
598 | * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34), | |
599 | (insert_pcrel, extract_pcrel, extract_pcrel0): New functions. | |
600 | (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment. | |
601 | (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0, | |
602 | XTOP>): Define and add entries. | |
603 | (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define. | |
604 | (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw, | |
605 | pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd, | |
606 | plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq. | |
607 | ||
dd7efa79 PB |
608 | 2019-05-24 Peter Bergner <bergner@linux.ibm.com> |
609 | Alan Modra <amodra@gmail.com> | |
610 | ||
611 | * ppc-dis.c (ppc_opts): Add "future" entry. | |
612 | (PREFIX_OPCD_SEGS): Define. | |
613 | (prefix_opcd_indices): New array. | |
614 | (disassemble_init_powerpc): Initialize prefix_opcd_indices. | |
615 | (lookup_prefix): New function. | |
616 | (print_insn_powerpc): Handle 64-bit prefix instructions. | |
617 | * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK), | |
618 | (PMRR, POWERXX): Define. | |
619 | (prefix_opcodes): New instruction table. | |
620 | (prefix_num_opcodes): New constant. | |
621 | ||
79472b45 JM |
622 | 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com> |
623 | ||
624 | * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch. | |
625 | * configure: Regenerated. | |
626 | * Makefile.am: Add rules for the files generated from cpu/bpf.cpu | |
627 | and cpu/bpf.opc. | |
628 | (HFILES): Add bpf-desc.h and bpf-opc.h. | |
629 | (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c, | |
630 | bpf-ibld.c and bpf-opc.c. | |
631 | (BPF_DEPS): Define. | |
632 | * Makefile.in: Regenerated. | |
633 | * disassemble.c (ARCH_bpf): Define. | |
634 | (disassembler): Add case for bfd_arch_bpf. | |
635 | (disassemble_init_for_target): Likewise. | |
636 | (enum epbf_isa_attr): Define. | |
637 | * disassemble.h: extern print_insn_bpf. | |
638 | * bpf-asm.c: Generated. | |
639 | * bpf-opc.h: Likewise. | |
640 | * bpf-opc.c: Likewise. | |
641 | * bpf-ibld.c: Likewise. | |
642 | * bpf-dis.c: Likewise. | |
643 | * bpf-desc.h: Likewise. | |
644 | * bpf-desc.c: Likewise. | |
645 | ||
ba6cd17f SD |
646 | 2019-05-21 Sudakshina Das <sudi.das@arm.com> |
647 | ||
648 | * arm-dis.c (coprocessor_opcodes): New instructions for VMRS | |
649 | and VMSR with the new operands. | |
650 | ||
e39c1607 SD |
651 | 2019-05-21 Sudakshina Das <sudi.das@arm.com> |
652 | ||
653 | * arm-dis.c (enum mve_instructions): New enum | |
654 | for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv | |
655 | and cneg. | |
656 | (mve_opcodes): New instructions as above. | |
657 | (is_mve_encoding_conflict): Add cases for csinc, csinv, | |
658 | csneg and csel. | |
659 | (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C. | |
660 | ||
23d00a41 SD |
661 | 2019-05-21 Sudakshina Das <sudi.das@arm.com> |
662 | ||
663 | * arm-dis.c (emun mve_instructions): Updated for new instructions. | |
664 | (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl, | |
665 | sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, | |
666 | uqshl, urshrl and urshr. | |
667 | (is_mve_okay_in_it): Add new instructions to TRUE list. | |
668 | (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15. | |
669 | (print_insn_mve): Updated to accept new %j, | |
670 | %<bitfield>m and %<bitfield>n patterns. | |
671 | ||
cd4797ee FS |
672 | 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com> |
673 | ||
674 | * mips-opc.c (mips_builtin_opcodes): Change source register | |
675 | constraint for DAUI. | |
676 | ||
999b073b NC |
677 | 2019-05-20 Nick Clifton <nickc@redhat.com> |
678 | ||
679 | * po/fr.po: Updated French translation. | |
680 | ||
14b456f2 AV |
681 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
682 | Michael Collison <michael.collison@arm.com> | |
683 | ||
684 | * arm-dis.c (thumb32_opcodes): Add new instructions. | |
685 | (enum mve_instructions): Likewise. | |
686 | (enum mve_undefined): Add new reasons. | |
687 | (is_mve_encoding_conflict): Handle new instructions. | |
688 | (is_mve_undefined): Likewise. | |
689 | (is_mve_unpredictable): Likewise. | |
690 | (print_mve_undefined): Likewise. | |
691 | (print_mve_size): Likewise. | |
692 | ||
f49bb598 AV |
693 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
694 | Michael Collison <michael.collison@arm.com> | |
695 | ||
696 | * arm-dis.c (thumb32_opcodes): Add new instructions. | |
697 | (enum mve_instructions): Likewise. | |
698 | (is_mve_encoding_conflict): Handle new instructions. | |
699 | (is_mve_undefined): Likewise. | |
700 | (is_mve_unpredictable): Likewise. | |
701 | (print_mve_size): Likewise. | |
702 | ||
56858bea AV |
703 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
704 | Michael Collison <michael.collison@arm.com> | |
705 | ||
706 | * arm-dis.c (thumb32_opcodes): Add new instructions. | |
707 | (enum mve_instructions): Likewise. | |
708 | (is_mve_encoding_conflict): Likewise. | |
709 | (is_mve_unpredictable): Likewise. | |
710 | (print_mve_size): Likewise. | |
711 | ||
e523f101 AV |
712 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
713 | Michael Collison <michael.collison@arm.com> | |
714 | ||
715 | * arm-dis.c (thumb32_opcodes): Add new instructions. | |
716 | (enum mve_instructions): Likewise. | |
717 | (is_mve_encoding_conflict): Handle new instructions. | |
718 | (is_mve_undefined): Likewise. | |
719 | (is_mve_unpredictable): Likewise. | |
720 | (print_mve_size): Likewise. | |
721 | ||
66dcaa5d AV |
722 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
723 | Michael Collison <michael.collison@arm.com> | |
724 | ||
725 | * arm-dis.c (thumb32_opcodes): Add new instructions. | |
726 | (enum mve_instructions): Likewise. | |
727 | (is_mve_encoding_conflict): Handle new instructions. | |
728 | (is_mve_undefined): Likewise. | |
729 | (is_mve_unpredictable): Likewise. | |
730 | (print_mve_size): Likewise. | |
731 | (print_insn_mve): Likewise. | |
732 | ||
d052b9b7 AV |
733 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
734 | Michael Collison <michael.collison@arm.com> | |
735 | ||
736 | * arm-dis.c (thumb32_opcodes): Add new instructions. | |
737 | (print_insn_thumb32): Handle new instructions. | |
738 | ||
ed63aa17 AV |
739 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
740 | Michael Collison <michael.collison@arm.com> | |
741 | ||
742 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
743 | (enum mve_undefined): Add new reasons. | |
744 | (is_mve_encoding_conflict): Handle new instructions. | |
745 | (is_mve_undefined): Likewise. | |
746 | (is_mve_unpredictable): Likewise. | |
747 | (print_mve_undefined): Likewise. | |
748 | (print_mve_size): Likewise. | |
749 | (print_mve_shift_n): Likewise. | |
750 | (print_insn_mve): Likewise. | |
751 | ||
897b9bbc AV |
752 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
753 | Michael Collison <michael.collison@arm.com> | |
754 | ||
755 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
756 | (is_mve_encoding_conflict): Handle new instructions. | |
757 | (is_mve_unpredictable): Likewise. | |
758 | (print_mve_rotate): Likewise. | |
759 | (print_mve_size): Likewise. | |
760 | (print_insn_mve): Likewise. | |
761 | ||
1c8f2df8 AV |
762 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
763 | Michael Collison <michael.collison@arm.com> | |
764 | ||
765 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
766 | (is_mve_encoding_conflict): Handle new instructions. | |
767 | (is_mve_unpredictable): Likewise. | |
768 | (print_mve_size): Likewise. | |
769 | (print_insn_mve): Likewise. | |
770 | ||
d3b63143 AV |
771 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
772 | Michael Collison <michael.collison@arm.com> | |
773 | ||
774 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
775 | (enum mve_undefined): Add new reasons. | |
776 | (is_mve_encoding_conflict): Handle new instructions. | |
777 | (is_mve_undefined): Likewise. | |
778 | (is_mve_unpredictable): Likewise. | |
779 | (print_mve_undefined): Likewise. | |
780 | (print_mve_size): Likewise. | |
781 | (print_insn_mve): Likewise. | |
782 | ||
14925797 AV |
783 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
784 | Michael Collison <michael.collison@arm.com> | |
785 | ||
786 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
787 | (is_mve_encoding_conflict): Handle new instructions. | |
788 | (is_mve_undefined): Likewise. | |
789 | (is_mve_unpredictable): Likewise. | |
790 | (print_mve_size): Likewise. | |
791 | (print_insn_mve): Likewise. | |
792 | ||
c507f10b AV |
793 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
794 | Michael Collison <michael.collison@arm.com> | |
795 | ||
796 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
797 | (enum mve_unpredictable): Add new reasons. | |
798 | (enum mve_undefined): Likewise. | |
799 | (is_mve_okay_in_it): Handle new isntructions. | |
800 | (is_mve_encoding_conflict): Likewise. | |
801 | (is_mve_undefined): Likewise. | |
802 | (is_mve_unpredictable): Likewise. | |
803 | (print_mve_vmov_index): Likewise. | |
804 | (print_simd_imm8): Likewise. | |
805 | (print_mve_undefined): Likewise. | |
806 | (print_mve_unpredictable): Likewise. | |
807 | (print_mve_size): Likewise. | |
808 | (print_insn_mve): Likewise. | |
809 | ||
bf0b396d AV |
810 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
811 | Michael Collison <michael.collison@arm.com> | |
812 | ||
813 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
814 | (enum mve_unpredictable): Add new reasons. | |
815 | (enum mve_undefined): Likewise. | |
816 | (is_mve_encoding_conflict): Handle new instructions. | |
817 | (is_mve_undefined): Likewise. | |
818 | (is_mve_unpredictable): Likewise. | |
819 | (print_mve_undefined): Likewise. | |
820 | (print_mve_unpredictable): Likewise. | |
821 | (print_mve_rounding_mode): Likewise. | |
822 | (print_mve_vcvt_size): Likewise. | |
823 | (print_mve_size): Likewise. | |
824 | (print_insn_mve): Likewise. | |
825 | ||
ef1576a1 AV |
826 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
827 | Michael Collison <michael.collison@arm.com> | |
828 | ||
829 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
830 | (enum mve_unpredictable): Add new reasons. | |
831 | (enum mve_undefined): Likewise. | |
832 | (is_mve_undefined): Handle new instructions. | |
833 | (is_mve_unpredictable): Likewise. | |
834 | (print_mve_undefined): Likewise. | |
835 | (print_mve_unpredictable): Likewise. | |
836 | (print_mve_size): Likewise. | |
837 | (print_insn_mve): Likewise. | |
838 | ||
aef6d006 AV |
839 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
840 | Michael Collison <michael.collison@arm.com> | |
841 | ||
842 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
843 | (enum mve_undefined): Add new reasons. | |
844 | (insns): Add new instructions. | |
845 | (is_mve_encoding_conflict): | |
846 | (print_mve_vld_str_addr): New print function. | |
847 | (is_mve_undefined): Handle new instructions. | |
848 | (is_mve_unpredictable): Likewise. | |
849 | (print_mve_undefined): Likewise. | |
850 | (print_mve_size): Likewise. | |
851 | (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions. | |
852 | (print_insn_mve): Handle new operands. | |
853 | ||
04d54ace AV |
854 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
855 | Michael Collison <michael.collison@arm.com> | |
856 | ||
857 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
858 | (enum mve_unpredictable): Add new reasons. | |
859 | (is_mve_encoding_conflict): Handle new instructions. | |
860 | (is_mve_unpredictable): Likewise. | |
861 | (mve_opcodes): Add new instructions. | |
862 | (print_mve_unpredictable): Handle new reasons. | |
863 | (print_mve_register_blocks): New print function. | |
864 | (print_mve_size): Handle new instructions. | |
865 | (print_insn_mve): Likewise. | |
866 | ||
9743db03 AV |
867 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
868 | Michael Collison <michael.collison@arm.com> | |
869 | ||
870 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
871 | (enum mve_unpredictable): Add new reasons. | |
872 | (enum mve_undefined): Likewise. | |
873 | (is_mve_encoding_conflict): Handle new instructions. | |
874 | (is_mve_undefined): Likewise. | |
875 | (is_mve_unpredictable): Likewise. | |
876 | (coprocessor_opcodes): Move NEON VDUP from here... | |
877 | (neon_opcodes): ... to here. | |
878 | (mve_opcodes): Add new instructions. | |
879 | (print_mve_undefined): Handle new reasons. | |
880 | (print_mve_unpredictable): Likewise. | |
881 | (print_mve_size): Handle new instructions. | |
882 | (print_insn_neon): Handle vdup. | |
883 | (print_insn_mve): Handle new operands. | |
884 | ||
143275ea AV |
885 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
886 | Michael Collison <michael.collison@arm.com> | |
887 | ||
888 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
889 | (enum mve_unpredictable): Add new values. | |
890 | (mve_opcodes): Add new instructions. | |
891 | (vec_condnames): New array with vector conditions. | |
892 | (mve_predicatenames): New array with predicate suffixes. | |
893 | (mve_vec_sizename): New array with vector sizes. | |
894 | (enum vpt_pred_state): New enum with vector predication states. | |
895 | (struct vpt_block): New struct type for vpt blocks. | |
896 | (vpt_block_state): Global struct to keep track of state. | |
897 | (mve_extract_pred_mask): New helper function. | |
898 | (num_instructions_vpt_block): Likewise. | |
899 | (mark_outside_vpt_block): Likewise. | |
900 | (mark_inside_vpt_block): Likewise. | |
901 | (invert_next_predicate_state): Likewise. | |
902 | (update_next_predicate_state): Likewise. | |
903 | (update_vpt_block_state): Likewise. | |
904 | (is_vpt_instruction): Likewise. | |
905 | (is_mve_encoding_conflict): Add entries for new instructions. | |
906 | (is_mve_unpredictable): Likewise. | |
907 | (print_mve_unpredictable): Handle new cases. | |
908 | (print_instruction_predicate): Likewise. | |
909 | (print_mve_size): New function. | |
910 | (print_vec_condition): New function. | |
911 | (print_insn_mve): Handle vpt blocks and new print operands. | |
912 | ||
f08d8ce3 AV |
913 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
914 | ||
915 | * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors | |
916 | 8, 14 and 15 for Armv8.1-M Mainline. | |
917 | ||
73cd51e5 AV |
918 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
919 | Michael Collison <michael.collison@arm.com> | |
920 | ||
921 | * arm-dis.c (enum mve_instructions): New enum. | |
922 | (enum mve_unpredictable): Likewise. | |
923 | (enum mve_undefined): Likewise. | |
924 | (struct mopcode32): New struct. | |
925 | (is_mve_okay_in_it): New function. | |
926 | (is_mve_architecture): Likewise. | |
927 | (arm_decode_field): Likewise. | |
928 | (arm_decode_field_multiple): Likewise. | |
929 | (is_mve_encoding_conflict): Likewise. | |
930 | (is_mve_undefined): Likewise. | |
931 | (is_mve_unpredictable): Likewise. | |
932 | (print_mve_undefined): Likewise. | |
933 | (print_mve_unpredictable): Likewise. | |
934 | (print_insn_coprocessor_1): Use arm_decode_field_multiple. | |
935 | (print_insn_mve): New function. | |
936 | (print_insn_thumb32): Handle MVE architecture. | |
937 | (select_arm_features): Force thumb for Armv8.1-m Mainline. | |
938 | ||
3076e594 NC |
939 | 2019-05-10 Nick Clifton <nickc@redhat.com> |
940 | ||
941 | PR 24538 | |
942 | * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the | |
943 | end of the table prematurely. | |
944 | ||
387e7624 FS |
945 | 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com> |
946 | ||
947 | * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB | |
948 | macros for R6. | |
949 | ||
0067be51 AM |
950 | 2019-05-11 Alan Modra <amodra@gmail.com> |
951 | ||
952 | * ppc-dis.c (print_insn_powerpc) Don't skip optional operands | |
953 | when -Mraw is in effect. | |
954 | ||
42e6288f MM |
955 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
956 | ||
957 | * aarch64-dis-2.c: Regenerate. | |
958 | * aarch64-tbl.h (OP_SVE_BBU): New variant set. | |
959 | (OP_SVE_BBB): New variant set. | |
960 | (OP_SVE_DDDD): New variant set. | |
961 | (OP_SVE_HHH): New variant set. | |
962 | (OP_SVE_HHHU): New variant set. | |
963 | (OP_SVE_SSS): New variant set. | |
964 | (OP_SVE_SSSU): New variant set. | |
965 | (OP_SVE_SHH): New variant set. | |
966 | (OP_SVE_SBBU): New variant set. | |
967 | (OP_SVE_DSS): New variant set. | |
968 | (OP_SVE_DHHU): New variant set. | |
969 | (OP_SVE_VMV_HSD_BHS): New variant set. | |
970 | (OP_SVE_VVU_HSD_BHS): New variant set. | |
971 | (OP_SVE_VVVU_SD_BH): New variant set. | |
972 | (OP_SVE_VVVU_BHSD): New variant set. | |
973 | (OP_SVE_VVV_QHD_DBS): New variant set. | |
974 | (OP_SVE_VVV_HSD_BHS): New variant set. | |
975 | (OP_SVE_VVV_HSD_BHS2): New variant set. | |
976 | (OP_SVE_VVV_BHS_HSD): New variant set. | |
977 | (OP_SVE_VV_BHS_HSD): New variant set. | |
978 | (OP_SVE_VVV_SD): New variant set. | |
979 | (OP_SVE_VVU_BHS_HSD): New variant set. | |
980 | (OP_SVE_VZVV_SD): New variant set. | |
981 | (OP_SVE_VZVV_BH): New variant set. | |
982 | (OP_SVE_VZV_SD): New variant set. | |
983 | (aarch64_opcode_table): Add sve2 instructions. | |
984 | ||
28ed815a MM |
985 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
986 | ||
987 | * aarch64-asm-2.c: Regenerated. | |
988 | * aarch64-dis-2.c: Regenerated. | |
989 | * aarch64-opc-2.c: Regenerated. | |
990 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
991 | for SVE_SHLIMM_UNPRED_22. | |
992 | (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22. | |
993 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22 | |
994 | operand. | |
995 | ||
fd1dc4a0 MM |
996 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
997 | ||
998 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
999 | sve_size_tsz_bhs iclass encode. | |
1000 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
1001 | sve_size_tsz_bhs iclass decode. | |
1002 | ||
31e36ab3 MM |
1003 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
1004 | ||
1005 | * aarch64-asm-2.c: Regenerated. | |
1006 | * aarch64-dis-2.c: Regenerated. | |
1007 | * aarch64-opc-2.c: Regenerated. | |
1008 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
1009 | for SVE_Zm4_11_INDEX. | |
1010 | (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX. | |
1011 | (fields): Handle SVE_i2h field. | |
1012 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field. | |
1013 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand. | |
1014 | ||
1be5f94f MM |
1015 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
1016 | ||
1017 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
1018 | sve_shift_tsz_bhsd iclass encode. | |
1019 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
1020 | sve_shift_tsz_bhsd iclass decode. | |
1021 | ||
3c17238b MM |
1022 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
1023 | ||
1024 | * aarch64-asm-2.c: Regenerated. | |
1025 | * aarch64-dis-2.c: Regenerated. | |
1026 | * aarch64-opc-2.c: Regenerated. | |
1027 | * aarch64-asm.c (aarch64_ins_sve_shrimm): | |
1028 | (aarch64_encode_variant_using_iclass): Handle | |
1029 | sve_shift_tsz_hsd iclass encode. | |
1030 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
1031 | sve_shift_tsz_hsd iclass decode. | |
1032 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
1033 | for SVE_SHRIMM_UNPRED_22. | |
1034 | (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. | |
1035 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 | |
1036 | operand. | |
1037 | ||
cd50a87a MM |
1038 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
1039 | ||
1040 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
1041 | sve_size_013 iclass encode. | |
1042 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
1043 | sve_size_013 iclass decode. | |
1044 | ||
3c705960 MM |
1045 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
1046 | ||
1047 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
1048 | sve_size_bh iclass encode. | |
1049 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
1050 | sve_size_bh iclass decode. | |
1051 | ||
0a57e14f MM |
1052 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
1053 | ||
1054 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
1055 | sve_size_sd2 iclass encode. | |
1056 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
1057 | sve_size_sd2 iclass decode. | |
1058 | * aarch64-opc.c (fields): Handle SVE_sz2 field. | |
1059 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field. | |
1060 | ||
c469c864 MM |
1061 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
1062 | ||
1063 | * aarch64-asm-2.c: Regenerated. | |
1064 | * aarch64-dis-2.c: Regenerated. | |
1065 | * aarch64-opc-2.c: Regenerated. | |
1066 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
1067 | for SVE_ADDR_ZX. | |
1068 | (aarch64_print_operand): Add printing for SVE_ADDR_ZX. | |
1069 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand. | |
1070 | ||
116adc27 MM |
1071 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
1072 | ||
1073 | * aarch64-asm-2.c: Regenerated. | |
1074 | * aarch64-dis-2.c: Regenerated. | |
1075 | * aarch64-opc-2.c: Regenerated. | |
1076 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
1077 | for SVE_Zm3_11_INDEX. | |
1078 | (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX. | |
1079 | (fields): Handle SVE_i3l and SVE_i3h2 fields. | |
1080 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2 | |
1081 | fields. | |
1082 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand. | |
1083 | ||
3bd82c86 MM |
1084 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
1085 | ||
1086 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
1087 | sve_size_hsd2 iclass encode. | |
1088 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
1089 | sve_size_hsd2 iclass decode. | |
1090 | * aarch64-opc.c (fields): Handle SVE_size field. | |
1091 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field. | |
1092 | ||
adccc507 MM |
1093 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
1094 | ||
1095 | * aarch64-asm-2.c: Regenerated. | |
1096 | * aarch64-dis-2.c: Regenerated. | |
1097 | * aarch64-opc-2.c: Regenerated. | |
1098 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
1099 | for SVE_IMM_ROT3. | |
1100 | (aarch64_print_operand): Add printing for SVE_IMM_ROT3. | |
1101 | (fields): Handle SVE_rot3 field. | |
1102 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field. | |
1103 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand. | |
1104 | ||
5cd99750 MM |
1105 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
1106 | ||
1107 | * aarch64-opc.c (verify_constraints): Check for movprfx for sve2 | |
1108 | instructions. | |
1109 | ||
7ce2460a MM |
1110 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
1111 | ||
1112 | * aarch64-tbl.h | |
1113 | (aarch64_feature_sve2, aarch64_feature_sve2aes, | |
1114 | aarch64_feature_sve2sha3, aarch64_feature_sve2sm4, | |
1115 | aarch64_feature_sve2bitperm): New feature sets. | |
1116 | (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros | |
1117 | for feature set addresses. | |
1118 | (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN, | |
1119 | SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros. | |
1120 | ||
41cee089 FS |
1121 | 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com> |
1122 | Faraz Shahbazker <fshahbazker@wavecomp.com> | |
1123 | ||
1124 | * mips-dis.c (mips_calculate_combination_ases): Add ISA | |
1125 | argument and set ASE_EVA_R6 appropriately. | |
1126 | (set_default_mips_dis_options): Pass ISA to above. | |
1127 | (parse_mips_dis_option): Likewise. | |
1128 | * mips-opc.c (EVAR6): New macro. | |
1129 | (mips_builtin_opcodes): Add llwpe, scwpe. | |
1130 | ||
b83b4b13 SD |
1131 | 2019-05-01 Sudakshina Das <sudi.das@arm.com> |
1132 | ||
1133 | * aarch64-asm-2.c: Regenerated. | |
1134 | * aarch64-dis-2.c: Regenerated. | |
1135 | * aarch64-opc-2.c: Regenerated. | |
1136 | * aarch64-opc.c (operand_general_constraint_met_p): Add case for | |
1137 | AARCH64_OPND_TME_UIMM16. | |
1138 | (aarch64_print_operand): Likewise. | |
1139 | * aarch64-tbl.h (QL_IMM_NIL): New. | |
1140 | (TME): New. | |
1141 | (_TME_INSN): New. | |
1142 | (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel. | |
1143 | ||
4a90ce95 JD |
1144 | 2019-04-29 John Darrington <john@darrington.wattle.id.au> |
1145 | ||
1146 | * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails. | |
1147 | ||
a45328b9 AB |
1148 | 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com> |
1149 | Faraz Shahbazker <fshahbazker@wavecomp.com> | |
1150 | ||
1151 | * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp. | |
1152 | ||
d10be0cb JD |
1153 | 2019-04-24 John Darrington <john@darrington.wattle.id.au> |
1154 | ||
1155 | * s12z-opc.h: Add extern "C" bracketing to help | |
1156 | users who wish to use this interface in c++ code. | |
1157 | ||
a679f24e JD |
1158 | 2019-04-24 John Darrington <john@darrington.wattle.id.au> |
1159 | ||
1160 | * s12z-opc.c (bm_decode): Handle bit map operations with the | |
1161 | "reserved0" mode. | |
1162 | ||
32c36c3c AV |
1163 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
1164 | ||
1165 | * arm-dis.c (coprocessor_opcodes): Document new %J and %K format | |
1166 | specifier. Add entries for VLDR and VSTR of system registers. | |
1167 | (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in | |
1168 | coprocessor instructions on Armv8.1-M Mainline targets. Add handling | |
1169 | of %J and %K format specifier. | |
1170 | ||
efd6b359 AV |
1171 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
1172 | ||
1173 | * arm-dis.c (coprocessor_opcodes): Document new %C format control code. | |
1174 | Add new entries for VSCCLRM instruction. | |
1175 | (print_insn_coprocessor): Handle new %C format control code. | |
1176 | ||
6b0dd094 AV |
1177 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
1178 | ||
1179 | * arm-dis.c (enum isa): New enum. | |
1180 | (struct sopcode32): New structure. | |
1181 | (coprocessor_opcodes): change type of entries to struct sopcode32 and | |
1182 | set isa field of all current entries to ANY. | |
1183 | (print_insn_coprocessor): Change type of insn to struct sopcode32. | |
1184 | Only match an entry if its isa field allows the current mode. | |
1185 | ||
4b5a202f AV |
1186 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
1187 | ||
1188 | * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for | |
1189 | CLRM. | |
1190 | (print_insn_thumb32): Add logic to print %n CLRM register list. | |
1191 | ||
60f993ce AV |
1192 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
1193 | ||
1194 | * arm-dis.c (print_insn_thumb32): Updated to accept new %P | |
1195 | and %Q patterns. | |
1196 | ||
f6b2b12d AV |
1197 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
1198 | ||
1199 | * arm-dis.c (thumb32_opcodes): New instruction bfcsel. | |
1200 | (print_insn_thumb32): Edit the switch case for %Z. | |
1201 | ||
1889da70 AV |
1202 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
1203 | ||
1204 | * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern. | |
1205 | ||
65d1bc05 AV |
1206 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
1207 | ||
1208 | * arm-dis.c (thumb32_opcodes): New instruction bfl. | |
1209 | ||
1caf72a5 AV |
1210 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
1211 | ||
1212 | * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern. | |
1213 | ||
f1c7f421 AV |
1214 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
1215 | ||
1216 | * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an | |
1217 | Arm register with r13 and r15 unpredictable. | |
1218 | (thumb32_opcodes): New instructions for bfx and bflx. | |
1219 | ||
4389b29a AV |
1220 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
1221 | ||
1222 | * arm-dis.c (thumb32_opcodes): New instructions for bf. | |
1223 | ||
e5d6e09e AV |
1224 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
1225 | ||
1226 | * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern. | |
1227 | ||
e12437dc AV |
1228 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
1229 | ||
1230 | * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern. | |
1231 | ||
031254f2 AV |
1232 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
1233 | ||
1234 | * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline. | |
1235 | ||
e5a557ac JD |
1236 | 2019-04-12 John Darrington <john@darrington.wattle.id.au> |
1237 | ||
1238 | s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with | |
1239 | "optr". ("operator" is a reserved word in c++). | |
1240 | ||
bd7ceb8d SD |
1241 | 2019-04-11 Sudakshina Das <sudi.das@arm.com> |
1242 | ||
1243 | * aarch64-opc.c (aarch64_print_operand): Add case for | |
1244 | AARCH64_OPND_Rt_SP. | |
1245 | (verify_constraints): Likewise. | |
1246 | * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier. | |
1247 | (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions | |
1248 | to accept Rt|SP as first operand. | |
1249 | (AARCH64_OPERANDS): Add new Rt_SP. | |
1250 | * aarch64-asm-2.c: Regenerated. | |
1251 | * aarch64-dis-2.c: Regenerated. | |
1252 | * aarch64-opc-2.c: Regenerated. | |
1253 | ||
e54010f1 SD |
1254 | 2019-04-11 Sudakshina Das <sudi.das@arm.com> |
1255 | ||
1256 | * aarch64-asm-2.c: Regenerated. | |
1257 | * aarch64-dis-2.c: Likewise. | |
1258 | * aarch64-opc-2.c: Likewise. | |
1259 | * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm. | |
1260 | ||
7e96e219 RS |
1261 | 2019-04-09 Robert Suchanek <robert.suchanek@mips.com> |
1262 | ||
1263 | * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel. | |
1264 | ||
6f2791d5 L |
1265 | 2019-04-08 H.J. Lu <hongjiu.lu@intel.com> |
1266 | ||
1267 | * i386-opc.tbl: Consolidate AVX512 BF16 entries. | |
1268 | * i386-init.h: Regenerated. | |
1269 | ||
e392bad3 AM |
1270 | 2019-04-07 Alan Modra <amodra@gmail.com> |
1271 | ||
1272 | * ppc-dis.c (print_insn_powerpc): Use a tiny state machine | |
1273 | op_separator to control printing of spaces, comma and parens | |
1274 | rather than need_comma, need_paren and spaces vars. | |
1275 | ||
dffaa15c AM |
1276 | 2019-04-07 Alan Modra <amodra@gmail.com> |
1277 | ||
1278 | PR 24421 | |
1279 | * arm-dis.c (print_insn_coprocessor): Correct bracket placement. | |
1280 | (print_insn_neon, print_insn_arm): Likewise. | |
1281 | ||
d6aab7a1 XG |
1282 | 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> |
1283 | ||
1284 | * i386-dis-evex.h (evex_table): Updated to support BF16 | |
1285 | instructions. | |
1286 | * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 | |
1287 | and EVEX_W_0F3872_P_3. | |
1288 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. | |
1289 | (cpu_flags): Add bitfield for CpuAVX512_BF16. | |
1290 | * i386-opc.h (enum): Add CpuAVX512_BF16. | |
1291 | (i386_cpu_flags): Add bitfield for cpuavx512_bf16. | |
1292 | * i386-opc.tbl: Add AVX512 BF16 instructions. | |
1293 | * i386-init.h: Regenerated. | |
1294 | * i386-tbl.h: Likewise. | |
1295 | ||
66e85460 AM |
1296 | 2019-04-05 Alan Modra <amodra@gmail.com> |
1297 | ||
1298 | * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK. | |
1299 | (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics | |
1300 | to favour printing of "-" branch hint when using the "y" bit. | |
1301 | Allow BH field on bc{ctr,lr,tar}{,l}{-,+}. | |
1302 | ||
c2b1c275 AM |
1303 | 2019-04-05 Alan Modra <amodra@gmail.com> |
1304 | ||
1305 | * ppc-dis.c (print_insn_powerpc): Delay printing spaces after | |
1306 | opcode until first operand is output. | |
1307 | ||
aae9718e PB |
1308 | 2019-04-04 Peter Bergner <bergner@linux.ibm.com> |
1309 | ||
1310 | PR gas/24349 | |
1311 | * ppc-opc.c (valid_bo_pre_v2): Add comments. | |
1312 | (valid_bo_post_v2): Add support for 'at' branch hints. | |
1313 | (insert_bo): Only error on branch on ctr. | |
1314 | (get_bo_hint_mask): New function. | |
1315 | (insert_boe): Add new 'branch_taken' formal argument. Add support | |
1316 | for inserting 'at' branch hints. | |
1317 | (extract_boe): Add new 'branch_taken' formal argument. Add support | |
1318 | for extracting 'at' branch hints. | |
1319 | (insert_bom, extract_bom, insert_bop, extract_bop): New functions. | |
1320 | (BOE): Delete operand. | |
1321 | (BOM, BOP): New operands. | |
1322 | (RM): Update value. | |
1323 | (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete. | |
1324 | (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-, | |
1325 | bcctrl-, bctar-, bctarl->: Replace BOE with BOM. | |
1326 | (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+, | |
1327 | bcctrl+, bctar+, bctarl+>: Replace BOE with BOP. | |
1328 | <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-, | |
1329 | bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar, | |
1330 | bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar, | |
1331 | bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, | |
1332 | bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, | |
1333 | bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, | |
1334 | bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, | |
1335 | bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, | |
1336 | beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-, | |
1337 | bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-, | |
1338 | buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+, | |
1339 | bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar, | |
1340 | bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar, | |
1341 | bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+, | |
1342 | bttarl+>: New extended mnemonics. | |
1343 | ||
96a86c01 AM |
1344 | 2019-03-28 Alan Modra <amodra@gmail.com> |
1345 | ||
1346 | PR 24390 | |
1347 | * ppc-opc.c (BTF): Define. | |
1348 | (powerpc_opcodes): Use for mtfsb*. | |
1349 | * ppc-dis.c (print_insn_powerpc): Print fields with both | |
1350 | PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number. | |
1351 | ||
796d6298 TC |
1352 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
1353 | ||
1354 | * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols. | |
1355 | (mapping_symbol_for_insn): Implement new algorithm. | |
1356 | (print_insn): Remove duplicate code. | |
1357 | ||
60df3720 TC |
1358 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
1359 | ||
1360 | * aarch64-dis.c (print_insn_aarch64): | |
1361 | Implement override. | |
1362 | ||
51457761 TC |
1363 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
1364 | ||
1365 | * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search | |
1366 | order. | |
1367 | ||
53b2f36b TC |
1368 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
1369 | ||
1370 | * aarch64-dis.c (last_stop_offset): New. | |
1371 | (print_insn_aarch64): Use stop_offset. | |
1372 | ||
89199bb5 L |
1373 | 2019-03-19 H.J. Lu <hongjiu.lu@intel.com> |
1374 | ||
1375 | PR gas/24359 | |
1376 | * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to | |
1377 | CPU_ANY_AVX2_FLAGS. | |
1378 | * i386-init.h: Regenerated. | |
1379 | ||
97ed31ae L |
1380 | 2019-03-18 H.J. Lu <hongjiu.lu@intel.com> |
1381 | ||
1382 | PR gas/24348 | |
1383 | * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8, | |
1384 | vmovdqu16, vmovdqu32 and vmovdqu64. | |
1385 | * i386-tbl.h: Regenerated. | |
1386 | ||
0919bfe9 AK |
1387 | 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com> |
1388 | ||
1389 | * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand | |
1390 | from vstrszb, vstrszh, and vstrszf. | |
1391 | ||
1392 | 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com> | |
1393 | ||
1394 | * s390-opc.txt: Add instruction descriptions. | |
1395 | ||
21820ebe JW |
1396 | 2019-02-08 Jim Wilson <jimw@sifive.com> |
1397 | ||
1398 | * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form. | |
1399 | <bne>: Likewise. | |
1400 | ||
f7dd2fb2 TC |
1401 | 2019-02-07 Tamar Christina <tamar.christina@arm.com> |
1402 | ||
1403 | * arm-dis.c (arm_opcodes): Redefine hlt to armv1. | |
1404 | ||
6456d318 TC |
1405 | 2019-02-07 Tamar Christina <tamar.christina@arm.com> |
1406 | ||
1407 | PR binutils/23212 | |
1408 | * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz. | |
1409 | * aarch64-opc.c (verify_elem_sd): New. | |
1410 | (fields): Add FLD_sz entr. | |
1411 | * aarch64-tbl.h (_SIMD_INSN): New. | |
1412 | (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and | |
1413 | fmulx scalar and vector by element isns. | |
1414 | ||
4a83b610 NC |
1415 | 2019-02-07 Nick Clifton <nickc@redhat.com> |
1416 | ||
1417 | * po/sv.po: Updated Swedish translation. | |
1418 | ||
fc60b8c8 AK |
1419 | 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> |
1420 | ||
1421 | * s390-mkopc.c (main): Accept arch13 as cpu string. | |
1422 | * s390-opc.c: Add new instruction formats and instruction opcode | |
1423 | masks. | |
1424 | * s390-opc.txt: Add new arch13 instructions. | |
1425 | ||
e10620d3 TC |
1426 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
1427 | ||
1428 | * aarch64-tbl.h (QL_LDST_AT): Update macro. | |
1429 | (aarch64_opcode): Change encoding for stg, stzg | |
1430 | st2g and st2zg. | |
1431 | * aarch64-asm-2.c: Regenerated. | |
1432 | * aarch64-dis-2.c: Regenerated. | |
1433 | * aarch64-opc-2.c: Regenerated. | |
1434 | ||
20a4ca55 SD |
1435 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
1436 | ||
1437 | * aarch64-asm-2.c: Regenerated. | |
1438 | * aarch64-dis-2.c: Likewise. | |
1439 | * aarch64-opc-2.c: Likewise. | |
1440 | * aarch64-tbl.h (aarch64_opcode): Add new stzgm. | |
1441 | ||
550fd7bf SD |
1442 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
1443 | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | |
1444 | ||
1445 | * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. | |
1446 | * aarch64-asm.h (ins_addr_simple_2): Likeiwse. | |
1447 | * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. | |
1448 | * aarch64-dis.h (ext_addr_simple_2): Likewise. | |
1449 | * aarch64-opc.c (operand_general_constraint_met_p): Remove | |
1450 | case for ldstgv_indexed. | |
1451 | (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. | |
1452 | * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. | |
1453 | (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. | |
1454 | * aarch64-asm-2.c: Regenerated. | |
1455 | * aarch64-dis-2.c: Regenerated. | |
1456 | * aarch64-opc-2.c: Regenerated. | |
1457 | ||
d9938630 NC |
1458 | 2019-01-23 Nick Clifton <nickc@redhat.com> |
1459 | ||
1460 | * po/pt_BR.po: Updated Brazilian Portuguese translation. | |
1461 | ||
375cd423 NC |
1462 | 2019-01-21 Nick Clifton <nickc@redhat.com> |
1463 | ||
1464 | * po/de.po: Updated German translation. | |
1465 | * po/uk.po: Updated Ukranian translation. | |
1466 | ||
57299f48 CX |
1467 | 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com> |
1468 | * mips-dis.c (mips_arch_choices): Fix typo in | |
1469 | gs464, gs464e and gs264e descriptors. | |
1470 | ||
f48dfe41 NC |
1471 | 2019-01-19 Nick Clifton <nickc@redhat.com> |
1472 | ||
1473 | * configure: Regenerate. | |
1474 | * po/opcodes.pot: Regenerate. | |
1475 | ||
f974f26c NC |
1476 | 2018-06-24 Nick Clifton <nickc@redhat.com> |
1477 | ||
1478 | 2.32 branch created. | |
1479 | ||
39f286cd JD |
1480 | 2019-01-09 John Darrington <john@darrington.wattle.id.au> |
1481 | ||
448b8ca8 JD |
1482 | * s12z-dis.c (print_insn_s12z): Do not dereference an operand |
1483 | if it is null. | |
1484 | -dis.c (opr_emit_disassembly): Do not omit an index if it is | |
39f286cd JD |
1485 | zero. |
1486 | ||
3107326d AP |
1487 | 2019-01-09 Andrew Paprocki <andrew@ishiboo.com> |
1488 | ||
1489 | * configure: Regenerate. | |
1490 | ||
7e9ca91e AM |
1491 | 2019-01-07 Alan Modra <amodra@gmail.com> |
1492 | ||
1493 | * configure: Regenerate. | |
1494 | * po/POTFILES.in: Regenerate. | |
1495 | ||
ef1ad42b JD |
1496 | 2019-01-03 John Darrington <john@darrington.wattle.id.au> |
1497 | ||
1498 | * s12z-opc.c: New file. | |
1499 | * s12z-opc.h: New file. | |
1500 | * s12z-dis.c: Removed all code not directly related to display | |
1501 | of instructions. Used the interface provided by the new files | |
1502 | instead. | |
1503 | * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c. | |
7e9ca91e | 1504 | * Makefile.in: Regenerate. |
ef1ad42b | 1505 | * configure.ac (bfd_s12z_arch): Correct the dependencies. |
7e9ca91e | 1506 | * configure: Regenerate. |
ef1ad42b | 1507 | |
82704155 AM |
1508 | 2019-01-01 Alan Modra <amodra@gmail.com> |
1509 | ||
1510 | Update year range in copyright notice of all files. | |
1511 | ||
d5c04e1b | 1512 | For older changes see ChangeLog-2018 |
3499769a | 1513 | \f |
d5c04e1b | 1514 | Copyright (C) 2019 Free Software Foundation, Inc. |
3499769a AM |
1515 | |
1516 | Copying and distribution of this file, with or without modification, | |
1517 | are permitted in any medium without royalty provided the copyright | |
1518 | notice and this notice are preserved. | |
1519 | ||
1520 | Local Variables: | |
1521 | mode: change-log | |
1522 | left-margin: 8 | |
1523 | fill-column: 74 | |
1524 | version-control: never | |
1525 | End: |