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[AArch64] Add ARMv8.2 instructions BFC and REV64.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
d685192a
MW		 12015-11-27 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64-asm-2.c: Regenerate.
4 * aarch64-asm.c (convert_bfc_to_bfm): New.
5 (convert_to_real): Add case for OP_BFC.
6 * aarch64-dis-2.c: Regenerate.
7 * aarch64-dis.c: (convert_bfm_to_bfc): New.
8 (convert_to_alias): Add case for OP_BFC.
9 * aarch64-opc-2.c: Regenerate.
10 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
11 to allow width operand in three-operand instructions.
12 * aarch64-tbl.h (QL_BF1): New.
13 (aarch64_feature_v8_2): New.
14 (ARMV8_2): New.
15 (aarch64_opcode_table): Add "bfc".
16
35822b38
MW		 172015-11-27 Matthew Wahab <matthew.wahab@arm.com>
18
19 * aarch64-asm-2.c: Regenerate.
20 * aarch64-dis-2.c: Regenerate.
21 * aarch64-dis.c: Weaken assert.
22 * aarch64-gen.c: Include the instruction in the list of its
23 possible aliases.
24
1a04d1a7
MW		 252015-11-27 Matthew Wahab <matthew.wahab@arm.com>
26
27 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
28 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
29 feature test.
30
e49d43ff
TG		 312015-11-23 Tristan Gingold <gingold@adacore.com>
32
33 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
34
250aafa4
MW		 352015-11-20 Matthew Wahab <matthew.wahab@arm.com>
36
37 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
38 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
39 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
40 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
41 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
42 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
43 cnthv_ctl_el2, cnthv_cval_el2.
44 (aarch64_sys_reg_supported_p): Update for the new system
45 registers.
46
a915c10f
NC		 472015-11-20 Nick Clifton <nickc@redhat.com>
48
49 PR binutils/19224
50 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
51
f8c2a965
NC		 522015-11-20 Nick Clifton <nickc@redhat.com>
53
54 * po/zh_CN.po: Updated simplified Chinese translation.
55
c2825638
MW		 562015-11-19 Matthew Wahab <matthew.wahab@arm.com>
57
58 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
59 of MSR PAN immediate operand.
60
e7286c56
NC		 612015-11-16 Nick Clifton <nickc@redhat.com>
62
63 * rx-dis.c (condition_names): Replace always and never with
64 invalid, since the always/never conditions can never be legal.
65
d8bd95ef
TG		 662015-11-13 Tristan Gingold <gingold@adacore.com>
67
68 * configure: Regenerate.
69
a680de9a
PB		 702015-11-11 Alan Modra <amodra@gmail.com>
71 Peter Bergner <bergner@vnet.ibm.com>
72
73 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
74 Add PPC_OPCODE_VSX3 to the vsx entry.
75 (powerpc_init_dialect): Set default dialect to power9.
76 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
77 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
78 extract_l1 insert_xtq6, extract_xtq6): New static functions.
79 (insert_esync): Test for illegal L operand value.
80 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
81 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
82 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
83 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
84 PPCVSX3): New defines.
85 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
86 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
87 <mcrxr>: Use XBFRARB_MASK.
88 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
89 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
90 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
91 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
92 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
93 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
94 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
95 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
96 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
97 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
98 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
99 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
100 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
101 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
102 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
103 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
104 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
105 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
106 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
107 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
108 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
109 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
110 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
111 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
112 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
113 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
114 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
115 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
116 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
117 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
118 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
119 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
120
854eb72b
NC		 1212015-11-02 Nick Clifton <nickc@redhat.com>
122
123 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
124 instructions.
125 * rx-decode.c: Regenerate.
126
e292aa7a
NC		 1272015-11-02 Nick Clifton <nickc@redhat.com>
128
129 * rx-decode.opc (rx_disp): If the displacement is zero, set the
130 type to RX_Operand_Zero_Indirect.
131 * rx-decode.c: Regenerate.
132 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
133
43cdf5ae
YQ		 1342015-10-28 Yao Qi <yao.qi@linaro.org>
135
136 * aarch64-dis.c (aarch64_decode_insn): Add one argument
137 noaliases_p. Update comments. Pass noaliases_p rather than
138 no_aliases to aarch64_opcode_decode.
139 (print_insn_aarch64_word): Pass no_aliases to
140 aarch64_decode_insn.
141
c2f28758
VK		 1422015-10-27 Vinay <Vinay.G@kpit.com>
143
144 PR binutils/19159
145 * rl78-decode.opc (MOV): Added offset to DE register in index
146 addressing mode.
147 * rl78-decode.c: Regenerate.
148
46662804
VK		 1492015-10-27 Vinay Kumar <vinay.g@kpit.com>
150
151 PR binutils/19158
152 * rl78-decode.opc: Add 's' print operator to instructions that
153 access system registers.
154 * rl78-decode.c: Regenerate.
155 * rl78-dis.c (print_insn_rl78_common): Decode all system
156 registers.
157
02f12cd4
VK		 1582015-10-27 Vinay Kumar <vinay.g@kpit.com>
159
160 PR binutils/19157
161 * rl78-decode.opc: Add 'a' print operator to mov instructions
162 using stack pointer plus index addressing.
163 * rl78-decode.c: Regenerate.
164
485f23cf
AK		 1652015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
166
167 * s390-opc.c: Fix comment.
168 * s390-opc.txt: Change instruction type for troo, trot, trto, and
169 trtt to RRF_U0RER since the second parameter does not need to be a
170 register pair.
171
3f94e60d
NC		 1722015-10-08 Nick Clifton <nickc@redhat.com>
173
174 * arc-dis.c (print_insn_arc): Initiallise insn array.
175
875880c6
YQ		 1762015-10-07 Yao Qi <yao.qi@linaro.org>
177
178 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
179 'name' rather than 'template'.
180 * aarch64-opc.c (aarch64_print_operand): Likewise.
181
886a2506
NC		 1822015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
183
184 * arc-dis.c: Revamped file for ARC support
185 * arc-dis.h: Likewise.
186 * arc-ext.c: Likewise.
187 * arc-ext.h: Likewise.
188 * arc-opc.c: Likewise.
189 * arc-fxi.h: New file.
190 * arc-regs.h: Likewise.
191 * arc-tbl.h: Likewise.
192
36f4aab1
YQ		 1932015-10-02 Yao Qi <yao.qi@linaro.org>
194
195 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
196 argument insn type to aarch64_insn. Rename to ...
197 (aarch64_decode_insn): ... it.
198 (print_insn_aarch64_word): Caller updated.
199
7232d389
YQ		 2002015-10-02 Yao Qi <yao.qi@linaro.org>
201
202 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
203 (print_insn_aarch64_word): Caller updated.
204
7ecc513a
DV		 2052015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
206
207 * s390-mkopc.c (main): Parse htm and vx flag.
208 * s390-opc.txt: Mark instructions from the hardware transactional
209 memory and vector facilities with the "htm"/"vx" flag.
210
b08b78e7
NC		 2112015-09-28 Nick Clifton <nickc@redhat.com>
212
213 * po/de.po: Updated German translation.
214
36f7a941
TR		 2152015-09-28 Tom Rix <tom@bumblecow.com>
216
217 * ppc-opc.c (PPC500): Mark some opcodes as invalid
218
b6518b38
NC		 2192015-09-23 Nick Clifton <nickc@redhat.com>
220
221 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
222 function.
223 * tic30-dis.c (print_branch): Likewise.
224 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
225 value before left shifting.
226 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
227 * hppa-dis.c (print_insn_hppa): Likewise.
228 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
229 array.
230 * msp430-dis.c (msp430_singleoperand): Likewise.
231 (msp430_doubleoperand): Likewise.
232 (print_insn_msp430): Likewise.
233 * nds32-asm.c (parse_operand): Likewise.
234 * sh-opc.h (MASK): Likewise.
235 * v850-dis.c (get_operand_value): Likewise.
236
f04265ec
NC		 2372015-09-22 Nick Clifton <nickc@redhat.com>
238
239 * rx-decode.opc (bwl): Use RX_Bad_Size.
240 (sbwl): Likewise.
241 (ubwl): Likewise. Rename to ubw.
242 (uBWL): Rename to uBW.
243 Replace all references to uBWL with uBW.
244 * rx-decode.c: Regenerate.
245 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
246 (opsize_names): Likewise.
247 (print_insn_rx): Detect and report RX_Bad_Size.
248
6dca4fd1
AB		 2492015-09-22 Anton Blanchard <anton@samba.org>
250
251 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
252
38074311
JM		 2532015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
254
255 * sparc-dis.c (print_insn_sparc): Handle the privileged register
256 %pmcdper.
257
5f40e14d
JS		 2582015-08-24 Jan Stancek <jstancek@redhat.com>
259
260 * i386-dis.c (print_insn): Fix decoding of three byte operands.
261
ab4e4ed5
AF		 2622015-08-21 Alexander Fomin <alexander.fomin@intel.com>
263
264 PR binutils/18257
265 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
266 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
267 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
268 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
269 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
270 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
271 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
272 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
273 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
274 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
275 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
276 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
277 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
278 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
279 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
280 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
281 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
282 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
283 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
284 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
285 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
286 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
287 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
288 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
289 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
290 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
291 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
292 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
293 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
294 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
295 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
296 (vex_w_table): Replace terminals with MOD_TABLE entries for
297 most of mask instructions.
298
919b75f7
AM		 2992015-08-17 Alan Modra <amodra@gmail.com>
300
301 * cgen.sh: Trim trailing space from cgen output.
302 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
303 (print_dis_table): Likewise.
304 * opc2c.c (dump_lines): Likewise.
305 (orig_filename): Warning fix.
306 * ia64-asmtab.c: Regenerate.
307
4ab90a7a
AV		 3082015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
309
310 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
311 and higher with ARM instruction set will now mark the 26-bit
312 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
313 (arm_opcodes): Fix for unpredictable nop being recognized as a
314 teq.
315
40fc1451
SD		 3162015-08-12 Simon Dardis <simon.dardis@imgtec.com>
317
318 * micromips-opc.c (micromips_opcodes): Re-order table so that move
319 based on 'or' is first.
320 * mips-opc.c (mips_builtin_opcodes): Ditto.
321
922c5db5
NC		 3222015-08-11 Nick Clifton <nickc@redhat.com>
323
324 PR 18800
325 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
326 instruction.
327
75fb7498
RS		 3282015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
329
330 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
331
36aed29d
AP		 3322015-08-07 Amit Pawar <Amit.Pawar@amd.com>
333
334 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
335 * i386-init.h: Regenerated.
336
a8484f96
L		 3372015-07-30 H.J. Lu <hongjiu.lu@intel.com>
338
339 PR binutils/13571
340 * i386-dis.c (MOD_0FC3): New.
341 (PREFIX_0FC3): Renamed to ...
342 (PREFIX_MOD_0_0FC3): This.
343 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
344 (prefix_table): Replace Ma with Ev on movntiS.
345 (mod_table): Add MOD_0FC3.
346
37a42ee9
L		 3472015-07-27 H.J. Lu <hongjiu.lu@intel.com>
348
349 * configure: Regenerated.
350
070fe95d
AM		 3512015-07-23 Alan Modra <amodra@gmail.com>
352
353 PR 18708
354 * i386-dis.c (get64): Avoid signed integer overflow.
355
20c2a615
L		 3562015-07-22 Alexander Fomin <alexander.fomin@intel.com>
357
358 PR binutils/18631
359 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
360 "EXEvexHalfBcstXmmq" for the second operand.
361 (EVEX_W_0F79_P_2): Likewise.
362 (EVEX_W_0F7A_P_2): Likewise.
363 (EVEX_W_0F7B_P_2): Likewise.
364
6f1c2142
AM		 3652015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
366
367 * arm-dis.c (print_insn_coprocessor): Added support for quarter
368 float bitfield format.
369 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
370 quarter float bitfield format.
371
8a643cc3
L		 3722015-07-14 H.J. Lu <hongjiu.lu@intel.com>
373
374 * configure: Regenerated.
375
ef5a96d5
AM		 3762015-07-03 Alan Modra <amodra@gmail.com>
377
378 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
379 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
380 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
381
c8c8175b
SL		 3822015-07-01 Sandra Loosemore <sandra@codesourcery.com>
383 Cesar Philippidis <cesar@codesourcery.com>
384
385 * nios2-dis.c (nios2_extract_opcode): New.
386 (nios2_disassembler_state): New.
387 (nios2_find_opcode_hash): Use mach parameter to select correct
388 disassembler state.
389 (nios2_print_insn_arg): Extend to support new R2 argument letters
390 and formats.
391 (print_insn_nios2): Check for 16-bit instruction at end of memory.
392 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
393 (NIOS2_NUM_OPCODES): Rename to...
394 (NIOS2_NUM_R1_OPCODES): This.
395 (nios2_r2_opcodes): New.
396 (NIOS2_NUM_R2_OPCODES): New.
397 (nios2_num_r2_opcodes): New.
398 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
399 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
400 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
401 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
402 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
403
9916071f
AP		 4042015-06-30 Amit Pawar <Amit.Pawar@amd.com>
405
406 * i386-dis.c (OP_Mwaitx): New.
407 (rm_table): Add monitorx/mwaitx.
408 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
409 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
410 (operand_type_init): Add CpuMWAITX.
411 * i386-opc.h (CpuMWAITX): New.
412 (i386_cpu_flags): Add cpumwaitx.
413 * i386-opc.tbl: Add monitorx and mwaitx.
414 * i386-init.h: Regenerated.
415 * i386-tbl.h: Likewise.
416
7b934113
PB		 4172015-06-22 Peter Bergner <bergner@vnet.ibm.com>
418
419 * ppc-opc.c (insert_ls): Test for invalid LS operands.
420 (insert_esync): New function.
421 (LS, WC): Use insert_ls.
422 (ESYNC): Use insert_esync.
423
bdc4de1b
NC		 4242015-06-22 Nick Clifton <nickc@redhat.com>
425
426 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
427 requested region lies beyond it.
428 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
429 looking for 32-bit insns.
430 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
431 data.
432 * sh-dis.c (print_insn_sh): Likewise.
433 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
434 blocks of instructions.
435 * vax-dis.c (print_insn_vax): Check that the requested address
436 does not clash with the stop_vma.
437
11a0cf2e
PB		 4382015-06-19 Peter Bergner <bergner@vnet.ibm.com>
439
070fe95d 440 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 441 * ppc-opc.c (FXM4): Add non-zero optional value.
442 (TBR): Likewise.
443 (SXL): Likewise.
444 (insert_fxm): Handle new default operand value.
445 (extract_fxm): Likewise.
446 (insert_tbr): Likewise.
447 (extract_tbr): Likewise.
448
bdfa8b95
MW		 4492015-06-16 Matthew Wahab <matthew.wahab@arm.com>
450
451 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
452
24b4cf66
SN		 4532015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
454
455 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
456
99a2c561
PB		 4572015-06-12 Peter Bergner <bergner@vnet.ibm.com>
458
459 * ppc-opc.c: Add comment accidentally removed by old commit.
460 (MTMSRD_L): Delete.
461
40f77f82
AM		 4622015-06-04 Peter Bergner <bergner@vnet.ibm.com>
463
464 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
465
13be46a2
NC		 4662015-06-04 Nick Clifton <nickc@redhat.com>
467
468 PR 18474
469 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
470
ddfded2f
MW		 4712015-06-02 Matthew Wahab <matthew.wahab@arm.com>
472
473 * arm-dis.c (arm_opcodes): Add "setpan".
474 (thumb_opcodes): Add "setpan".
475
1af1dd51
MW		 4762015-06-02 Matthew Wahab <matthew.wahab@arm.com>
477
478 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
479 macros.
480
9e1f0fa7
MW		 4812015-06-02 Matthew Wahab <matthew.wahab@arm.com>
482
483 * aarch64-tbl.h (aarch64_feature_rdma): New.
484 (RDMA): New.
485 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
486 * aarch64-asm-2.c: Regenerate.
487 * aarch64-dis-2.c: Regenerate.
488 * aarch64-opc-2.c: Regenerate.
489
290806fd
MW		 4902015-06-02 Matthew Wahab <matthew.wahab@arm.com>
491
492 * aarch64-tbl.h (aarch64_feature_lor): New.
493 (LOR): New.
494 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
495 "stllrb", "stllrh".
496 * aarch64-asm-2.c: Regenerate.
497 * aarch64-dis-2.c: Regenerate.
498 * aarch64-opc-2.c: Regenerate.
499
f21cce2c
MW		 5002015-06-01 Matthew Wahab <matthew.wahab@arm.com>
501
502 * aarch64-opc.c (F_ARCHEXT): New.
503 (aarch64_sys_regs): Add "pan".
504 (aarch64_sys_reg_supported_p): New.
505 (aarch64_pstatefields): Add "pan".
506 (aarch64_pstatefield_supported_p): New.
507
d194d186
JB		 5082015-06-01 Jan Beulich <jbeulich@suse.com>
509
510 * i386-tbl.h: Regenerate.
511
3a8547d2
JB		 5122015-06-01 Jan Beulich <jbeulich@suse.com>
513
514 * i386-dis.c (print_insn): Swap rounding mode specifier and
515 general purpose register in Intel mode.
516
015c54d5
JB		 5172015-06-01 Jan Beulich <jbeulich@suse.com>
518
519 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
520 * i386-tbl.h: Regenerate.
521
071f0063
L		 5222015-05-18 H.J. Lu <hongjiu.lu@intel.com>
523
524 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
525 * i386-init.h: Regenerated.
526
5db04b09
L		 5272015-05-15 H.J. Lu <hongjiu.lu@intel.com>
528
529 PR binutis/18386
530 * i386-dis.c: Add comments for '@'.
531 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
532 (enum x86_64_isa): New.
533 (isa64): Likewise.
534 (print_i386_disassembler_options): Add amd64 and intel64.
535 (print_insn): Handle amd64 and intel64.
536 (putop): Handle '@'.
537 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
538 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
539 * i386-opc.h (AMD64): New.
540 (CpuIntel64): Likewise.
541 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
542 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
543 Mark direct call/jmp without Disp16|Disp32 as Intel64.
544 * i386-init.h: Regenerated.
545 * i386-tbl.h: Likewise.
546
4bc0608a
PB		 5472015-05-14 Peter Bergner <bergner@vnet.ibm.com>
548
549 * ppc-opc.c (IH) New define.
550 (powerpc_opcodes) <wait>: Do not enable for POWER7.
551 <tlbie>: Add RS operand for POWER7.
552 <slbia>: Add IH operand for POWER6.
553
70cead07
L		 5542015-05-11 H.J. Lu <hongjiu.lu@intel.com>
555
556 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
557 direct branch.
558 (jmp): Likewise.
559 * i386-tbl.h: Regenerated.
560
7b6d09fb
L		 5612015-05-11 H.J. Lu <hongjiu.lu@intel.com>
562
563 * configure.ac: Support bfd_iamcu_arch.
564 * disassemble.c (disassembler): Support bfd_iamcu_arch.
565 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
566 CPU_IAMCU_COMPAT_FLAGS.
567 (cpu_flags): Add CpuIAMCU.
568 * i386-opc.h (CpuIAMCU): New.
569 (i386_cpu_flags): Add cpuiamcu.
570 * configure: Regenerated.
571 * i386-init.h: Likewise.
572 * i386-tbl.h: Likewise.
573
31955f99
L		 5742015-05-08 H.J. Lu <hongjiu.lu@intel.com>
575
576 PR binutis/18386
577 * i386-dis.c (X86_64_E8): New.
578 (X86_64_E9): Likewise.
579 Update comments on 'T', 'U', 'V'. Add comments for '^'.
580 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
581 (x86_64_table): Add X86_64_E8 and X86_64_E9.
582 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
583 (putop): Handle '^'.
584 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
585 REX_W.
586
0952813b
DD		 5872015-04-30 DJ Delorie <dj@redhat.com>
588
589 * disassemble.c (disassembler): Choose suitable disassembler based
590 on E_ABI.
591 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
592 it to decode mul/div insns.
593 * rl78-decode.c: Regenerate.
594 * rl78-dis.c (print_insn_rl78): Rename to...
595 (print_insn_rl78_common): ...this, take ISA parameter.
596 (print_insn_rl78): New.
597 (print_insn_rl78_g10): New.
598 (print_insn_rl78_g13): New.
599 (print_insn_rl78_g14): New.
600 (rl78_get_disassembler): New.
601
f9d3ecaa
NC		 6022015-04-29 Nick Clifton <nickc@redhat.com>
603
604 * po/fr.po: Updated French translation.
605
4fff86c5
PB		 6062015-04-27 Peter Bergner <bergner@vnet.ibm.com>
607
608 * ppc-opc.c (DCBT_EO): New define.
609 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
610 <lharx>: Likewise.
611 <stbcx.>: Likewise.
612 <sthcx.>: Likewise.
613 <waitrsv>: Do not enable for POWER7 and later.
614 <waitimpl>: Likewise.
615 <dcbt>: Default to the two operand form of the instruction for all
616 "old" cpus. For "new" cpus, use the operand ordering that matches
617 whether the cpu is server or embedded.
618 <dcbtst>: Likewise.
619
3b78cfe1
AK		 6202015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
621
622 * s390-opc.c: New instruction type VV0UU2.
623 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
624 and WFC.
625
04d824a4
JB		 6262015-04-23 Jan Beulich <jbeulich@suse.com>
627
628 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
629 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
630 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
631 (vfpclasspd, vfpclassps): Add %XZ.
632
09708981
L		 6332015-04-15 H.J. Lu <hongjiu.lu@intel.com>
634
635 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
636 (PREFIX_UD_REPZ): Likewise.
637 (PREFIX_UD_REPNZ): Likewise.
638 (PREFIX_UD_DATA): Likewise.
639 (PREFIX_UD_ADDR): Likewise.
640 (PREFIX_UD_LOCK): Likewise.
641
3888916d
L		 6422015-04-15 H.J. Lu <hongjiu.lu@intel.com>
643
644 * i386-dis.c (prefix_requirement): Removed.
645 (print_insn): Don't set prefix_requirement. Check
646 dp->prefix_requirement instead of prefix_requirement.
647
f24bcbaa
L		 6482015-04-15 H.J. Lu <hongjiu.lu@intel.com>
649
650 PR binutils/17898
651 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
652 (PREFIX_MOD_0_0FC7_REG_6): This.
653 (PREFIX_MOD_3_0FC7_REG_6): New.
654 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
655 (prefix_table): Replace PREFIX_0FC7_REG_6 with
656 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
657 PREFIX_MOD_3_0FC7_REG_7.
658 (mod_table): Replace PREFIX_0FC7_REG_6 with
659 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
660 PREFIX_MOD_3_0FC7_REG_7.
661
507bd325
L		 6622015-04-15 H.J. Lu <hongjiu.lu@intel.com>
663
664 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
665 (PREFIX_MANDATORY_REPNZ): Likewise.
666 (PREFIX_MANDATORY_DATA): Likewise.
667 (PREFIX_MANDATORY_ADDR): Likewise.
668 (PREFIX_MANDATORY_LOCK): Likewise.
669 (PREFIX_MANDATORY): Likewise.
670 (PREFIX_UD_SHIFT): Set to 8
671 (PREFIX_UD_REPZ): Updated.
672 (PREFIX_UD_REPNZ): Likewise.
673 (PREFIX_UD_DATA): Likewise.
674 (PREFIX_UD_ADDR): Likewise.
675 (PREFIX_UD_LOCK): Likewise.
676 (PREFIX_IGNORED_SHIFT): New.
677 (PREFIX_IGNORED_REPZ): Likewise.
678 (PREFIX_IGNORED_REPNZ): Likewise.
679 (PREFIX_IGNORED_DATA): Likewise.
680 (PREFIX_IGNORED_ADDR): Likewise.
681 (PREFIX_IGNORED_LOCK): Likewise.
682 (PREFIX_OPCODE): Likewise.
683 (PREFIX_IGNORED): Likewise.
684 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
685 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
686 (three_byte_table): Likewise.
687 (mod_table): Likewise.
688 (mandatory_prefix): Renamed to ...
689 (prefix_requirement): This.
690 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
691 Update PREFIX_90 entry.
692 (get_valid_dis386): Check prefix_requirement to see if a prefix
693 should be ignored.
694 (print_insn): Replace mandatory_prefix with prefix_requirement.
695
f0fba320
RL		 6962015-04-15 Renlin Li <renlin.li@arm.com>
697
698 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
699 use it for ssat and ssat16.
700 (print_insn_thumb32): Add handle case for 'D' control code.
701
bf890a93
IT		 7022015-04-06 Ilya Tocar <ilya.tocar@intel.com>
703 H.J. Lu <hongjiu.lu@intel.com>
704
705 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
706 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
707 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
708 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
709 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
710 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
711 Fill prefix_requirement field.
712 (struct dis386): Add prefix_requirement field.
713 (dis386): Fill prefix_requirement field.
714 (dis386_twobyte): Ditto.
715 (twobyte_has_mandatory_prefix_: Remove.
716 (reg_table): Fill prefix_requirement field.
717 (prefix_table): Ditto.
718 (x86_64_table): Ditto.
719 (three_byte_table): Ditto.
720 (xop_table): Ditto.
721 (vex_table): Ditto.
722 (vex_len_table): Ditto.
723 (vex_w_table): Ditto.
724 (mod_table): Ditto.
725 (bad_opcode): Ditto.
726 (print_insn): Use prefix_requirement.
727 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
728 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
729 (float_reg): Ditto.
730
2f783c1f
MF		 7312015-03-30 Mike Frysinger <vapier@gentoo.org>
732
733 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
734
b9d94d62
L		 7352015-03-29 H.J. Lu <hongjiu.lu@intel.com>
736
737 * Makefile.in: Regenerated.
738
27c49e9a
AB		 7392015-03-25 Anton Blanchard <anton@samba.org>
740
741 * ppc-dis.c (disassemble_init_powerpc): Only initialise
742 powerpc_opcd_indices and vle_opcd_indices once.
743
c4e676f1
AB		 7442015-03-25 Anton Blanchard <anton@samba.org>
745
746 * ppc-opc.c (powerpc_opcodes): Add slbfee.
747
823d2571
TG		 7482015-03-24 Terry Guo <terry.guo@arm.com>
749
750 * arm-dis.c (opcode32): Updated to use new arm feature struct.
751 (opcode16): Likewise.
752 (coprocessor_opcodes): Replace bit with feature struct.
753 (neon_opcodes): Likewise.
754 (arm_opcodes): Likewise.
755 (thumb_opcodes): Likewise.
756 (thumb32_opcodes): Likewise.
757 (print_insn_coprocessor): Likewise.
758 (print_insn_arm): Likewise.
759 (select_arm_features): Follow new feature struct.
760
029f3522
GG		 7612015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
762
763 * i386-dis.c (rm_table): Add clzero.
764 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
765 Add CPU_CLZERO_FLAGS.
766 (cpu_flags): Add CpuCLZERO.
767 * i386-opc.h: Add CpuCLZERO.
768 * i386-opc.tbl: Add clzero.
769 * i386-init.h: Re-generated.
770 * i386-tbl.h: Re-generated.
771
6914869a
AB		 7722015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
773
774 * mips-opc.c (decode_mips_operand): Fix constraint issues
775 with u and y operands.
776
21e20815
AB		 7772015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
778
779 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
780
6b1d7593
AK		 7812015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
782
783 * s390-opc.c: Add new IBM z13 instructions.
784 * s390-opc.txt: Likewise.
785
c8f89a34
JW		 7862015-03-10 Renlin Li <renlin.li@arm.com>
787
788 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
789 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
790 related alias.
791 * aarch64-asm-2.c: Regenerate.
792 * aarch64-dis-2.c: Likewise.
793 * aarch64-opc-2.c: Likewise.
794
d8282f0e
JW		 7952015-03-03 Jiong Wang <jiong.wang@arm.com>
796
797 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
798
ac994365
OE		 7992015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
800
801 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
802 arch_sh_up.
803 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
804 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
805
fd63f640
V		 8062015-02-23 Vinay <Vinay.G@kpit.com>
807
808 * rl78-decode.opc (MOV): Added space between two operands for
809 'mov' instruction in index addressing mode.
810 * rl78-decode.c: Regenerate.
811
f63c1776
PA		 8122015-02-19 Pedro Alves <palves@redhat.com>
813
814 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
815
07774fcc
PA		 8162015-02-10 Pedro Alves <palves@redhat.com>
817 Tom Tromey <tromey@redhat.com>
818
819 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
820 microblaze_and, microblaze_xor.
821 * microblaze-opc.h (opcodes): Adjust.
822
3f8107ab
AM		 8232015-01-28 James Bowman <james.bowman@ftdichip.com>
824
825 * Makefile.am: Add FT32 files.
826 * configure.ac: Handle FT32.
827 * disassemble.c (disassembler): Call print_insn_ft32.
828 * ft32-dis.c: New file.
829 * ft32-opc.c: New file.
830 * Makefile.in: Regenerate.
831 * configure: Regenerate.
832 * po/POTFILES.in: Regenerate.
833
e5fe4957
KLC		 8342015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
835
836 * nds32-asm.c (keyword_sr): Add new system registers.
837
1e2e8c52
AK		 8382015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
839
840 * s390-dis.c (s390_extract_operand): Support vector register
841 operands.
842 (s390_print_insn_with_opcode): Support new operands types and add
843 new handling of optional operands.
844 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
845 and include opcode/s390.h instead.
846 (struct op_struct): New field `flags'.
847 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
848 (dumpTable): Dump flags.
849 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
850 string.
851 * s390-opc.c: Add new operands types, instruction formats, and
852 instruction masks.
853 (s390_opformats): Add new formats for .insn.
854 * s390-opc.txt: Add new instructions.
855
b90efa5b 8562015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 857
b90efa5b 858 Update year range in copyright notice of all files.
bffb6004 859
b90efa5b 860For older changes see ChangeLog-2014
252b5132 861\f
b90efa5b 862Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 863
864Copying and distribution of this file, with or without modification,
865are permitted in any medium without royalty provided the copyright
866notice and this notice are preserved.
867
252b5132 868Local Variables:
2f6d2f85
NC		 869mode: change-log
870left-margin: 8
871fill-column: 74
252b5132
RH		 872version-control: never
873End:
GDB Binutils - Deliverables
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