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Fix prints in tests for Python 3
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
8514e4db
AM		 12014-11-28 Alan Modra <amodra@gmail.com>
2
3 * ppc-opc.c (powerpc_opcodes <mftb>): Don't deprecate for power7.
4 (TB): Delete.
5 (insert_tbr, extract_tbr): Validate tbr number.
6
6e733cce
L		 72014-11-24 H.J. Lu <hongjiu.lu@intel.com>
8
9 * configure: Regenerated.
10
14f195c9
IT		 112014-11-17 Ilya Tocar <ilya.tocar@intel.com>
12
13 * i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb,
14 vpmultishiftqb.
15 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2.
16 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS.
17 (cpu_flags): Add CpuAVX512VBMI.
18 * i386-opc.h (enum): Add CpuAVX512VBMI.
19 (i386_cpu_flags): Add cpuavx512vbmi.
20 * i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b,
21 vpermt2b.
22 * i386-init.h: Regenerated.
23 * i386-tbl.h: Likewise.
24
2cc1b5aa
IT		 252014-11-17 Ilya Tocar <ilya.tocar@intel.com>
26
27 * i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
28 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4,
29 PREFIX_EVEX_0F38B5.
30 * i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS.
31 (cpu_flags): Add CpuAVX512IFMA.
32 * i386-opc.h (enum): Add CpuAVX512IFMA.
33 (i386_cpu_flags): Add cpuavx512ifma.
34 * i386-opc.tbl: Add vpmadd52huq, vpmadd52luq.
35 * i386-init.h: Regenerated.
36 * i386-tbl.h: Likewise.
37
9d8596f0
IT		 382014-11-17 Ilya Tocar <ilya.tocar@intel.com>
39
40 * i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7.
41 (prefix_table): Add pcommit.
42 * i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS.
43 (cpu_flags): Add CpuPCOMMIT.
44 * i386-opc.h (enum): Add CpuPCOMMIT.
45 (i386_cpu_flags): Add cpupcommit.
46 * i386-opc.tbl: Add pcommit.
47 * i386-init.h: Regenerated.
48 * i386-tbl.h: Likewise.
49
c5e7287a
IT		 502014-11-17 Ilya Tocar <ilya.tocar@intel.com>
51
52 * i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
53 (prefix_table): Add clwb.
54 * i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
55 (cpu_flags): Add CpuCLWB.
56 * i386-opc.h (enum): Add CpuCLWB.
57 (i386_cpu_flags): Add cpuclwb.
58 * i386-opc.tbl: Add clwb.
59 * i386-init.h: Regenerated.
60 * i386-tbl.h: Likewise.
61
b4714c7c
SL		 622014-11-06 Sandra Loosemore <sandra@codesourcery.com>
63
64 * nios2-dis.c (nios2_find_opcode_hash): Add mach parameter.
65 (nios2_disassemble): Adjust call to nios2_find_opcode_hash.
66
ba241f2d
NC		 672014-11-03 Nick Clifton <nickc@redhat.com>
68
69 * po/fi.po: Updated Finnish translation.
70
2c629856
N		 712014-10-31 Andrew Pinski <apinski@cavium.com>
72 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
73
74 * mips-dis.c (mips_arch_choices): Add octeon3.
75 * mips-opc.c (IOCT): Include INSN_OCTEON3.
76 (IOCT2): Likewise.
77 (IOCT3): New define.
78 (IVIRT): New define.
79 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
80 tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
81 IVIRT instructions.
82 Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
83 operand for IOCT3.
84
64b588b5
NC		 852014-10-29 Nick Clifton <nickc@redhat.com>
86
87 * po/de.po: Updated German translation.
88
96ba4233
SL		 892014-10-23 Sandra Loosemore <sandra@codesourcery.com>
90
91 * nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
92 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes. Use new
93 MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers. Add
94 size and format initializers. Merge 'b' arguments into 'j'.
95 (NIOS2_NUM_OPCODES): Adjust definition.
96 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
97 (nios2_opcodes): Adjust.
98 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
99 * nios2-dis.c (INSNLEN): Update comment.
100 (nios2_hash_init, nios2_hash): Delete.
101 (OPCODE_HASH_SIZE): New.
102 (nios2_r1_extract_opcode): New.
103 (nios2_disassembler_state): New.
104 (nios2_r1_disassembler_state): New.
105 (nios2_init_opcode_hash): Add state parameter. Adjust to use it.
106 (nios2_find_opcode_hash): Use state object.
107 (bad_opcode): New.
108 (nios2_print_insn_arg): Add op parameter. Use it to access
109 format. Remove 'b' case.
110 (nios2_disassemble): Remove special case for nop. Remove
111 hard-coded instruction size.
112
12e87fac
JB		 1132014-10-21 Jan Beulich <jbeulich@suse.com>
114
115 * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
116
d9490cd4
JM		 1172014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
118
119 * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
120 entries.
0b6be415 121 Annotate several instructions with the HWCAP2_VIS3B hwcap.
d9490cd4 122
91dc4e0a
TG		 1232014-10-15 Tristan Gingold <gingold@adacore.com>
124
125 * configure: Regenerate.
126
3d68f91c
JM		 1272014-10-09 Jose E. Marchesi &lt;jose.marchesi@oracle.com&gt;
128
129 * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
130 `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
131 Annotate table with HWCAP2 bits.
132 Add instructions xmontmul, xmontsqr, xmpmul.
133 (sparc-opcodes): Add the `mwait', `wr r,r,%mwait', `wr
134 r,i,%mwait' and `rd %mwait,r' instructions.
135 Add rd/wr instructions for accessing the %mcdper ancillary state
136 register.
137 (sparc-opcodes): Add sparc5/vis4.0 instructions:
138 subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
139 fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
140 fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
141 fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
142 fpsubus16, and faligndatai.
143 * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
144 ancillary state register to the table.
145 (print_insn_sparc): Handle the %mcdper ancillary state register.
146 (print_insn_sparc): Handle new operand type '}'.
147
68f34464
L		 1482014-09-22 H.J. Lu <hongjiu.lu@intel.com>
149
150 * i386-dis.c (MOD_0F20): Removed.
151 (MOD_0F21): Likewise.
152 (MOD_0F22): Likewise.
153 (MOD_0F23): Likewise.
154 (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
155 MOD_0F23 with "movZ".
156 (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
157 (OP_R): Check mod/rm byte and call OP_E_register.
158
40c7a7cb
KLC		 1592014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
160
161 * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
162 keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
163 keyword_aridxi): Add audio ISA extension.
164 (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
165 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
166 keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
167 for nds32-dis.c using.
168 (build_opcode_syntax): Remove dead code.
169 (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
170 parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
171 parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
172 operand parser.
173 * nds32-asm.h: Declare.
174 * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
175 decoding by switch.
176
7361da2c
AB		 1772014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
178 Matthew Fortune <matthew.fortune@imgtec.com>
179
180 * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
181 mips64r6.
182 (parse_mips_dis_option): Allow MSA and virtualization support for
183 mips64r6.
184 (mips_print_arg_state): Add fields dest_regno and seen_dest.
185 (mips_seen_register): New function.
186 (print_insn_arg): Refactored code to use mips_seen_register
187 function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
188 OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
189 the register rather than aborting.
190 (print_insn_args): Add length argument. Add code to correctly
191 calculate the instruction address for pc relative instructions.
192 (validate_insn_args): New static function.
193 (print_insn_mips): Prevent jalx disassembling for r6. Use
194 validate_insn_args.
195 (print_insn_micromips): Use validate_insn_args.
196 all the arguments are valid.
197 * mips-formats.h (PREV_CHECK): New define.
198 * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
199 -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
200 (RD_pc): New define.
201 (FS): New define.
202 (I37): New define.
203 (I69): New define.
204 (mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
205 MIPS R6 instructions from MIPS R2 instructions.
206
4b4c407a
L		 2072014-09-10 H.J. Lu <hongjiu.lu@intel.com>
208
209 * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
210 (putop): Handle "%LP".
211
df7b4545
JW		 2122014-09-03 Jiong Wang <jiong.wang@arm.com>
213
214 * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
215 * aarch64-dis-2.c: Update auto-generated file.
216
ee804238
JW		 2172014-09-03 Jiong Wang <jiong.wang@arm.com>
218
219 * aarch64-tbl.h (QL_R4NIL): New qualifiers.
220 (aarch64_feature_lse): New feature added.
221 (LSE): New Added.
222 (aarch64_opcode_table): New LSE instructions added. Improve
223 descriptions for ldarb/ldarh/ldar.
224 (aarch64_opcode_table): Describe PAIRREG.
225 * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
226 * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
227 (aarch64_print_operand): Recognize PAIRREG.
228 (operand_general_constraint_met_p): Check reg pair constraints for CASP
229 instructions.
230 * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
231 (do_special_decoding): Recognize F_LSE_SZ.
232 * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
233
5575639b
MR		 2342014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
235
236 * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
237 (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
238 "sdbbp", "syscall" and "wait".
239
84919466
MR		 2402014-08-21 Nathan Sidwell <nathan@codesourcery.com>
241 Maciej W. Rozycki <macro@codesourcery.com>
242
243 * arm-dis.c (print_arm_address): Negate the GPR-relative offset
244 returned if the U bit is set.
245
a6c70539
MR		 2462014-08-21 Maciej W. Rozycki <macro@codesourcery.com>
247
248 * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
249 48-bit "li" encoding.
250
9ace48f3
AA		 2512014-08-19 Andreas Arnez <arnez@linux.vnet.ibm.com>
252
253 * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
254 (s390_print_insn_with_opcode, opcode_mask_more_specific): New
255 static functions, code was moved from...
256 (print_insn_s390): ...here.
257 (s390_extract_operand): Adjust comment. Change type of first
258 parameter from 'unsigned char *' to 'const bfd_byte *'.
259 (union operand_value): New.
260 (s390_extract_operand): Change return type to union operand_value.
261 Also avoid integer overflow in sign-extension.
262 (s390_print_insn_with_opcode): Adjust to changed return value from
263 s390_extract_operand(). Change "%i" printf format to "%u" for
264 unsigned values.
265 (init_disasm): Simplify initialization of opc_index[]. This also
266 fixes an access after the last element of s390_opcodes[].
267 (print_insn_s390): Simplify the opcode search loop.
268 Check architecture mask against all searched opcodes, not just the
269 first matching one.
270 (s390_print_insn_with_opcode): Drop function pointer dereferences
271 without effect.
272 (print_insn_s390): Likewise.
273 (s390_insn_length): Simplify formula for return value.
274 (s390_print_insn_with_opcode): Avoid special handling for the
275 separator before the first operand. Use new local variable
276 'flags' in place of 'operand->flags'.
277
60ac5798
MF		 2782014-08-14 Mike Frysinger <vapier@gentoo.org>
279
280 * bfin-dis.c (struct private): Change int's to bfd_boolean's.
281 (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
282 decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
283 Change assignment of 1 to priv->comment to TRUE.
284 (print_insn_bfin): Change legal to a bfd_boolean. Change
285 assignment of 0/1 with priv comment and parallel and legal
286 to FALSE/TRUE.
287
b3f3b4b0
MF		 2882014-08-14 Mike Frysinger <vapier@gentoo.org>
289
290 * bfin-dis.c (OUT): Define.
291 (decode_CC2stat_0): Declare new op_names array.
292 Replace multiple if statements with a single one.
293
a4e600b2
MF		 2942014-08-14 Mike Frysinger <vapier@gentoo.org>
295
296 * bfin-dis.c (struct private): Add iw0.
297 (_print_insn_bfin): Assign iw0 to priv.iw0.
298 (print_insn_bfin): Drop ifetch and use priv.iw0.
299
703ec4e8
MF		 3002014-08-13 Mike Frysinger <vapier@gentoo.org>
301
302 * bfin-dis.c (comment, parallel): Move from global scope ...
303 (struct private): ... to this new struct.
304 (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
305 decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
306 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
307 decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
308 decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
309 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
310 decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
311 print_insn_bfin): Declare private struct. Use priv's comment and
312 parallel members.
313
ed2c4879
MF		 3142014-08-13 Mike Frysinger <vapier@gentoo.org>
315
316 * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
317 (_print_insn_bfin): Add check for unaligned pc.
318
ba329817
MF		 3192014-08-13 Mike Frysinger <vapier@gentoo.org>
320
321 * bfin-dis.c (ifetch): New function.
322 (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
323 -1 when it errors.
324
43885403
MF		 3252014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
326
327 * micromips-opc.c (COD): Rename throughout to...
328 (CM): New define, update to use INSN_COPROC_MOVE.
329 (LCD): Rename throughout to...
330 (LC): New define, update to use INSN_LOAD_COPROC.
331 * mips-opc.c: Likewise.
332
351cdf24
MF		 3332014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
334
335 * micromips-opc.c (COD, LCD) New macros.
336 (cfc1, ctc1): Remove FP_S attribute.
337 (dmfc1, mfc1, mfhc1): Add LCD attribute.
338 (dmtc1, mtc1, mthc1): Add COD attribute.
339 * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
340
90a915bf
IT		 3412014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
342 Alexander Ivchenko <alexander.ivchenko@intel.com>
343 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
344 Sergey Lega <sergey.s.lega@intel.com>
345 Anna Tikhonova <anna.tikhonova@intel.com>
346 Ilya Tocar <ilya.tocar@intel.com>
347 Andrey Turetskiy <andrey.turetskiy@intel.com>
348 Ilya Verbin <ilya.verbin@intel.com>
349 Kirill Yukhin <kirill.yukhin@intel.com>
350 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
351
352 * i386-dis-evex.h: Updated.
353 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
354 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
355 PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
356 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
357 PREFIX_EVEX_0F3A67.
358 (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
359 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
360 (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
361 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
362 EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
363 EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
364 EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
365 EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
366 EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
367 (prefix_table): Add entries for new instructions.
368 (vex_len_table): Ditto.
369 (vex_w_table): Ditto.
370 (OP_E_memory): Update xmmq_mode handling.
371 * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
372 (cpu_flags): Add CpuAVX512DQ.
373 * i386-init.h: Regenerared.
374 * i386-opc.h (CpuAVX512DQ): New.
375 (i386_cpu_flags): Add cpuavx512dq.
376 * i386-opc.tbl: Add AVX512DQ instructions.
377 * i386-tbl.h: Regenerate.
378
1ba585e8
IT		 3792014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
380 Alexander Ivchenko <alexander.ivchenko@intel.com>
381 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
382 Sergey Lega <sergey.s.lega@intel.com>
383 Anna Tikhonova <anna.tikhonova@intel.com>
384 Ilya Tocar <ilya.tocar@intel.com>
385 Andrey Turetskiy <andrey.turetskiy@intel.com>
386 Ilya Verbin <ilya.verbin@intel.com>
387 Kirill Yukhin <kirill.yukhin@intel.com>
388 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
389
390 * i386-dis-evex.h: Add new instructions (prefixes bellow).
391 * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
392 (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
393 (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
394 PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
395 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
396 PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
397 PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
398 PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
399 PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
400 PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
401 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
402 PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
403 PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
404 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
405 PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
406 PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
407 PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
408 PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
409 PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
410 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
411 PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
412 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
413 (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
414 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
415 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
416 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
417 VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
418 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
419 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
420 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
421 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
422 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
423 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
424 (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
425 EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
426 EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
427 EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
428 EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
429 EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
430 EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
431 (prefix_table): Add entries for new instructions.
432 (vex_table) : Ditto.
433 (vex_len_table): Ditto.
434 (vex_w_table): Ditto.
435 (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
436 mask_bd_mode handling.
437 (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
438 handling.
439 (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
440 handling.
441 (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
442 (OP_EX): Add dqw_swap_mode handling.
443 (OP_VEX): Add mask_bd_mode handling.
444 (OP_Mask): Add mask_bd_mode handling.
445 * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
446 (cpu_flags): Add CpuAVX512BW.
447 * i386-init.h: Regenerated.
448 * i386-opc.h (CpuAVX512BW): New.
449 (i386_cpu_flags): Add cpuavx512bw.
450 * i386-opc.tbl: Add AVX512BW instructions.
451 * i386-tbl.h: Regenerate.
452
99282af6
IT		 4532014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
454 Alexander Ivchenko <alexander.ivchenko@intel.com>
455 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
456 Sergey Lega <sergey.s.lega@intel.com>
457 Anna Tikhonova <anna.tikhonova@intel.com>
458 Ilya Tocar <ilya.tocar@intel.com>
459 Andrey Turetskiy <andrey.turetskiy@intel.com>
460 Ilya Verbin <ilya.verbin@intel.com>
461 Kirill Yukhin <kirill.yukhin@intel.com>
462 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
463
464 * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
465 * i386-tbl.h: Regenerate.
466
b28d1bda
IT		 4672014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
468 Alexander Ivchenko <alexander.ivchenko@intel.com>
469 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
470 Sergey Lega <sergey.s.lega@intel.com>
471 Anna Tikhonova <anna.tikhonova@intel.com>
472 Ilya Tocar <ilya.tocar@intel.com>
473 Andrey Turetskiy <andrey.turetskiy@intel.com>
474 Ilya Verbin <ilya.verbin@intel.com>
475 Kirill Yukhin <kirill.yukhin@intel.com>
476 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
477
478 * i386-dis.c (intel_operand_size): Support 128/256 length in
479 vex_vsib_q_w_dq_mode.
480 (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
481 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
482 (cpu_flags): Add CpuAVX512VL.
483 * i386-init.h: Regenerated.
484 * i386-opc.h (CpuAVX512VL): New.
485 (i386_cpu_flags): Add cpuavx512vl.
486 (BROADCAST_1TO4, BROADCAST_1TO2): Define.
487 * i386-opc.tbl: Add AVX512VL instructions.
488 * i386-tbl.h: Regenerate.
489
018dc9be
SK		 4902014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
491
492 * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
493 * or1k-opinst.c: Regenerate.
494
792f7758
IT		 4952014-07-08 Ilya Tocar <ilya.tocar@intel.com>
496
497 * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
498 (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
499
35eafcc7
AM		 5002014-07-04 Alan Modra <amodra@gmail.com>
501
502 * configure.ac: Rename from configure.in.
503 * Makefile.in: Regenerate.
504 * config.in: Regenerate.
505
2e98a7bd
AM		 5062014-07-04 Alan Modra <amodra@gmail.com>
507
508 * configure.in: Include bfd/version.m4.
509 (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
510 (BFD_VERSION): Delete.
511 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
512 * configure: Regenerate.
513 * Makefile.in: Regenerate.
514
f36e8886
BS		 5152014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
516 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
517 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
518 Soundararajan <Sounderarajan.D@atmel.com>
519
520 * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
2e98a7bd
AM		 521 (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
522 machine is not avrtiny.
f36e8886 523
6ddf779d
PDM		 5242014-06-26 Philippe De Muyter <phdm@macqel.be>
525
526 * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
527 constants.
528
c151b1c6
AM		 5292014-06-12 Alan Modra <amodra@gmail.com>
530
531 * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
532 * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
533
d9949a36
L		 5342014-06-10 H.J. Lu <hongjiu.lu@intel.com>
535
536 * i386-dis.c (fwait_prefix): New.
537 (ckprefix): Set fwait_prefix.
538 (print_insn): Properly print prefixes before fwait.
539
a47622ac
AM		 5402014-06-07 Alan Modra <amodra@gmail.com>
541
542 * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
543
270c9937
JB		 5442014-06-05 Joel Brobecker <brobecker@adacore.com>
545
546 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
547 bfd's development.sh.
548 * Makefile.in, configure: Regenerate.
549
9f445129
NC		 5502014-06-03 Nick Clifton <nickc@redhat.com>
551
552 * msp430-dis.c (msp430_doubleoperand): Use extension_word to
553 decide when extended addressing is being used.
554
ec9a8169
EB		 5552014-06-02 Eric Botcazou <ebotcazou@adacore.com>
556
557 * sparc-opc.c (cas): Disable for LEON.
558 (casl): Likewise.
559
cdf2a8b7
AM		 5602014-05-20 Alan Modra <amodra@gmail.com>
561
562 * m68k-dis.c: Don't include setjmp.h.
563
df18fdba
L		 5642014-05-09 H.J. Lu <hongjiu.lu@intel.com>
565
566 * i386-dis.c (ADDR16_PREFIX): Removed.
567 (ADDR32_PREFIX): Likewise.
568 (DATA16_PREFIX): Likewise.
569 (DATA32_PREFIX): Likewise.
570 (prefix_name): Updated.
571 (print_insn): Simplify data and address size prefixes processing.
572
999b995d
SK		 5732014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
574
575 * or1k-desc.c: Regenerated.
576 * or1k-desc.h: Likewise.
577 * or1k-opc.c: Likewise.
578 * or1k-opc.h: Likewise.
579 * or1k-opinst.c: Likewise.
580
ae52f483
AB		 5812014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
582
583 * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
584 (I34): New define.
585 (I36): New define.
586 (I66): New define.
587 (I68): New define.
588 * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
589 mips64r5.
590 (parse_mips_dis_option): Update MSA and virtualization support to
9f445129 591 allow mips64r3 and mips64r5.
ae52f483 592
f7730599
AB		 5932014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
594
595 * mips-opc.c (G3): Remove I4.
596
285ca992
L		 5972014-05-05 H.J. Lu <hongjiu.lu@intel.com>
598
599 PR binutils/16893
600 * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
601 (end_codep): Likewise.
602 (mandatory_prefix): Likewise.
603 (active_seg_prefix): Likewise.
604 (ckprefix): Set active_seg_prefix to the active segment register
605 prefix.
606 (seg_prefix): Removed.
607 (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
608 for prefix index. Ignore the index if it is invalid and the
609 mandatory prefix isn't required.
610 (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
611 mandatory. Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
612 in used_prefixes here. Don't print unused prefixes. Check
613 active_seg_prefix for the active segment register prefix.
614 Restore the DFLAG bit in sizeflag if the data size prefix is
615 unused. Check the unused mandatory PREFIX_XXX prefixes
616 (append_seg): Only print the segment register which gets used.
617 (OP_E_memory): Check active_seg_prefix for the segment register
618 prefix.
619 (OP_OFF): Likewise.
620 (OP_OFF64): Likewise.
621 (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
622
8df14d78
L		 6232014-05-02 H.J. Lu <hongjiu.lu@intel.com>
624
625 PR binutils/16886
626 * config.in: Regenerated.
627 * configure: Likewise.
628 * configure.in: Check if sigsetjmp is available.
629 * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
630 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
631 (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
632 * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
633 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
634 (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
635 * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
636 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
637 (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
638 * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
639 (OPCODES_SIGSETJMP): Likewise.
640 (OPCODES_SIGLONGJMP): Likewise.
641 * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
642 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
643 (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
644 * xtensa-dis.c (dis_private): Replace jmp_buf with
645 OPCODES_SIGJMP_BUF.
646 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
647 (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
648 * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
649 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
650 (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
651
86a80a50
L		 6522014-05-01 H.J. Lu <hongjiu.lu@intel.com>
653
654 PR binutils/16891
655 * i386-dis.c (print_insn): Handle prefixes before fwait.
656
a9e18c6a
AM		 6572014-04-26 Alan Modra <amodra@gmail.com>
658
659 * po/POTFILES.in: Regenerate.
660
7d64c587
AB		 6612014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
662
663 * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
664 to allow the MIPS XPA ASE.
665 (parse_mips_dis_option): Process the -Mxpa option.
666 * mips-opc.c (XPA): New define.
667 (mips_builtin_opcodes): Add MIPS XPA instructions and move the
668 locations of the ctc0 and cfc0 instructions.
669
73589c9d
CS		 6702014-04-22 Christian Svensson <blue@cmd.nu>
671
672 * Makefile.am: Remove openrisc and or32 support. Add support for or1k.
673 * configure.in: Likewise.
674 * disassemble.c: Likewise.
675 * or1k-asm.c: New file.
676 * or1k-desc.c: New file.
677 * or1k-desc.h: New file.
678 * or1k-dis.c: New file.
679 * or1k-ibld.c: New file.
680 * or1k-opc.c: New file.
681 * or1k-opc.h: New file.
682 * or1k-opinst.c: New file.
683 * Makefile.in: Regenerate.
684 * configure: Regenerate.
685 * openrisc-asm.c: Delete.
686 * openrisc-desc.c: Delete.
687 * openrisc-desc.h: Delete.
688 * openrisc-dis.c: Delete.
689 * openrisc-ibld.c: Delete.
690 * openrisc-opc.c: Delete.
691 * openrisc-opc.h: Delete.
692 * or32-dis.c: Delete.
693 * or32-opc.c: Delete.
694
2cf200a4
IT		 6952014-04-04 Ilya Tocar <ilya.tocar@intel.com>
696
697 * i386-dis.c (rm_table): Add encls, enclu.
698 * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
699 (cpu_flags): Add CpuSE1.
700 * i386-opc.h (enum): Add CpuSE1.
701 (i386_cpu_flags): Add cpuse1.
702 * i386-opc.tbl: Add encls, enclu.
703 * i386-init.h: Regenerated.
704 * i386-tbl.h: Likewise.
705
31c981bc
AG		 7062014-04-02 Anthony Green <green@moxielogic.com>
707
708 * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
709 instructions, sex.b and sex.s.
710
76dfed02
YZ		 7112014-03-26 Jiong Wang <jiong.wang@arm.com>
712
713 * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
714 instructions.
715
5fc35d96
IT		 7162014-03-20 Ilya Tocar <ilya.tocar@intel.com>
717
718 * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
719 vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
720 vscatterqps.
721 * i386-tbl.h: Regenerate.
722
ec92c392
JM		 7232014-03-19 Jose E. Marchesi <jose.marchesi@oracle.com>
724
725 * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
726 %hstick_enable added.
727
b8985e5c
NC		 7282014-03-19 Nick Clifton <nickc@redhat.com>
729
730 * rx-decode.opc (bwl): Allow for bogus instructions with a size
731 field of 3.
b41c812c 732 (sbwl, ubwl, SCALE): Likewise.
b8985e5c
NC		 733 * rx-decode.c: Regenerate.
734
fa47fa92
AM		 7352014-03-12 Alan Modra <amodra@gmail.com>
736
737 * Makefile.in: Regenerate.
738
4b95cf5c
AM		 7392014-03-05 Alan Modra <amodra@gmail.com>
740
741 Update copyright years.
742
cd0c81e9 7432014-03-04 Heiher <r@hev.cc>
4ba154f5
RS		 744
745 * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
746
079b5aec
RS		 7472014-03-04 Richard Sandiford <rdsandiford@googlemail.com>
748
749 * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
750 so that they come after the Loongson extensions.
751
2c80b753
AM		 7522014-03-03 Alan Modra <amodra@gmail.com>
753
754 * i386-gen.c (process_copyright): Emit copyright notice on one line.
755
b721f1fa
AM		 7562014-02-28 Alan Modra <amodra@gmail.com>
757
758 * msp430-decode.c: Regenerate.
759
f17c8bfc
YZ		 7602014-02-27 Jiong Wang <jiong.wang@arm.com>
761
762 * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
763 FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
764
a58549dd
YZ		 7652014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
766
767 * aarch64-opc.c (print_register_offset_address): Call
768 get_int_reg_name to prepare the register name.
769
d6e9dd78
IT		 7702014-02-25 Ilya Tocar <ilya.tocar@intel.com>
771
772 * i386-opc.tbl: Remove wrong variant of vcvtps2ph
773 * i386-tbl.h: Regenerate.
774
7752014-02-20 Ilya Tocar <ilya.tocar@intel.com>
dcf893b5
IT		 776
777 * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
778 (cpu_flags): Add CpuPREFETCHWT1.
779 * i386-init.h: Regenerate.
780 * i386-opc.h (CpuPREFETCHWT1): New.
781 (i386_cpu_flags): Add cpuprefetchwt1.
782 * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
783 * i386-tbl.h: Regenerate.
784
957d0955
IT		 7852014-02-20 Ilya Tocar <ilya.tocar@intel.com>
786
787 * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
788 to CpuAVX512F.
789 * i386-tbl.h: Regenerate.
790
10632b79
L		 7912014-02-19 H.J. Lu <hongjiu.lu@intel.com>
792
793 * i386-gen.c (output_cpu_flags): Don't output trailing space.
794 (output_opcode_modifier): Likewise.
795 (output_operand_type): Likewise.
796 * i386-init.h: Regenerated.
797 * i386-tbl.h: Likewise.
798
963f3586
IT		 7992014-02-12 Ilya Tocar <ilya.tocar@intel.com>
800
801 * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
802 MOD_0FC7_REG_5.
803 (PREFIX enum): Add PREFIX_0FAE_REG_7.
804 (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
805 (prefix_table): Add clflusopt.
806 (mod_table): Add xrstors, xsavec, xsaves.
807 * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
808 CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
809 (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
810 * i386-init.h: Regenerate.
811 * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
812 xsaves64, xsavec, xsavec64.
813 * i386-tbl.h: Regenerate.
814
c1c69e83
AM		 8152014-02-10 Alan Modra <amodra@gmail.com>
816
817 * po/POTFILES.in: Regenerate.
818 * po/opcodes.pot: Regenerate.
819
eaa9d1ad
MZ		 8202014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
821 Jan Beulich <jbeulich@suse.com>
822
823 PR binutils/16490
824 * i386-dis.c (OP_E_memory): Fix shift computation for
825 vex_vsib_q_w_dq_mode.
826
e2e6193d
RM		 8272014-01-09 Bradley Nelson <bradnelson@google.com>
828 Roland McGrath <mcgrathr@google.com>
829
830 * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
831 last_rex_prefix is -1.
832
221fd5d5
L		 8332014-01-08 H.J. Lu <hongjiu.lu@intel.com>
834
835 * i386-gen.c (process_copyright): Update copyright year to 2014.
836
b0b0c9fc
MR		 8372014-01-03 Maciej W. Rozycki <macro@codesourcery.com>
838
839 * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
840
5fb776a6 841For older changes see ChangeLog-2013
252b5132 842\f
5fb776a6 843Copyright (C) 2014 Free Software Foundation, Inc.
752937aa
NC		 844
845Copying and distribution of this file, with or without modification,
846are permitted in any medium without royalty provided the copyright
847notice and this notice are preserved.
848
252b5132 849Local Variables:
2f6d2f85
NC		 850mode: change-log
851left-margin: 8
852fill-column: 74
252b5132
RH		 853version-control: never
854End:
GDB Binutils - Deliverables
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