projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Bump version to 2.26.51
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
d8bd95ef
TG		 12015-11-13 Tristan Gingold <gingold@adacore.com>
2
3 * configure: Regenerate.
4
a680de9a
PB		 52015-11-11 Alan Modra <amodra@gmail.com>
6 Peter Bergner <bergner@vnet.ibm.com>
7
8 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
9 Add PPC_OPCODE_VSX3 to the vsx entry.
10 (powerpc_init_dialect): Set default dialect to power9.
11 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
12 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
13 extract_l1 insert_xtq6, extract_xtq6): New static functions.
14 (insert_esync): Test for illegal L operand value.
15 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
16 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
17 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
18 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
19 PPCVSX3): New defines.
20 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
21 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
22 <mcrxr>: Use XBFRARB_MASK.
23 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
24 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
25 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
26 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
27 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
28 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
29 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
30 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
31 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
32 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
33 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
34 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
35 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
36 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
37 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
38 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
39 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
40 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
41 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
42 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
43 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
44 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
45 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
46 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
47 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
48 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
49 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
50 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
51 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
52 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
53 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
54 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
55
854eb72b
NC		 562015-11-02 Nick Clifton <nickc@redhat.com>
57
58 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
59 instructions.
60 * rx-decode.c: Regenerate.
61
e292aa7a
NC		 622015-11-02 Nick Clifton <nickc@redhat.com>
63
64 * rx-decode.opc (rx_disp): If the displacement is zero, set the
65 type to RX_Operand_Zero_Indirect.
66 * rx-decode.c: Regenerate.
67 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
68
43cdf5ae
YQ		 692015-10-28 Yao Qi <yao.qi@linaro.org>
70
71 * aarch64-dis.c (aarch64_decode_insn): Add one argument
72 noaliases_p. Update comments. Pass noaliases_p rather than
73 no_aliases to aarch64_opcode_decode.
74 (print_insn_aarch64_word): Pass no_aliases to
75 aarch64_decode_insn.
76
c2f28758
VK		 772015-10-27 Vinay <Vinay.G@kpit.com>
78
79 PR binutils/19159
80 * rl78-decode.opc (MOV): Added offset to DE register in index
81 addressing mode.
82 * rl78-decode.c: Regenerate.
83
46662804
VK		 842015-10-27 Vinay Kumar <vinay.g@kpit.com>
85
86 PR binutils/19158
87 * rl78-decode.opc: Add 's' print operator to instructions that
88 access system registers.
89 * rl78-decode.c: Regenerate.
90 * rl78-dis.c (print_insn_rl78_common): Decode all system
91 registers.
92
02f12cd4
VK		 932015-10-27 Vinay Kumar <vinay.g@kpit.com>
94
95 PR binutils/19157
96 * rl78-decode.opc: Add 'a' print operator to mov instructions
97 using stack pointer plus index addressing.
98 * rl78-decode.c: Regenerate.
99
485f23cf
AK		 1002015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
101
102 * s390-opc.c: Fix comment.
103 * s390-opc.txt: Change instruction type for troo, trot, trto, and
104 trtt to RRF_U0RER since the second parameter does not need to be a
105 register pair.
106
3f94e60d
NC		 1072015-10-08 Nick Clifton <nickc@redhat.com>
108
109 * arc-dis.c (print_insn_arc): Initiallise insn array.
110
875880c6
YQ		 1112015-10-07 Yao Qi <yao.qi@linaro.org>
112
113 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
114 'name' rather than 'template'.
115 * aarch64-opc.c (aarch64_print_operand): Likewise.
116
886a2506
NC		 1172015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
118
119 * arc-dis.c: Revamped file for ARC support
120 * arc-dis.h: Likewise.
121 * arc-ext.c: Likewise.
122 * arc-ext.h: Likewise.
123 * arc-opc.c: Likewise.
124 * arc-fxi.h: New file.
125 * arc-regs.h: Likewise.
126 * arc-tbl.h: Likewise.
127
36f4aab1
YQ		 1282015-10-02 Yao Qi <yao.qi@linaro.org>
129
130 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
131 argument insn type to aarch64_insn. Rename to ...
132 (aarch64_decode_insn): ... it.
133 (print_insn_aarch64_word): Caller updated.
134
7232d389
YQ		 1352015-10-02 Yao Qi <yao.qi@linaro.org>
136
137 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
138 (print_insn_aarch64_word): Caller updated.
139
7ecc513a
DV		 1402015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
141
142 * s390-mkopc.c (main): Parse htm and vx flag.
143 * s390-opc.txt: Mark instructions from the hardware transactional
144 memory and vector facilities with the "htm"/"vx" flag.
145
b08b78e7
NC		 1462015-09-28 Nick Clifton <nickc@redhat.com>
147
148 * po/de.po: Updated German translation.
149
36f7a941
TR		 1502015-09-28 Tom Rix <tom@bumblecow.com>
151
152 * ppc-opc.c (PPC500): Mark some opcodes as invalid
153
b6518b38
NC		 1542015-09-23 Nick Clifton <nickc@redhat.com>
155
156 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
157 function.
158 * tic30-dis.c (print_branch): Likewise.
159 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
160 value before left shifting.
161 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
162 * hppa-dis.c (print_insn_hppa): Likewise.
163 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
164 array.
165 * msp430-dis.c (msp430_singleoperand): Likewise.
166 (msp430_doubleoperand): Likewise.
167 (print_insn_msp430): Likewise.
168 * nds32-asm.c (parse_operand): Likewise.
169 * sh-opc.h (MASK): Likewise.
170 * v850-dis.c (get_operand_value): Likewise.
171
f04265ec
NC		 1722015-09-22 Nick Clifton <nickc@redhat.com>
173
174 * rx-decode.opc (bwl): Use RX_Bad_Size.
175 (sbwl): Likewise.
176 (ubwl): Likewise. Rename to ubw.
177 (uBWL): Rename to uBW.
178 Replace all references to uBWL with uBW.
179 * rx-decode.c: Regenerate.
180 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
181 (opsize_names): Likewise.
182 (print_insn_rx): Detect and report RX_Bad_Size.
183
6dca4fd1
AB		 1842015-09-22 Anton Blanchard <anton@samba.org>
185
186 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
187
38074311
JM		 1882015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
189
190 * sparc-dis.c (print_insn_sparc): Handle the privileged register
191 %pmcdper.
192
5f40e14d
JS		 1932015-08-24 Jan Stancek <jstancek@redhat.com>
194
195 * i386-dis.c (print_insn): Fix decoding of three byte operands.
196
ab4e4ed5
AF		 1972015-08-21 Alexander Fomin <alexander.fomin@intel.com>
198
199 PR binutils/18257
200 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
201 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
202 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
203 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
204 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
205 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
206 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
207 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
208 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
209 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
210 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
211 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
212 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
213 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
214 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
215 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
216 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
217 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
218 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
219 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
220 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
221 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
222 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
223 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
224 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
225 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
226 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
227 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
228 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
229 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
230 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
231 (vex_w_table): Replace terminals with MOD_TABLE entries for
232 most of mask instructions.
233
919b75f7
AM		 2342015-08-17 Alan Modra <amodra@gmail.com>
235
236 * cgen.sh: Trim trailing space from cgen output.
237 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
238 (print_dis_table): Likewise.
239 * opc2c.c (dump_lines): Likewise.
240 (orig_filename): Warning fix.
241 * ia64-asmtab.c: Regenerate.
242
4ab90a7a
AV		 2432015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
244
245 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
246 and higher with ARM instruction set will now mark the 26-bit
247 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
248 (arm_opcodes): Fix for unpredictable nop being recognized as a
249 teq.
250
40fc1451
SD		 2512015-08-12 Simon Dardis <simon.dardis@imgtec.com>
252
253 * micromips-opc.c (micromips_opcodes): Re-order table so that move
254 based on 'or' is first.
255 * mips-opc.c (mips_builtin_opcodes): Ditto.
256
922c5db5
NC		 2572015-08-11 Nick Clifton <nickc@redhat.com>
258
259 PR 18800
260 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
261 instruction.
262
75fb7498
RS		 2632015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
264
265 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
266
36aed29d
AP		 2672015-08-07 Amit Pawar <Amit.Pawar@amd.com>
268
269 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
270 * i386-init.h: Regenerated.
271
a8484f96
L		 2722015-07-30 H.J. Lu <hongjiu.lu@intel.com>
273
274 PR binutils/13571
275 * i386-dis.c (MOD_0FC3): New.
276 (PREFIX_0FC3): Renamed to ...
277 (PREFIX_MOD_0_0FC3): This.
278 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
279 (prefix_table): Replace Ma with Ev on movntiS.
280 (mod_table): Add MOD_0FC3.
281
37a42ee9
L		 2822015-07-27 H.J. Lu <hongjiu.lu@intel.com>
283
284 * configure: Regenerated.
285
070fe95d
AM		 2862015-07-23 Alan Modra <amodra@gmail.com>
287
288 PR 18708
289 * i386-dis.c (get64): Avoid signed integer overflow.
290
20c2a615
L		 2912015-07-22 Alexander Fomin <alexander.fomin@intel.com>
292
293 PR binutils/18631
294 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
295 "EXEvexHalfBcstXmmq" for the second operand.
296 (EVEX_W_0F79_P_2): Likewise.
297 (EVEX_W_0F7A_P_2): Likewise.
298 (EVEX_W_0F7B_P_2): Likewise.
299
6f1c2142
AM		 3002015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
301
302 * arm-dis.c (print_insn_coprocessor): Added support for quarter
303 float bitfield format.
304 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
305 quarter float bitfield format.
306
8a643cc3
L		 3072015-07-14 H.J. Lu <hongjiu.lu@intel.com>
308
309 * configure: Regenerated.
310
ef5a96d5
AM		 3112015-07-03 Alan Modra <amodra@gmail.com>
312
313 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
314 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
315 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
316
c8c8175b
SL		 3172015-07-01 Sandra Loosemore <sandra@codesourcery.com>
318 Cesar Philippidis <cesar@codesourcery.com>
319
320 * nios2-dis.c (nios2_extract_opcode): New.
321 (nios2_disassembler_state): New.
322 (nios2_find_opcode_hash): Use mach parameter to select correct
323 disassembler state.
324 (nios2_print_insn_arg): Extend to support new R2 argument letters
325 and formats.
326 (print_insn_nios2): Check for 16-bit instruction at end of memory.
327 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
328 (NIOS2_NUM_OPCODES): Rename to...
329 (NIOS2_NUM_R1_OPCODES): This.
330 (nios2_r2_opcodes): New.
331 (NIOS2_NUM_R2_OPCODES): New.
332 (nios2_num_r2_opcodes): New.
333 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
334 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
335 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
336 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
337 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
338
9916071f
AP		 3392015-06-30 Amit Pawar <Amit.Pawar@amd.com>
340
341 * i386-dis.c (OP_Mwaitx): New.
342 (rm_table): Add monitorx/mwaitx.
343 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
344 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
345 (operand_type_init): Add CpuMWAITX.
346 * i386-opc.h (CpuMWAITX): New.
347 (i386_cpu_flags): Add cpumwaitx.
348 * i386-opc.tbl: Add monitorx and mwaitx.
349 * i386-init.h: Regenerated.
350 * i386-tbl.h: Likewise.
351
7b934113
PB		 3522015-06-22 Peter Bergner <bergner@vnet.ibm.com>
353
354 * ppc-opc.c (insert_ls): Test for invalid LS operands.
355 (insert_esync): New function.
356 (LS, WC): Use insert_ls.
357 (ESYNC): Use insert_esync.
358
bdc4de1b
NC		 3592015-06-22 Nick Clifton <nickc@redhat.com>
360
361 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
362 requested region lies beyond it.
363 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
364 looking for 32-bit insns.
365 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
366 data.
367 * sh-dis.c (print_insn_sh): Likewise.
368 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
369 blocks of instructions.
370 * vax-dis.c (print_insn_vax): Check that the requested address
371 does not clash with the stop_vma.
372
11a0cf2e
PB		 3732015-06-19 Peter Bergner <bergner@vnet.ibm.com>
374
070fe95d 375 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 376 * ppc-opc.c (FXM4): Add non-zero optional value.
377 (TBR): Likewise.
378 (SXL): Likewise.
379 (insert_fxm): Handle new default operand value.
380 (extract_fxm): Likewise.
381 (insert_tbr): Likewise.
382 (extract_tbr): Likewise.
383
bdfa8b95
MW		 3842015-06-16 Matthew Wahab <matthew.wahab@arm.com>
385
386 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
387
24b4cf66
SN		 3882015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
389
390 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
391
99a2c561
PB		 3922015-06-12 Peter Bergner <bergner@vnet.ibm.com>
393
394 * ppc-opc.c: Add comment accidentally removed by old commit.
395 (MTMSRD_L): Delete.
396
40f77f82
AM		 3972015-06-04 Peter Bergner <bergner@vnet.ibm.com>
398
399 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
400
13be46a2
NC		 4012015-06-04 Nick Clifton <nickc@redhat.com>
402
403 PR 18474
404 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
405
ddfded2f
MW		 4062015-06-02 Matthew Wahab <matthew.wahab@arm.com>
407
408 * arm-dis.c (arm_opcodes): Add "setpan".
409 (thumb_opcodes): Add "setpan".
410
1af1dd51
MW		 4112015-06-02 Matthew Wahab <matthew.wahab@arm.com>
412
413 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
414 macros.
415
9e1f0fa7
MW		 4162015-06-02 Matthew Wahab <matthew.wahab@arm.com>
417
418 * aarch64-tbl.h (aarch64_feature_rdma): New.
419 (RDMA): New.
420 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
421 * aarch64-asm-2.c: Regenerate.
422 * aarch64-dis-2.c: Regenerate.
423 * aarch64-opc-2.c: Regenerate.
424
290806fd
MW		 4252015-06-02 Matthew Wahab <matthew.wahab@arm.com>
426
427 * aarch64-tbl.h (aarch64_feature_lor): New.
428 (LOR): New.
429 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
430 "stllrb", "stllrh".
431 * aarch64-asm-2.c: Regenerate.
432 * aarch64-dis-2.c: Regenerate.
433 * aarch64-opc-2.c: Regenerate.
434
f21cce2c
MW		 4352015-06-01 Matthew Wahab <matthew.wahab@arm.com>
436
437 * aarch64-opc.c (F_ARCHEXT): New.
438 (aarch64_sys_regs): Add "pan".
439 (aarch64_sys_reg_supported_p): New.
440 (aarch64_pstatefields): Add "pan".
441 (aarch64_pstatefield_supported_p): New.
442
d194d186
JB		 4432015-06-01 Jan Beulich <jbeulich@suse.com>
444
445 * i386-tbl.h: Regenerate.
446
3a8547d2
JB		 4472015-06-01 Jan Beulich <jbeulich@suse.com>
448
449 * i386-dis.c (print_insn): Swap rounding mode specifier and
450 general purpose register in Intel mode.
451
015c54d5
JB		 4522015-06-01 Jan Beulich <jbeulich@suse.com>
453
454 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
455 * i386-tbl.h: Regenerate.
456
071f0063
L		 4572015-05-18 H.J. Lu <hongjiu.lu@intel.com>
458
459 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
460 * i386-init.h: Regenerated.
461
5db04b09
L		 4622015-05-15 H.J. Lu <hongjiu.lu@intel.com>
463
464 PR binutis/18386
465 * i386-dis.c: Add comments for '@'.
466 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
467 (enum x86_64_isa): New.
468 (isa64): Likewise.
469 (print_i386_disassembler_options): Add amd64 and intel64.
470 (print_insn): Handle amd64 and intel64.
471 (putop): Handle '@'.
472 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
473 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
474 * i386-opc.h (AMD64): New.
475 (CpuIntel64): Likewise.
476 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
477 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
478 Mark direct call/jmp without Disp16|Disp32 as Intel64.
479 * i386-init.h: Regenerated.
480 * i386-tbl.h: Likewise.
481
4bc0608a
PB		 4822015-05-14 Peter Bergner <bergner@vnet.ibm.com>
483
484 * ppc-opc.c (IH) New define.
485 (powerpc_opcodes) <wait>: Do not enable for POWER7.
486 <tlbie>: Add RS operand for POWER7.
487 <slbia>: Add IH operand for POWER6.
488
70cead07
L		 4892015-05-11 H.J. Lu <hongjiu.lu@intel.com>
490
491 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
492 direct branch.
493 (jmp): Likewise.
494 * i386-tbl.h: Regenerated.
495
7b6d09fb
L		 4962015-05-11 H.J. Lu <hongjiu.lu@intel.com>
497
498 * configure.ac: Support bfd_iamcu_arch.
499 * disassemble.c (disassembler): Support bfd_iamcu_arch.
500 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
501 CPU_IAMCU_COMPAT_FLAGS.
502 (cpu_flags): Add CpuIAMCU.
503 * i386-opc.h (CpuIAMCU): New.
504 (i386_cpu_flags): Add cpuiamcu.
505 * configure: Regenerated.
506 * i386-init.h: Likewise.
507 * i386-tbl.h: Likewise.
508
31955f99
L		 5092015-05-08 H.J. Lu <hongjiu.lu@intel.com>
510
511 PR binutis/18386
512 * i386-dis.c (X86_64_E8): New.
513 (X86_64_E9): Likewise.
514 Update comments on 'T', 'U', 'V'. Add comments for '^'.
515 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
516 (x86_64_table): Add X86_64_E8 and X86_64_E9.
517 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
518 (putop): Handle '^'.
519 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
520 REX_W.
521
0952813b
DD		 5222015-04-30 DJ Delorie <dj@redhat.com>
523
524 * disassemble.c (disassembler): Choose suitable disassembler based
525 on E_ABI.
526 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
527 it to decode mul/div insns.
528 * rl78-decode.c: Regenerate.
529 * rl78-dis.c (print_insn_rl78): Rename to...
530 (print_insn_rl78_common): ...this, take ISA parameter.
531 (print_insn_rl78): New.
532 (print_insn_rl78_g10): New.
533 (print_insn_rl78_g13): New.
534 (print_insn_rl78_g14): New.
535 (rl78_get_disassembler): New.
536
f9d3ecaa
NC		 5372015-04-29 Nick Clifton <nickc@redhat.com>
538
539 * po/fr.po: Updated French translation.
540
4fff86c5
PB		 5412015-04-27 Peter Bergner <bergner@vnet.ibm.com>
542
543 * ppc-opc.c (DCBT_EO): New define.
544 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
545 <lharx>: Likewise.
546 <stbcx.>: Likewise.
547 <sthcx.>: Likewise.
548 <waitrsv>: Do not enable for POWER7 and later.
549 <waitimpl>: Likewise.
550 <dcbt>: Default to the two operand form of the instruction for all
551 "old" cpus. For "new" cpus, use the operand ordering that matches
552 whether the cpu is server or embedded.
553 <dcbtst>: Likewise.
554
3b78cfe1
AK		 5552015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
556
557 * s390-opc.c: New instruction type VV0UU2.
558 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
559 and WFC.
560
04d824a4
JB		 5612015-04-23 Jan Beulich <jbeulich@suse.com>
562
563 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
564 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
565 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
566 (vfpclasspd, vfpclassps): Add %XZ.
567
09708981
L		 5682015-04-15 H.J. Lu <hongjiu.lu@intel.com>
569
570 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
571 (PREFIX_UD_REPZ): Likewise.
572 (PREFIX_UD_REPNZ): Likewise.
573 (PREFIX_UD_DATA): Likewise.
574 (PREFIX_UD_ADDR): Likewise.
575 (PREFIX_UD_LOCK): Likewise.
576
3888916d
L		 5772015-04-15 H.J. Lu <hongjiu.lu@intel.com>
578
579 * i386-dis.c (prefix_requirement): Removed.
580 (print_insn): Don't set prefix_requirement. Check
581 dp->prefix_requirement instead of prefix_requirement.
582
f24bcbaa
L		 5832015-04-15 H.J. Lu <hongjiu.lu@intel.com>
584
585 PR binutils/17898
586 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
587 (PREFIX_MOD_0_0FC7_REG_6): This.
588 (PREFIX_MOD_3_0FC7_REG_6): New.
589 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
590 (prefix_table): Replace PREFIX_0FC7_REG_6 with
591 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
592 PREFIX_MOD_3_0FC7_REG_7.
593 (mod_table): Replace PREFIX_0FC7_REG_6 with
594 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
595 PREFIX_MOD_3_0FC7_REG_7.
596
507bd325
L		 5972015-04-15 H.J. Lu <hongjiu.lu@intel.com>
598
599 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
600 (PREFIX_MANDATORY_REPNZ): Likewise.
601 (PREFIX_MANDATORY_DATA): Likewise.
602 (PREFIX_MANDATORY_ADDR): Likewise.
603 (PREFIX_MANDATORY_LOCK): Likewise.
604 (PREFIX_MANDATORY): Likewise.
605 (PREFIX_UD_SHIFT): Set to 8
606 (PREFIX_UD_REPZ): Updated.
607 (PREFIX_UD_REPNZ): Likewise.
608 (PREFIX_UD_DATA): Likewise.
609 (PREFIX_UD_ADDR): Likewise.
610 (PREFIX_UD_LOCK): Likewise.
611 (PREFIX_IGNORED_SHIFT): New.
612 (PREFIX_IGNORED_REPZ): Likewise.
613 (PREFIX_IGNORED_REPNZ): Likewise.
614 (PREFIX_IGNORED_DATA): Likewise.
615 (PREFIX_IGNORED_ADDR): Likewise.
616 (PREFIX_IGNORED_LOCK): Likewise.
617 (PREFIX_OPCODE): Likewise.
618 (PREFIX_IGNORED): Likewise.
619 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
620 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
621 (three_byte_table): Likewise.
622 (mod_table): Likewise.
623 (mandatory_prefix): Renamed to ...
624 (prefix_requirement): This.
625 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
626 Update PREFIX_90 entry.
627 (get_valid_dis386): Check prefix_requirement to see if a prefix
628 should be ignored.
629 (print_insn): Replace mandatory_prefix with prefix_requirement.
630
f0fba320
RL		 6312015-04-15 Renlin Li <renlin.li@arm.com>
632
633 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
634 use it for ssat and ssat16.
635 (print_insn_thumb32): Add handle case for 'D' control code.
636
bf890a93
IT		 6372015-04-06 Ilya Tocar <ilya.tocar@intel.com>
638 H.J. Lu <hongjiu.lu@intel.com>
639
640 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
641 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
642 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
643 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
644 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
645 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
646 Fill prefix_requirement field.
647 (struct dis386): Add prefix_requirement field.
648 (dis386): Fill prefix_requirement field.
649 (dis386_twobyte): Ditto.
650 (twobyte_has_mandatory_prefix_: Remove.
651 (reg_table): Fill prefix_requirement field.
652 (prefix_table): Ditto.
653 (x86_64_table): Ditto.
654 (three_byte_table): Ditto.
655 (xop_table): Ditto.
656 (vex_table): Ditto.
657 (vex_len_table): Ditto.
658 (vex_w_table): Ditto.
659 (mod_table): Ditto.
660 (bad_opcode): Ditto.
661 (print_insn): Use prefix_requirement.
662 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
663 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
664 (float_reg): Ditto.
665
2f783c1f
MF		 6662015-03-30 Mike Frysinger <vapier@gentoo.org>
667
668 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
669
b9d94d62
L		 6702015-03-29 H.J. Lu <hongjiu.lu@intel.com>
671
672 * Makefile.in: Regenerated.
673
27c49e9a
AB		 6742015-03-25 Anton Blanchard <anton@samba.org>
675
676 * ppc-dis.c (disassemble_init_powerpc): Only initialise
677 powerpc_opcd_indices and vle_opcd_indices once.
678
c4e676f1
AB		 6792015-03-25 Anton Blanchard <anton@samba.org>
680
681 * ppc-opc.c (powerpc_opcodes): Add slbfee.
682
823d2571
TG		 6832015-03-24 Terry Guo <terry.guo@arm.com>
684
685 * arm-dis.c (opcode32): Updated to use new arm feature struct.
686 (opcode16): Likewise.
687 (coprocessor_opcodes): Replace bit with feature struct.
688 (neon_opcodes): Likewise.
689 (arm_opcodes): Likewise.
690 (thumb_opcodes): Likewise.
691 (thumb32_opcodes): Likewise.
692 (print_insn_coprocessor): Likewise.
693 (print_insn_arm): Likewise.
694 (select_arm_features): Follow new feature struct.
695
029f3522
GG		 6962015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
697
698 * i386-dis.c (rm_table): Add clzero.
699 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
700 Add CPU_CLZERO_FLAGS.
701 (cpu_flags): Add CpuCLZERO.
702 * i386-opc.h: Add CpuCLZERO.
703 * i386-opc.tbl: Add clzero.
704 * i386-init.h: Re-generated.
705 * i386-tbl.h: Re-generated.
706
6914869a
AB		 7072015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
708
709 * mips-opc.c (decode_mips_operand): Fix constraint issues
710 with u and y operands.
711
21e20815
AB		 7122015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
713
714 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
715
6b1d7593
AK		 7162015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
717
718 * s390-opc.c: Add new IBM z13 instructions.
719 * s390-opc.txt: Likewise.
720
c8f89a34
JW		 7212015-03-10 Renlin Li <renlin.li@arm.com>
722
723 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
724 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
725 related alias.
726 * aarch64-asm-2.c: Regenerate.
727 * aarch64-dis-2.c: Likewise.
728 * aarch64-opc-2.c: Likewise.
729
d8282f0e
JW		 7302015-03-03 Jiong Wang <jiong.wang@arm.com>
731
732 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
733
ac994365
OE		 7342015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
735
736 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
737 arch_sh_up.
738 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
739 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
740
fd63f640
V		 7412015-02-23 Vinay <Vinay.G@kpit.com>
742
743 * rl78-decode.opc (MOV): Added space between two operands for
744 'mov' instruction in index addressing mode.
745 * rl78-decode.c: Regenerate.
746
f63c1776
PA		 7472015-02-19 Pedro Alves <palves@redhat.com>
748
749 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
750
07774fcc
PA		 7512015-02-10 Pedro Alves <palves@redhat.com>
752 Tom Tromey <tromey@redhat.com>
753
754 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
755 microblaze_and, microblaze_xor.
756 * microblaze-opc.h (opcodes): Adjust.
757
3f8107ab
AM		 7582015-01-28 James Bowman <james.bowman@ftdichip.com>
759
760 * Makefile.am: Add FT32 files.
761 * configure.ac: Handle FT32.
762 * disassemble.c (disassembler): Call print_insn_ft32.
763 * ft32-dis.c: New file.
764 * ft32-opc.c: New file.
765 * Makefile.in: Regenerate.
766 * configure: Regenerate.
767 * po/POTFILES.in: Regenerate.
768
e5fe4957
KLC		 7692015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
770
771 * nds32-asm.c (keyword_sr): Add new system registers.
772
1e2e8c52
AK		 7732015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
774
775 * s390-dis.c (s390_extract_operand): Support vector register
776 operands.
777 (s390_print_insn_with_opcode): Support new operands types and add
778 new handling of optional operands.
779 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
780 and include opcode/s390.h instead.
781 (struct op_struct): New field `flags'.
782 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
783 (dumpTable): Dump flags.
784 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
785 string.
786 * s390-opc.c: Add new operands types, instruction formats, and
787 instruction masks.
788 (s390_opformats): Add new formats for .insn.
789 * s390-opc.txt: Add new instructions.
790
b90efa5b 7912015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 792
b90efa5b 793 Update year range in copyright notice of all files.
bffb6004 794
b90efa5b 795For older changes see ChangeLog-2014
252b5132 796\f
b90efa5b 797Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 798
799Copying and distribution of this file, with or without modification,
800are permitted in any medium without royalty provided the copyright
801notice and this notice are preserved.
802
252b5132 803Local Variables:
2f6d2f85
NC		 804mode: change-log
805left-margin: 8
806fill-column: 74
252b5132
RH		 807version-control: never
808End:
GDB Binutils - Deliverables
This page took 0.788121 seconds and 4 git commands to generate.