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Remove the remaining SSE5 support
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
da8d7d66
L		 12016-10-18 H.J. Lu <hongjiu.lu@intel.com>
2
3 PR binutis/20704
4 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
5
eaf02703
MR		 62016-10-18 Maciej W. Rozycki <macro@imgtec.com>
7
8 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
9 local variable to `index_regno'.
10
decf5bd1
CM		 112016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
12
13 * arc-tbl.h: Removed any "inv.+" instructions from the table.
14
e5b06ef0
CZ		 152016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
16
17 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
18 usage on ISA basis.
19
93562a34
JW		 202016-10-11 Jiong Wang <jiong.wang@arm.com>
21
22 PR target/20666
23 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
24
362c0c4d
JW		 252016-10-07 Jiong Wang <jiong.wang@arm.com>
26
27 PR target/20667
28 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
29 available.
30
1047201f
AM		 312016-10-07 Alan Modra <amodra@gmail.com>
32
33 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
34
1a0670f3
AM		 352016-10-06 Alan Modra <amodra@gmail.com>
36
37 * aarch64-opc.c: Spell fall through comments consistently.
38 * i386-dis.c: Likewise.
39 * aarch64-dis.c: Add missing fall through comments.
40 * aarch64-opc.c: Likewise.
41 * arc-dis.c: Likewise.
42 * arm-dis.c: Likewise.
43 * i386-dis.c: Likewise.
44 * m68k-dis.c: Likewise.
45 * mep-asm.c: Likewise.
46 * ns32k-dis.c: Likewise.
47 * sh-dis.c: Likewise.
48 * tic4x-dis.c: Likewise.
49 * tic6x-dis.c: Likewise.
50 * vax-dis.c: Likewise.
51
2b804145
AM		 522016-10-06 Alan Modra <amodra@gmail.com>
53
54 * arc-ext.c (create_map): Add missing break.
55 * msp430-decode.opc (encode_as): Likewise.
56 * msp430-decode.c: Regenerate.
57
616ec358
AM		 582016-10-06 Alan Modra <amodra@gmail.com>
59
60 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
61 * crx-dis.c (print_insn_crx): Likewise.
62
72da393d
L		 632016-09-30 H.J. Lu <hongjiu.lu@intel.com>
64
65 PR binutils/20657
66 * i386-dis.c (putop): Don't assign alt twice.
67
744ce302
JW		 682016-09-29 Jiong Wang <jiong.wang@arm.com>
69
70 PR target/20553
71 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
72
a5721ba2
AM		 732016-09-29 Alan Modra <amodra@gmail.com>
74
75 * ppc-opc.c (L): Make compulsory.
76 (LOPT): New, optional form of L.
77 (HTM_R): Define as LOPT.
78 (L0, L1): Delete.
79 (L32OPT): New, optional for 32-bit L.
80 (L2OPT): New, 2-bit L for dcbf.
81 (SVC_LEC): Update.
82 (L2): Define.
83 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
84 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
85 <dcbf>: Use L2OPT.
86 <tlbiel, tlbie>: Use LOPT.
87 <wclr, wclrall>: Use L2.
88
c5da1932
VZ		 892016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
90
91 * Makefile.in: Regenerate.
92 * configure: Likewise.
93
2b848ebd
CZ		 942016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
95
96 * arc-ext-tbl.h (EXTINSN2OPF): Define.
97 (EXTINSN2OP): Use EXTINSN2OPF.
98 (bspeekm, bspop, modapp): New extension instructions.
99 * arc-opc.c (F_DNZ_ND): Define.
100 (F_DNZ_D): Likewise.
101 (F_SIZEB1): Changed.
102 (C_DNZ_D): Define.
103 (C_HARD): Changed.
104 * arc-tbl.h (dbnz): New instruction.
105 (prealloc): Allow it for ARC EM.
106 (xbfu): Likewise.
107
ad43e107
RS		 1082016-09-21 Richard Sandiford <richard.sandiford@arm.com>
109
110 * aarch64-opc.c (print_immediate_offset_address): Print spaces
111 after commas in addresses.
112 (aarch64_print_operand): Likewise.
113
ab3b8fcf
RS		 1142016-09-21 Richard Sandiford <richard.sandiford@arm.com>
115
116 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
117 rather than "should be" or "expected to be" in error messages.
118
bb7eff52
RS		 1192016-09-21 Richard Sandiford <richard.sandiford@arm.com>
120
121 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
122 (print_mnemonic_name): ...here.
123 (print_comment): New function.
124 (print_aarch64_insn): Call it.
125 * aarch64-opc.c (aarch64_conds): Add SVE names.
126 (aarch64_print_operand): Print alternative condition names in
127 a comment.
128
c0890d26
RS		 1292016-09-21 Richard Sandiford <richard.sandiford@arm.com>
130
131 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
132 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
133 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
134 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
135 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
136 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
137 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
138 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
139 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
140 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
141 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
142 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
143 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
144 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
145 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
146 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
147 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
148 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
149 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
150 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
151 (OP_SVE_XWU, OP_SVE_XXU): New macros.
152 (aarch64_feature_sve): New variable.
153 (SVE): New macro.
154 (_SVE_INSN): Likewise.
155 (aarch64_opcode_table): Add SVE instructions.
156 * aarch64-opc.h (extract_fields): Declare.
157 * aarch64-opc-2.c: Regenerate.
158 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
159 * aarch64-asm-2.c: Regenerate.
160 * aarch64-dis.c (extract_fields): Make global.
161 (do_misc_decoding): Handle the new SVE aarch64_ops.
162 * aarch64-dis-2.c: Regenerate.
163
116b6019
RS		 1642016-09-21 Richard Sandiford <richard.sandiford@arm.com>
165
166 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
167 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
168 aarch64_field_kinds.
169 * aarch64-opc.c (fields): Add corresponding entries.
170 * aarch64-asm.c (aarch64_get_variant): New function.
171 (aarch64_encode_variant_using_iclass): Likewise.
172 (aarch64_opcode_encode): Call it.
173 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
174 (aarch64_opcode_decode): Call it.
175
047cd301
RS		 1762016-09-21 Richard Sandiford <richard.sandiford@arm.com>
177
178 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
179 and FP register operands.
180 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
181 (FLD_SVE_Vn): New aarch64_field_kinds.
182 * aarch64-opc.c (fields): Add corresponding entries.
183 (aarch64_print_operand): Handle the new SVE core and FP register
184 operands.
185 * aarch64-opc-2.c: Regenerate.
186 * aarch64-asm-2.c: Likewise.
187 * aarch64-dis-2.c: Likewise.
188
165d4950
RS		 1892016-09-21 Richard Sandiford <richard.sandiford@arm.com>
190
191 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
192 immediate operands.
193 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
194 * aarch64-opc.c (fields): Add corresponding entry.
195 (operand_general_constraint_met_p): Handle the new SVE FP immediate
196 operands.
197 (aarch64_print_operand): Likewise.
198 * aarch64-opc-2.c: Regenerate.
199 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
200 (ins_sve_float_zero_one): New inserters.
201 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
202 (aarch64_ins_sve_float_half_two): Likewise.
203 (aarch64_ins_sve_float_zero_one): Likewise.
204 * aarch64-asm-2.c: Regenerate.
205 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
206 (ext_sve_float_zero_one): New extractors.
207 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
208 (aarch64_ext_sve_float_half_two): Likewise.
209 (aarch64_ext_sve_float_zero_one): Likewise.
210 * aarch64-dis-2.c: Regenerate.
211
e950b345
RS		 2122016-09-21 Richard Sandiford <richard.sandiford@arm.com>
213
214 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
215 integer immediate operands.
216 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
217 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
218 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
219 * aarch64-opc.c (fields): Add corresponding entries.
220 (operand_general_constraint_met_p): Handle the new SVE integer
221 immediate operands.
222 (aarch64_print_operand): Likewise.
223 (aarch64_sve_dupm_mov_immediate_p): New function.
224 * aarch64-opc-2.c: Regenerate.
225 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
226 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
227 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
228 (aarch64_ins_limm): ...here.
229 (aarch64_ins_inv_limm): New function.
230 (aarch64_ins_sve_aimm): Likewise.
231 (aarch64_ins_sve_asimm): Likewise.
232 (aarch64_ins_sve_limm_mov): Likewise.
233 (aarch64_ins_sve_shlimm): Likewise.
234 (aarch64_ins_sve_shrimm): Likewise.
235 * aarch64-asm-2.c: Regenerate.
236 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
237 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
238 * aarch64-dis.c (decode_limm): New function, split out from...
239 (aarch64_ext_limm): ...here.
240 (aarch64_ext_inv_limm): New function.
241 (decode_sve_aimm): Likewise.
242 (aarch64_ext_sve_aimm): Likewise.
243 (aarch64_ext_sve_asimm): Likewise.
244 (aarch64_ext_sve_limm_mov): Likewise.
245 (aarch64_top_bit): Likewise.
246 (aarch64_ext_sve_shlimm): Likewise.
247 (aarch64_ext_sve_shrimm): Likewise.
248 * aarch64-dis-2.c: Regenerate.
249
98907a70
RS		 2502016-09-21 Richard Sandiford <richard.sandiford@arm.com>
251
252 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
253 operands.
254 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
255 the AARCH64_MOD_MUL_VL entry.
256 (value_aligned_p): Cope with non-power-of-two alignments.
257 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
258 (print_immediate_offset_address): Likewise.
259 (aarch64_print_operand): Likewise.
260 * aarch64-opc-2.c: Regenerate.
261 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
262 (ins_sve_addr_ri_s9xvl): New inserters.
263 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
264 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
265 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
266 * aarch64-asm-2.c: Regenerate.
267 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
268 (ext_sve_addr_ri_s9xvl): New extractors.
269 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
270 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
271 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
272 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
273 * aarch64-dis-2.c: Regenerate.
274
4df068de
RS		 2752016-09-21 Richard Sandiford <richard.sandiford@arm.com>
276
277 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
278 address operands.
279 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
280 (FLD_SVE_xs_22): New aarch64_field_kinds.
281 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
282 (get_operand_specific_data): New function.
283 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
284 FLD_SVE_xs_14 and FLD_SVE_xs_22.
285 (operand_general_constraint_met_p): Handle the new SVE address
286 operands.
287 (sve_reg): New array.
288 (get_addr_sve_reg_name): New function.
289 (aarch64_print_operand): Handle the new SVE address operands.
290 * aarch64-opc-2.c: Regenerate.
291 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
292 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
293 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
294 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
295 (aarch64_ins_sve_addr_rr_lsl): Likewise.
296 (aarch64_ins_sve_addr_rz_xtw): Likewise.
297 (aarch64_ins_sve_addr_zi_u5): Likewise.
298 (aarch64_ins_sve_addr_zz): Likewise.
299 (aarch64_ins_sve_addr_zz_lsl): Likewise.
300 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
301 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
302 * aarch64-asm-2.c: Regenerate.
303 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
304 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
305 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
306 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
307 (aarch64_ext_sve_addr_ri_u6): Likewise.
308 (aarch64_ext_sve_addr_rr_lsl): Likewise.
309 (aarch64_ext_sve_addr_rz_xtw): Likewise.
310 (aarch64_ext_sve_addr_zi_u5): Likewise.
311 (aarch64_ext_sve_addr_zz): Likewise.
312 (aarch64_ext_sve_addr_zz_lsl): Likewise.
313 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
314 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
315 * aarch64-dis-2.c: Regenerate.
316
2442d846
RS		 3172016-09-21 Richard Sandiford <richard.sandiford@arm.com>
318
319 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
320 AARCH64_OPND_SVE_PATTERN_SCALED.
321 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
322 * aarch64-opc.c (fields): Add a corresponding entry.
323 (set_multiplier_out_of_range_error): New function.
324 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
325 (operand_general_constraint_met_p): Handle
326 AARCH64_OPND_SVE_PATTERN_SCALED.
327 (print_register_offset_address): Use PRIi64 to print the
328 shift amount.
329 (aarch64_print_operand): Likewise. Handle
330 AARCH64_OPND_SVE_PATTERN_SCALED.
331 * aarch64-opc-2.c: Regenerate.
332 * aarch64-asm.h (ins_sve_scale): New inserter.
333 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
334 * aarch64-asm-2.c: Regenerate.
335 * aarch64-dis.h (ext_sve_scale): New inserter.
336 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
337 * aarch64-dis-2.c: Regenerate.
338
245d2e3f
RS		 3392016-09-21 Richard Sandiford <richard.sandiford@arm.com>
340
341 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
342 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
343 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
344 (FLD_SVE_prfop): Likewise.
345 * aarch64-opc.c: Include libiberty.h.
346 (aarch64_sve_pattern_array): New variable.
347 (aarch64_sve_prfop_array): Likewise.
348 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
349 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
350 AARCH64_OPND_SVE_PRFOP.
351 * aarch64-asm-2.c: Regenerate.
352 * aarch64-dis-2.c: Likewise.
353 * aarch64-opc-2.c: Likewise.
354
d50c751e
RS		 3552016-09-21 Richard Sandiford <richard.sandiford@arm.com>
356
357 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
358 AARCH64_OPND_QLF_P_[ZM].
359 (aarch64_print_operand): Print /z and /m where appropriate.
360
f11ad6bc
RS		 3612016-09-21 Richard Sandiford <richard.sandiford@arm.com>
362
363 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
364 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
365 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
366 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
367 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
368 * aarch64-opc.c (fields): Add corresponding entries here.
369 (operand_general_constraint_met_p): Check that SVE register lists
370 have the correct length. Check the ranges of SVE index registers.
371 Check for cases where p8-p15 are used in 3-bit predicate fields.
372 (aarch64_print_operand): Handle the new SVE operands.
373 * aarch64-opc-2.c: Regenerate.
374 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
375 * aarch64-asm.c (aarch64_ins_sve_index): New function.
376 (aarch64_ins_sve_reglist): Likewise.
377 * aarch64-asm-2.c: Regenerate.
378 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
379 * aarch64-dis.c (aarch64_ext_sve_index): New function.
380 (aarch64_ext_sve_reglist): Likewise.
381 * aarch64-dis-2.c: Regenerate.
382
0c608d6b
RS		 3832016-09-21 Richard Sandiford <richard.sandiford@arm.com>
384
385 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
386 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
387 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
388 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
389 tied operands.
390
01dbfe4c
RS		 3912016-09-21 Richard Sandiford <richard.sandiford@arm.com>
392
393 * aarch64-opc.c (get_offset_int_reg_name): New function.
394 (print_immediate_offset_address): Likewise.
395 (print_register_offset_address): Take the base and offset
396 registers as parameters.
397 (aarch64_print_operand): Update caller accordingly. Use
398 print_immediate_offset_address.
399
72e9f319
RS		 4002016-09-21 Richard Sandiford <richard.sandiford@arm.com>
401
402 * aarch64-opc.c (BANK): New macro.
403 (R32, R64): Take a register number as argument
404 (int_reg): Use BANK.
405
8a7f0c1b
RS		 4062016-09-21 Richard Sandiford <richard.sandiford@arm.com>
407
408 * aarch64-opc.c (print_register_list): Add a prefix parameter.
409 (aarch64_print_operand): Update accordingly.
410
aa2aa4c6
RS		 4112016-09-21 Richard Sandiford <richard.sandiford@arm.com>
412
413 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
414 for FPIMM.
415 * aarch64-asm.h (ins_fpimm): New inserter.
416 * aarch64-asm.c (aarch64_ins_fpimm): New function.
417 * aarch64-asm-2.c: Regenerate.
418 * aarch64-dis.h (ext_fpimm): New extractor.
419 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
420 (aarch64_ext_fpimm): New function.
421 * aarch64-dis-2.c: Regenerate.
422
b5464a68
RS		 4232016-09-21 Richard Sandiford <richard.sandiford@arm.com>
424
425 * aarch64-asm.c: Include libiberty.h.
426 (insert_fields): New function.
427 (aarch64_ins_imm): Use it.
428 * aarch64-dis.c (extract_fields): New function.
429 (aarch64_ext_imm): Use it.
430
42408347
RS		 4312016-09-21 Richard Sandiford <richard.sandiford@arm.com>
432
433 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
434 with an esize parameter.
435 (operand_general_constraint_met_p): Update accordingly.
436 Fix misindented code.
437 * aarch64-asm.c (aarch64_ins_limm): Update call to
438 aarch64_logical_immediate_p.
439
4989adac
RS		 4402016-09-21 Richard Sandiford <richard.sandiford@arm.com>
441
442 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
443
bd11d5d8
RS		 4442016-09-21 Richard Sandiford <richard.sandiford@arm.com>
445
446 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
447
f807f43d
CZ		 4482016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
449
450 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
451
fd486b63
PB		 4522016-09-14 Peter Bergner <bergner@vnet.ibm.com>
453
454 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
455 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
456 xor3>: Delete mnemonics.
457 <cp_abort>: Rename mnemonic from ...
458 <cpabort>: ...to this.
459 <setb>: Change to a X form instruction.
460 <sync>: Change to 1 operand form.
461 <copy>: Delete mnemonic.
462 <copy_first>: Rename mnemonic from ...
463 <copy>: ...to this.
464 <paste, paste.>: Delete mnemonics.
465 <paste_last>: Rename mnemonic from ...
466 <paste.>: ...to this.
467
dce08442
AK		 4682016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
469
470 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
471
952c3f51
AK		 4722016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
473
474 * s390-mkopc.c (main): Support alternate arch strings.
475
8b71537b
PS		 4762016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
477
478 * s390-opc.txt: Fix kmctr instruction type.
479
5b64d091
L		 4802016-09-07 H.J. Lu <hongjiu.lu@intel.com>
481
482 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
483 * i386-init.h: Regenerated.
484
7763838e
CM		 4852016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
486
487 * opcodes/arc-dis.c (print_insn_arc): Changed.
488
1b8b6532
JM		 4892016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
490
491 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
492 camellia_fl.
493
1a336194
TP		 4942016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
495
496 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
497 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
498 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
499
6b40c462
L		 5002016-08-24 H.J. Lu <hongjiu.lu@intel.com>
501
502 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
503 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
504 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
505 PREFIX_MOD_3_0FAE_REG_4.
506 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
507 PREFIX_MOD_3_0FAE_REG_4.
508 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
509 (cpu_flags): Add CpuPTWRITE.
510 * i386-opc.h (CpuPTWRITE): New.
511 (i386_cpu_flags): Add cpuptwrite.
512 * i386-opc.tbl: Add ptwrite instruction.
513 * i386-init.h: Regenerated.
514 * i386-tbl.h: Likewise.
515
ab548d2d
AK		 5162016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
517
518 * arc-dis.h: Wrap around in extern "C".
519
344bde0a
RS		 5202016-08-23 Richard Sandiford <richard.sandiford@arm.com>
521
522 * aarch64-tbl.h (V8_2_INSN): New macro.
523 (aarch64_opcode_table): Use it.
524
5ce912d8
RS		 5252016-08-23 Richard Sandiford <richard.sandiford@arm.com>
526
527 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
528 CORE_INSN, __FP_INSN and SIMD_INSN.
529
9d30b0bd
RS		 5302016-08-23 Richard Sandiford <richard.sandiford@arm.com>
531
532 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
533 (aarch64_opcode_table): Update uses accordingly.
534
dfdaec14
AJ		 5352016-07-25 Andrew Jenner <andrew@codesourcery.com>
536 Kwok Cheung Yeung <kcy@codesourcery.com>
537
538 opcodes/
539 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
540 'e_cmplwi' to 'e_cmpli' instead.
541 (OPVUPRT, OPVUPRT_MASK): Define.
542 (powerpc_opcodes): Add E200Z4 insns.
543 (vle_opcodes): Add context save/restore insns.
544
7bd374a4
MR		 5452016-07-27 Maciej W. Rozycki <macro@imgtec.com>
546
547 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
548 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
549 "j".
550
db18dbab
GM		 5512016-07-27 Graham Markall <graham.markall@embecosm.com>
552
553 * arc-nps400-tbl.h: Change block comments to GNU format.
554 * arc-dis.c: Add new globals addrtypenames,
555 addrtypenames_max, and addtypeunknown.
556 (get_addrtype): New function.
557 (print_insn_arc): Print colons and address types when
558 required.
559 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
560 define insert and extract functions for all address types.
561 (arc_operands): Add operands for colon and all address
562 types.
563 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
564 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
565 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
566 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
567 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
568 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
569
fecd57f9
L		 5702016-07-21 H.J. Lu <hongjiu.lu@intel.com>
571
572 * configure: Regenerated.
573
37fd5ef3
CZ		 5742016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
575
576 * arc-dis.c (skipclass): New structure.
577 (decodelist): New variable.
578 (is_compatible_p): New function.
579 (new_element): Likewise.
580 (skip_class_p): Likewise.
581 (find_format_from_table): Use skip_class_p function.
582 (find_format): Decode first the extension instructions.
583 (print_insn_arc): Select either ARCEM or ARCHS based on elf
584 e_flags.
585 (parse_option): New function.
586 (parse_disassembler_options): Likewise.
587 (print_arc_disassembler_options): Likewise.
588 (print_insn_arc): Use parse_disassembler_options function. Proper
589 select ARCv2 cpu variant.
590 * disassemble.c (disassembler_usage): Add ARC disassembler
591 options.
592
92281a5b
MR		 5932016-07-13 Maciej W. Rozycki <macro@imgtec.com>
594
595 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
596 annotation from the "nal" entry and reorder it beyond "bltzal".
597
6e7ced37
JM		 5982016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
599
600 * sparc-opc.c (ldtxa): New macro.
601 (sparc_opcodes): Use the macro defined above to add entries for
602 the LDTXA instructions.
603 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
604 instruction.
605
2f831b9a 6062016-07-07 James Bowman <james.bowman@ftdichip.com>
607
608 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
609 and "jmpc".
610
c07315e0
JB		 6112016-07-01 Jan Beulich <jbeulich@suse.com>
612
613 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
614 (movzb): Adjust to cover all permitted suffixes.
615 (movzw): New.
616 * i386-tbl.h: Re-generate.
617
9243100a
JB		 6182016-07-01 Jan Beulich <jbeulich@suse.com>
619
620 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
621 (lgdt): Remove Tbyte from non-64-bit variant.
622 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
623 xsaves64, xsavec64): Remove Disp16.
624 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
625 Remove Disp32S from non-64-bit variants. Remove Disp16 from
626 64-bit variants.
627 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
628 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
629 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
630 64-bit variants.
631 * i386-tbl.h: Re-generate.
632
8325cc63
JB		 6332016-07-01 Jan Beulich <jbeulich@suse.com>
634
635 * i386-opc.tbl (xlat): Remove RepPrefixOk.
636 * i386-tbl.h: Re-generate.
637
838441e4
YQ		 6382016-06-30 Yao Qi <yao.qi@linaro.org>
639
640 * arm-dis.c (print_insn): Fix typo in comment.
641
dab26bf4
RS		 6422016-06-28 Richard Sandiford <richard.sandiford@arm.com>
643
644 * aarch64-opc.c (operand_general_constraint_met_p): Check the
645 range of ldst_elemlist operands.
646 (print_register_list): Use PRIi64 to print the index.
647 (aarch64_print_operand): Likewise.
648
5703197e
TS		 6492016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
650
651 * mcore-opc.h: Remove sentinal.
652 * mcore-dis.c (print_insn_mcore): Adjust.
653
ce440d63
GM		 6542016-06-23 Graham Markall <graham.markall@embecosm.com>
655
656 * arc-opc.c: Correct description of availability of NPS400
657 features.
658
6fd3a02d
PB		 6592016-06-22 Peter Bergner <bergner@vnet.ibm.com>
660
661 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
662 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
663 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
664 xor3>: New mnemonics.
665 <setb>: Change to a VX form instruction.
666 (insert_sh6): Add support for rldixor.
667 (extract_sh6): Likewise.
668
6b477896
TS		 6692016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
670
671 * arc-ext.h: Wrap in extern C.
672
bdd582db
GM		 6732016-06-21 Graham Markall <graham.markall@embecosm.com>
674
675 * arc-dis.c (arc_insn_length): Add comment on instruction length.
676 Use same method for determining instruction length on ARC700 and
677 NPS-400.
678 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
679 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
680 with the NPS400 subclass.
681 * arc-opc.c: Likewise.
682
96074adc
JM		 6832016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
684
685 * sparc-opc.c (rdasr): New macro.
686 (wrasr): Likewise.
687 (rdpr): Likewise.
688 (wrpr): Likewise.
689 (rdhpr): Likewise.
690 (wrhpr): Likewise.
691 (sparc_opcodes): Use the macros above to fix and expand the
692 definition of read/write instructions from/to
693 asr/privileged/hyperprivileged instructions.
694 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
695 %hva_mask_nz. Prefer softint_set and softint_clear over
696 set_softint and clear_softint.
697 (print_insn_sparc): Support %ver in Rd.
698
7a10c22f
JM		 6992016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
700
701 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
702 architecture according to the hardware capabilities they require.
703
4f26fb3a
JM		 7042016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
705
706 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
707 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
708 bfd_mach_sparc_v9{c,d,e,v,m}.
709 * sparc-opc.c (MASK_V9C): Define.
710 (MASK_V9D): Likewise.
711 (MASK_V9E): Likewise.
712 (MASK_V9V): Likewise.
713 (MASK_V9M): Likewise.
714 (v6): Add MASK_V9{C,D,E,V,M}.
715 (v6notlet): Likewise.
716 (v7): Likewise.
717 (v8): Likewise.
718 (v9): Likewise.
719 (v9andleon): Likewise.
720 (v9a): Likewise.
721 (v9b): Likewise.
722 (v9c): Define.
723 (v9d): Likewise.
724 (v9e): Likewise.
725 (v9v): Likewise.
726 (v9m): Likewise.
727 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
728
3ee6e4fb
NC		 7292016-06-15 Nick Clifton <nickc@redhat.com>
730
731 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
732 constants to match expected behaviour.
733 (nds32_parse_opcode): Likewise. Also for whitespace.
734
02f3be19
AB		 7352016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
736
737 * arc-opc.c (extract_rhv1): Extract value from insn.
738
6f9f37ed 7392016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 740
741 * arc-nps400-tbl.h: Add ldbit instruction.
742 * arc-opc.c: Add flag classes required for ldbit.
743
6f9f37ed 7442016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 745
746 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
747 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
748 support the above instructions.
749
6f9f37ed 7502016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 751
752 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
753 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
754 csma, cbba, zncv, and hofs.
755 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
756 support the above instructions.
757
7582016-06-06 Graham Markall <graham.markall@embecosm.com>
759
760 * arc-nps400-tbl.h: Add andab and orab instructions.
761
7622016-06-06 Graham Markall <graham.markall@embecosm.com>
763
764 * arc-nps400-tbl.h: Add addl-like instructions.
765
7662016-06-06 Graham Markall <graham.markall@embecosm.com>
767
768 * arc-nps400-tbl.h: Add mxb and imxb instructions.
769
7702016-06-06 Graham Markall <graham.markall@embecosm.com>
771
772 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
773 instructions.
774
b2cc3f6f
AK		 7752016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
776
777 * s390-dis.c (option_use_insn_len_bits_p): New file scope
778 variable.
779 (init_disasm): Handle new command line option "insnlength".
780 (print_s390_disassembler_options): Mention new option in help
781 output.
782 (print_insn_s390): Use the encoded insn length when dumping
783 unknown instructions.
784
1857fe72
DC		 7852016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
786
787 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
788 to the address and set as symbol address for LDS/ STS immediate operands.
789
14b57c7c
AM		 7902016-06-07 Alan Modra <amodra@gmail.com>
791
792 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
793 cpu for "vle" to e500.
794 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
795 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
796 (PPCNONE): Delete, substitute throughout.
797 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
798 except for major opcode 4 and 31.
799 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
800
4d1464f2
MW		 8012016-06-07 Matthew Wahab <matthew.wahab@arm.com>
802
803 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
804 ARM_EXT_RAS in relevant entries.
805
026122a6
PB		 8062016-06-03 Peter Bergner <bergner@vnet.ibm.com>
807
808 PR binutils/20196
809 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
810 opcodes for E6500.
811
07f5af7d
L		 8122016-06-03 H.J. Lu <hongjiu.lu@intel.com>
813
814 PR binutis/18386
815 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
816 (indir_v_mode): New.
817 Add comments for '&'.
818 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
819 (putop): Handle '&'.
820 (intel_operand_size): Handle indir_v_mode.
821 (OP_E_register): Likewise.
822 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
823 64-bit indirect call/jmp for AMD64.
824 * i386-tbl.h: Regenerated
825
4eb6f892
AB		 8262016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
827
828 * arc-dis.c (struct arc_operand_iterator): New structure.
829 (find_format_from_table): All the old content from find_format,
830 with some minor adjustments, and parameter renaming.
831 (find_format_long_instructions): New function.
832 (find_format): Rewritten.
833 (arc_insn_length): Add LSB parameter.
834 (extract_operand_value): New function.
835 (operand_iterator_next): New function.
836 (print_insn_arc): Use new functions to find opcode, and iterator
837 over operands.
838 * arc-opc.c (insert_nps_3bit_dst_short): New function.
839 (extract_nps_3bit_dst_short): New function.
840 (insert_nps_3bit_src2_short): New function.
841 (extract_nps_3bit_src2_short): New function.
842 (insert_nps_bitop1_size): New function.
843 (extract_nps_bitop1_size): New function.
844 (insert_nps_bitop2_size): New function.
845 (extract_nps_bitop2_size): New function.
846 (insert_nps_bitop_mod4_msb): New function.
847 (extract_nps_bitop_mod4_msb): New function.
848 (insert_nps_bitop_mod4_lsb): New function.
849 (extract_nps_bitop_mod4_lsb): New function.
850 (insert_nps_bitop_dst_pos3_pos4): New function.
851 (extract_nps_bitop_dst_pos3_pos4): New function.
852 (insert_nps_bitop_ins_ext): New function.
853 (extract_nps_bitop_ins_ext): New function.
854 (arc_operands): Add new operands.
855 (arc_long_opcodes): New global array.
856 (arc_num_long_opcodes): New global.
857 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
858
1fe0971e
TS		 8592016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
860
861 * nds32-asm.h: Add extern "C".
862 * sh-opc.h: Likewise.
863
315f180f
GM		 8642016-06-01 Graham Markall <graham.markall@embecosm.com>
865
866 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
867 0,b,limm to the rflt instruction.
868
a2b5fccc
TS		 8692016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
870
871 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
872 constant.
873
0cbd0046
L		 8742016-05-29 H.J. Lu <hongjiu.lu@intel.com>
875
876 PR gas/20145
877 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
878 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
879 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
880 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
881 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
882 * i386-init.h: Regenerated.
883
1848e567
L		 8842016-05-27 H.J. Lu <hongjiu.lu@intel.com>
885
886 PR gas/20145
887 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
888 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
889 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
890 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
891 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
892 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
893 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
894 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
895 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
896 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
897 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
898 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
899 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
900 CpuRegMask for AVX512.
901 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
902 and CpuRegMask.
903 (set_bitfield_from_cpu_flag_init): New function.
904 (set_bitfield): Remove const on f. Call
905 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
906 * i386-opc.h (CpuRegMMX): New.
907 (CpuRegXMM): Likewise.
908 (CpuRegYMM): Likewise.
909 (CpuRegZMM): Likewise.
910 (CpuRegMask): Likewise.
911 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
912 and cpuregmask.
913 * i386-init.h: Regenerated.
914 * i386-tbl.h: Likewise.
915
e92bae62
L		 9162016-05-27 H.J. Lu <hongjiu.lu@intel.com>
917
918 PR gas/20154
919 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
920 (opcode_modifiers): Add AMD64 and Intel64.
921 (main): Properly verify CpuMax.
922 * i386-opc.h (CpuAMD64): Removed.
923 (CpuIntel64): Likewise.
924 (CpuMax): Set to CpuNo64.
925 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
926 (AMD64): New.
927 (Intel64): Likewise.
928 (i386_opcode_modifier): Add amd64 and intel64.
929 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
930 on call and jmp.
931 * i386-init.h: Regenerated.
932 * i386-tbl.h: Likewise.
933
e89c5eaa
L		 9342016-05-27 H.J. Lu <hongjiu.lu@intel.com>
935
936 PR gas/20154
937 * i386-gen.c (main): Fail if CpuMax is incorrect.
938 * i386-opc.h (CpuMax): Set to CpuIntel64.
939 * i386-tbl.h: Regenerated.
940
77d66e7b
NC		 9412016-05-27 Nick Clifton <nickc@redhat.com>
942
943 PR target/20150
944 * msp430-dis.c (msp430dis_read_two_bytes): New function.
945 (msp430dis_opcode_unsigned): New function.
946 (msp430dis_opcode_signed): New function.
947 (msp430_singleoperand): Use the new opcode reading functions.
948 Only disassenmble bytes if they were successfully read.
949 (msp430_doubleoperand): Likewise.
950 (msp430_branchinstr): Likewise.
951 (msp430x_callx_instr): Likewise.
952 (print_insn_msp430): Check that it is safe to read bytes before
953 attempting disassembly. Use the new opcode reading functions.
954
19dfcc89
PB		 9552016-05-26 Peter Bergner <bergner@vnet.ibm.com>
956
957 * ppc-opc.c (CY): New define. Document it.
958 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
959
f3ad7637
L		 9602016-05-25 H.J. Lu <hongjiu.lu@intel.com>
961
962 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
963 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
964 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
965 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
966 CPU_ANY_AVX_FLAGS.
967 * i386-init.h: Regenerated.
968
f1360d58
L		 9692016-05-25 H.J. Lu <hongjiu.lu@intel.com>
970
971 PR gas/20141
972 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
973 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
974 * i386-init.h: Regenerated.
975
293f5f65
L		 9762016-05-25 H.J. Lu <hongjiu.lu@intel.com>
977
978 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
979 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
980 * i386-init.h: Regenerated.
981
d9eca1df
CZ		 9822016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
983
984 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
985 information.
986 (print_insn_arc): Set insn_type information.
987 * arc-opc.c (C_CC): Add F_CLASS_COND.
988 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
989 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
990 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
991 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
992 (brne, brne_s, jeq_s, jne_s): Likewise.
993
87789e08
CZ		 9942016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
995
996 * arc-tbl.h (neg): New instruction variant.
997
c810e0b8
CZ		 9982016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
999
1000 * arc-dis.c (find_format, find_format, get_auxreg)
1001 (print_insn_arc): Changed.
1002 * arc-ext.h (INSERT_XOP): Likewise.
1003
3d207518
TS		 10042016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1005
1006 * tic54x-dis.c (sprint_mmr): Adjust.
1007 * tic54x-opc.c: Likewise.
1008
514e58b7
AM		 10092016-05-19 Alan Modra <amodra@gmail.com>
1010
1011 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1012
e43de63c
AM		 10132016-05-19 Alan Modra <amodra@gmail.com>
1014
1015 * ppc-opc.c: Formatting.
1016 (NSISIGNOPT): Define.
1017 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1018
1401d2fe
MR		 10192016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1020
1021 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1022 replacing references to `micromips_ase' throughout.
1023 (_print_insn_mips): Don't use file-level microMIPS annotation to
1024 determine the disassembly mode with the symbol table.
1025
1178da44
PB		 10262016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1027
1028 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1029
8f4f9071
MF		 10302016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1031
1032 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1033 mips64r6.
1034 * mips-opc.c (D34): New macro.
1035 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1036
8bc52696
AF		 10372016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1038
1039 * i386-dis.c (prefix_table): Add RDPID instruction.
1040 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1041 (cpu_flags): Add RDPID bitfield.
1042 * i386-opc.h (enum): Add RDPID element.
1043 (i386_cpu_flags): Add RDPID field.
1044 * i386-opc.tbl: Add RDPID instruction.
1045 * i386-init.h: Regenerate.
1046 * i386-tbl.h: Regenerate.
1047
39d911fc
TP		 10482016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1049
1050 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1051 branch type of a symbol.
1052 (print_insn): Likewise.
1053
16a1fa25
TP		 10542016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1055
1056 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1057 Mainline Security Extensions instructions.
1058 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1059 Extensions instructions.
1060 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1061 instructions.
1062 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1063 special registers.
1064
d751b79e
JM		 10652016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1066
1067 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1068
945e0f82
CZ		 10692016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1070
1071 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1072 (arcExtMap_genOpcode): Likewise.
1073 * arc-opc.c (arg_32bit_rc): Define new variable.
1074 (arg_32bit_u6): Likewise.
1075 (arg_32bit_limm): Likewise.
1076
20f55f38
SN		 10772016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1078
1079 * aarch64-gen.c (VERIFIER): Define.
1080 * aarch64-opc.c (VERIFIER): Define.
1081 (verify_ldpsw): Use static linkage.
1082 * aarch64-opc.h (verify_ldpsw): Remove.
1083 * aarch64-tbl.h: Use VERIFIER for verifiers.
1084
4bd13cde
NC		 10852016-04-28 Nick Clifton <nickc@redhat.com>
1086
1087 PR target/19722
1088 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1089 * aarch64-opc.c (verify_ldpsw): New function.
1090 * aarch64-opc.h (verify_ldpsw): New prototype.
1091 * aarch64-tbl.h: Add initialiser for verifier field.
1092 (LDPSW): Set verifier to verify_ldpsw.
1093
c0f92bf9
L		 10942016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1095
1096 PR binutils/19983
1097 PR binutils/19984
1098 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1099 smaller than address size.
1100
e6c7cdec
TS		 11012016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1102
1103 * alpha-dis.c: Regenerate.
1104 * crx-dis.c: Likewise.
1105 * disassemble.c: Likewise.
1106 * epiphany-opc.c: Likewise.
1107 * fr30-opc.c: Likewise.
1108 * frv-opc.c: Likewise.
1109 * ip2k-opc.c: Likewise.
1110 * iq2000-opc.c: Likewise.
1111 * lm32-opc.c: Likewise.
1112 * lm32-opinst.c: Likewise.
1113 * m32c-opc.c: Likewise.
1114 * m32r-opc.c: Likewise.
1115 * m32r-opinst.c: Likewise.
1116 * mep-opc.c: Likewise.
1117 * mt-opc.c: Likewise.
1118 * or1k-opc.c: Likewise.
1119 * or1k-opinst.c: Likewise.
1120 * tic80-opc.c: Likewise.
1121 * xc16x-opc.c: Likewise.
1122 * xstormy16-opc.c: Likewise.
1123
537aefaf
AB		 11242016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1125
1126 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1127 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1128 calcsd, and calcxd instructions.
1129 * arc-opc.c (insert_nps_bitop_size): Delete.
1130 (extract_nps_bitop_size): Delete.
1131 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1132 (extract_nps_qcmp_m3): Define.
1133 (extract_nps_qcmp_m2): Define.
1134 (extract_nps_qcmp_m1): Define.
1135 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1136 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1137 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1138 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1139 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1140 NPS_QCMP_M3.
1141
c8f785f2
AB		 11422016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1143
1144 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1145
6fd8e7c2
L		 11462016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1147
1148 * Makefile.in: Regenerated with automake 1.11.6.
1149 * aclocal.m4: Likewise.
1150
4b0c052e
AB		 11512016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1152
1153 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1154 instructions.
1155 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1156 (extract_nps_cmem_uimm16): New function.
1157 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1158
cb040366
AB		 11592016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1160
1161 * arc-dis.c (arc_insn_length): New function.
1162 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1163 (find_format): Change insnLen parameter to unsigned.
1164
accc0180
NC		 11652016-04-13 Nick Clifton <nickc@redhat.com>
1166
1167 PR target/19937
1168 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1169 the LD.B and LD.BU instructions.
1170
f36e33da
CZ		 11712016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1172
1173 * arc-dis.c (find_format): Check for extension flags.
1174 (print_flags): New function.
1175 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1176 .extAuxRegister.
1177 * arc-ext.c (arcExtMap_coreRegName): Use
1178 LAST_EXTENSION_CORE_REGISTER.
1179 (arcExtMap_coreReadWrite): Likewise.
1180 (dump_ARC_extmap): Update printing.
1181 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1182 (arc_aux_regs): Add cpu field.
1183 * arc-regs.h: Add cpu field, lower case name aux registers.
1184
1c2e355e
CZ		 11852016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1186
1187 * arc-tbl.h: Add rtsc, sleep with no arguments.
1188
b99747ae
CZ		 11892016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1190
1191 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1192 Initialize.
1193 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1194 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1195 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1196 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1197 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1198 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1199 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1200 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1201 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1202 (arc_opcode arc_opcodes): Null terminate the array.
1203 (arc_num_opcodes): Remove.
1204 * arc-ext.h (INSERT_XOP): Define.
1205 (extInstruction_t): Likewise.
1206 (arcExtMap_instName): Delete.
1207 (arcExtMap_insn): New function.
1208 (arcExtMap_genOpcode): Likewise.
1209 * arc-ext.c (ExtInstruction): Remove.
1210 (create_map): Zero initialize instruction fields.
1211 (arcExtMap_instName): Remove.
1212 (arcExtMap_insn): New function.
1213 (dump_ARC_extmap): More info while debuging.
1214 (arcExtMap_genOpcode): New function.
1215 * arc-dis.c (find_format): New function.
1216 (print_insn_arc): Use find_format.
1217 (arc_get_disassembler): Enable dump_ARC_extmap only when
1218 debugging.
1219
92708cec
MR		 12202016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1221
1222 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1223 instruction bits out.
1224
a42a4f84
AB		 12252016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1226
1227 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1228 * arc-opc.c (arc_flag_operands): Add new flags.
1229 (arc_flag_classes): Add new classes.
1230
1328504b
AB		 12312016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1232
1233 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1234
820f03ff
AB		 12352016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1236
1237 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1238 encode1, rflt, crc16, and crc32 instructions.
1239 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1240 (arc_flag_classes): Add C_NPS_R.
1241 (insert_nps_bitop_size_2b): New function.
1242 (extract_nps_bitop_size_2b): Likewise.
1243 (insert_nps_bitop_uimm8): Likewise.
1244 (extract_nps_bitop_uimm8): Likewise.
1245 (arc_operands): Add new operand entries.
1246
8ddf6b2a
CZ		 12472016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1248
b99747ae
CZ		 1249 * arc-regs.h: Add a new subclass field. Add double assist
1250 accumulator register values.
1251 * arc-tbl.h: Use DPA subclass to mark the double assist
1252 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1253 * arc-opc.c (RSP): Define instead of SP.
1254 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1255
589a7d88
JW		 12562016-04-05 Jiong Wang <jiong.wang@arm.com>
1257
1258 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1259
0a191de9 12602016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1261
1262 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1263 NPS_R_SRC1.
1264
0a106562
AB		 12652016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1266
1267 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1268 issues. No functional changes.
1269
bd05ac5f
CZ		 12702016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1271
b99747ae
CZ		 1272 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1273 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1274 (RTT): Remove duplicate.
1275 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1276 (PCT_CONFIG*): Remove.
1277 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1278
9885948f
CZ		 12792016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1280
b99747ae 1281 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1282
f2dd8838
CZ		 12832016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1284
b99747ae
CZ		 1285 * arc-tbl.h (invld07): Remove.
1286 * arc-ext-tbl.h: New file.
1287 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1288 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1289
0d2f91fe
JK		 12902016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1291
1292 Fix -Wstack-usage warnings.
1293 * aarch64-dis.c (print_operands): Substitute size.
1294 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1295
a6b71f42
JM		 12962016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1297
1298 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1299 to get a proper diagnostic when an invalid ASR register is used.
1300
9780e045
NC		 13012016-03-22 Nick Clifton <nickc@redhat.com>
1302
1303 * configure: Regenerate.
1304
e23e8ebe
AB		 13052016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1306
1307 * arc-nps400-tbl.h: New file.
1308 * arc-opc.c: Add top level comment.
1309 (insert_nps_3bit_dst): New function.
1310 (extract_nps_3bit_dst): New function.
1311 (insert_nps_3bit_src2): New function.
1312 (extract_nps_3bit_src2): New function.
1313 (insert_nps_bitop_size): New function.
1314 (extract_nps_bitop_size): New function.
1315 (arc_flag_operands): Add nps400 entries.
1316 (arc_flag_classes): Add nps400 entries.
1317 (arc_operands): Add nps400 entries.
1318 (arc_opcodes): Add nps400 include.
1319
1ae8ab47
AB		 13202016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1321
1322 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1323 the new class enum values.
1324
8699fc3e
AB		 13252016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1326
1327 * arc-dis.c (print_insn_arc): Handle nps400.
1328
24740d83
AB		 13292016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1330
1331 * arc-opc.c (BASE): Delete.
1332
8678914f
NC		 13332016-03-18 Nick Clifton <nickc@redhat.com>
1334
1335 PR target/19721
1336 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1337 of MOV insn that aliases an ORR insn.
1338
cc933301
JW		 13392016-03-16 Jiong Wang <jiong.wang@arm.com>
1340
1341 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1342
f86f5863
TS		 13432016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1344
1345 * mcore-opc.h: Add const qualifiers.
1346 * microblaze-opc.h (struct op_code_struct): Likewise.
1347 * sh-opc.h: Likewise.
1348 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1349 (tic4x_print_op): Likewise.
1350
62de1c63
AM		 13512016-03-02 Alan Modra <amodra@gmail.com>
1352
d11698cd 1353 * or1k-desc.h: Regenerate.
62de1c63 1354 * fr30-ibld.c: Regenerate.
c697cf0b 1355 * rl78-decode.c: Regenerate.
62de1c63 1356
020efce5
NC		 13572016-03-01 Nick Clifton <nickc@redhat.com>
1358
1359 PR target/19747
1360 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1361
b0c11777
RL		 13622016-02-24 Renlin Li <renlin.li@arm.com>
1363
1364 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1365 (print_insn_coprocessor): Support fp16 instructions.
1366
3e309328
RL		 13672016-02-24 Renlin Li <renlin.li@arm.com>
1368
1369 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1370 vminnm, vrint(mpna).
1371
8afc7bea
RL		 13722016-02-24 Renlin Li <renlin.li@arm.com>
1373
1374 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1375 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1376
4fd7268a
L		 13772016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1378
1379 * i386-dis.c (print_insn): Parenthesize expression to prevent
1380 truncated addresses.
1381 (OP_J): Likewise.
1382
4670103e
CZ		 13832016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1384 Janek van Oirschot <jvanoirs@synopsys.com>
1385
b99747ae
CZ		 1386 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1387 variable.
4670103e 1388
c1d9289f
NC		 13892016-02-04 Nick Clifton <nickc@redhat.com>
1390
1391 PR target/19561
1392 * msp430-dis.c (print_insn_msp430): Add a special case for
1393 decoding an RRC instruction with the ZC bit set in the extension
1394 word.
1395
a143b004
AB		 13962016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1397
1398 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1399 * epiphany-ibld.c: Regenerate.
1400 * fr30-ibld.c: Regenerate.
1401 * frv-ibld.c: Regenerate.
1402 * ip2k-ibld.c: Regenerate.
1403 * iq2000-ibld.c: Regenerate.
1404 * lm32-ibld.c: Regenerate.
1405 * m32c-ibld.c: Regenerate.
1406 * m32r-ibld.c: Regenerate.
1407 * mep-ibld.c: Regenerate.
1408 * mt-ibld.c: Regenerate.
1409 * or1k-ibld.c: Regenerate.
1410 * xc16x-ibld.c: Regenerate.
1411 * xstormy16-ibld.c: Regenerate.
1412
b89807c6
AB		 14132016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1414
1415 * epiphany-dis.c: Regenerated from latest cpu files.
1416
d8c823c8
MM		 14172016-02-01 Michael McConville <mmcco@mykolab.com>
1418
1419 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1420 test bit.
1421
5bc5ae88
RL		 14222016-01-25 Renlin Li <renlin.li@arm.com>
1423
1424 * arm-dis.c (mapping_symbol_for_insn): New function.
1425 (find_ifthen_state): Call mapping_symbol_for_insn().
1426
0bff6e2d
MW		 14272016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1428
1429 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1430 of MSR UAO immediate operand.
1431
100b4f2e
MR		 14322016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1433
1434 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1435 instruction support.
1436
5c14705f
AM		 14372016-01-17 Alan Modra <amodra@gmail.com>
1438
1439 * configure: Regenerate.
1440
4d82fe66
NC		 14412016-01-14 Nick Clifton <nickc@redhat.com>
1442
1443 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1444 instructions that can support stack pointer operations.
1445 * rl78-decode.c: Regenerate.
1446 * rl78-dis.c: Fix display of stack pointer in MOVW based
1447 instructions.
1448
651657fa
MW		 14492016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1450
1451 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1452 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1453 erxtatus_el1 and erxaddr_el1.
1454
105bde57
MW		 14552016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1456
1457 * arm-dis.c (arm_opcodes): Add "esb".
1458 (thumb_opcodes): Likewise.
1459
afa8d405
PB		 14602016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1461
1462 * ppc-opc.c <xscmpnedp>: Delete.
1463 <xvcmpnedp>: Likewise.
1464 <xvcmpnedp.>: Likewise.
1465 <xvcmpnesp>: Likewise.
1466 <xvcmpnesp.>: Likewise.
1467
83c3256e
AS		 14682016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1469
1470 PR gas/13050
1471 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1472 addition to ISA_A.
1473
6f2750fe
AM		 14742016-01-01 Alan Modra <amodra@gmail.com>
1475
1476 Update year range in copyright notice of all files.
1477
3499769a
AM		 1478For older changes see ChangeLog-2015
1479\f
1480Copyright (C) 2016 Free Software Foundation, Inc.
1481
1482Copying and distribution of this file, with or without modification,
1483are permitted in any medium without royalty provided the copyright
1484notice and this notice are preserved.
1485
1486Local Variables:
1487mode: change-log
1488left-margin: 8
1489fill-column: 74
1490version-control: never
1491End:
GDB Binutils - Deliverables
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