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* mips16-opc.c (mips16_opcodes): Add the MIPS16e jalrc/jrc
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
dd8b7c22
DU		 12005-08-23 David Ung <davidu@mips.com>
2
3 * mips16-opc.c (mips16_opcodes): Add the MIPS16e jalrc/jrc
4 instructions to the table.
5
c17ae8a2
AM		 62005-08-18 Alan Modra <amodra@bigpond.net.au>
7
848cf006 8 * a29k-dis.c: Delete.
c17ae8a2
AM		 9 * Makefile.am: Remove a29k support.
10 * configure.in: Likewise.
11 * disassemble.c: Likewise.
12 * Makefile.in: Regenerate.
13 * configure: Regenerate.
14 * po/POTFILES.in: Regenerate.
15
36ae0db3
DJ		 162005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
17
18 * ppc-dis.c (powerpc_dialect): Handle e300.
19 (print_ppc_disassembler_options): Likewise.
20 * ppc-opc.c (PPCE300): Define.
21 (powerpc_opcodes): Mark icbt as available for the e300.
22
63a3357b
DA		 232005-08-13 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
24
25 * hppa-dis.c (print_insn_hppa): Don't print '%' before register names.
26 Use "rp" instead of "%r2" in "b,l" insns.
27
ad101263
MS		 282005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
29
30 * s390-dis.c (print_insn_s390): Print unsigned operands with %u.
31 * s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z9-109.
32 (main): Likewise.
33 * s390-opc.c (I32_16, U32_16, M_16): Add defines 32 bit immediates
34 and 4 bit optional masks.
35 (INSTR_RIL_RI, INSTR_RIL_RU, INSTR_RRF_M0RR, INSTR_RSE_CCRD,
36 INSTR_RSY_CCRD, INSTR_SSF_RRDRD): Add new instruction formats.
37 (MASK_RIL_RI, MASK_RIL_RU, MASK_RRF_M0RR, MASK_RSE_CCRD,
38 MASK_RSY_CCRD, MASK_SSF_RRDRD): Likewise.
39 (s390_opformats): Likewise.
40 * s390-opc.txt: Add new instructions for cpu type z9-109.
41
f1fa1093
DA		 422005-08-05 John David Anglin <dave.anglin@nrc-crnc.gc.ca>
43
44 * hppa-dis.c (print_insn_hppa): Prefix 21-bit values with "L%".
45
e9f89963
PB		 462005-07-29 Paul Brook <paul@codesourcery.com>
47
48 * arm-dis.c: Fix disassebly of thumb2 writeback addressing modes.
49
92e90b6e
PB		 502005-07-29 Paul Brook <paul@codesourcery.com>
51
52 * arm-dis.c (thumb32_opc): Fix addressing mode for tbh.
53 (print_insn_thumb32): Fix decoding of thumb2 'I' operands.
54
fd54057a
DD		 552005-07-25 DJ Delorie <dj@redhat.com>
56
57 * m32c-asm.c Regenerate.
58 * m32c-dis.c Regenerate.
59
760c0f6a
DD		 602005-07-20 DJ Delorie <dj@redhat.com>
61
62 * disassemble.c (disassemble_init_for_target): M32C ISAs are
63 enums, so convert them to bit masks, which attributes are.
64
85da3a56
NC		 652005-07-18 Nick Clifton <nickc@redhat.com>
66
67 * configure.in: Restore alpha ordering to list of arches.
68 * configure: Regenerate.
69 * disassemble.c: Restore alpha ordering to list of arches.
70
712005-07-18 Nick Clifton <nickc@redhat.com>
72
73 * m32c-asm.c: Regenerate.
74 * m32c-desc.c: Regenerate.
75 * m32c-desc.h: Regenerate.
76 * m32c-dis.c: Regenerate.
77 * m32c-ibld.h: Regenerate.
78 * m32c-opc.c: Regenerate.
79 * m32c-opc.h: Regenerate.
80
22cbf2e7
L		 812005-07-18 H.J. Lu <hongjiu.lu@intel.com>
82
83 * i386-dis.c (PNI_Fixup): Update comment.
84 (VMX_Fixup): Properly handle the suffix check.
85
0aea0460
DA		 862005-07-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
87
88 * hppa-dis.c (print_insn_hppa): Add space after 'w' in wide-mode
89 mfctl disassembly.
90
0f82ff91
AM		 912005-07-16 Alan Modra <amodra@bigpond.net.au>
92
93 * Makefile.am: Run "make dep-am".
94 (stamp-m32c): Fix cpu dependencies.
95 * Makefile.in: Regenerate.
96 * ip2k-dis.c: Regenerate.
97
90700ea2
L		 982007-07-15 H.J. Lu <hongjiu.lu@intel.com>
99
100 * i386-dis.c (OP_VMX): New. Handle Intel VMX Instructions.
101 (VMX_Fixup): New. Fix up Intel VMX Instructions.
102 (Em): New.
103 (Gm): New.
104 (VM): New.
105 (dis386_twobyte): Updated entries 0x78 and 0x79.
106 (twobyte_has_modrm): Likewise.
107 (grps): Use OP_VMX in the "sgdtIQ" entry. Updated GRP9.
108 (OP_G): Handle m_mode.
109
49f58d10
JB		 1102005-07-14 Jim Blandy <jimb@redhat.com>
111
112 Add support for the Renesas M32C and M16C.
113 * m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c: New.
114 * m32c-desc.h, m32c-opc.h: New.
115 * Makefile.am (HFILES): List m32c-desc.h and m32c-opc.h.
116 (CFILES): List m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c,
117 m32c-opc.c.
118 (ALL_MACHINES): List m32c-asm.lo, m32c-desc.lo, m32c-dis.lo,
119 m32c-ibld.lo, m32c-opc.lo.
120 (CLEANFILES): List stamp-m32c.
121 (M32C_DEPS): List stamp-m32c, if CGEN_MAINT.
122 (CGEN_CPUS): Add m32c.
123 (m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c)
124 (m32c-desc.h, m32c-opc.h): Depend on M32C_DEPS.
125 (m32c_opc_h): New variable.
126 (stamp-m32c, m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo)
127 (m32c-opc.lo): New rules.
128 * Makefile.in: Regenerated.
129 * configure.in: Add case for bfd_m32c_arch.
130 * configure: Regenerated.
131 * disassemble.c (ARCH_m32c): New.
132 [ARCH_m32c]: #include "m32c-desc.h".
133 (disassembler) [ARCH_m32c]: Add case for bfd_arch_m32c.
134 (disassemble_init_for_target) [ARCH_m32c]: Same.
135
136 * cgen-ops.h, cgen-types.h: New files.
137 * Makefile.am (HFILES): List them.
138 * Makefile.in: Regenerated.
139
0fd3a477
JW		 1402005-07-07 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
141
142 * arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c,
143 d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c,
144 ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c,
145 m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c,
146 ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c,
147 v850-dis.c: Fix format bugs.
148 * ia64-gen.c (fail, warn): Add format attribute.
149 * or32-opc.c (debug): Likewise.
150
22f8fcbd
NC		 1512005-07-07 Khem Raj <kraj@mvista.com>
152
153 * arm-dis.c (opcode32 arm_opcodes): Fix ARM VFP fadds instruction
154 disassembly pattern.
155
d125c27b
AM		 1562005-07-06 Alan Modra <amodra@bigpond.net.au>
157
158 * Makefile.am (stamp-m32r): Fix path to cpu files.
159 (stamp-m32r, stamp-iq2000): Likewise.
160 * Makefile.in: Regenerate.
161 * m32r-asm.c: Regenerate.
162 * po/POTFILES.in: Remove arm-opc.h. Add ms1-asm.c, ms1-desc.c,
163 ms1-desc.h, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h.
164
3ec2b351
NC		 1652005-07-05 Nick Clifton <nickc@redhat.com>
166
167 * iq2000-asm.c: Regenerate.
168 * ms1-asm.c: Regenerate.
169
30123838
JB		 1702005-07-05 Jan Beulich <jbeulich@novell.com>
171
172 * i386-dis.c (SVME_Fixup): New.
173 (grps): Use it for the lidt entry.
174 (PNI_Fixup): Call OP_M rather than OP_E.
175 (INVLPG_Fixup): Likewise.
176
b0eec63e
L		 1772005-07-04 H.J. Lu <hongjiu.lu@intel.com>
178
179 * tic30-dis.c (cnvt_tmsfloat_ieee): Use HUGE_VALF if defined.
180
47b0e7ad
NC		 1812005-07-01 Nick Clifton <nickc@redhat.com>
182
183 * a29k-dis.c: Update to ISO C90 style function declarations and
184 fix formatting.
185 * alpha-opc.c: Likewise.
186 * arc-dis.c: Likewise.
187 * arc-opc.c: Likewise.
188 * avr-dis.c: Likewise.
189 * cgen-asm.in: Likewise.
190 * cgen-dis.in: Likewise.
191 * cgen-ibld.in: Likewise.
192 * cgen-opc.c: Likewise.
193 * cris-dis.c: Likewise.
194 * d10v-dis.c: Likewise.
195 * d30v-dis.c: Likewise.
196 * d30v-opc.c: Likewise.
197 * dis-buf.c: Likewise.
198 * dlx-dis.c: Likewise.
199 * h8300-dis.c: Likewise.
200 * h8500-dis.c: Likewise.
201 * hppa-dis.c: Likewise.
202 * i370-dis.c: Likewise.
203 * i370-opc.c: Likewise.
204 * m10200-dis.c: Likewise.
205 * m10300-dis.c: Likewise.
206 * m68k-dis.c: Likewise.
207 * m88k-dis.c: Likewise.
208 * mips-dis.c: Likewise.
209 * mmix-dis.c: Likewise.
210 * msp430-dis.c: Likewise.
211 * ns32k-dis.c: Likewise.
212 * or32-dis.c: Likewise.
213 * or32-opc.c: Likewise.
214 * pdp11-dis.c: Likewise.
215 * pj-dis.c: Likewise.
216 * s390-dis.c: Likewise.
217 * sh-dis.c: Likewise.
218 * sh64-dis.c: Likewise.
219 * sparc-dis.c: Likewise.
220 * sparc-opc.c: Likewise.
221 * sysdep.h: Likewise.
222 * tic30-dis.c: Likewise.
223 * tic4x-dis.c: Likewise.
224 * tic80-dis.c: Likewise.
225 * v850-dis.c: Likewise.
226 * v850-opc.c: Likewise.
227 * vax-dis.c: Likewise.
228 * w65-dis.c: Likewise.
229 * z8kgen.c: Likewise.
230
231 * fr30-*: Regenerate.
232 * frv-*: Regenerate.
233 * ip2k-*: Regenerate.
234 * iq2000-*: Regenerate.
235 * m32r-*: Regenerate.
236 * ms1-*: Regenerate.
237 * openrisc-*: Regenerate.
238 * xstormy16-*: Regenerate.
239
cc16ba8c
BE		 2402005-06-23 Ben Elliston <bje@gnu.org>
241
242 * m68k-dis.c: Use ISC C90.
243 * m68k-opc.c: Formatting fixes.
244
4b185e97
DU		 2452005-06-16 David Ung <davidu@mips.com>
246
247 * mips16-opc.c (mips16_opcodes): Add the following MIPS16e
248 instructions to the table; seb/seh/sew/zeb/zeh/zew.
249
ac188222
DB		 2502005-06-15 Dave Brolley <brolley@redhat.com>
251
252 Contribute Morpho ms1 on behalf of Red Hat
253 * ms1-asm.c, ms1-desc.c, ms1-dis.c, ms1-ibld.c, ms1-opc.c,
254 ms1-opc.h: New files, Morpho ms1 target.
255
256 2004-05-14 Stan Cox <scox@redhat.com>
257
258 * disassemble.c (ARCH_ms1): Define.
259 (disassembler): Handle bfd_arch_ms1
260
261 2004-05-13 Michael Snyder <msnyder@redhat.com>
262
263 * Makefile.am, Makefile.in: Add ms1 target.
264 * configure.in: Ditto.
265
6b5d3a4d
ZW		 2662005-06-08 Zack Weinberg <zack@codesourcery.com>
267
268 * arm-opc.h: Delete; fold contents into ...
269 * arm-dis.c: ... here. Move includes of internal COFF headers
270 next to includes of internal ELF headers.
271 (streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
272 (struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
273 (struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
274 (arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
275 (iwmmxt_wwnames, iwmmxt_wwssnames):
276 Make const.
277 (regnames): Remove iWMMXt coprocessor register sets.
278 (iwmmxt_regnames, iwmmxt_cregnames): New statics.
279 (get_arm_regnames): Adjust fourth argument to match above changes.
280 (set_iwmmxt_regnames): Delete.
281 (print_insn_arm): Constify 'c'. Use ISO syntax for function
282 pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
283 and iwmmxt_cregnames, not set_iwmmxt_regnames.
284 (print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
285 ISO syntax for function pointer calls.
286
4a5329c6
ZW		 2872005-06-07 Zack Weinberg <zack@codesourcery.com>
288
289 * arm-dis.c: Split up the comments describing the format codes, so
290 that the ARM and 16-bit Thumb opcode tables each have comments
291 preceding them that describe all the codes, and only the codes,
292 valid in those tables. (32-bit Thumb table is already like this.)
293 Reorder the lists in all three comments to match the order in
294 which the codes are implemented.
295 Remove all forward declarations of static functions. Convert all
296 function definitions to ISO C format.
297 (print_insn_arm, print_insn_thumb16, print_insn_thumb32):
298 Return nothing.
299 (print_insn_thumb16): Remove unused case 'I'.
300 (print_insn): Update for changed calling convention of subroutines.
301
3d456fa1
JB		 3022005-05-25 Jan Beulich <jbeulich@novell.com>
303
304 * i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
305 hex (but retain it being displayed as signed). Remove redundant
306 checks. Add handling of displacements for 16-bit addressing in Intel
307 mode.
308
2888cb7a
JB		 3092005-05-25 Jan Beulich <jbeulich@novell.com>
310
311 * i386-dis.c (prefix_name): Remove pointless mode_64bit check.
312 (OP_E): Remove redundant REX_EXTZ handling. Remove pointless
313 masking of 'rm' in 16-bit memory address handling.
314
1ed8e1e4
AM		 3152005-05-19 Anton Blanchard <anton@samba.org>
316
317 * ppc-dis.c (powerpc_dialect): Handle "-Mpower5".
318 (print_ppc_disassembler_options): Document it.
319 * ppc-opc.c (SVC_LEV): Define.
320 (LEV): Allow optional operand.
321 (POWER5): Define.
322 (powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add
323 "hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
324
49cc2e69
KC		 3252005-05-19 Kelley Cook <kcook@gcc.gnu.org>
326
327 * Makefile.in: Regenerate.
328
c19d1205
ZW		 3292005-05-17 Zack Weinberg <zack@codesourcery.com>
330
331 * arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
332 instructions. Adjust disassembly of some opcodes to match
333 unified syntax.
334 (thumb32_opcodes): New table.
335 (print_insn_thumb): Rename print_insn_thumb16; don't handle
336 two-halfword branches here.
337 (print_insn_thumb32): New function.
338 (print_insn): Choose among print_insn_arm, print_insn_thumb16,
339 and print_insn_thumb32. Be consistent about order of
340 halfwords when printing 32-bit instructions.
341
003519a7
L		 3422005-05-07 H.J. Lu <hongjiu.lu@intel.com>
343
344 PR 843
345 * i386-dis.c (branch_v_mode): New.
346 (indirEv): Use branch_v_mode instead of v_mode.
347 (OP_E): Handle branch_v_mode.
348
920a34a7
L		 3492005-05-07 H.J. Lu <hongjiu.lu@intel.com>
350
351 * d10v-dis.c (dis_2_short): Support 64bit host.
352
5de773c1
NC		 3532005-05-07 Nick Clifton <nickc@redhat.com>
354
355 * po/nl.po: Updated translation.
356
f4321104
NC		 3572005-05-07 Nick Clifton <nickc@redhat.com>
358
359 * Update the address and phone number of the FSF organization in
360 the GPL notices in the following files:
361 a29k-dis.c, aclocal.m4, alpha-dis.c, alpha-opc.c, arc-dis.c,
362 arc-dis.h, arc-ext.c, arc-ext.h, arc-opc.c, arm-dis.c, arm-opc.h,
363 avr-dis.c, cgen-asm.c, cgen-asm.in, cgen-dis.c, cgen-dis.in,
364 cgen-ibld.in, cgen-opc.c, cgen.sh, cris-dis.c, cris-opc.c,
365 crx-dis.c, crx-opc.c, d10v-dis.c, d10v-opc.c, d30v-dis.c,
366 d30v-opc.c, dis-buf.c, dis-init.c, disassemble.c, dlx-dis.c,
367 fr30-asm.c, fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c,
368 fr30-opc.c, fr30-opc.h, frv-asm.c, frv-desc.c, frv-desc.h,
369 frv-dis.c, frv-ibld.c, frv-opc.c, frv-opc.h, h8300-dis.c,
370 h8500-dis.c, h8500-opc.h, hppa-dis.c, i370-dis.c, i370-opc.c,
371 i386-dis.c, i860-dis.c, i960-dis.c, ia64-asmtab.h, ia64-dis.c,
372 ia64-gen.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c,
373 ia64-opc-f.c, ia64-opc-i.c, ia64-opc-m.c, ia64-opc-x.c,
374 ia64-opc.c, ia64-opc.h, ip2k-asm.c, ip2k-desc.c, ip2k-desc.h,
375 ip2k-dis.c, ip2k-ibld.c, ip2k-opc.c, ip2k-opc.h, iq2000-asm.c,
376 iq2000-desc.c, iq2000-desc.h, iq2000-dis.c, iq2000-ibld.c,
377 iq2000-opc.c, iq2000-opc.h, m10200-dis.c, m10200-opc.c,
378 m10300-dis.c, m10300-opc.c, m32r-asm.c, m32r-desc.c, m32r-desc.h,
379 m32r-dis.c, m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c,
380 m68hc11-dis.c, m68hc11-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c,
381 maxq-dis.c, mcore-dis.c, mcore-opc.h, mips-dis.c, mips-opc.c,
382 mips16-opc.c, mmix-dis.c, mmix-opc.c, msp430-dis.c, ns32k-dis.c,
383 openrisc-asm.c, openrisc-desc.c, openrisc-desc.h, openrisc-dis.c,
384 openrisc-ibld.c, openrisc-opc.c, openrisc-opc.h, opintl.h,
385 or32-dis.c, or32-opc.c, pdp11-dis.c, pdp11-opc.c, pj-dis.c,
386 pj-opc.c, ppc-dis.c, ppc-opc.c, s390-dis.c, s390-mkopc.c,
387 s390-opc.c, sh-dis.c, sh-opc.h, sh64-dis.c, sh64-opc.c,
388 sh64-opc.h, sparc-dis.c, sparc-opc.c, sysdep.h, tic30-dis.c,
389 tic4x-dis.c, tic54x-dis.c, tic54x-opc.c, tic80-dis.c, tic80-opc.c,
390 v850-dis.c, v850-opc.c, vax-dis.c, w65-dis.c, w65-opc.h,
391 xstormy16-asm.c, xstormy16-desc.c, xstormy16-desc.h,
392 xstormy16-dis.c, xstormy16-ibld.c, xstormy16-opc.c,
393 xstormy16-opc.h, xtensa-dis.c, z8k-dis.c, z8kgen.c
394
10b076a2
JW		 3952005-05-05 James E Wilson <wilson@specifixinc.com>
396
397 * ia64-opc.c: Include sysdep.h before libiberty.h.
398
022716b6
NC		 3992005-05-05 Nick Clifton <nickc@redhat.com>
400
401 * configure.in (ALL_LINGUAS): Add vi.
402 * configure: Regenerate.
403 * po/vi.po: New.
404
db5152b4
JG		 4052005-04-26 Jerome Guitton <guitton@gnat.com>
406
407 * configure.in: Fix the check for basename declaration.
408 * configure: Regenerate.
409
eed0d89a
AM		 4102005-04-19 Alan Modra <amodra@bigpond.net.au>
411
412 * ppc-opc.c (RTO): Define.
413 (powerpc_opcodes <tlbsx, tlbsx., tlbre>): Combine PPC403 and BOOKE
414 entries to suit PPC440.
415
791fe849
MK		 4162005-04-18 Mark Kettenis <kettenis@gnu.org>
417
418 * i386-dis.c: Insert hyphens into selected VIA PadLock extensions.
419 Add xcrypt-ctr.
420
ffe58f7c
NC		 4212005-04-14 Nick Clifton <nickc@redhat.com>
422
423 * po/fi.po: New translation: Finnish.
424 * configure.in (ALL_LINGUAS): Add fi.
425 * configure: Regenerate.
426
9e9b66a9
AM		 4272005-04-14 Alan Modra <amodra@bigpond.net.au>
428
429 * Makefile.am (NO_WERROR): Define.
430 * configure.in: Invoke AM_BINUTILS_WARNINGS.
431 * Makefile.in: Regenerate.
432 * aclocal.m4: Regenerate.
433 * configure: Regenerate.
434
9494d739
NC		 4352005-04-04 Nick Clifton <nickc@redhat.com>
436
437 * fr30-asm.c: Regenerate.
438 * frv-asm.c: Regenerate.
439 * iq2000-asm.c: Regenerate.
440 * m32r-asm.c: Regenerate.
441 * openrisc-asm.c: Regenerate.
442
6128c599
JB		 4432005-04-01 Jan Beulich <jbeulich@novell.com>
444
445 * i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any
446 visible operands in Intel mode. The first operand of monitor is
447 %rax in 64-bit mode.
448
373ff435
JB		 4492005-04-01 Jan Beulich <jbeulich@novell.com>
450
451 * i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for
452 easier future additions.
453
4bd60896
JG		 4542005-03-31 Jerome Guitton <guitton@gnat.com>
455
456 * configure.in: Check for basename.
457 * configure: Regenerate.
458 * config.in: Ditto.
459
4cc91dba
L		 4602005-03-29 H.J. Lu <hongjiu.lu@intel.com>
461
462 * i386-dis.c (SEG_Fixup): New.
463 (Sv): New.
464 (dis386): Use "Sv" for 0x8c and 0x8e.
465
ec72cfe5
NC		 4662005-03-21 Jan-Benedict Glaw <jbglaw@lug-owl.de>
467 Nick Clifton <nickc@redhat.com>
c19d1205 468
ec72cfe5
NC		 469 * vax-dis.c: (entry_addr): New varible: An array of user supplied
470 function entry mask addresses.
471 (entry_addr_occupied_slots): New variable: The number of occupied
c19d1205 472 elements in entry_addr.
ec72cfe5
NC		 473 (entry_addr_total_slots): New variable: The total number of
474 elements in entry_addr.
475 (parse_disassembler_options): New function. Fills in the entry_addr
476 array.
477 (free_entry_array): New function. Release the memory used by the
478 entry addr array. Suppressed because there is no way to call it.
479 (is_function_entry): Check if a given address is a function's
480 start address by looking at supplied entry mask addresses and
481 symbol information, if available.
482 (print_insn_vax): Use parse_disassembler_options and is_function_entry.
483
85064c79
L		 4842005-03-23 H.J. Lu <hongjiu.lu@intel.com>
485
486 * cris-dis.c (print_with_operands): Use ~31L for long instead
487 of ~31.
488
de7141c7
L		 4892005-03-20 H.J. Lu <hongjiu.lu@intel.com>
490
491 * mmix-opc.c (O): Revert the last change.
492 (Z): Likewise.
493
e493ab45
L		 4942005-03-19 H.J. Lu <hongjiu.lu@intel.com>
495
496 * mmix-opc.c (O): Use 24UL instead of 24 for unsigned long.
497 (Z): Likewise.
498
d8d7c459
HPN		 4992005-03-19 Hans-Peter Nilsson <hp@bitrange.com>
500
501 * mmix-opc.c (O, Z): Force expression as unsigned long.
502
ebdb0383
NC		 5032005-03-18 Nick Clifton <nickc@redhat.com>
504
505 * ip2k-asm.c: Regenerate.
506 * op/opcodes.pot: Regenerate.
507
1ad12f97
NC		 5082005-03-16 Nick Clifton <nickc@redhat.com>
509 Ben Elliston <bje@au.ibm.com>
510
569acd2c 511 * configure.in (werror): New switch: Add -Werror to the
1ad12f97 512 compiler command line. Enabled by default. Disable via
569acd2c 513 --disable-werror.
1ad12f97
NC		 514 * configure: Regenerate.
515
4eb30afc
AM		 5162005-03-16 Alan Modra <amodra@bigpond.net.au>
517
518 * ppc-dis.c (powerpc_dialect): Don't set PPC_OPCODE_ALTIVEC when
519 BOOKE.
520
ea8409f7
AM		 5212005-03-15 Alan Modra <amodra@bigpond.net.au>
522
729ae8d2
AM		 523 * po/es.po: Commit new Spanish translation.
524
ea8409f7
AM		 525 * po/fr.po: Commit new French translation.
526
4f495e61
NC		 5272005-03-14 Jan-Benedict Glaw <jbglaw@lug-owl.de>
528
529 * vax-dis.c: Fix spelling error
530 (print_insn_vax): Use ".word 0x0012 # Entry mask: r1 r2 >" instead
531 of just "Entry mask: < r1 ... >"
532
0a003adc
ZW		 5332005-03-12 Zack Weinberg <zack@codesourcery.com>
534
535 * arm-dis.c (arm_opcodes): Document %E and %V.
536 Add entries for v6T2 ARM instructions:
537 bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
538 (print_insn_arm): Add support for %E and %V.
885fc257 539 (thumb_opcodes): Add ARMv6K instructions nop, sev, wfe, wfi, yield.
0a003adc 540
da99ee72
AM		 5412005-03-10 Jeff Baker <jbaker@qnx.com>
542 Alan Modra <amodra@bigpond.net.au>
543
544 * ppc-opc.c (insert_sprg, extract_sprg): New Functions.
545 (powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
546 (SPRG_MASK): Delete.
547 (XSPRG_MASK): Mask off extra bits now part of sprg field.
0a003adc 548 (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
da99ee72
AM		 549 mfsprg4..7 after msprg and consolidate.
550
220abb21
AM		 5512005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
552
553 * vax-dis.c (entry_mask_bit): New array.
554 (print_insn_vax): Decode function entry mask.
555
0e06657a
AH		 5562005-03-07 Aldy Hernandez <aldyh@redhat.com>
557
558 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
559
06647dfd
AM		 5602005-03-05 Alan Modra <amodra@bigpond.net.au>
561
562 * po/opcodes.pot: Regenerate.
563
82b829a7
RR		 5642005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
565
220abb21 566 * arc-dis.c (a4_decoding_class): New enum.
06647dfd
AM		 567 (dsmOneArcInst): Use the enum values for the decoding class.
568 Remove redundant case in the switch for decodingClass value 11.
82b829a7 569
c4a530c5
JB		 5702005-03-02 Jan Beulich <jbeulich@novell.com>
571
572 * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
573 accesses.
574 (OP_C): Consider lock prefix in non-64-bit modes.
575
47d8304e
AM		 5762005-02-24 Alan Modra <amodra@bigpond.net.au>
577
578 * cris-dis.c (format_hex): Remove ineffective warning fix.
579 * crx-dis.c (make_instruction): Warning fix.
580 * frv-asm.c: Regenerate.
581
ec36c4a4
NC		 5822005-02-23 Nick Clifton <nickc@redhat.com>
583
33b71eeb
NC		 584 * cgen-dis.in: Use bfd_byte for buffers that are passed to
585 read_memory.
06647dfd 586
33b71eeb 587 * ia64-opc.c (locate_opcode_ent): Initialise opval array.
06647dfd 588
ec36c4a4
NC		 589 * crx-dis.c (make_instruction): Move argument structure into inner
590 scope and ensure that all of its fields are initialised before
591 they are used.
592
33b71eeb
NC		 593 * fr30-asm.c: Regenerate.
594 * fr30-dis.c: Regenerate.
595 * frv-asm.c: Regenerate.
596 * frv-dis.c: Regenerate.
597 * ip2k-asm.c: Regenerate.
598 * ip2k-dis.c: Regenerate.
599 * iq2000-asm.c: Regenerate.
600 * iq2000-dis.c: Regenerate.
601 * m32r-asm.c: Regenerate.
602 * m32r-dis.c: Regenerate.
603 * openrisc-asm.c: Regenerate.
604 * openrisc-dis.c: Regenerate.
605 * xstormy16-asm.c: Regenerate.
606 * xstormy16-dis.c: Regenerate.
607
53c9ebc5
AM		 6082005-02-22 Alan Modra <amodra@bigpond.net.au>
609
610 * arc-ext.c: Warning fixes.
611 * arc-ext.h: Likewise.
612 * cgen-opc.c: Likewise.
613 * ia64-gen.c: Likewise.
614 * maxq-dis.c: Likewise.
615 * ns32k-dis.c: Likewise.
616 * w65-dis.c: Likewise.
617 * ia64-asmtab.c: Regenerate.
618
610ad19b
AM		 6192005-02-22 Alan Modra <amodra@bigpond.net.au>
620
621 * fr30-desc.c: Regenerate.
622 * fr30-desc.h: Regenerate.
623 * fr30-opc.c: Regenerate.
624 * fr30-opc.h: Regenerate.
625 * frv-desc.c: Regenerate.
626 * frv-desc.h: Regenerate.
627 * frv-opc.c: Regenerate.
628 * frv-opc.h: Regenerate.
629 * ip2k-desc.c: Regenerate.
630 * ip2k-desc.h: Regenerate.
631 * ip2k-opc.c: Regenerate.
632 * ip2k-opc.h: Regenerate.
633 * iq2000-desc.c: Regenerate.
634 * iq2000-desc.h: Regenerate.
635 * iq2000-opc.c: Regenerate.
636 * iq2000-opc.h: Regenerate.
637 * m32r-desc.c: Regenerate.
638 * m32r-desc.h: Regenerate.
639 * m32r-opc.c: Regenerate.
640 * m32r-opc.h: Regenerate.
641 * m32r-opinst.c: Regenerate.
642 * openrisc-desc.c: Regenerate.
643 * openrisc-desc.h: Regenerate.
644 * openrisc-opc.c: Regenerate.
645 * openrisc-opc.h: Regenerate.
646 * xstormy16-desc.c: Regenerate.
647 * xstormy16-desc.h: Regenerate.
648 * xstormy16-opc.c: Regenerate.
649 * xstormy16-opc.h: Regenerate.
650
db9db6f2
AM		 6512005-02-21 Alan Modra <amodra@bigpond.net.au>
652
653 * Makefile.am: Run "make dep-am"
654 * Makefile.in: Regenerate.
655
bf143b25
NC		 6562005-02-15 Nick Clifton <nickc@redhat.com>
657
658 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
659 compile time warnings.
660 (print_keyword): Likewise.
661 (default_print_insn): Likewise.
662
663 * fr30-desc.c: Regenerated.
664 * fr30-desc.h: Regenerated.
665 * fr30-dis.c: Regenerated.
666 * fr30-opc.c: Regenerated.
667 * fr30-opc.h: Regenerated.
668 * frv-desc.c: Regenerated.
669 * frv-dis.c: Regenerated.
670 * frv-opc.c: Regenerated.
671 * ip2k-asm.c: Regenerated.
672 * ip2k-desc.c: Regenerated.
673 * ip2k-desc.h: Regenerated.
674 * ip2k-dis.c: Regenerated.
675 * ip2k-opc.c: Regenerated.
676 * ip2k-opc.h: Regenerated.
677 * iq2000-desc.c: Regenerated.
678 * iq2000-dis.c: Regenerated.
679 * iq2000-opc.c: Regenerated.
680 * m32r-asm.c: Regenerated.
681 * m32r-desc.c: Regenerated.
682 * m32r-desc.h: Regenerated.
683 * m32r-dis.c: Regenerated.
684 * m32r-opc.c: Regenerated.
685 * m32r-opc.h: Regenerated.
686 * m32r-opinst.c: Regenerated.
687 * openrisc-desc.c: Regenerated.
688 * openrisc-desc.h: Regenerated.
689 * openrisc-dis.c: Regenerated.
690 * openrisc-opc.c: Regenerated.
691 * openrisc-opc.h: Regenerated.
692 * xstormy16-desc.c: Regenerated.
693 * xstormy16-desc.h: Regenerated.
694 * xstormy16-dis.c: Regenerated.
695 * xstormy16-opc.c: Regenerated.
696 * xstormy16-opc.h: Regenerated.
697
d6098898
L		 6982005-02-14 H.J. Lu <hongjiu.lu@intel.com>
699
700 * dis-buf.c (perror_memory): Use sprintf_vma to print out
701 address.
702
5a84f3e0
NC		 7032005-02-11 Nick Clifton <nickc@redhat.com>
704
bc18c937
NC		 705 * iq2000-asm.c: Regenerate.
706
5a84f3e0
NC		 707 * frv-dis.c: Regenerate.
708
0a40490e
JB		 7092005-02-07 Jim Blandy <jimb@redhat.com>
710
711 * Makefile.am (CGEN): Load guile.scm before calling the main
712 application script.
713 * Makefile.in: Regenerated.
714 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
715 Simply pass the cgen-opc.scm path to ${cgen} as its first
716 argument; ${cgen} itself now contains the '-s', or whatever is
717 appropriate for the Scheme being used.
718
c46f8c51
AC		 7192005-01-31 Andrew Cagney <cagney@gnu.org>
720
721 * configure: Regenerate to track ../gettext.m4.
722
60b9a617
JB		 7232005-01-31 Jan Beulich <jbeulich@novell.com>
724
725 * ia64-gen.c (NELEMS): Define.
726 (shrink): Generate alias with missing second predicate register when
727 opcode has two outputs and these are both predicates.
728 * ia64-opc-i.c (FULL17): Define.
729 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
730 here to generate output template.
731 (TBITCM, TNATCM): Undefine after use.
732 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
733 first input. Add ld16 aliases without ar.csd as second output. Add
734 st16 aliases without ar.csd as second input. Add cmpxchg aliases
735 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
736 ar.ccv as third/fourth inputs. Consolidate through...
737 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
738 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
739 * ia64-asmtab.c: Regenerate.
740
a53bf506
AC		 7412005-01-27 Andrew Cagney <cagney@gnu.org>
742
743 * configure: Regenerate to track ../gettext.m4 change.
744
90219bd0
AO		 7452005-01-25 Alexandre Oliva <aoliva@redhat.com>
746
747 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
748 * frv-asm.c: Rebuilt.
749 * frv-desc.c: Rebuilt.
750 * frv-desc.h: Rebuilt.
751 * frv-dis.c: Rebuilt.
752 * frv-ibld.c: Rebuilt.
753 * frv-opc.c: Rebuilt.
754 * frv-opc.h: Rebuilt.
755
45181ed1
AC		 7562005-01-24 Andrew Cagney <cagney@gnu.org>
757
758 * configure: Regenerate, ../gettext.m4 was updated.
759
9e836e3d
FF		 7602005-01-21 Fred Fish <fnf@specifixinc.com>
761
762 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
763 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
764 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
765 * mips-dis.c: Ditto.
766
5e8cb021
AM		 7672005-01-20 Alan Modra <amodra@bigpond.net.au>
768
769 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
770
986e18a5
FF		 7712005-01-19 Fred Fish <fnf@specifixinc.com>
772
773 * mips-dis.c (no_aliases): New disassembly option flag.
774 (set_default_mips_dis_options): Init no_aliases to zero.
775 (parse_mips_dis_option): Handle no-aliases option.
776 (print_insn_mips): Ignore table entries that are aliases
777 if no_aliases is set.
778 (print_insn_mips16): Ditto.
779 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
780 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
781 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
782 * mips16-opc.c (mips16_opcodes): Ditto.
783
e38bc3b5
NC		 7842005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
785
786 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
787 (inheritance diagram): Add missing edge.
788 (arch_sh1_up): Rename arch_sh_up to match external name to make life
789 easier for the testsuite.
790 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
791 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
610ad19b 792 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
e38bc3b5
NC		 793 arch_sh2a_or_sh4_up child.
794 (sh_table): Do renaming as above.
795 Correct comment for ldc.l for gas testsuite to read.
796 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
797 Correct comments for movy.w and movy.l for gas testsuite to read.
798 Correct comments for fmov.d and fmov.s for gas testsuite to read.
799
9df48ba9
L		 8002005-01-12 H.J. Lu <hongjiu.lu@intel.com>
801
802 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
803
2033b4b9
L		 8042005-01-12 H.J. Lu <hongjiu.lu@intel.com>
805
806 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
807
0bcb06d2
AS		 8082005-01-10 Andreas Schwab <schwab@suse.de>
809
810 * disassemble.c (disassemble_init_for_target) <case
811 bfd_arch_ia64>: Set skip_zeroes to 16.
812 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
813
47add74d
TL		 8142004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
815
816 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
817
246f4c05
SS		 8182004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
819
820 * avr-dis.c: Prettyprint. Added printing of symbol names in all
821 memory references. Convert avr_operand() to C90 formatting.
822
0e1200e5
TL		 8232004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
824
825 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
826
89a649f7
TL		 8272004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
828
829 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
830 (no_op_insn): Initialize array with instructions that have no
831 operands.
832 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
833
6255809c
RE		 8342004-11-29 Richard Earnshaw <rearnsha@arm.com>
835
836 * arm-dis.c: Correct top-level comment.
837
2fbad815
RE		 8382004-11-27 Richard Earnshaw <rearnsha@arm.com>
839
840 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
841 architecuture defining the insn.
842 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 843 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
844 field.
2fbad815
RE		 845 Also include opcode/arm.h.
846 * Makefile.am (arm-dis.lo): Update dependency list.
847 * Makefile.in: Regenerate.
848
d81acc42
NC		 8492004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
850
851 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
852 reflect the change to the short immediate syntax.
853
ca4f2377
AM		 8542004-11-19 Alan Modra <amodra@bigpond.net.au>
855
5da8bf1b
AM		 856 * or32-opc.c (debug): Warning fix.
857 * po/POTFILES.in: Regenerate.
858
ca4f2377
AM		 859 * maxq-dis.c: Formatting.
860 (print_insn): Warning fix.
861
b7693d02
DJ		 8622004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
863
864 * arm-dis.c (WORD_ADDRESS): Define.
865 (print_insn): Use it. Correct big-endian end-of-section handling.
866
300dac7e
NC		 8672004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
868 Vineet Sharma <vineets@noida.hcltech.com>
869
870 * maxq-dis.c: New file.
871 * disassemble.c (ARCH_maxq): Define.
610ad19b 872 (disassembler): Add 'print_insn_maxq_little' for handling maxq
300dac7e
NC		 873 instructions..
874 * configure.in: Add case for bfd_maxq_arch.
875 * configure: Regenerate.
876 * Makefile.am: Add support for maxq-dis.c
877 * Makefile.in: Regenerate.
878 * aclocal.m4: Regenerate.
879
42048ee7
TL		 8802004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
881
882 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
883 mode.
884 * crx-dis.c: Likewise.
885
bd21e58e
HPN		 8862004-11-04 Hans-Peter Nilsson <hp@axis.com>
887
888 Generally, handle CRISv32.
889 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
890 (struct cris_disasm_data): New type.
891 (format_reg, format_hex, cris_constraint, print_flags)
892 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
893 callers changed.
894 (format_sup_reg, print_insn_crisv32_with_register_prefix)
895 (print_insn_crisv32_without_register_prefix)
896 (print_insn_crisv10_v32_with_register_prefix)
897 (print_insn_crisv10_v32_without_register_prefix)
898 (cris_parse_disassembler_options): New functions.
899 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
900 parameter. All callers changed.
901 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
902 failure.
903 (cris_constraint) <case 'Y', 'U'>: New cases.
904 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
905 for constraint 'n'.
906 (print_with_operands) <case 'Y'>: New case.
907 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
908 <case 'N', 'Y', 'Q'>: New cases.
909 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
910 (print_insn_cris_with_register_prefix)
911 (print_insn_cris_without_register_prefix): Call
912 cris_parse_disassembler_options.
913 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
914 for CRISv32 and the size of immediate operands. New v32-only
915 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
916 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
917 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
918 Change brp to be v3..v10.
919 (cris_support_regs): New vector.
920 (cris_opcodes): Update head comment. New format characters '[',
921 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
922 Add new opcodes for v32 and adjust existing opcodes to accommodate
923 differences to earlier variants.
924 (cris_cond15s): New vector.
925
9306ca4a
JB		 9262004-11-04 Jan Beulich <jbeulich@novell.com>
927
928 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
929 (indirEb): Remove.
930 (Mp): Use f_mode rather than none at all.
931 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
932 replaces what previously was x_mode; x_mode now means 128-bit SSE
933 operands.
934 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
935 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
936 pinsrw's second operand is Edqw.
937 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
938 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
939 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
940 mode when an operand size override is present or always suffixing.
941 More instructions will need to be added to this group.
942 (putop): Handle new macro chars 'C' (short/long suffix selector),
943 'I' (Intel mode override for following macro char), and 'J' (for
944 adding the 'l' prefix to far branches in AT&T mode). When an
945 alternative was specified in the template, honor macro character when
946 specified for Intel mode.
947 (OP_E): Handle new *_mode values. Correct pointer specifications for
948 memory operands. Consolidate output of index register.
949 (OP_G): Handle new *_mode values.
950 (OP_I): Handle const_1_mode.
951 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
952 respective opcode prefix bits have been consumed.
953 (OP_EM, OP_EX): Provide some default handling for generating pointer
954 specifications.
955
f39c96a9
TL		 9562004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
957
958 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
959 COP_INST macro.
960
812337be
TL		 9612004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
962
963 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
964 (getregliststring): Support HI/LO and user registers.
610ad19b 965 * crx-opc.c (crx_instruction): Update data structure according to the
812337be
TL		 966 rearrangement done in CRX opcode header file.
967 (crx_regtab): Likewise.
968 (crx_optab): Likewise.
610ad19b 969 (crx_instruction): Reorder load/stor instructions, remove unsupported
812337be
TL		 970 formats.
971 support new Co-Processor instruction 'cpi'.
972
4030fa5a
NC		 9732004-10-27 Nick Clifton <nickc@redhat.com>
974
975 * opcodes/iq2000-asm.c: Regenerate.
976 * opcodes/iq2000-desc.c: Regenerate.
977 * opcodes/iq2000-desc.h: Regenerate.
978 * opcodes/iq2000-dis.c: Regenerate.
979 * opcodes/iq2000-ibld.c: Regenerate.
980 * opcodes/iq2000-opc.c: Regenerate.
981 * opcodes/iq2000-opc.h: Regenerate.
982
fc3d45e8
TL		 9832004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
984
985 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
986 us4, us5 (respectively).
987 Remove unsupported 'popa' instruction.
988 Reverse operands order in store co-processor instructions.
989
3c55da70
AM		 9902004-10-15 Alan Modra <amodra@bigpond.net.au>
991
992 * Makefile.am: Run "make dep-am"
993 * Makefile.in: Regenerate.
994
7fa3d080
BW		 9952004-10-12 Bob Wilson <bob.wilson@acm.org>
996
997 * xtensa-dis.c: Use ISO C90 formatting.
998
e612bb4d
AM		 9992004-10-09 Alan Modra <amodra@bigpond.net.au>
1000
1001 * ppc-opc.c: Revert 2004-09-09 change.
1002
43cd72b9
BW		 10032004-10-07 Bob Wilson <bob.wilson@acm.org>
1004
1005 * xtensa-dis.c (state_names): Delete.
1006 (fetch_data): Use xtensa_isa_maxlength.
1007 (print_xtensa_operand): Replace operand parameter with opcode/operand
1008 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
1009 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
1010 instruction bundles. Use xmalloc instead of malloc.
1011
bbac1f2a
NC		 10122004-10-07 David Gibson <david@gibson.dropbear.id.au>
1013
1014 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
1015 initializers.
1016
48c9f030
NC		 10172004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1018
1019 * crx-opc.c (crx_instruction): Support Co-processor insns.
1020 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
1021 (getregliststring): Change function to use the above enum.
1022 (print_arg): Handle CO-Processor insns.
1023 (crx_cinvs): Add 'b' option to invalidate the branch-target
1024 cache.
1025
12c64a4e
AH		 10262004-10-06 Aldy Hernandez <aldyh@redhat.com>
1027
1028 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
1029 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
1030 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
1031 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
1032 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
1033
14127cc4
NC		 10342004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
1035
1036 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
1037 rather than add it.
1038
0dd132b6
NC		 10392004-09-30 Paul Brook <paul@codesourcery.com>
1040
1041 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
1042 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
1043
3f85e526
L		 10442004-09-17 H.J. Lu <hongjiu.lu@intel.com>
1045
1046 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
1047 (CONFIG_STATUS_DEPENDENCIES): New.
1048 (Makefile): Removed.
1049 (config.status): Likewise.
1050 * Makefile.in: Regenerated.
1051
8ae85421
AM		 10522004-09-17 Alan Modra <amodra@bigpond.net.au>
1053
1054 * Makefile.am: Run "make dep-am".
1055 * Makefile.in: Regenerate.
1056 * aclocal.m4: Regenerate.
1057 * configure: Regenerate.
1058 * po/POTFILES.in: Regenerate.
1059 * po/opcodes.pot: Regenerate.
1060
24443139
AS		 10612004-09-11 Andreas Schwab <schwab@suse.de>
1062
1063 * configure: Rebuild.
1064
2a309db0
AM		 10652004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1066
1067 * ppc-opc.c (L): Make this field not optional.
1068
42851540
NC		 10692004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
1070
1071 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
1072 Fix parameter to 'm[t|f]csr' insns.
1073
979273e3
NN		 10742004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
1075
1076 * configure.in: Autoupdate to autoconf 2.59.
1077 * aclocal.m4: Rebuild with aclocal 1.4p6.
1078 * configure: Rebuild with autoconf 2.59.
1079 * Makefile.in: Rebuild with automake 1.4p6 (picking up
1080 bfd changes for autoconf 2.59 on the way).
1081 * config.in: Rebuild with autoheader 2.59.
1082
ac28a1cb
RS		 10832004-08-27 Richard Sandiford <rsandifo@redhat.com>
1084
1085 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
1086
30d1c836
ML		 10872004-07-30 Michal Ludvig <mludvig@suse.cz>
1088
1089 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
1090 (GRPPADLCK2): New define.
1091 (twobyte_has_modrm): True for 0xA6.
1092 (grps): GRPPADLCK2 for opcode 0xA6.
1093
0b0ac059
AO		 10942004-07-29 Alexandre Oliva <aoliva@redhat.com>
1095
1096 Introduce SH2a support.
1097 * sh-opc.h (arch_sh2a_base): Renumber.
1098 (arch_sh2a_nofpu_base): Remove.
1099 (arch_sh_base_mask): Adjust.
1100 (arch_opann_mask): New.
1101 (arch_sh2a, arch_sh2a_nofpu): Adjust.
1102 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
1103 (sh_table): Adjust whitespace.
1104 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
1105 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
1106 instruction list throughout.
1107 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
1108 of arch_sh2a in instruction list throughout.
1109 (arch_sh2e_up): Accomodate above changes.
1110 (arch_sh2_up): Ditto.
1111 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
1112 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
1113 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
1114 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
1115 * sh-opc.h (arch_sh2a_nofpu): New.
1116 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
1117 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
1118 instruction.
1119 2004-01-20 DJ Delorie <dj@redhat.com>
1120 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
1121 2003-12-29 DJ Delorie <dj@redhat.com>
1122 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
1123 sh_opcode_info, sh_table): Add sh2a support.
1124 (arch_op32): New, to tag 32-bit opcodes.
1125 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
1126 2003-12-02 Michael Snyder <msnyder@redhat.com>
1127 * sh-opc.h (arch_sh2a): Add.
1128 * sh-dis.c (arch_sh2a): Handle.
1129 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
1130
670ec21d
NC		 11312004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
1132
1133 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
1134
ed049af3
NC		 11352004-07-22 Nick Clifton <nickc@redhat.com>
1136
1137 PR/280
1138 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
1139 insns - this is done by objdump itself.
1140 * h8500-dis.c (print_insn_h8500): Likewise.
1141
20f0a1fc
NC		 11422004-07-21 Jan Beulich <jbeulich@novell.com>
1143
1144 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
1145 regardless of address size prefix in effect.
1146 (ptr_reg): Size or address registers does not depend on rex64, but
1147 on the presence of an address size override.
1148 (OP_MMX): Use rex.x only for xmm registers.
1149 (OP_EM): Use rex.z only for xmm registers.
1150
6f14957b
MR		 11512004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
1152
1153 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
1154 move/branch operations to the bottom so that VR5400 multimedia
1155 instructions take precedence in disassembly.
1156
1586d91e
MR		 11572004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
1158
1159 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
1160 ISA-specific "break" encoding.
1161
982de27a
NC		 11622004-07-13 Elvis Chiang <elvisfb@gmail.com>
1163
1164 * arm-opc.h: Fix typo in comment.
1165
4300ab10
AS		 11662004-07-11 Andreas Schwab <schwab@suse.de>
1167
1168 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
1169
8577e690
AS		 11702004-07-09 Andreas Schwab <schwab@suse.de>
1171
1172 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
1173
1fe1f39c
NC		 11742004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1175
1176 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
1177 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
1178 (crx-dis.lo): New target.
1179 (crx-opc.lo): Likewise.
1180 * Makefile.in: Regenerate.
1181 * configure.in: Handle bfd_crx_arch.
1182 * configure: Regenerate.
1183 * crx-dis.c: New file.
1184 * crx-opc.c: New file.
1185 * disassemble.c (ARCH_crx): Define.
1186 (disassembler): Handle ARCH_crx.
1187
7a33b495
JW		 11882004-06-29 James E Wilson <wilson@specifixinc.com>
1189
1190 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
1191 * ia64-asmtab.c: Regnerate.
1192
98e69875
AM		 11932004-06-28 Alan Modra <amodra@bigpond.net.au>
1194
1195 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
1196 (extract_fxm): Don't test dialect.
1197 (XFXFXM_MASK): Include the power4 bit.
1198 (XFXM): Add p4 param.
1199 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
1200
a53b85e2
AO		 12012004-06-27 Alexandre Oliva <aoliva@redhat.com>
1202
1203 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
1204 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
1205
d0618d1c
AM		 12062004-06-26 Alan Modra <amodra@bigpond.net.au>
1207
1208 * ppc-opc.c (BH, XLBH_MASK): Define.
1209 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
1210
1d9f512f
AM		 12112004-06-24 Alan Modra <amodra@bigpond.net.au>
1212
1213 * i386-dis.c (x_mode): Comment.
1214 (two_source_ops): File scope.
1215 (float_mem): Correct fisttpll and fistpll.
1216 (float_mem_mode): New table.
1217 (dofloat): Use it.
1218 (OP_E): Correct intel mode PTR output.
1219 (ptr_reg): Use open_char and close_char.
1220 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
1221 operands. Set two_source_ops.
1222
52886d70
AM		 12232004-06-15 Alan Modra <amodra@bigpond.net.au>
1224
1225 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
1226 instead of _raw_size.
1227
bad9ceea
JJ		 12282004-06-08 Jakub Jelinek <jakub@redhat.com>
1229
1230 * ia64-gen.c (in_iclass): Handle more postinc st
1231 and ld variants.
1232 * ia64-asmtab.c: Rebuilt.
1233
0451f5df
MS		 12342004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
1235
1236 * s390-opc.txt: Correct architecture mask for some opcodes.
1237 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
1238 in the esa mode as well.
1239
f6f9408f
JR		 12402004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
1241
1242 * sh-dis.c (target_arch): Make unsigned.
1243 (print_insn_sh): Replace (most of) switch with a call to
1244 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
1245 * sh-opc.h: Redefine architecture flags values.
1246 Add sh3-nommu architecture.
1247 Reorganise <arch>_up macros so they make more visual sense.
1248 (SH_MERGE_ARCH_SET): Define new macro.
1249 (SH_VALID_BASE_ARCH_SET): Likewise.
1250 (SH_VALID_MMU_ARCH_SET): Likewise.
1251 (SH_VALID_CO_ARCH_SET): Likewise.
1252 (SH_VALID_ARCH_SET): Likewise.
1253 (SH_MERGE_ARCH_SET_VALID): Likewise.
1254 (SH_ARCH_SET_HAS_FPU): Likewise.
1255 (SH_ARCH_SET_HAS_DSP): Likewise.
1256 (SH_ARCH_UNKNOWN_ARCH): Likewise.
1257 (sh_get_arch_from_bfd_mach): Add prototype.
1258 (sh_get_arch_up_from_bfd_mach): Likewise.
1259 (sh_get_bfd_mach_from_arch_set): Likewise.
1260 (sh_merge_bfd_arc): Likewise.
1261
be8c092b
NC		 12622004-05-24 Peter Barada <peter@the-baradas.com>
1263
1264 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
610ad19b
AM		 1265 into new match_insn_m68k function. Loop over canidate
1266 matches and select first that completely matches.
be8c092b
NC		 1267 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
1268 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
610ad19b 1269 to verify addressing for MAC/EMAC.
be8c092b
NC		 1270 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
1271 reigster halves since 'fpu' and 'spl' look misleading.
1272 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
1273 * m68k-opc.c: Rearragne mac/emac cases to use longest for
1274 first, tighten up match masks.
1275 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
1276 'size' from special case code in print_insn_m68k to
1277 determine decode size of insns.
1278
a30e9cc4
AM		 12792004-05-19 Alan Modra <amodra@bigpond.net.au>
1280
1281 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
1282 well as when -mpower4.
1283
9598fbe5
NC		 12842004-05-13 Nick Clifton <nickc@redhat.com>
1285
1286 * po/fr.po: Updated French translation.
1287
6b6e92f4
NC		 12882004-05-05 Peter Barada <peter@the-baradas.com>
1289
1290 * m68k-dis.c(print_insn_m68k): Add new chips, use core
1291 variants in arch_mask. Only set m68881/68851 for 68k chips.
1292 * m68k-op.c: Switch from ColdFire chips to core variants.
1293
a404d431
AM		 12942004-05-05 Alan Modra <amodra@bigpond.net.au>
1295
a30e9cc4 1296 PR 147.
a404d431
AM		 1297 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
1298
f3806e43
BE		 12992004-04-29 Ben Elliston <bje@au.ibm.com>
1300
520ceea4
BE		 1301 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
1302 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 1303
1f1799d5
KK		 13042004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
1305
1306 * sh-dis.c (print_insn_sh): Print the value in constant pool
1307 as a symbol if it looks like a symbol.
1308
fd99574b
NC		 13092004-04-22 Peter Barada <peter@the-baradas.com>
1310
1311 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
1312 appropriate ColdFire architectures.
1313 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
1314 mask addressing.
1315 Add EMAC instructions, fix MAC instructions. Remove
1316 macmw/macml/msacmw/msacml instructions since mask addressing now
1317 supported.
1318
b4781d44
JJ		 13192004-04-20 Jakub Jelinek <jakub@redhat.com>
1320
1321 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
1322 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
1323 suffix. Use fmov*x macros, create all 3 fpsize variants in one
1324 macro. Adjust all users.
1325
91809fda 13262004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
610ad19b 1327
91809fda
NC		 1328 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
1329 separately.
1330
f4453dfa
NC		 13312004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
1332
1333 * m32r-asm.c: Regenerate.
1334
9b0de91a
SS		 13352004-03-29 Stan Shebs <shebs@apple.com>
1336
1337 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
1338 used.
1339
e20c0b3d
AM		 13402004-03-19 Alan Modra <amodra@bigpond.net.au>
1341
1342 * aclocal.m4: Regenerate.
1343 * config.in: Regenerate.
1344 * configure: Regenerate.
1345 * po/POTFILES.in: Regenerate.
1346 * po/opcodes.pot: Regenerate.
1347
fdd12ef3
AM		 13482004-03-16 Alan Modra <amodra@bigpond.net.au>
1349
1350 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
1351 PPC_OPERANDS_GPR_0.
1352 * ppc-opc.c (RA0): Define.
1353 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
1354 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 1355 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 1356
2dc111b3 13572004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 1358
1359 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 1360
7bfeee7b
AM		 13612004-03-15 Alan Modra <amodra@bigpond.net.au>
1362
1363 * sparc-dis.c (print_insn_sparc): Update getword prototype.
1364
7ffdda93
ML		 13652004-03-12 Michal Ludvig <mludvig@suse.cz>
1366
1367 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 1368 (grps): Delete GRPPLOCK entry.
7ffdda93 1369
cc0ec051
AM		 13702004-03-12 Alan Modra <amodra@bigpond.net.au>
1371
1372 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
1373 (M, Mp): Use OP_M.
1374 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
1375 (GRPPADLCK): Define.
1376 (dis386): Use NOP_Fixup on "nop".
1377 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
1378 (twobyte_has_modrm): Set for 0xa7.
1379 (padlock_table): Delete. Move to..
1380 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
1381 and clflush.
1382 (print_insn): Revert PADLOCK_SPECIAL code.
1383 (OP_E): Delete sfence, lfence, mfence checks.
1384
4fd61dcb
JJ		 13852004-03-12 Jakub Jelinek <jakub@redhat.com>
1386
1387 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
1388 (INVLPG_Fixup): New function.
1389 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
1390
0f10071e
ML		 13912004-03-12 Michal Ludvig <mludvig@suse.cz>
1392
1393 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
1394 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
1395 (padlock_table): New struct with PadLock instructions.
1396 (print_insn): Handle PADLOCK_SPECIAL.
1397
c02908d2
AM		 13982004-03-12 Alan Modra <amodra@bigpond.net.au>
1399
1400 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
1401 (OP_E): Twiddle clflush to sfence here.
1402
d5bb7600
NC		 14032004-03-08 Nick Clifton <nickc@redhat.com>
1404
1405 * po/de.po: Updated German translation.
1406
ae51a426
JR		 14072003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
1408
1409 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
1410 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
1411 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
1412 accordingly.
1413
676a64f4
RS		 14142004-03-01 Richard Sandiford <rsandifo@redhat.com>
1415
1416 * frv-asm.c: Regenerate.
1417 * frv-desc.c: Regenerate.
1418 * frv-desc.h: Regenerate.
1419 * frv-dis.c: Regenerate.
1420 * frv-ibld.c: Regenerate.
1421 * frv-opc.c: Regenerate.
1422 * frv-opc.h: Regenerate.
1423
c7a48b9a
RS		 14242004-03-01 Richard Sandiford <rsandifo@redhat.com>
1425
1426 * frv-desc.c, frv-opc.c: Regenerate.
1427
8ae0baa2
RS		 14282004-03-01 Richard Sandiford <rsandifo@redhat.com>
1429
1430 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
1431
ce11586c
JR		 14322004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1433
1434 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
1435 Also correct mistake in the comment.
1436
6a5709a5
JR		 14372004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1438
1439 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
1440 ensure that double registers have even numbers.
1441 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
1442 that reserved instruction 0xfffd does not decode the same
1443 as 0xfdfd (ftrv).
1444 * sh-opc.h: Add REG_N_D nibble type and use it whereever
1445 REG_N refers to a double register.
1446 Add REG_N_B01 nibble type and use it instead of REG_NM
1447 in ftrv.
1448 Adjust the bit patterns in a few comments.
1449
e5d2b64f 14502004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1451
1452 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 1453
1f04b05f
AH		 14542004-02-20 Aldy Hernandez <aldyh@redhat.com>
1455
1456 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
1457
2f3b8700
AH		 14582004-02-20 Aldy Hernandez <aldyh@redhat.com>
1459
1460 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
1461
f0b26da6 14622004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1463
1464 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
1465 mtivor32, mtivor33, mtivor34.
f0b26da6 1466
23d59c56 14672004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1468
1469 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 1470
34920d91
NC		 14712004-02-10 Petko Manolov <petkan@nucleusys.com>
1472
1473 * arm-opc.h Maverick accumulator register opcode fixes.
1474
44d86481
BE		 14752004-02-13 Ben Elliston <bje@wasabisystems.com>
1476
1477 * m32r-dis.c: Regenerate.
1478
17707c23
MS		 14792004-01-27 Michael Snyder <msnyder@redhat.com>
1480
1481 * sh-opc.h (sh_table): "fsrra", not "fssra".
1482
fe3a9bc4
NC		 14832004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
1484
1485 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
1486 contraints.
1487
ff24f124
JJ		 14882004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
1489
1490 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
1491
a02a862a
AM		 14922004-01-19 Alan Modra <amodra@bigpond.net.au>
1493
1494 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
1495 1. Don't print scale factor on AT&T mode when index missing.
1496
d164ea7f
AO		 14972004-01-16 Alexandre Oliva <aoliva@redhat.com>
1498
1499 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
1500 when loaded into XR registers.
1501
cb10e79a
RS		 15022004-01-14 Richard Sandiford <rsandifo@redhat.com>
1503
1504 * frv-desc.h: Regenerate.
1505 * frv-desc.c: Regenerate.
1506 * frv-opc.c: Regenerate.
1507
f532f3fa
MS		 15082004-01-13 Michael Snyder <msnyder@redhat.com>
1509
1510 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
1511
e45d0630
PB		 15122004-01-09 Paul Brook <paul@codesourcery.com>
1513
1514 * arm-opc.h (arm_opcodes): Move generic mcrr after known
1515 specific opcodes.
1516
3ba7a1aa
DJ		 15172004-01-07 Daniel Jacobowitz <drow@mvista.com>
1518
1519 * Makefile.am (libopcodes_la_DEPENDENCIES)
1520 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
1521 comment about the problem.
1522 * Makefile.in: Regenerate.
1523
ba2d3f07
AO		 15242004-01-06 Alexandre Oliva <aoliva@redhat.com>
1525
1526 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
1527 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
1528 cut&paste errors in shifting/truncating numerical operands.
1529 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1530 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
1531 (parse_uslo16): Likewise.
1532 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
1533 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
1534 (parse_s12): Likewise.
1535 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1536 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
1537 (parse_uslo16): Likewise.
1538 (parse_uhi16): Parse gothi and gotfuncdeschi.
1539 (parse_d12): Parse got12 and gotfuncdesc12.
1540 (parse_s12): Likewise.
1541
3ab48931
NC		 15422004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
1543
1544 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
1545 instruction which looks similar to an 'rla' instruction.
a0bd404e 1546
c9e214e5 1547For older changes see ChangeLog-0203
252b5132
RH		 1548\f
1549Local Variables:
2f6d2f85
NC		 1550mode: change-log
1551left-margin: 8
1552fill-column: 74
252b5132
RH		 1553version-control: never
1554End:
GDB Binutils - Deliverables
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