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Adds command line support for Armv8.4-A, via the new command line option -march=armv8...
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
dec41383
JW		 12017-11-08 Jiong Wang <jiong.wang@arm.com>
2 Tamar Christina <tamar.christina@arm.com>
3
4 * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
5 FP16 instructions, including vfmal.f16 and vfmsl.f16.
6
52eab766
AB		 72017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
8
9 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
10
6003e27e
AM		 112017-11-07 Alan Modra <amodra@gmail.com>
12
13 * opintl.h: Formatting, comment fixes.
14 (gettext, ngettext): Redefine when ENABLE_NLS.
15 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
16 (_): Define using gettext.
17 (textdomain, bindtextdomain): Use safer "do nothing".
18
fdddd290 192017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
20
21 * arc-dis.c (print_hex): New variable.
22 (parse_option): Check for hex option.
23 (print_insn_arc): Use hexadecimal representation for short
24 immediate values when requested.
25 (print_arc_disassembler_options): Add hex option to the list.
26
3334eba7 272017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
28
29 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
30 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
31 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
32 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
33 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
34 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
35 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
36 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
37 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
38 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
39 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
40 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
41 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
42 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
43 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
44 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
45 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
46 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
47 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
48 Changed opcodes.
49 (prealloc, prefetch*): Place them before ld instruction.
50 * arc-opc.c (skip_this_opcode): Add ARITH class.
51
e5d70d6b
AM		 522017-10-25 Alan Modra <amodra@gmail.com>
53
54 PR 22348
55 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
56 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
57 (imm4flag, size_changed): Likewise.
58 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
59 (words, allWords, processing_argument_number): Likewise.
60 (cst4flag, size_changed): Likewise.
61 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
62 (crx_cst4_maps): Rename from cst4_maps.
63 (crx_no_op_insn): Rename from no_op_insn.
64
63a25ea0
AW		 652017-10-24 Andrew Waterman <andrew@sifive.com>
66
67 * riscv-opc.c (match_c_addi16sp) : New function.
68 (match_c_addi4spn): New function.
69 (match_c_lui): Don't allow 0-immediate encodings.
70 (riscv_opcodes) <addi>: Use the above functions.
71 <add>: Likewise.
72 <c.addi4spn>: Likewise.
73 <c.addi16sp>: Likewise.
74
fe4e2a3c
IT		 752017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
76
77 * i386-init.h: Regenerate
78 * i386-tbl.h: Likewise
79
2739ef6d
IT		 802017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
81
82 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
83 (enum): Add EVEX_W_0F3854_P_2.
84 * i386-dis-evex.h (evex_table): Updated.
85 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
86 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
87 (cpu_flags): Add CpuAVX512_BITALG.
88 * i386-opc.h (enum): Add CpuAVX512_BITALG.
89 (i386_cpu_flags): Add cpuavx512_bitalg..
90 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
91 * i386-init.h: Regenerate.
92 * i386-tbl.h: Likewise.
93
942017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
95
96 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
97 * i386-dis-evex.h (evex_table): Updated.
98 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
99 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
100 (cpu_flags): Add CpuAVX512_VNNI.
101 * i386-opc.h (enum): Add CpuAVX512_VNNI.
102 (i386_cpu_flags): Add cpuavx512_vnni.
103 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
104 * i386-init.h: Regenerate.
105 * i386-tbl.h: Likewise.
106
1072017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
108
109 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
110 (enum): Remove VEX_LEN_0F3A44_P_2.
111 (vex_len_table): Ditto.
112 (enum): Remove VEX_W_0F3A44_P_2.
113 (vew_w_table): Ditto.
114 (prefix_table): Adjust instructions (see prefixes above).
115 * i386-dis-evex.h (evex_table):
116 Add new instructions (see prefixes above).
117 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
118 (bitfield_cpu_flags): Ditto.
119 * i386-opc.h (enum): Ditto.
120 (i386_cpu_flags): Ditto.
121 (CpuUnused): Comment out to avoid zero-width field problem.
122 * i386-opc.tbl (vpclmulqdq): New instruction.
123 * i386-init.h: Regenerate.
124 * i386-tbl.h: Ditto.
125
1262017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
127
128 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
129 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
130 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
131 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
132 (vex_len_table): Ditto.
133 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
134 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
135 (vew_w_table): Ditto.
136 (prefix_table): Adjust instructions (see prefixes above).
137 * i386-dis-evex.h (evex_table):
138 Add new instructions (see prefixes above).
139 * i386-gen.c (cpu_flag_init): Add VAES.
140 (bitfield_cpu_flags): Ditto.
141 * i386-opc.h (enum): Ditto.
142 (i386_cpu_flags): Ditto.
143 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
144 * i386-init.h: Regenerate.
145 * i386-tbl.h: Ditto.
146
1472017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
148
149 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
150 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
151 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
152 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
153 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
154 (prefix_table): Updated (see prefixes above).
155 (three_byte_table): Likewise.
156 (vex_w_table): Likewise.
157 * i386-dis-evex.h: Likewise.
158 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
159 (cpu_flags): Add CpuGFNI.
160 * i386-opc.h (enum): Add CpuGFNI.
161 (i386_cpu_flags): Add cpugfni.
162 * i386-opc.tbl: Add Intel GFNI instructions.
163 * i386-init.h: Regenerate.
164 * i386-tbl.h: Likewise.
165
1662017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
167
168 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
169 Define EXbScalar and EXwScalar for OP_EX.
170 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
171 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
172 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
173 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
174 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
175 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
176 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
177 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
178 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
179 (OP_E_memory): Likewise.
180 * i386-dis-evex.h: Updated.
181 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
182 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
183 (cpu_flags): Add CpuAVX512_VBMI2.
184 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
185 (i386_cpu_flags): Add cpuavx512_vbmi2.
186 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
187 * i386-init.h: Regenerate.
188 * i386-tbl.h: Likewise.
189
2a6969e1
EB		 1902017-10-18 Eric Botcazou <ebotcazou@adacore.com>
191
192 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
193
3b4b0a62
JB		 1942017-10-12 James Bowman <james.bowman@ftdichip.com>
195
196 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
197 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
198 K15. Add jmpix pattern.
199
8e464506
AK		 2002017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
201
202 * s390-opc.txt (prno, tpei, irbm): New instructions added.
203
ee6767da
AK		 2042017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
205
206 * s390-opc.c (INSTR_SI_RD): New macro.
207 (INSTR_S_RD): Adjust example instruction.
208 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
209 SI_RD.
210
d2e6c9a3
AF		 2112017-10-01 Alexander Fedotov <alfedotov@gmail.com>
212
213 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
214 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
215 VLE multimple load/store instructions. Old e_ldm* variants are
216 kept as aliases.
217 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
218
8e43602e
NC		 2192017-09-27 Nick Clifton <nickc@redhat.com>
220
221 PR 22179
222 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
223 names for the fmv.x.s and fmv.s.x instructions respectively.
224
58a0b827
NC		 2252017-09-26 do <do@nerilex.org>
226
227 PR 22123
228 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
229 be used on CPUs that have emacs support.
230
57a024f4
SDJ		 2312017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
232
233 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
234
4ec521f2
KLC		 2352017-09-09 Kamil Rytarowski <n54@gmx.com>
236
237 * nds32-asm.c: Rename __BIT() to N32_BIT().
238 * nds32-asm.h: Likewise.
239 * nds32-dis.c: Likewise.
240
4e9ac44a
L		 2412017-09-09 H.J. Lu <hongjiu.lu@intel.com>
242
243 * i386-dis.c (last_active_prefix): Removed.
244 (ckprefix): Don't set last_active_prefix.
245 (NOTRACK_Fixup): Don't check last_active_prefix.
246
b55f3386
NC		 2472017-08-31 Nick Clifton <nickc@redhat.com>
248
249 * po/fr.po: Updated French translation.
250
59e8523b
JB		 2512017-08-31 James Bowman <james.bowman@ftdichip.com>
252
253 * ft32-dis.c (print_insn_ft32): Correct display of non-address
254 fields.
255
74081948
AF		 2562017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
257 Edmar Wienskoski <edmar.wienskoski@nxp.com>
258
259 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
260 PPC_OPCODE_EFS2 flag to "e200z4" entry.
261 New entries efs2 and spe2.
262 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
263 (SPE2_OPCD_SEGS): New macro.
264 (spe2_opcd_indices): New.
265 (disassemble_init_powerpc): Handle SPE2 opcodes.
266 (lookup_spe2): New function.
267 (print_insn_powerpc): call lookup_spe2.
268 * ppc-opc.c (insert_evuimm1_ex0): New function.
269 (extract_evuimm1_ex0): Likewise.
270 (insert_evuimm_lt8): Likewise.
271 (extract_evuimm_lt8): Likewise.
272 (insert_off_spe2): Likewise.
273 (extract_off_spe2): Likewise.
274 (insert_Ddd): Likewise.
275 (extract_Ddd): Likewise.
276 (DD): New operand.
277 (EVUIMM_LT8): Likewise.
278 (EVUIMM_LT16): Adjust.
279 (MMMM): New operand.
280 (EVUIMM_1): Likewise.
281 (EVUIMM_1_EX0): Likewise.
282 (EVUIMM_2): Adjust.
283 (NNN): New operand.
284 (VX_OFF_SPE2): Likewise.
285 (BBB): Likewise.
286 (DDD): Likewise.
287 (VX_MASK_DDD): New mask.
288 (HH): New operand.
289 (VX_RA_CONST): New macro.
290 (VX_RA_CONST_MASK): Likewise.
291 (VX_RB_CONST): Likewise.
292 (VX_RB_CONST_MASK): Likewise.
293 (VX_OFF_SPE2_MASK): Likewise.
294 (VX_SPE_CRFD): Likewise.
295 (VX_SPE_CRFD_MASK VX): Likewise.
296 (VX_SPE2_CLR): Likewise.
297 (VX_SPE2_CLR_MASK): Likewise.
298 (VX_SPE2_SPLATB): Likewise.
299 (VX_SPE2_SPLATB_MASK): Likewise.
300 (VX_SPE2_OCTET): Likewise.
301 (VX_SPE2_OCTET_MASK): Likewise.
302 (VX_SPE2_DDHH): Likewise.
303 (VX_SPE2_DDHH_MASK): Likewise.
304 (VX_SPE2_HH): Likewise.
305 (VX_SPE2_HH_MASK): Likewise.
306 (VX_SPE2_EVMAR): Likewise.
307 (VX_SPE2_EVMAR_MASK): Likewise.
308 (PPCSPE2): Likewise.
309 (PPCEFS2): Likewise.
310 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
311 (powerpc_macros): Map old SPE instructions have new names
312 with the same opcodes. Add SPE2 instructions which just are
313 mapped to SPE2.
314 (spe2_opcodes): Add SPE2 opcodes.
315
b80c7270
AM		 3162017-08-23 Alan Modra <amodra@gmail.com>
317
318 * ppc-opc.c: Formatting and comment fixes. Move insert and
319 extract functions earlier, deleting forward declarations.
320 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
321 RA_MASK.
322
67d888f5
PD		 3232017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
324
325 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
326
e3c2f928
AF		 3272017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
328 Edmar Wienskoski <edmar.wienskoski@nxp.com>
329
330 * ppc-opc.c (insert_evuimm2_ex0): New function.
331 (extract_evuimm2_ex0): Likewise.
332 (insert_evuimm4_ex0): Likewise.
333 (extract_evuimm4_ex0): Likewise.
334 (insert_evuimm8_ex0): Likewise.
335 (extract_evuimm8_ex0): Likewise.
336 (insert_evuimm_lt16): Likewise.
337 (extract_evuimm_lt16): Likewise.
338 (insert_rD_rS_even): Likewise.
339 (extract_rD_rS_even): Likewise.
340 (insert_off_lsp): Likewise.
341 (extract_off_lsp): Likewise.
342 (RD_EVEN): New operand.
343 (RS_EVEN): Likewise.
344 (RSQ): Adjust.
345 (EVUIMM_LT16): New operand.
346 (HTM_SI): Adjust.
347 (EVUIMM_2_EX0): New operand.
348 (EVUIMM_4): Adjust.
349 (EVUIMM_4_EX0): New operand.
350 (EVUIMM_8): Adjust.
351 (EVUIMM_8_EX0): New operand.
352 (WS): Adjust.
353 (VX_OFF): New operand.
354 (VX_LSP): New macro.
355 (VX_LSP_MASK): Likewise.
356 (VX_LSP_OFF_MASK): Likewise.
357 (PPC_OPCODE_LSP): Likewise.
358 (vle_opcodes): Add LSP opcodes.
359 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
360
cc4a945a
JW		 3612017-08-09 Jiong Wang <jiong.wang@arm.com>
362
363 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
364 register operands in CRC instructions.
365 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
366 comments.
367
b28b8b5e
L		 3682017-08-07 H.J. Lu <hongjiu.lu@intel.com>
369
370 * disassemble.c (disassembler): Mark big and mach with
371 ATTRIBUTE_UNUSED.
372
e347efc3
MR		 3732017-08-07 Maciej W. Rozycki <macro@imgtec.com>
374
375 * disassemble.c (disassembler): Remove arch/mach/endian
376 assertions.
377
7cbc739c
NC		 3782017-07-25 Nick Clifton <nickc@redhat.com>
379
380 PR 21739
381 * arc-opc.c (insert_rhv2): Use lower case first letter in error
382 message.
383 (insert_r0): Likewise.
384 (insert_r1): Likewise.
385 (insert_r2): Likewise.
386 (insert_r3): Likewise.
387 (insert_sp): Likewise.
388 (insert_gp): Likewise.
389 (insert_pcl): Likewise.
390 (insert_blink): Likewise.
391 (insert_ilink1): Likewise.
392 (insert_ilink2): Likewise.
393 (insert_ras): Likewise.
394 (insert_rbs): Likewise.
395 (insert_rcs): Likewise.
396 (insert_simm3s): Likewise.
397 (insert_rrange): Likewise.
398 (insert_r13el): Likewise.
399 (insert_fpel): Likewise.
400 (insert_blinkel): Likewise.
401 (insert_pclel): Likewise.
402 (insert_nps_bitop_size_2b): Likewise.
403 (insert_nps_imm_offset): Likewise.
404 (insert_nps_imm_entry): Likewise.
405 (insert_nps_size_16bit): Likewise.
406 (insert_nps_##NAME##_pos): Likewise.
407 (insert_nps_##NAME): Likewise.
408 (insert_nps_bitop_ins_ext): Likewise.
409 (insert_nps_##NAME): Likewise.
410 (insert_nps_min_hofs): Likewise.
411 (insert_nps_##NAME): Likewise.
412 (insert_nps_rbdouble_64): Likewise.
413 (insert_nps_misc_imm_offset): Likewise.
414 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
415 option description.
416
7684e580
JW		 4172017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
418 Jiong Wang <jiong.wang@arm.com>
419
420 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
421 correct the print.
422 * aarch64-dis-2.c: Regenerated.
423
47826cdb
AK		 4242017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
425
426 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
427 table.
428
2d2dbad0
NC		 4292017-07-20 Nick Clifton <nickc@redhat.com>
430
431 * po/de.po: Updated German translation.
432
70b448ba 4332017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
434
435 * arc-regs.h (sec_stat): New aux register.
436 (aux_kernel_sp): Likewise.
437 (aux_sec_u_sp): Likewise.
438 (aux_sec_k_sp): Likewise.
439 (sec_vecbase_build): Likewise.
440 (nsc_table_top): Likewise.
441 (nsc_table_base): Likewise.
442 (ersec_stat): Likewise.
443 (aux_sec_except): Likewise.
444
7179e0e6
CZ		 4452017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
446
447 * arc-opc.c (extract_uimm12_20): New function.
448 (UIMM12_20): New operand.
449 (SIMM3_5_S): Adjust.
450 * arc-tbl.h (sjli): Add new instruction.
451
684d5a10
JEM		 4522017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
453 John Eric Martin <John.Martin@emmicro-us.com>
454
455 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
456 (UIMM3_23): Adjust accordingly.
457 * arc-regs.h: Add/correct jli_base register.
458 * arc-tbl.h (jli_s): Likewise.
459
de194d85
YC		 4602017-07-18 Nick Clifton <nickc@redhat.com>
461
462 PR 21775
463 * aarch64-opc.c: Fix spelling typos.
464 * i386-dis.c: Likewise.
465
0f6329bd
RB		 4662017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
467
468 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
469 max_addr_offset and octets variables to size_t.
470
429d795d
AM		 4712017-07-12 Alan Modra <amodra@gmail.com>
472
473 * po/da.po: Update from translationproject.org/latest/opcodes/.
474 * po/de.po: Likewise.
475 * po/es.po: Likewise.
476 * po/fi.po: Likewise.
477 * po/fr.po: Likewise.
478 * po/id.po: Likewise.
479 * po/it.po: Likewise.
480 * po/nl.po: Likewise.
481 * po/pt_BR.po: Likewise.
482 * po/ro.po: Likewise.
483 * po/sv.po: Likewise.
484 * po/tr.po: Likewise.
485 * po/uk.po: Likewise.
486 * po/vi.po: Likewise.
487 * po/zh_CN.po: Likewise.
488
4162bb66
AM		 4892017-07-11 Yao Qi <yao.qi@linaro.org>
490 Alan Modra <amodra@gmail.com>
491
492 * cgen.sh: Mark generated files read-only.
493 * epiphany-asm.c: Regenerate.
494 * epiphany-desc.c: Regenerate.
495 * epiphany-desc.h: Regenerate.
496 * epiphany-dis.c: Regenerate.
497 * epiphany-ibld.c: Regenerate.
498 * epiphany-opc.c: Regenerate.
499 * epiphany-opc.h: Regenerate.
500 * fr30-asm.c: Regenerate.
501 * fr30-desc.c: Regenerate.
502 * fr30-desc.h: Regenerate.
503 * fr30-dis.c: Regenerate.
504 * fr30-ibld.c: Regenerate.
505 * fr30-opc.c: Regenerate.
506 * fr30-opc.h: Regenerate.
507 * frv-asm.c: Regenerate.
508 * frv-desc.c: Regenerate.
509 * frv-desc.h: Regenerate.
510 * frv-dis.c: Regenerate.
511 * frv-ibld.c: Regenerate.
512 * frv-opc.c: Regenerate.
513 * frv-opc.h: Regenerate.
514 * ip2k-asm.c: Regenerate.
515 * ip2k-desc.c: Regenerate.
516 * ip2k-desc.h: Regenerate.
517 * ip2k-dis.c: Regenerate.
518 * ip2k-ibld.c: Regenerate.
519 * ip2k-opc.c: Regenerate.
520 * ip2k-opc.h: Regenerate.
521 * iq2000-asm.c: Regenerate.
522 * iq2000-desc.c: Regenerate.
523 * iq2000-desc.h: Regenerate.
524 * iq2000-dis.c: Regenerate.
525 * iq2000-ibld.c: Regenerate.
526 * iq2000-opc.c: Regenerate.
527 * iq2000-opc.h: Regenerate.
528 * lm32-asm.c: Regenerate.
529 * lm32-desc.c: Regenerate.
530 * lm32-desc.h: Regenerate.
531 * lm32-dis.c: Regenerate.
532 * lm32-ibld.c: Regenerate.
533 * lm32-opc.c: Regenerate.
534 * lm32-opc.h: Regenerate.
535 * lm32-opinst.c: Regenerate.
536 * m32c-asm.c: Regenerate.
537 * m32c-desc.c: Regenerate.
538 * m32c-desc.h: Regenerate.
539 * m32c-dis.c: Regenerate.
540 * m32c-ibld.c: Regenerate.
541 * m32c-opc.c: Regenerate.
542 * m32c-opc.h: Regenerate.
543 * m32r-asm.c: Regenerate.
544 * m32r-desc.c: Regenerate.
545 * m32r-desc.h: Regenerate.
546 * m32r-dis.c: Regenerate.
547 * m32r-ibld.c: Regenerate.
548 * m32r-opc.c: Regenerate.
549 * m32r-opc.h: Regenerate.
550 * m32r-opinst.c: Regenerate.
551 * mep-asm.c: Regenerate.
552 * mep-desc.c: Regenerate.
553 * mep-desc.h: Regenerate.
554 * mep-dis.c: Regenerate.
555 * mep-ibld.c: Regenerate.
556 * mep-opc.c: Regenerate.
557 * mep-opc.h: Regenerate.
558 * mt-asm.c: Regenerate.
559 * mt-desc.c: Regenerate.
560 * mt-desc.h: Regenerate.
561 * mt-dis.c: Regenerate.
562 * mt-ibld.c: Regenerate.
563 * mt-opc.c: Regenerate.
564 * mt-opc.h: Regenerate.
565 * or1k-asm.c: Regenerate.
566 * or1k-desc.c: Regenerate.
567 * or1k-desc.h: Regenerate.
568 * or1k-dis.c: Regenerate.
569 * or1k-ibld.c: Regenerate.
570 * or1k-opc.c: Regenerate.
571 * or1k-opc.h: Regenerate.
572 * or1k-opinst.c: Regenerate.
573 * xc16x-asm.c: Regenerate.
574 * xc16x-desc.c: Regenerate.
575 * xc16x-desc.h: Regenerate.
576 * xc16x-dis.c: Regenerate.
577 * xc16x-ibld.c: Regenerate.
578 * xc16x-opc.c: Regenerate.
579 * xc16x-opc.h: Regenerate.
580 * xstormy16-asm.c: Regenerate.
581 * xstormy16-desc.c: Regenerate.
582 * xstormy16-desc.h: Regenerate.
583 * xstormy16-dis.c: Regenerate.
584 * xstormy16-ibld.c: Regenerate.
585 * xstormy16-opc.c: Regenerate.
586 * xstormy16-opc.h: Regenerate.
587
7639175c
AM		 5882017-07-07 Alan Modra <amodra@gmail.com>
589
590 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
591 * m32c-dis.c: Regenerate.
592 * mep-dis.c: Regenerate.
593
e4bdd679
BP		 5942017-07-05 Borislav Petkov <bp@suse.de>
595
596 * i386-dis.c: Enable ModRM.reg /6 aliases.
597
60c96dbf
RR		 5982017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
599
600 * opcodes/arm-dis.c: Support MVFR2 in disassembly
601 with vmrs and vmsr.
602
0d702cfe
TG		 6032017-07-04 Tristan Gingold <gingold@adacore.com>
604
605 * configure: Regenerate.
606
15e6ed8c
TG		 6072017-07-03 Tristan Gingold <gingold@adacore.com>
608
609 * po/opcodes.pot: Regenerate.
610
b1d3c886
MR		 6112017-06-30 Maciej W. Rozycki <macro@imgtec.com>
612
613 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
614 entries to the MSA ASE instruction block.
615
909b4e3d
MR		 6162017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
617 Maciej W. Rozycki <macro@imgtec.com>
618
619 * micromips-opc.c (XPA, XPAVZ): New macros.
620 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
621 "mthgc0".
622
f5b2fd52
MR		 6232017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
624 Maciej W. Rozycki <macro@imgtec.com>
625
626 * micromips-opc.c (I36): New macro.
627 (micromips_opcodes): Add "eretnc".
628
9785fc2a
MR		 6292017-06-30 Maciej W. Rozycki <macro@imgtec.com>
630 Andrew Bennett <andrew.bennett@imgtec.com>
631
632 * mips-dis.c (mips_calculate_combination_ases): Handle the
633 ASE_XPA_VIRT flag.
634 (parse_mips_ase_option): New function.
635 (parse_mips_dis_option): Factor out ASE option handling to the
636 new function. Call `mips_calculate_combination_ases'.
637 * mips-opc.c (XPAVZ): New macro.
638 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
639 "mfhgc0", "mthc0" and "mthgc0".
640
60804c53
MR		 6412017-06-29 Maciej W. Rozycki <macro@imgtec.com>
642
643 * mips-dis.c (mips_calculate_combination_ases): New function.
644 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
645 calculation to the new function.
646 (set_default_mips_dis_options): Call the new function.
647
2e74f9dd
AK		 6482017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
649
650 * arc-dis.c (parse_disassembler_options): Use
651 FOR_EACH_DISASSEMBLER_OPTION.
652
e1e94c49
AK		 6532017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
654
655 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
656 disassembler option strings.
657 (parse_cpu_option): Likewise.
658
65a55fbb
TC		 6592017-06-28 Tamar Christina <tamar.christina@arm.com>
660
661 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
662 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
663 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
664 (aarch64_feature_dotprod, DOT_INSN): New.
665 (udot, sdot): New.
666 * aarch64-dis-2.c: Regenerated.
667
c604a79a
JW		 6682017-06-28 Jiong Wang <jiong.wang@arm.com>
669
670 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
671
38bf472a
MR		 6722017-06-28 Maciej W. Rozycki <macro@imgtec.com>
673 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 674 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 675
676 * mips-formats.h (INT_BIAS): New macro.
677 (INT_ADJ): Redefine in INT_BIAS terms.
678 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
679 (mips_print_save_restore): New function.
680 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
681 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
682 call.
683 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
684 (print_mips16_insn_arg): Call `mips_print_save_restore' for
685 OP_SAVE_RESTORE_LIST handling, factored out from here.
686 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
687 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
688 (mips_builtin_opcodes): Add "restore" and "save" entries.
689 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
690 (IAMR2): New macro.
691 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
692
9bdfdbf9
AW		 6932017-06-23 Andrew Waterman <andrew@sifive.com>
694
695 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
696 alias; do not mark SLTI instruction as an alias.
697
2234eee6
L		 6982017-06-21 H.J. Lu <hongjiu.lu@intel.com>
699
700 * i386-dis.c (RM_0FAE_REG_5): Removed.
701 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
702 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
703 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
704 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
705 PREFIX_MOD_3_0F01_REG_5_RM_0.
706 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
707 PREFIX_MOD_3_0FAE_REG_5.
708 (mod_table): Update MOD_0FAE_REG_5.
709 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
710 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
711 * i386-tbl.h: Regenerated.
712
c2f76402
L		 7132017-06-21 H.J. Lu <hongjiu.lu@intel.com>
714
715 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
716 * i386-opc.tbl: Likewise.
717 * i386-tbl.h: Regenerated.
718
9fef80d6
L		 7192017-06-21 H.J. Lu <hongjiu.lu@intel.com>
720
721 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
722 and "jmp{&|}".
723 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
724 prefix.
725
0f6d864d
NC		 7262017-06-19 Nick Clifton <nickc@redhat.com>
727
728 PR binutils/21614
729 * score-dis.c (score_opcodes): Add sentinel.
730
e197589b
AM		 7312017-06-16 Alan Modra <amodra@gmail.com>
732
733 * rx-decode.c: Regenerate.
734
0d96e4df
L		 7352017-06-15 H.J. Lu <hongjiu.lu@intel.com>
736
737 PR binutils/21594
738 * i386-dis.c (OP_E_register): Check valid bnd register.
739 (OP_G): Likewise.
740
cd3ea7c6
NC		 7412017-06-15 Nick Clifton <nickc@redhat.com>
742
743 PR binutils/21595
744 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
745 range value.
746
63323b5b
NC		 7472017-06-15 Nick Clifton <nickc@redhat.com>
748
749 PR binutils/21588
750 * rl78-decode.opc (OP_BUF_LEN): Define.
751 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
752 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
753 array.
754 * rl78-decode.c: Regenerate.
755
08c7881b
NC		 7562017-06-15 Nick Clifton <nickc@redhat.com>
757
758 PR binutils/21586
759 * bfin-dis.c (gregs): Clip index to prevent overflow.
760 (regs): Likewise.
761 (regs_lo): Likewise.
762 (regs_hi): Likewise.
763
e64519d1
NC		 7642017-06-14 Nick Clifton <nickc@redhat.com>
765
766 PR binutils/21576
767 * score7-dis.c (score_opcodes): Add sentinel.
768
6394c606
YQ		 7692017-06-14 Yao Qi <yao.qi@linaro.org>
770
771 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
772 * arm-dis.c: Likewise.
773 * ia64-dis.c: Likewise.
774 * mips-dis.c: Likewise.
775 * spu-dis.c: Likewise.
776 * disassemble.h (print_insn_aarch64): New declaration, moved from
777 include/dis-asm.h.
778 (print_insn_big_arm, print_insn_big_mips): Likewise.
779 (print_insn_i386, print_insn_ia64): Likewise.
780 (print_insn_little_arm, print_insn_little_mips): Likewise.
781
db5fa770
NC		 7822017-06-14 Nick Clifton <nickc@redhat.com>
783
784 PR binutils/21587
785 * rx-decode.opc: Include libiberty.h
786 (GET_SCALE): New macro - validates access to SCALE array.
787 (GET_PSCALE): New macro - validates access to PSCALE array.
788 (DIs, SIs, S2Is, rx_disp): Use new macros.
789 * rx-decode.c: Regenerate.
790
05c966f3
AV		 7912017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
792
793 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
794
10045478
AK		 7952017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
796
797 * arc-dis.c (enforced_isa_mask): Declare.
798 (cpu_types): Likewise.
799 (parse_cpu_option): New function.
800 (parse_disassembler_options): Use it.
801 (print_insn_arc): Use enforced_isa_mask.
802 (print_arc_disassembler_options): Document new options.
803
88c1242d
YQ		 8042017-05-24 Yao Qi <yao.qi@linaro.org>
805
806 * alpha-dis.c: Include disassemble.h, don't include
807 dis-asm.h.
808 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
809 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
810 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
811 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
812 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
813 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
814 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
815 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
816 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
817 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
818 * moxie-dis.c, msp430-dis.c, mt-dis.c:
819 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
820 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
821 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
822 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
823 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
824 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
825 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
826 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
827 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
828 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
829 * z80-dis.c, z8k-dis.c: Likewise.
830 * disassemble.h: New file.
831
ab20fa4a
YQ		 8322017-05-24 Yao Qi <yao.qi@linaro.org>
833
834 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
835 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
836
003ca0fd
YQ		 8372017-05-24 Yao Qi <yao.qi@linaro.org>
838
839 * disassemble.c (disassembler): Add arguments a, big and mach.
840 Use them.
841
04ef582a
L		 8422017-05-22 H.J. Lu <hongjiu.lu@intel.com>
843
844 * i386-dis.c (NOTRACK_Fixup): New.
845 (NOTRACK): Likewise.
846 (NOTRACK_PREFIX): Likewise.
847 (last_active_prefix): Likewise.
848 (reg_table): Use NOTRACK on indirect call and jmp.
849 (ckprefix): Set last_active_prefix.
850 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
851 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
852 * i386-opc.h (NoTrackPrefixOk): New.
853 (i386_opcode_modifier): Add notrackprefixok.
854 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
855 Add notrack.
856 * i386-tbl.h: Regenerated.
857
64517994
JM		 8582017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
859
860 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
861 (X_IMM2): Define.
862 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
863 bfd_mach_sparc_v9m8.
864 (print_insn_sparc): Handle new operand types.
865 * sparc-opc.c (MASK_M8): Define.
866 (v6): Add MASK_M8.
867 (v6notlet): Likewise.
868 (v7): Likewise.
869 (v8): Likewise.
870 (v9): Likewise.
871 (v9a): Likewise.
872 (v9b): Likewise.
873 (v9c): Likewise.
874 (v9d): Likewise.
875 (v9e): Likewise.
876 (v9v): Likewise.
877 (v9m): Likewise.
878 (v9andleon): Likewise.
879 (m8): Define.
880 (HWS_VM8): Define.
881 (HWS2_VM8): Likewise.
882 (sparc_opcode_archs): Add entry for "m8".
883 (sparc_opcodes): Add OSA2017 and M8 instructions
884 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
885 fpx{ll,ra,rl}64x,
886 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
887 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
888 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
889 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
890 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
891 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
892 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
893 ASI_CORE_SELECT_COMMIT_NHT.
894
535b785f
AM		 8952017-05-18 Alan Modra <amodra@gmail.com>
896
897 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
898 * aarch64-dis.c: Likewise.
899 * aarch64-gen.c: Likewise.
900 * aarch64-opc.c: Likewise.
901
25499ac7
MR		 9022017-05-15 Maciej W. Rozycki <macro@imgtec.com>
903 Matthew Fortune <matthew.fortune@imgtec.com>
904
905 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
906 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
907 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
908 (print_insn_arg) <OP_REG28>: Add handler.
909 (validate_insn_args) <OP_REG28>: Handle.
910 (print_mips16_insn_arg): Handle MIPS16 instructions that require
911 32-bit encoding and 9-bit immediates.
912 (print_insn_mips16): Handle MIPS16 instructions that require
913 32-bit encoding and MFC0/MTC0 operand decoding.
914 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
915 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
916 (RD_C0, WR_C0, E2, E2MT): New macros.
917 (mips16_opcodes): Add entries for MIPS16e2 instructions:
918 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
919 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
920 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
921 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
922 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
923 instructions, "swl", "swr", "sync" and its "sync_acquire",
924 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
925 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
926 regular/extended entries for original MIPS16 ISA revision
927 instructions whose extended forms are subdecoded in the MIPS16e2
928 ISA revision: "li", "sll" and "srl".
929
fdfb4752
MR		 9302017-05-15 Maciej W. Rozycki <macro@imgtec.com>
931
932 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
933 reference in CP0 move operand decoding.
934
a4f89915
MR		 9352017-05-12 Maciej W. Rozycki <macro@imgtec.com>
936
937 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
938 type to hexadecimal.
939 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
940
99e2d67a
MR		 9412017-05-11 Maciej W. Rozycki <macro@imgtec.com>
942
943 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
944 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
945 "sync_rmb" and "sync_wmb" as aliases.
946 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
947 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
948
53a346d8
CZ		 9492017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
950
951 * arc-dis.c (parse_option): Update quarkse_em option..
952 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
953 QUARKSE1.
954 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
955
f91d48de
KC		 9562017-05-03 Kito Cheng <kito.cheng@gmail.com>
957
958 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
959
43e379d7
MC		 9602017-05-01 Michael Clark <michaeljclark@mac.com>
961
962 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
963 register.
964
a4ddc54e
MR		 9652017-05-02 Maciej W. Rozycki <macro@imgtec.com>
966
967 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
968 and branches and not synthetic data instructions.
969
fe50e98c
BE		 9702017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
971
972 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
973
126124cc
CZ		 9742017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
975
976 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
977 * arc-opc.c (insert_r13el): New function.
978 (R13_EL): Define.
979 * arc-tbl.h: Add new enter/leave variants.
980
be6a24d8
CZ		 9812017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
982
983 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
984
0348fd79
MR		 9852017-04-25 Maciej W. Rozycki <macro@imgtec.com>
986
987 * mips-dis.c (print_mips_disassembler_options): Add
988 `no-aliases'.
989
6e3d1f07
MR		 9902017-04-25 Maciej W. Rozycki <macro@imgtec.com>
991
992 * mips16-opc.c (AL): New macro.
993 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
994 of "ld" and "lw" as aliases.
995
957f6b39
TC		 9962017-04-24 Tamar Christina <tamar.christina@arm.com>
997
998 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
999 arguments.
1000
a8cc8a54
AM		 10012017-04-22 Alexander Fedotov <alfedotov@gmail.com>
1002 Alan Modra <amodra@gmail.com>
1003
1004 * ppc-opc.c (ELEV): Define.
1005 (vle_opcodes): Add se_rfgi and e_sc.
1006 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1007 for E200Z4.
1008
3ab87b68
JM		 10092017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1010
1011 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1012
792f174f
NC		 10132017-04-21 Nick Clifton <nickc@redhat.com>
1014
1015 PR binutils/21380
1016 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1017 LD3R and LD4R.
1018
42742084
AM		 10192017-04-13 Alan Modra <amodra@gmail.com>
1020
1021 * epiphany-desc.c: Regenerate.
1022 * fr30-desc.c: Regenerate.
1023 * frv-desc.c: Regenerate.
1024 * ip2k-desc.c: Regenerate.
1025 * iq2000-desc.c: Regenerate.
1026 * lm32-desc.c: Regenerate.
1027 * m32c-desc.c: Regenerate.
1028 * m32r-desc.c: Regenerate.
1029 * mep-desc.c: Regenerate.
1030 * mt-desc.c: Regenerate.
1031 * or1k-desc.c: Regenerate.
1032 * xc16x-desc.c: Regenerate.
1033 * xstormy16-desc.c: Regenerate.
1034
9a85b496
AM		 10352017-04-11 Alan Modra <amodra@gmail.com>
1036
ef85eab0 1037 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 1038 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1039 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 1040 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1041 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 1042 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1043 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 1044 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 1045 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 1046
62adc510
AM		 10472017-04-10 Alan Modra <amodra@gmail.com>
1048
1049 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1050 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1051 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1052 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1053
aa808707
PC		 10542017-04-09 Pip Cet <pipcet@gmail.com>
1055
1056 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1057 appropriate floating-point precision directly.
1058
ac8f0f72
AM		 10592017-04-07 Alan Modra <amodra@gmail.com>
1060
1061 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1062 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1063 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1064 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1065 vector instructions with E6500 not PPCVEC2.
1066
62ecb94c
PC		 10672017-04-06 Pip Cet <pipcet@gmail.com>
1068
1069 * Makefile.am: Add wasm32-dis.c.
1070 * configure.ac: Add wasm32-dis.c to wasm32 target.
1071 * disassemble.c: Add wasm32 disassembler code.
1072 * wasm32-dis.c: New file.
1073 * Makefile.in: Regenerate.
1074 * configure: Regenerate.
1075 * po/POTFILES.in: Regenerate.
1076 * po/opcodes.pot: Regenerate.
1077
f995bbe8
PA		 10782017-04-05 Pedro Alves <palves@redhat.com>
1079
1080 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1081 * arm-dis.c (parse_arm_disassembler_options): Constify.
1082 * ppc-dis.c (powerpc_init_dialect): Constify local.
1083 * vax-dis.c (parse_disassembler_options): Constify.
1084
b5292032
PD		 10852017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1086
1087 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1088 RISCV_GP_SYMBOL.
1089
f96bd6c2
PC		 10902017-03-30 Pip Cet <pipcet@gmail.com>
1091
1092 * configure.ac: Add (empty) bfd_wasm32_arch target.
1093 * configure: Regenerate
1094 * po/opcodes.pot: Regenerate.
1095
f7c514a3
JM		 10962017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1097
1098 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1099 OSA2015.
1100 * opcodes/sparc-opc.c (asi_table): New ASIs.
1101
52be03fd
AM		 11022017-03-29 Alan Modra <amodra@gmail.com>
1103
1104 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1105 "raw" option.
1106 (lookup_powerpc): Don't special case -1 dialect. Handle
1107 PPC_OPCODE_RAW.
1108 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1109 lookup_powerpc call, pass it on second.
1110
9b753937
AM		 11112017-03-27 Alan Modra <amodra@gmail.com>
1112
1113 PR 21303
1114 * ppc-dis.c (struct ppc_mopt): Comment.
1115 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1116
c0c31e91
RZ		 11172017-03-27 Rinat Zelig <rinat@mellanox.com>
1118
1119 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1120 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1121 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1122 (insert_nps_misc_imm_offset): New function.
1123 (extract_nps_misc imm_offset): New function.
1124 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1125 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1126
2253c8f0
AK		 11272017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1128
1129 * s390-mkopc.c (main): Remove vx2 check.
1130 * s390-opc.txt: Remove vx2 instruction flags.
1131
645d3342
RZ		 11322017-03-21 Rinat Zelig <rinat@mellanox.com>
1133
1134 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1135 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1136 (insert_nps_imm_offset): New function.
1137 (extract_nps_imm_offset): New function.
1138 (insert_nps_imm_entry): New function.
1139 (extract_nps_imm_entry): New function.
1140
4b94dd2d
AM		 11412017-03-17 Alan Modra <amodra@gmail.com>
1142
1143 PR 21248
1144 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1145 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1146 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1147
b416fe87
KC		 11482017-03-14 Kito Cheng <kito.cheng@gmail.com>
1149
1150 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1151 <c.andi>: Likewise.
1152 <c.addiw> Likewise.
1153
03b039a5
KC		 11542017-03-14 Kito Cheng <kito.cheng@gmail.com>
1155
1156 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1157
2c232b83
AW		 11582017-03-13 Andrew Waterman <andrew@sifive.com>
1159
1160 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1161 <srl> Likewise.
1162 <srai> Likewise.
1163 <sra> Likewise.
1164
86fa6981
L		 11652017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1166
1167 * i386-gen.c (opcode_modifiers): Replace S with Load.
1168 * i386-opc.h (S): Removed.
1169 (Load): New.
1170 (i386_opcode_modifier): Replace s with load.
1171 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1172 and {evex}. Replace S with Load.
1173 * i386-tbl.h: Regenerated.
1174
c1fe188b
L		 11752017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1176
1177 * i386-opc.tbl: Use CpuCET on rdsspq.
1178 * i386-tbl.h: Regenerated.
1179
4b8b687e
PB		 11802017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1181
1182 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1183 <vsx>: Do not use PPC_OPCODE_VSX3;
1184
1437d063
PB		 11852017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1186
1187 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1188
603555e5
L		 11892017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1190
1191 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1192 (MOD_0F1E_PREFIX_1): Likewise.
1193 (MOD_0F38F5_PREFIX_2): Likewise.
1194 (MOD_0F38F6_PREFIX_0): Likewise.
1195 (RM_0F1E_MOD_3_REG_7): Likewise.
1196 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1197 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1198 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1199 (PREFIX_0F1E): Likewise.
1200 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1201 (PREFIX_0F38F5): Likewise.
1202 (dis386_twobyte): Use PREFIX_0F1E.
1203 (reg_table): Add REG_0F1E_MOD_3.
1204 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1205 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1206 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1207 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1208 (three_byte_table): Use PREFIX_0F38F5.
1209 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1210 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1211 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1212 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1213 PREFIX_MOD_3_0F01_REG_5_RM_2.
1214 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1215 (cpu_flags): Add CpuCET.
1216 * i386-opc.h (CpuCET): New enum.
1217 (CpuUnused): Commented out.
1218 (i386_cpu_flags): Add cpucet.
1219 * i386-opc.tbl: Add Intel CET instructions.
1220 * i386-init.h: Regenerated.
1221 * i386-tbl.h: Likewise.
1222
73f07bff
AM		 12232017-03-06 Alan Modra <amodra@gmail.com>
1224
1225 PR 21124
1226 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1227 (extract_raq, extract_ras, extract_rbx): New functions.
1228 (powerpc_operands): Use opposite corresponding insert function.
1229 (Q_MASK): Define.
1230 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1231 register restriction.
1232
65b48a81
PB		 12332017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1234
1235 * disassemble.c Include "safe-ctype.h".
1236 (disassemble_init_for_target): Handle s390 init.
1237 (remove_whitespace_and_extra_commas): New function.
1238 (disassembler_options_cmp): Likewise.
1239 * arm-dis.c: Include "libiberty.h".
1240 (NUM_ELEM): Delete.
1241 (regnames): Use long disassembler style names.
1242 Add force-thumb and no-force-thumb options.
1243 (NUM_ARM_REGNAMES): Rename from this...
1244 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1245 (get_arm_regname_num_options): Delete.
1246 (set_arm_regname_option): Likewise.
1247 (get_arm_regnames): Likewise.
1248 (parse_disassembler_options): Likewise.
1249 (parse_arm_disassembler_option): Rename from this...
1250 (parse_arm_disassembler_options): ...to this. Make static.
1251 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1252 (print_insn): Use parse_arm_disassembler_options.
1253 (disassembler_options_arm): New function.
1254 (print_arm_disassembler_options): Handle updated regnames.
1255 * ppc-dis.c: Include "libiberty.h".
1256 (ppc_opts): Add "32" and "64" entries.
1257 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1258 (powerpc_init_dialect): Add break to switch statement.
1259 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1260 (disassembler_options_powerpc): New function.
1261 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1262 Remove printing of "32" and "64".
1263 * s390-dis.c: Include "libiberty.h".
1264 (init_flag): Remove unneeded variable.
1265 (struct s390_options_t): New structure type.
1266 (options): New structure.
1267 (init_disasm): Rename from this...
1268 (disassemble_init_s390): ...to this. Add initializations for
1269 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1270 (print_insn_s390): Delete call to init_disasm.
1271 (disassembler_options_s390): New function.
1272 (print_s390_disassembler_options): Print using information from
1273 struct 'options'.
1274 * po/opcodes.pot: Regenerate.
1275
15c7c1d8
JB		 12762017-02-28 Jan Beulich <jbeulich@suse.com>
1277
1278 * i386-dis.c (PCMPESTR_Fixup): New.
1279 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1280 (prefix_table): Use PCMPESTR_Fixup.
1281 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1282 PCMPESTR_Fixup.
1283 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1284 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1285 Split 64-bit and non-64-bit variants.
1286 * opcodes/i386-tbl.h: Re-generate.
1287
582e12bf
RS		 12882017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1289
1290 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1291 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1292 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1293 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1294 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1295 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1296 (OP_SVE_V_HSD): New macros.
1297 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1298 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1299 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1300 (aarch64_opcode_table): Add new SVE instructions.
1301 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1302 for rotation operands. Add new SVE operands.
1303 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1304 (ins_sve_quad_index): Likewise.
1305 (ins_imm_rotate): Split into...
1306 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1307 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1308 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1309 functions.
1310 (aarch64_ins_sve_addr_ri_s4): New function.
1311 (aarch64_ins_sve_quad_index): Likewise.
1312 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1313 * aarch64-asm-2.c: Regenerate.
1314 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1315 (ext_sve_quad_index): Likewise.
1316 (ext_imm_rotate): Split into...
1317 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1318 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1319 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1320 functions.
1321 (aarch64_ext_sve_addr_ri_s4): New function.
1322 (aarch64_ext_sve_quad_index): Likewise.
1323 (aarch64_ext_sve_index): Allow quad indices.
1324 (do_misc_decoding): Likewise.
1325 * aarch64-dis-2.c: Regenerate.
1326 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1327 aarch64_field_kinds.
1328 (OPD_F_OD_MASK): Widen by one bit.
1329 (OPD_F_NO_ZR): Bump accordingly.
1330 (get_operand_field_width): New function.
1331 * aarch64-opc.c (fields): Add new SVE fields.
1332 (operand_general_constraint_met_p): Handle new SVE operands.
1333 (aarch64_print_operand): Likewise.
1334 * aarch64-opc-2.c: Regenerate.
1335
f482d304
RS		 13362017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1337
1338 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1339 (aarch64_feature_compnum): ...this.
1340 (SIMD_V8_3): Replace with...
1341 (COMPNUM): ...this.
1342 (CNUM_INSN): New macro.
1343 (aarch64_opcode_table): Use it for the complex number instructions.
1344
7db2c588
JB		 13452017-02-24 Jan Beulich <jbeulich@suse.com>
1346
1347 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1348
1e9d41d4
SL		 13492017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1350
1351 Add support for associating SPARC ASIs with an architecture level.
1352 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1353 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1354 decoding of SPARC ASIs.
1355
53c4d625
JB		 13562017-02-23 Jan Beulich <jbeulich@suse.com>
1357
1358 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1359 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1360
11648de5
JB		 13612017-02-21 Jan Beulich <jbeulich@suse.com>
1362
1363 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1364 1 (instead of to itself). Correct typo.
1365
f98d33be
AW		 13662017-02-14 Andrew Waterman <andrew@sifive.com>
1367
1368 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1369 pseudoinstructions.
1370
773fb663
RS		 13712017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1372
1373 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1374 (aarch64_sys_reg_supported_p): Handle them.
1375
cc07cda6
CZ		 13762017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1377
1378 * arc-opc.c (UIMM6_20R): Define.
1379 (SIMM12_20): Use above.
1380 (SIMM12_20R): Define.
1381 (SIMM3_5_S): Use above.
1382 (UIMM7_A32_11R_S): Define.
1383 (UIMM7_9_S): Use above.
1384 (UIMM3_13R_S): Define.
1385 (SIMM11_A32_7_S): Use above.
1386 (SIMM9_8R): Define.
1387 (UIMM10_A32_8_S): Use above.
1388 (UIMM8_8R_S): Define.
1389 (W6): Use above.
1390 (arc_relax_opcodes): Use all above defines.
1391
66a5a740
VG		 13922017-02-15 Vineet Gupta <vgupta@synopsys.com>
1393
1394 * arc-regs.h: Distinguish some of the registers different on
1395 ARC700 and HS38 cpus.
1396
7e0de605
AM		 13972017-02-14 Alan Modra <amodra@gmail.com>
1398
1399 PR 21118
1400 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1401 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1402
54064fdb
AM		 14032017-02-11 Stafford Horne <shorne@gmail.com>
1404 Alan Modra <amodra@gmail.com>
1405
1406 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1407 Use insn_bytes_value and insn_int_value directly instead. Don't
1408 free allocated memory until function exit.
1409
dce75bf9
NP		 14102017-02-10 Nicholas Piggin <npiggin@gmail.com>
1411
1412 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1413
1b7e3d2f
NC		 14142017-02-03 Nick Clifton <nickc@redhat.com>
1415
1416 PR 21096
1417 * aarch64-opc.c (print_register_list): Ensure that the register
1418 list index will fir into the tb buffer.
1419 (print_register_offset_address): Likewise.
1420 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1421
8ec5cf65
AD		 14222017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1423
1424 PR 21056
1425 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1426 instructions when the previous fetch packet ends with a 32-bit
1427 instruction.
1428
a1aa5e81
DD		 14292017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1430
1431 * pru-opc.c: Remove vague reference to a future GDB port.
1432
add3afb2
NC		 14332017-01-20 Nick Clifton <nickc@redhat.com>
1434
1435 * po/ga.po: Updated Irish translation.
1436
c13a63b0
SN		 14372017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1438
1439 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1440
9608051a
YQ		 14412017-01-13 Yao Qi <yao.qi@linaro.org>
1442
1443 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1444 if FETCH_DATA returns 0.
1445 (m68k_scan_mask): Likewise.
1446 (print_insn_m68k): Update code to handle -1 return value.
1447
f622ea96
YQ		 14482017-01-13 Yao Qi <yao.qi@linaro.org>
1449
1450 * m68k-dis.c (enum print_insn_arg_error): New.
1451 (NEXTBYTE): Replace -3 with
1452 PRINT_INSN_ARG_MEMORY_ERROR.
1453 (NEXTULONG): Likewise.
1454 (NEXTSINGLE): Likewise.
1455 (NEXTDOUBLE): Likewise.
1456 (NEXTDOUBLE): Likewise.
1457 (NEXTPACKED): Likewise.
1458 (FETCH_ARG): Likewise.
1459 (FETCH_DATA): Update comments.
1460 (print_insn_arg): Update comments. Replace magic numbers with
1461 enum.
1462 (match_insn_m68k): Likewise.
1463
620214f7
IT		 14642017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1465
1466 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1467 * i386-dis-evex.h (evex_table): Updated.
1468 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1469 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1470 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1471 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1472 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1473 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1474 * i386-init.h: Regenerate.
1475 * i386-tbl.h: Ditto.
1476
d95014a2
YQ		 14772017-01-12 Yao Qi <yao.qi@linaro.org>
1478
1479 * msp430-dis.c (msp430_singleoperand): Return -1 if
1480 msp430dis_opcode_signed returns false.
1481 (msp430_doubleoperand): Likewise.
1482 (msp430_branchinstr): Return -1 if
1483 msp430dis_opcode_unsigned returns false.
1484 (msp430x_calla_instr): Likewise.
1485 (print_insn_msp430): Likewise.
1486
0ae60c3e
NC		 14872017-01-05 Nick Clifton <nickc@redhat.com>
1488
1489 PR 20946
1490 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1491 could not be matched.
1492 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1493 NULL.
1494
d74d4880
SN		 14952017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1496
1497 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1498 (aarch64_opcode_table): Use RCPC_INSN.
1499
cc917fd9
KC		 15002017-01-03 Kito Cheng <kito.cheng@gmail.com>
1501
1502 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1503 extension.
1504 * riscv-opcodes/all-opcodes: Likewise.
1505
b52d3cfc
DP		 15062017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1507
1508 * riscv-dis.c (print_insn_args): Add fall through comment.
1509
f90c58d5
NC		 15102017-01-03 Nick Clifton <nickc@redhat.com>
1511
1512 * po/sr.po: New Serbian translation.
1513 * configure.ac (ALL_LINGUAS): Add sr.
1514 * configure: Regenerate.
1515
f47b0d4a
AM		 15162017-01-02 Alan Modra <amodra@gmail.com>
1517
1518 * epiphany-desc.h: Regenerate.
1519 * epiphany-opc.h: Regenerate.
1520 * fr30-desc.h: Regenerate.
1521 * fr30-opc.h: Regenerate.
1522 * frv-desc.h: Regenerate.
1523 * frv-opc.h: Regenerate.
1524 * ip2k-desc.h: Regenerate.
1525 * ip2k-opc.h: Regenerate.
1526 * iq2000-desc.h: Regenerate.
1527 * iq2000-opc.h: Regenerate.
1528 * lm32-desc.h: Regenerate.
1529 * lm32-opc.h: Regenerate.
1530 * m32c-desc.h: Regenerate.
1531 * m32c-opc.h: Regenerate.
1532 * m32r-desc.h: Regenerate.
1533 * m32r-opc.h: Regenerate.
1534 * mep-desc.h: Regenerate.
1535 * mep-opc.h: Regenerate.
1536 * mt-desc.h: Regenerate.
1537 * mt-opc.h: Regenerate.
1538 * or1k-desc.h: Regenerate.
1539 * or1k-opc.h: Regenerate.
1540 * xc16x-desc.h: Regenerate.
1541 * xc16x-opc.h: Regenerate.
1542 * xstormy16-desc.h: Regenerate.
1543 * xstormy16-opc.h: Regenerate.
1544
2571583a
AM		 15452017-01-02 Alan Modra <amodra@gmail.com>
1546
1547 Update year range in copyright notice of all files.
1548
5c1ad6b5 1549For older changes see ChangeLog-2016
3499769a 1550\f
5c1ad6b5 1551Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1552
1553Copying and distribution of this file, with or without modification,
1554are permitted in any medium without royalty provided the copyright
1555notice and this notice are preserved.
1556
1557Local Variables:
1558mode: change-log
1559left-margin: 8
1560fill-column: 74
1561version-control: never
1562End:
GDB Binutils - Deliverables
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