2005-05-24 Paolo Bonzini <bonzini@gnu.org>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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12004-05-19 Alan Modra <amodra@bigpond.net.au>
2
3 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
4 well as when -mpower4.
5
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62004-05-13 Nick Clifton <nickc@redhat.com>
7
8 * po/fr.po: Updated French translation.
9
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102004-05-05 Peter Barada <peter@the-baradas.com>
11
12 * m68k-dis.c(print_insn_m68k): Add new chips, use core
13 variants in arch_mask. Only set m68881/68851 for 68k chips.
14 * m68k-op.c: Switch from ColdFire chips to core variants.
15
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162004-05-05 Alan Modra <amodra@bigpond.net.au>
17
a30e9cc4 18 PR 147.
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19 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
20
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212004-04-29 Ben Elliston <bje@au.ibm.com>
22
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23 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
24 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 25
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262004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
27
28 * sh-dis.c (print_insn_sh): Print the value in constant pool
29 as a symbol if it looks like a symbol.
30
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312004-04-22 Peter Barada <peter@the-baradas.com>
32
33 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
34 appropriate ColdFire architectures.
35 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
36 mask addressing.
37 Add EMAC instructions, fix MAC instructions. Remove
38 macmw/macml/msacmw/msacml instructions since mask addressing now
39 supported.
40
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412004-04-20 Jakub Jelinek <jakub@redhat.com>
42
43 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
44 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
45 suffix. Use fmov*x macros, create all 3 fpsize variants in one
46 macro. Adjust all users.
47
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482004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
49
50 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
51 separately.
52
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532004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
54
55 * m32r-asm.c: Regenerate.
56
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572004-03-29 Stan Shebs <shebs@apple.com>
58
59 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
60 used.
61
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622004-03-19 Alan Modra <amodra@bigpond.net.au>
63
64 * aclocal.m4: Regenerate.
65 * config.in: Regenerate.
66 * configure: Regenerate.
67 * po/POTFILES.in: Regenerate.
68 * po/opcodes.pot: Regenerate.
69
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702004-03-16 Alan Modra <amodra@bigpond.net.au>
71
72 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
73 PPC_OPERANDS_GPR_0.
74 * ppc-opc.c (RA0): Define.
75 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
76 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 77 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 78
2dc111b3 792004-03-15 Aldy Hernandez <aldyh@redhat.com>
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80
81 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 82
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832004-03-15 Alan Modra <amodra@bigpond.net.au>
84
85 * sparc-dis.c (print_insn_sparc): Update getword prototype.
86
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872004-03-12 Michal Ludvig <mludvig@suse.cz>
88
89 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 90 (grps): Delete GRPPLOCK entry.
7ffdda93 91
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922004-03-12 Alan Modra <amodra@bigpond.net.au>
93
94 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
95 (M, Mp): Use OP_M.
96 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
97 (GRPPADLCK): Define.
98 (dis386): Use NOP_Fixup on "nop".
99 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
100 (twobyte_has_modrm): Set for 0xa7.
101 (padlock_table): Delete. Move to..
102 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
103 and clflush.
104 (print_insn): Revert PADLOCK_SPECIAL code.
105 (OP_E): Delete sfence, lfence, mfence checks.
106
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1072004-03-12 Jakub Jelinek <jakub@redhat.com>
108
109 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
110 (INVLPG_Fixup): New function.
111 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
112
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1132004-03-12 Michal Ludvig <mludvig@suse.cz>
114
115 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
116 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
117 (padlock_table): New struct with PadLock instructions.
118 (print_insn): Handle PADLOCK_SPECIAL.
119
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1202004-03-12 Alan Modra <amodra@bigpond.net.au>
121
122 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
123 (OP_E): Twiddle clflush to sfence here.
124
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1252004-03-08 Nick Clifton <nickc@redhat.com>
126
127 * po/de.po: Updated German translation.
128
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1292003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
130
131 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
132 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
133 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
134 accordingly.
135
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1362004-03-01 Richard Sandiford <rsandifo@redhat.com>
137
138 * frv-asm.c: Regenerate.
139 * frv-desc.c: Regenerate.
140 * frv-desc.h: Regenerate.
141 * frv-dis.c: Regenerate.
142 * frv-ibld.c: Regenerate.
143 * frv-opc.c: Regenerate.
144 * frv-opc.h: Regenerate.
145
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1462004-03-01 Richard Sandiford <rsandifo@redhat.com>
147
148 * frv-desc.c, frv-opc.c: Regenerate.
149
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1502004-03-01 Richard Sandiford <rsandifo@redhat.com>
151
152 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
153
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1542004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
155
156 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
157 Also correct mistake in the comment.
158
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1592004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
160
161 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
162 ensure that double registers have even numbers.
163 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
164 that reserved instruction 0xfffd does not decode the same
165 as 0xfdfd (ftrv).
166 * sh-opc.h: Add REG_N_D nibble type and use it whereever
167 REG_N refers to a double register.
168 Add REG_N_B01 nibble type and use it instead of REG_NM
169 in ftrv.
170 Adjust the bit patterns in a few comments.
171
e5d2b64f 1722004-02-25 Aldy Hernandez <aldyh@redhat.com>
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173
174 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 175
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1762004-02-20 Aldy Hernandez <aldyh@redhat.com>
177
178 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
179
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1802004-02-20 Aldy Hernandez <aldyh@redhat.com>
181
182 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
183
f0b26da6 1842004-02-20 Aldy Hernandez <aldyh@redhat.com>
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185
186 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
187 mtivor32, mtivor33, mtivor34.
f0b26da6 188
23d59c56 1892004-02-19 Aldy Hernandez <aldyh@redhat.com>
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190
191 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 192
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1932004-02-10 Petko Manolov <petkan@nucleusys.com>
194
195 * arm-opc.h Maverick accumulator register opcode fixes.
196
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1972004-02-13 Ben Elliston <bje@wasabisystems.com>
198
199 * m32r-dis.c: Regenerate.
200
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2012004-01-27 Michael Snyder <msnyder@redhat.com>
202
203 * sh-opc.h (sh_table): "fsrra", not "fssra".
204
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2052004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
206
207 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
208 contraints.
209
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2102004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
211
212 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
213
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2142004-01-19 Alan Modra <amodra@bigpond.net.au>
215
216 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
217 1. Don't print scale factor on AT&T mode when index missing.
218
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2192004-01-16 Alexandre Oliva <aoliva@redhat.com>
220
221 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
222 when loaded into XR registers.
223
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2242004-01-14 Richard Sandiford <rsandifo@redhat.com>
225
226 * frv-desc.h: Regenerate.
227 * frv-desc.c: Regenerate.
228 * frv-opc.c: Regenerate.
229
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2302004-01-13 Michael Snyder <msnyder@redhat.com>
231
232 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
233
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2342004-01-09 Paul Brook <paul@codesourcery.com>
235
236 * arm-opc.h (arm_opcodes): Move generic mcrr after known
237 specific opcodes.
238
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2392004-01-07 Daniel Jacobowitz <drow@mvista.com>
240
241 * Makefile.am (libopcodes_la_DEPENDENCIES)
242 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
243 comment about the problem.
244 * Makefile.in: Regenerate.
245
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2462004-01-06 Alexandre Oliva <aoliva@redhat.com>
247
248 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
249 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
250 cut&paste errors in shifting/truncating numerical operands.
251 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
252 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
253 (parse_uslo16): Likewise.
254 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
255 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
256 (parse_s12): Likewise.
257 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
258 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
259 (parse_uslo16): Likewise.
260 (parse_uhi16): Parse gothi and gotfuncdeschi.
261 (parse_d12): Parse got12 and gotfuncdesc12.
262 (parse_s12): Likewise.
263
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2642004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
265
266 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
267 instruction which looks similar to an 'rla' instruction.
a0bd404e 268
c9e214e5 269For older changes see ChangeLog-0203
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271Local Variables:
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273left-margin: 8
274fill-column: 74
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