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remote.c: Add missing cast
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
35822b38
MW		 12015-11-27 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64-asm-2.c: Regenerate.
4 * aarch64-dis-2.c: Regenerate.
5 * aarch64-dis.c: Weaken assert.
6 * aarch64-gen.c: Include the instruction in the list of its
7 possible aliases.
8
1a04d1a7
MW		 92015-11-27 Matthew Wahab <matthew.wahab@arm.com>
10
11 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
12 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
13 feature test.
14
e49d43ff
TG		 152015-11-23 Tristan Gingold <gingold@adacore.com>
16
17 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
18
250aafa4
MW		 192015-11-20 Matthew Wahab <matthew.wahab@arm.com>
20
21 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
22 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
23 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
24 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
25 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
26 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
27 cnthv_ctl_el2, cnthv_cval_el2.
28 (aarch64_sys_reg_supported_p): Update for the new system
29 registers.
30
a915c10f
NC		 312015-11-20 Nick Clifton <nickc@redhat.com>
32
33 PR binutils/19224
34 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
35
f8c2a965
NC		 362015-11-20 Nick Clifton <nickc@redhat.com>
37
38 * po/zh_CN.po: Updated simplified Chinese translation.
39
c2825638
MW		 402015-11-19 Matthew Wahab <matthew.wahab@arm.com>
41
42 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
43 of MSR PAN immediate operand.
44
e7286c56
NC		 452015-11-16 Nick Clifton <nickc@redhat.com>
46
47 * rx-dis.c (condition_names): Replace always and never with
48 invalid, since the always/never conditions can never be legal.
49
d8bd95ef
TG		 502015-11-13 Tristan Gingold <gingold@adacore.com>
51
52 * configure: Regenerate.
53
a680de9a
PB		 542015-11-11 Alan Modra <amodra@gmail.com>
55 Peter Bergner <bergner@vnet.ibm.com>
56
57 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
58 Add PPC_OPCODE_VSX3 to the vsx entry.
59 (powerpc_init_dialect): Set default dialect to power9.
60 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
61 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
62 extract_l1 insert_xtq6, extract_xtq6): New static functions.
63 (insert_esync): Test for illegal L operand value.
64 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
65 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
66 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
67 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
68 PPCVSX3): New defines.
69 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
70 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
71 <mcrxr>: Use XBFRARB_MASK.
72 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
73 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
74 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
75 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
76 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
77 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
78 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
79 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
80 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
81 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
82 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
83 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
84 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
85 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
86 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
87 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
88 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
89 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
90 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
91 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
92 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
93 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
94 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
95 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
96 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
97 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
98 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
99 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
100 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
101 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
102 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
103 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
104
854eb72b
NC		 1052015-11-02 Nick Clifton <nickc@redhat.com>
106
107 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
108 instructions.
109 * rx-decode.c: Regenerate.
110
e292aa7a
NC		 1112015-11-02 Nick Clifton <nickc@redhat.com>
112
113 * rx-decode.opc (rx_disp): If the displacement is zero, set the
114 type to RX_Operand_Zero_Indirect.
115 * rx-decode.c: Regenerate.
116 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
117
43cdf5ae
YQ		 1182015-10-28 Yao Qi <yao.qi@linaro.org>
119
120 * aarch64-dis.c (aarch64_decode_insn): Add one argument
121 noaliases_p. Update comments. Pass noaliases_p rather than
122 no_aliases to aarch64_opcode_decode.
123 (print_insn_aarch64_word): Pass no_aliases to
124 aarch64_decode_insn.
125
c2f28758
VK		 1262015-10-27 Vinay <Vinay.G@kpit.com>
127
128 PR binutils/19159
129 * rl78-decode.opc (MOV): Added offset to DE register in index
130 addressing mode.
131 * rl78-decode.c: Regenerate.
132
46662804
VK		 1332015-10-27 Vinay Kumar <vinay.g@kpit.com>
134
135 PR binutils/19158
136 * rl78-decode.opc: Add 's' print operator to instructions that
137 access system registers.
138 * rl78-decode.c: Regenerate.
139 * rl78-dis.c (print_insn_rl78_common): Decode all system
140 registers.
141
02f12cd4
VK		 1422015-10-27 Vinay Kumar <vinay.g@kpit.com>
143
144 PR binutils/19157
145 * rl78-decode.opc: Add 'a' print operator to mov instructions
146 using stack pointer plus index addressing.
147 * rl78-decode.c: Regenerate.
148
485f23cf
AK		 1492015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
150
151 * s390-opc.c: Fix comment.
152 * s390-opc.txt: Change instruction type for troo, trot, trto, and
153 trtt to RRF_U0RER since the second parameter does not need to be a
154 register pair.
155
3f94e60d
NC		 1562015-10-08 Nick Clifton <nickc@redhat.com>
157
158 * arc-dis.c (print_insn_arc): Initiallise insn array.
159
875880c6
YQ		 1602015-10-07 Yao Qi <yao.qi@linaro.org>
161
162 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
163 'name' rather than 'template'.
164 * aarch64-opc.c (aarch64_print_operand): Likewise.
165
886a2506
NC		 1662015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
167
168 * arc-dis.c: Revamped file for ARC support
169 * arc-dis.h: Likewise.
170 * arc-ext.c: Likewise.
171 * arc-ext.h: Likewise.
172 * arc-opc.c: Likewise.
173 * arc-fxi.h: New file.
174 * arc-regs.h: Likewise.
175 * arc-tbl.h: Likewise.
176
36f4aab1
YQ		 1772015-10-02 Yao Qi <yao.qi@linaro.org>
178
179 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
180 argument insn type to aarch64_insn. Rename to ...
181 (aarch64_decode_insn): ... it.
182 (print_insn_aarch64_word): Caller updated.
183
7232d389
YQ		 1842015-10-02 Yao Qi <yao.qi@linaro.org>
185
186 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
187 (print_insn_aarch64_word): Caller updated.
188
7ecc513a
DV		 1892015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
190
191 * s390-mkopc.c (main): Parse htm and vx flag.
192 * s390-opc.txt: Mark instructions from the hardware transactional
193 memory and vector facilities with the "htm"/"vx" flag.
194
b08b78e7
NC		 1952015-09-28 Nick Clifton <nickc@redhat.com>
196
197 * po/de.po: Updated German translation.
198
36f7a941
TR		 1992015-09-28 Tom Rix <tom@bumblecow.com>
200
201 * ppc-opc.c (PPC500): Mark some opcodes as invalid
202
b6518b38
NC		 2032015-09-23 Nick Clifton <nickc@redhat.com>
204
205 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
206 function.
207 * tic30-dis.c (print_branch): Likewise.
208 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
209 value before left shifting.
210 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
211 * hppa-dis.c (print_insn_hppa): Likewise.
212 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
213 array.
214 * msp430-dis.c (msp430_singleoperand): Likewise.
215 (msp430_doubleoperand): Likewise.
216 (print_insn_msp430): Likewise.
217 * nds32-asm.c (parse_operand): Likewise.
218 * sh-opc.h (MASK): Likewise.
219 * v850-dis.c (get_operand_value): Likewise.
220
f04265ec
NC		 2212015-09-22 Nick Clifton <nickc@redhat.com>
222
223 * rx-decode.opc (bwl): Use RX_Bad_Size.
224 (sbwl): Likewise.
225 (ubwl): Likewise. Rename to ubw.
226 (uBWL): Rename to uBW.
227 Replace all references to uBWL with uBW.
228 * rx-decode.c: Regenerate.
229 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
230 (opsize_names): Likewise.
231 (print_insn_rx): Detect and report RX_Bad_Size.
232
6dca4fd1
AB		 2332015-09-22 Anton Blanchard <anton@samba.org>
234
235 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
236
38074311
JM		 2372015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
238
239 * sparc-dis.c (print_insn_sparc): Handle the privileged register
240 %pmcdper.
241
5f40e14d
JS		 2422015-08-24 Jan Stancek <jstancek@redhat.com>
243
244 * i386-dis.c (print_insn): Fix decoding of three byte operands.
245
ab4e4ed5
AF		 2462015-08-21 Alexander Fomin <alexander.fomin@intel.com>
247
248 PR binutils/18257
249 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
250 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
251 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
252 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
253 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
254 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
255 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
256 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
257 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
258 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
259 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
260 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
261 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
262 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
263 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
264 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
265 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
266 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
267 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
268 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
269 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
270 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
271 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
272 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
273 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
274 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
275 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
276 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
277 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
278 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
279 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
280 (vex_w_table): Replace terminals with MOD_TABLE entries for
281 most of mask instructions.
282
919b75f7
AM		 2832015-08-17 Alan Modra <amodra@gmail.com>
284
285 * cgen.sh: Trim trailing space from cgen output.
286 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
287 (print_dis_table): Likewise.
288 * opc2c.c (dump_lines): Likewise.
289 (orig_filename): Warning fix.
290 * ia64-asmtab.c: Regenerate.
291
4ab90a7a
AV		 2922015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
293
294 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
295 and higher with ARM instruction set will now mark the 26-bit
296 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
297 (arm_opcodes): Fix for unpredictable nop being recognized as a
298 teq.
299
40fc1451
SD		 3002015-08-12 Simon Dardis <simon.dardis@imgtec.com>
301
302 * micromips-opc.c (micromips_opcodes): Re-order table so that move
303 based on 'or' is first.
304 * mips-opc.c (mips_builtin_opcodes): Ditto.
305
922c5db5
NC		 3062015-08-11 Nick Clifton <nickc@redhat.com>
307
308 PR 18800
309 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
310 instruction.
311
75fb7498
RS		 3122015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
313
314 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
315
36aed29d
AP		 3162015-08-07 Amit Pawar <Amit.Pawar@amd.com>
317
318 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
319 * i386-init.h: Regenerated.
320
a8484f96
L		 3212015-07-30 H.J. Lu <hongjiu.lu@intel.com>
322
323 PR binutils/13571
324 * i386-dis.c (MOD_0FC3): New.
325 (PREFIX_0FC3): Renamed to ...
326 (PREFIX_MOD_0_0FC3): This.
327 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
328 (prefix_table): Replace Ma with Ev on movntiS.
329 (mod_table): Add MOD_0FC3.
330
37a42ee9
L		 3312015-07-27 H.J. Lu <hongjiu.lu@intel.com>
332
333 * configure: Regenerated.
334
070fe95d
AM		 3352015-07-23 Alan Modra <amodra@gmail.com>
336
337 PR 18708
338 * i386-dis.c (get64): Avoid signed integer overflow.
339
20c2a615
L		 3402015-07-22 Alexander Fomin <alexander.fomin@intel.com>
341
342 PR binutils/18631
343 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
344 "EXEvexHalfBcstXmmq" for the second operand.
345 (EVEX_W_0F79_P_2): Likewise.
346 (EVEX_W_0F7A_P_2): Likewise.
347 (EVEX_W_0F7B_P_2): Likewise.
348
6f1c2142
AM		 3492015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
350
351 * arm-dis.c (print_insn_coprocessor): Added support for quarter
352 float bitfield format.
353 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
354 quarter float bitfield format.
355
8a643cc3
L		 3562015-07-14 H.J. Lu <hongjiu.lu@intel.com>
357
358 * configure: Regenerated.
359
ef5a96d5
AM		 3602015-07-03 Alan Modra <amodra@gmail.com>
361
362 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
363 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
364 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
365
c8c8175b
SL		 3662015-07-01 Sandra Loosemore <sandra@codesourcery.com>
367 Cesar Philippidis <cesar@codesourcery.com>
368
369 * nios2-dis.c (nios2_extract_opcode): New.
370 (nios2_disassembler_state): New.
371 (nios2_find_opcode_hash): Use mach parameter to select correct
372 disassembler state.
373 (nios2_print_insn_arg): Extend to support new R2 argument letters
374 and formats.
375 (print_insn_nios2): Check for 16-bit instruction at end of memory.
376 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
377 (NIOS2_NUM_OPCODES): Rename to...
378 (NIOS2_NUM_R1_OPCODES): This.
379 (nios2_r2_opcodes): New.
380 (NIOS2_NUM_R2_OPCODES): New.
381 (nios2_num_r2_opcodes): New.
382 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
383 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
384 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
385 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
386 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
387
9916071f
AP		 3882015-06-30 Amit Pawar <Amit.Pawar@amd.com>
389
390 * i386-dis.c (OP_Mwaitx): New.
391 (rm_table): Add monitorx/mwaitx.
392 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
393 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
394 (operand_type_init): Add CpuMWAITX.
395 * i386-opc.h (CpuMWAITX): New.
396 (i386_cpu_flags): Add cpumwaitx.
397 * i386-opc.tbl: Add monitorx and mwaitx.
398 * i386-init.h: Regenerated.
399 * i386-tbl.h: Likewise.
400
7b934113
PB		 4012015-06-22 Peter Bergner <bergner@vnet.ibm.com>
402
403 * ppc-opc.c (insert_ls): Test for invalid LS operands.
404 (insert_esync): New function.
405 (LS, WC): Use insert_ls.
406 (ESYNC): Use insert_esync.
407
bdc4de1b
NC		 4082015-06-22 Nick Clifton <nickc@redhat.com>
409
410 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
411 requested region lies beyond it.
412 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
413 looking for 32-bit insns.
414 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
415 data.
416 * sh-dis.c (print_insn_sh): Likewise.
417 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
418 blocks of instructions.
419 * vax-dis.c (print_insn_vax): Check that the requested address
420 does not clash with the stop_vma.
421
11a0cf2e
PB		 4222015-06-19 Peter Bergner <bergner@vnet.ibm.com>
423
070fe95d 424 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 425 * ppc-opc.c (FXM4): Add non-zero optional value.
426 (TBR): Likewise.
427 (SXL): Likewise.
428 (insert_fxm): Handle new default operand value.
429 (extract_fxm): Likewise.
430 (insert_tbr): Likewise.
431 (extract_tbr): Likewise.
432
bdfa8b95
MW		 4332015-06-16 Matthew Wahab <matthew.wahab@arm.com>
434
435 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
436
24b4cf66
SN		 4372015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
438
439 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
440
99a2c561
PB		 4412015-06-12 Peter Bergner <bergner@vnet.ibm.com>
442
443 * ppc-opc.c: Add comment accidentally removed by old commit.
444 (MTMSRD_L): Delete.
445
40f77f82
AM		 4462015-06-04 Peter Bergner <bergner@vnet.ibm.com>
447
448 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
449
13be46a2
NC		 4502015-06-04 Nick Clifton <nickc@redhat.com>
451
452 PR 18474
453 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
454
ddfded2f
MW		 4552015-06-02 Matthew Wahab <matthew.wahab@arm.com>
456
457 * arm-dis.c (arm_opcodes): Add "setpan".
458 (thumb_opcodes): Add "setpan".
459
1af1dd51
MW		 4602015-06-02 Matthew Wahab <matthew.wahab@arm.com>
461
462 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
463 macros.
464
9e1f0fa7
MW		 4652015-06-02 Matthew Wahab <matthew.wahab@arm.com>
466
467 * aarch64-tbl.h (aarch64_feature_rdma): New.
468 (RDMA): New.
469 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
470 * aarch64-asm-2.c: Regenerate.
471 * aarch64-dis-2.c: Regenerate.
472 * aarch64-opc-2.c: Regenerate.
473
290806fd
MW		 4742015-06-02 Matthew Wahab <matthew.wahab@arm.com>
475
476 * aarch64-tbl.h (aarch64_feature_lor): New.
477 (LOR): New.
478 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
479 "stllrb", "stllrh".
480 * aarch64-asm-2.c: Regenerate.
481 * aarch64-dis-2.c: Regenerate.
482 * aarch64-opc-2.c: Regenerate.
483
f21cce2c
MW		 4842015-06-01 Matthew Wahab <matthew.wahab@arm.com>
485
486 * aarch64-opc.c (F_ARCHEXT): New.
487 (aarch64_sys_regs): Add "pan".
488 (aarch64_sys_reg_supported_p): New.
489 (aarch64_pstatefields): Add "pan".
490 (aarch64_pstatefield_supported_p): New.
491
d194d186
JB		 4922015-06-01 Jan Beulich <jbeulich@suse.com>
493
494 * i386-tbl.h: Regenerate.
495
3a8547d2
JB		 4962015-06-01 Jan Beulich <jbeulich@suse.com>
497
498 * i386-dis.c (print_insn): Swap rounding mode specifier and
499 general purpose register in Intel mode.
500
015c54d5
JB		 5012015-06-01 Jan Beulich <jbeulich@suse.com>
502
503 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
504 * i386-tbl.h: Regenerate.
505
071f0063
L		 5062015-05-18 H.J. Lu <hongjiu.lu@intel.com>
507
508 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
509 * i386-init.h: Regenerated.
510
5db04b09
L		 5112015-05-15 H.J. Lu <hongjiu.lu@intel.com>
512
513 PR binutis/18386
514 * i386-dis.c: Add comments for '@'.
515 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
516 (enum x86_64_isa): New.
517 (isa64): Likewise.
518 (print_i386_disassembler_options): Add amd64 and intel64.
519 (print_insn): Handle amd64 and intel64.
520 (putop): Handle '@'.
521 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
522 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
523 * i386-opc.h (AMD64): New.
524 (CpuIntel64): Likewise.
525 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
526 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
527 Mark direct call/jmp without Disp16|Disp32 as Intel64.
528 * i386-init.h: Regenerated.
529 * i386-tbl.h: Likewise.
530
4bc0608a
PB		 5312015-05-14 Peter Bergner <bergner@vnet.ibm.com>
532
533 * ppc-opc.c (IH) New define.
534 (powerpc_opcodes) <wait>: Do not enable for POWER7.
535 <tlbie>: Add RS operand for POWER7.
536 <slbia>: Add IH operand for POWER6.
537
70cead07
L		 5382015-05-11 H.J. Lu <hongjiu.lu@intel.com>
539
540 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
541 direct branch.
542 (jmp): Likewise.
543 * i386-tbl.h: Regenerated.
544
7b6d09fb
L		 5452015-05-11 H.J. Lu <hongjiu.lu@intel.com>
546
547 * configure.ac: Support bfd_iamcu_arch.
548 * disassemble.c (disassembler): Support bfd_iamcu_arch.
549 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
550 CPU_IAMCU_COMPAT_FLAGS.
551 (cpu_flags): Add CpuIAMCU.
552 * i386-opc.h (CpuIAMCU): New.
553 (i386_cpu_flags): Add cpuiamcu.
554 * configure: Regenerated.
555 * i386-init.h: Likewise.
556 * i386-tbl.h: Likewise.
557
31955f99
L		 5582015-05-08 H.J. Lu <hongjiu.lu@intel.com>
559
560 PR binutis/18386
561 * i386-dis.c (X86_64_E8): New.
562 (X86_64_E9): Likewise.
563 Update comments on 'T', 'U', 'V'. Add comments for '^'.
564 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
565 (x86_64_table): Add X86_64_E8 and X86_64_E9.
566 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
567 (putop): Handle '^'.
568 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
569 REX_W.
570
0952813b
DD		 5712015-04-30 DJ Delorie <dj@redhat.com>
572
573 * disassemble.c (disassembler): Choose suitable disassembler based
574 on E_ABI.
575 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
576 it to decode mul/div insns.
577 * rl78-decode.c: Regenerate.
578 * rl78-dis.c (print_insn_rl78): Rename to...
579 (print_insn_rl78_common): ...this, take ISA parameter.
580 (print_insn_rl78): New.
581 (print_insn_rl78_g10): New.
582 (print_insn_rl78_g13): New.
583 (print_insn_rl78_g14): New.
584 (rl78_get_disassembler): New.
585
f9d3ecaa
NC		 5862015-04-29 Nick Clifton <nickc@redhat.com>
587
588 * po/fr.po: Updated French translation.
589
4fff86c5
PB		 5902015-04-27 Peter Bergner <bergner@vnet.ibm.com>
591
592 * ppc-opc.c (DCBT_EO): New define.
593 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
594 <lharx>: Likewise.
595 <stbcx.>: Likewise.
596 <sthcx.>: Likewise.
597 <waitrsv>: Do not enable for POWER7 and later.
598 <waitimpl>: Likewise.
599 <dcbt>: Default to the two operand form of the instruction for all
600 "old" cpus. For "new" cpus, use the operand ordering that matches
601 whether the cpu is server or embedded.
602 <dcbtst>: Likewise.
603
3b78cfe1
AK		 6042015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
605
606 * s390-opc.c: New instruction type VV0UU2.
607 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
608 and WFC.
609
04d824a4
JB		 6102015-04-23 Jan Beulich <jbeulich@suse.com>
611
612 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
613 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
614 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
615 (vfpclasspd, vfpclassps): Add %XZ.
616
09708981
L		 6172015-04-15 H.J. Lu <hongjiu.lu@intel.com>
618
619 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
620 (PREFIX_UD_REPZ): Likewise.
621 (PREFIX_UD_REPNZ): Likewise.
622 (PREFIX_UD_DATA): Likewise.
623 (PREFIX_UD_ADDR): Likewise.
624 (PREFIX_UD_LOCK): Likewise.
625
3888916d
L		 6262015-04-15 H.J. Lu <hongjiu.lu@intel.com>
627
628 * i386-dis.c (prefix_requirement): Removed.
629 (print_insn): Don't set prefix_requirement. Check
630 dp->prefix_requirement instead of prefix_requirement.
631
f24bcbaa
L		 6322015-04-15 H.J. Lu <hongjiu.lu@intel.com>
633
634 PR binutils/17898
635 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
636 (PREFIX_MOD_0_0FC7_REG_6): This.
637 (PREFIX_MOD_3_0FC7_REG_6): New.
638 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
639 (prefix_table): Replace PREFIX_0FC7_REG_6 with
640 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
641 PREFIX_MOD_3_0FC7_REG_7.
642 (mod_table): Replace PREFIX_0FC7_REG_6 with
643 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
644 PREFIX_MOD_3_0FC7_REG_7.
645
507bd325
L		 6462015-04-15 H.J. Lu <hongjiu.lu@intel.com>
647
648 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
649 (PREFIX_MANDATORY_REPNZ): Likewise.
650 (PREFIX_MANDATORY_DATA): Likewise.
651 (PREFIX_MANDATORY_ADDR): Likewise.
652 (PREFIX_MANDATORY_LOCK): Likewise.
653 (PREFIX_MANDATORY): Likewise.
654 (PREFIX_UD_SHIFT): Set to 8
655 (PREFIX_UD_REPZ): Updated.
656 (PREFIX_UD_REPNZ): Likewise.
657 (PREFIX_UD_DATA): Likewise.
658 (PREFIX_UD_ADDR): Likewise.
659 (PREFIX_UD_LOCK): Likewise.
660 (PREFIX_IGNORED_SHIFT): New.
661 (PREFIX_IGNORED_REPZ): Likewise.
662 (PREFIX_IGNORED_REPNZ): Likewise.
663 (PREFIX_IGNORED_DATA): Likewise.
664 (PREFIX_IGNORED_ADDR): Likewise.
665 (PREFIX_IGNORED_LOCK): Likewise.
666 (PREFIX_OPCODE): Likewise.
667 (PREFIX_IGNORED): Likewise.
668 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
669 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
670 (three_byte_table): Likewise.
671 (mod_table): Likewise.
672 (mandatory_prefix): Renamed to ...
673 (prefix_requirement): This.
674 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
675 Update PREFIX_90 entry.
676 (get_valid_dis386): Check prefix_requirement to see if a prefix
677 should be ignored.
678 (print_insn): Replace mandatory_prefix with prefix_requirement.
679
f0fba320
RL		 6802015-04-15 Renlin Li <renlin.li@arm.com>
681
682 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
683 use it for ssat and ssat16.
684 (print_insn_thumb32): Add handle case for 'D' control code.
685
bf890a93
IT		 6862015-04-06 Ilya Tocar <ilya.tocar@intel.com>
687 H.J. Lu <hongjiu.lu@intel.com>
688
689 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
690 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
691 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
692 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
693 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
694 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
695 Fill prefix_requirement field.
696 (struct dis386): Add prefix_requirement field.
697 (dis386): Fill prefix_requirement field.
698 (dis386_twobyte): Ditto.
699 (twobyte_has_mandatory_prefix_: Remove.
700 (reg_table): Fill prefix_requirement field.
701 (prefix_table): Ditto.
702 (x86_64_table): Ditto.
703 (three_byte_table): Ditto.
704 (xop_table): Ditto.
705 (vex_table): Ditto.
706 (vex_len_table): Ditto.
707 (vex_w_table): Ditto.
708 (mod_table): Ditto.
709 (bad_opcode): Ditto.
710 (print_insn): Use prefix_requirement.
711 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
712 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
713 (float_reg): Ditto.
714
2f783c1f
MF		 7152015-03-30 Mike Frysinger <vapier@gentoo.org>
716
717 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
718
b9d94d62
L		 7192015-03-29 H.J. Lu <hongjiu.lu@intel.com>
720
721 * Makefile.in: Regenerated.
722
27c49e9a
AB		 7232015-03-25 Anton Blanchard <anton@samba.org>
724
725 * ppc-dis.c (disassemble_init_powerpc): Only initialise
726 powerpc_opcd_indices and vle_opcd_indices once.
727
c4e676f1
AB		 7282015-03-25 Anton Blanchard <anton@samba.org>
729
730 * ppc-opc.c (powerpc_opcodes): Add slbfee.
731
823d2571
TG		 7322015-03-24 Terry Guo <terry.guo@arm.com>
733
734 * arm-dis.c (opcode32): Updated to use new arm feature struct.
735 (opcode16): Likewise.
736 (coprocessor_opcodes): Replace bit with feature struct.
737 (neon_opcodes): Likewise.
738 (arm_opcodes): Likewise.
739 (thumb_opcodes): Likewise.
740 (thumb32_opcodes): Likewise.
741 (print_insn_coprocessor): Likewise.
742 (print_insn_arm): Likewise.
743 (select_arm_features): Follow new feature struct.
744
029f3522
GG		 7452015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
746
747 * i386-dis.c (rm_table): Add clzero.
748 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
749 Add CPU_CLZERO_FLAGS.
750 (cpu_flags): Add CpuCLZERO.
751 * i386-opc.h: Add CpuCLZERO.
752 * i386-opc.tbl: Add clzero.
753 * i386-init.h: Re-generated.
754 * i386-tbl.h: Re-generated.
755
6914869a
AB		 7562015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
757
758 * mips-opc.c (decode_mips_operand): Fix constraint issues
759 with u and y operands.
760
21e20815
AB		 7612015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
762
763 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
764
6b1d7593
AK		 7652015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
766
767 * s390-opc.c: Add new IBM z13 instructions.
768 * s390-opc.txt: Likewise.
769
c8f89a34
JW		 7702015-03-10 Renlin Li <renlin.li@arm.com>
771
772 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
773 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
774 related alias.
775 * aarch64-asm-2.c: Regenerate.
776 * aarch64-dis-2.c: Likewise.
777 * aarch64-opc-2.c: Likewise.
778
d8282f0e
JW		 7792015-03-03 Jiong Wang <jiong.wang@arm.com>
780
781 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
782
ac994365
OE		 7832015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
784
785 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
786 arch_sh_up.
787 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
788 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
789
fd63f640
V		 7902015-02-23 Vinay <Vinay.G@kpit.com>
791
792 * rl78-decode.opc (MOV): Added space between two operands for
793 'mov' instruction in index addressing mode.
794 * rl78-decode.c: Regenerate.
795
f63c1776
PA		 7962015-02-19 Pedro Alves <palves@redhat.com>
797
798 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
799
07774fcc
PA		 8002015-02-10 Pedro Alves <palves@redhat.com>
801 Tom Tromey <tromey@redhat.com>
802
803 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
804 microblaze_and, microblaze_xor.
805 * microblaze-opc.h (opcodes): Adjust.
806
3f8107ab
AM		 8072015-01-28 James Bowman <james.bowman@ftdichip.com>
808
809 * Makefile.am: Add FT32 files.
810 * configure.ac: Handle FT32.
811 * disassemble.c (disassembler): Call print_insn_ft32.
812 * ft32-dis.c: New file.
813 * ft32-opc.c: New file.
814 * Makefile.in: Regenerate.
815 * configure: Regenerate.
816 * po/POTFILES.in: Regenerate.
817
e5fe4957
KLC		 8182015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
819
820 * nds32-asm.c (keyword_sr): Add new system registers.
821
1e2e8c52
AK		 8222015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
823
824 * s390-dis.c (s390_extract_operand): Support vector register
825 operands.
826 (s390_print_insn_with_opcode): Support new operands types and add
827 new handling of optional operands.
828 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
829 and include opcode/s390.h instead.
830 (struct op_struct): New field `flags'.
831 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
832 (dumpTable): Dump flags.
833 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
834 string.
835 * s390-opc.c: Add new operands types, instruction formats, and
836 instruction masks.
837 (s390_opformats): Add new formats for .insn.
838 * s390-opc.txt: Add new instructions.
839
b90efa5b 8402015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 841
b90efa5b 842 Update year range in copyright notice of all files.
bffb6004 843
b90efa5b 844For older changes see ChangeLog-2014
252b5132 845\f
b90efa5b 846Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 847
848Copying and distribution of this file, with or without modification,
849are permitted in any medium without royalty provided the copyright
850notice and this notice are preserved.
851
252b5132 852Local Variables:
2f6d2f85
NC		 853mode: change-log
854left-margin: 8
855fill-column: 74
252b5132
RH		 856version-control: never
857End:
GDB Binutils - Deliverables
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