RISC-V: Fix bug in prior addi/c.nop patch.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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e925c834
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12018-01-17 Jim Wilson <jimw@sifive.com>
2
3 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
4
d777820b
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52018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
6
7 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
8 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
9 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
10 (cpu_flags): Add CpuIBT, CpuSHSTK.
11 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
12 (i386_cpu_flags): Add cpuibt, cpushstk.
13 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
14 * i386-init.h: Regenerate.
15 * i386-tbl.h: Likewise.
16
f6efed01
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172018-01-16 Nick Clifton <nickc@redhat.com>
18
19 * po/pt_BR.po: Updated Brazilian Portugese translation.
20 * po/de.po: Updated German translation.
21
2721d702
JW
222018-01-15 Jim Wilson <jimw@sifive.com>
23
24 * riscv-opc.c (match_c_nop): New.
25 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
26
616dcb87
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272018-01-15 Nick Clifton <nickc@redhat.com>
28
29 * po/uk.po: Updated Ukranian translation.
30
3957a496
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312018-01-13 Nick Clifton <nickc@redhat.com>
32
33 * po/opcodes.pot: Regenerated.
34
769c7ea5
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352018-01-13 Nick Clifton <nickc@redhat.com>
36
37 * configure: Regenerate.
38
faf766e3
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392018-01-13 Nick Clifton <nickc@redhat.com>
40
41 2.30 branch created.
42
888a89da
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432018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
44
45 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
46 * i386-tbl.h: Regenerate.
47
cbda583a
JB
482018-01-10 Jan Beulich <jbeulich@suse.com>
49
50 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
51 * i386-tbl.h: Re-generate.
52
c9e92278
JB
532018-01-10 Jan Beulich <jbeulich@suse.com>
54
55 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
56 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
57 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
58 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
59 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
60 Disp8MemShift of AVX512VL forms.
61 * i386-tbl.h: Re-generate.
62
35fd2b2b
JW
632018-01-09 Jim Wilson <jimw@sifive.com>
64
65 * riscv-dis.c (maybe_print_address): If base_reg is zero,
66 then the hi_addr value is zero.
67
91d8b670
JG
682018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
69
70 * arm-dis.c (arm_opcodes): Add csdb.
71 (thumb32_opcodes): Add csdb.
72
be2e7d95
JG
732018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
74
75 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
76 * aarch64-asm-2.c: Regenerate.
77 * aarch64-dis-2.c: Regenerate.
78 * aarch64-opc-2.c: Regenerate.
79
704a705d
L
802018-01-08 H.J. Lu <hongjiu.lu@intel.com>
81
82 PR gas/22681
83 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
84 Remove AVX512 vmovd with 64-bit operands.
85 * i386-tbl.h: Regenerated.
86
35eeb78f
JW
872018-01-05 Jim Wilson <jimw@sifive.com>
88
89 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
90 jalr.
91
219d1afa
AM
922018-01-03 Alan Modra <amodra@gmail.com>
93
94 Update year range in copyright notice of all files.
95
1508bbf5
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962018-01-02 Jan Beulich <jbeulich@suse.com>
97
98 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
99 and OPERAND_TYPE_REGZMM entries.
100
1e563868 101For older changes see ChangeLog-2017
3499769a 102\f
1e563868 103Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
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104
105Copying and distribution of this file, with or without modification,
106are permitted in any medium without royalty provided the copyright
107notice and this notice are preserved.
108
109Local Variables:
110mode: change-log
111left-margin: 8
112fill-column: 74
113version-control: never
114End:
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