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x86: fold RegEip/RegRip and RegEiz/RegRiz
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
e968fc9b
JB		 12018-08-06 Jan Beulich <jbeulich@suse.com>
2
3 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
4 (RegIP, RegIZ): Define.
5 * i386-reg.tbl: Adjust comments.
6 (rip): Use Qword instead of BaseIndex. Use RegIP.
7 (eip): Use Dword instead of BaseIndex. Use RegIP.
8 (riz): Add Qword. Use RegIZ.
9 (eiz): Add Dword. Use RegIZ.
10 * i386-tbl.h: Re-generate.
11
dbf8be89
JB		 122018-08-03 Jan Beulich <jbeulich@suse.com>
13
14 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
15 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
16 vpmovzxdq, vpmovzxwd): Remove NoRex64.
17 * i386-tbl.h: Re-generate.
18
c48dadc9
JB		 192018-08-03 Jan Beulich <jbeulich@suse.com>
20
21 * i386-gen.c (operand_types): Remove Mem field.
22 * i386-opc.h (union i386_operand_type): Remove mem field.
23 * i386-init.h, i386-tbl.h: Re-generate.
24
cb86a42a
AM		 252018-08-01 Alan Modra <amodra@gmail.com>
26
27 * po/POTFILES.in: Regenerate.
28
07cc0450
NC		 292018-07-31 Nick Clifton <nickc@redhat.com>
30
31 * po/sv.po: Updated Swedish translation.
32
1424ad86
JB		 332018-07-31 Jan Beulich <jbeulich@suse.com>
34
35 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
36 * i386-init.h, i386-tbl.h: Re-generate.
37
ae2387fe
JB		 382018-07-31 Jan Beulich <jbeulich@suse.com>
39
40 * i386-opc.h (ZEROING_MASKING) Rename to ...
41 (DYNAMIC_MASKING): ... this. Adjust comment.
42 * i386-opc.tbl (MaskingMorZ): Define.
43 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
44 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
45 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
46 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
47 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
48 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
49 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
50 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
51 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
52
6ff00b5e
JB		 532018-07-31 Jan Beulich <jbeulich@suse.com>
54
55 * i386-opc.tbl: Use element rather than vector size for AVX512*
56 scatter/gather insns.
57 * i386-tbl.h: Re-generate.
58
e951d5ca
JB		 592018-07-31 Jan Beulich <jbeulich@suse.com>
60
61 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
62 (cpu_flags): Drop CpuVREX.
63 * i386-opc.h (CpuVREX): Delete.
64 (union i386_cpu_flags): Remove cpuvrex.
65 * i386-init.h, i386-tbl.h: Re-generate.
66
eb41b248
JW		 672018-07-30 Jim Wilson <jimw@sifive.com>
68
69 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
70 fields.
71 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
72
b8891f8d
AJ		 732018-07-30 Andrew Jenner <andrew@codesourcery.com>
74
75 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
76 * Makefile.in: Regenerated.
77 * configure.ac: Add C-SKY.
78 * configure: Regenerated.
79 * csky-dis.c: New file.
80 * csky-opc.h: New file.
81 * disassemble.c (ARCH_csky): Define.
82 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
83 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
84
16065af1
AM		 852018-07-27 Alan Modra <amodra@gmail.com>
86
87 * ppc-opc.c (insert_sprbat): Correct function parameter and
88 return type.
89 (extract_sprbat): Likewise, variable too.
90
fa758a70
AC		 912018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
92 Alan Modra <amodra@gmail.com>
93
94 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
95 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
96 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
97 support disjointed BAT.
98 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
99 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
100 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
101
4a1b91ea
L		 1022018-07-25 H.J. Lu <hongjiu.lu@intel.com>
103 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
104
105 * i386-gen.c (adjust_broadcast_modifier): New function.
106 (process_i386_opcode_modifier): Add an argument for operands.
107 Adjust the Broadcast value based on operands.
108 (output_i386_opcode): Pass operand_types to
109 process_i386_opcode_modifier.
110 (process_i386_opcodes): Pass NULL as operands to
111 process_i386_opcode_modifier.
112 * i386-opc.h (BYTE_BROADCAST): New.
113 (WORD_BROADCAST): Likewise.
114 (DWORD_BROADCAST): Likewise.
115 (QWORD_BROADCAST): Likewise.
116 (i386_opcode_modifier): Expand broadcast to 3 bits.
117 * i386-tbl.h: Regenerated.
118
67ce483b
AM		 1192018-07-24 Alan Modra <amodra@gmail.com>
120
121 PR 23430
122 * or1k-desc.h: Regenerate.
123
4174bfff
JB		 1242018-07-24 Jan Beulich <jbeulich@suse.com>
125
126 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
127 vcvtusi2ss, and vcvtusi2sd.
128 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
129 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
130 * i386-tbl.h: Re-generate.
131
04e65276
CZ		 1322018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
133
134 * arc-opc.c (extract_w6): Fix extending the sign.
135
47e6f81c
CZ		 1362018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
137
138 * arc-tbl.h (vewt): Allow it for ARC EM family.
139
bb71536f
AM		 1402018-07-23 Alan Modra <amodra@gmail.com>
141
142 PR 23419
143 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
144 opcode variants for mtspr/mfspr encodings.
145
8095d2f7
CX		 1462018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
147 Maciej W. Rozycki <macro@mips.com>
148
149 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
150 loongson3a descriptors.
151 (parse_mips_ase_option): Handle -M loongson-mmi option.
152 (print_mips_disassembler_options): Document -M loongson-mmi.
153 * mips-opc.c (LMMI): New macro.
154 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
155 instructions.
156
5f32791e
JB		 1572018-07-19 Jan Beulich <jbeulich@suse.com>
158
159 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
160 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
161 IgnoreSize and [XYZ]MMword where applicable.
162 * i386-tbl.h: Re-generate.
163
625cbd7a
JB		 1642018-07-19 Jan Beulich <jbeulich@suse.com>
165
166 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
167 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
168 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
169 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
170 * i386-tbl.h: Re-generate.
171
86b15c32
JB		 1722018-07-19 Jan Beulich <jbeulich@suse.com>
173
174 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
175 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
176 VPCLMULQDQ templates into their respective AVX512VL counterparts
177 where possible, using Disp8ShiftVL and CheckRegSize instead of
178 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
179 * i386-tbl.h: Re-generate.
180
cf769ed5
JB		 1812018-07-19 Jan Beulich <jbeulich@suse.com>
182
183 * i386-opc.tbl: Fold AVX512DQ templates into their respective
184 AVX512VL counterparts where possible, using Disp8ShiftVL and
185 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
186 IgnoreSize) as appropriate.
187 * i386-tbl.h: Re-generate.
188
8282b7ad
JB		 1892018-07-19 Jan Beulich <jbeulich@suse.com>
190
191 * i386-opc.tbl: Fold AVX512BW templates into their respective
192 AVX512VL counterparts where possible, using Disp8ShiftVL and
193 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
194 IgnoreSize) as appropriate.
195 * i386-tbl.h: Re-generate.
196
755908cc
JB		 1972018-07-19 Jan Beulich <jbeulich@suse.com>
198
199 * i386-opc.tbl: Fold AVX512CD templates into their respective
200 AVX512VL counterparts where possible, using Disp8ShiftVL and
201 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
202 IgnoreSize) as appropriate.
203 * i386-tbl.h: Re-generate.
204
7091c612
JB		 2052018-07-19 Jan Beulich <jbeulich@suse.com>
206
207 * i386-opc.h (DISP8_SHIFT_VL): New.
208 * i386-opc.tbl (Disp8ShiftVL): Define.
209 (various): Fold AVX512VL templates into their respective
210 AVX512F counterparts where possible, using Disp8ShiftVL and
211 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
212 IgnoreSize) as appropriate.
213 * i386-tbl.h: Re-generate.
214
c30be56e
JB		 2152018-07-19 Jan Beulich <jbeulich@suse.com>
216
217 * Makefile.am: Change dependencies and rule for
218 $(srcdir)/i386-init.h.
219 * Makefile.in: Re-generate.
220 * i386-gen.c (process_i386_opcodes): New local variable
221 "marker". Drop opening of input file. Recognize marker and line
222 number directives.
223 * i386-opc.tbl (OPCODE_I386_H): Define.
224 (i386-opc.h): Include it.
225 (None): Undefine.
226
11a322db
L		 2272018-07-18 H.J. Lu <hongjiu.lu@intel.com>
228
229 PR gas/23418
230 * i386-opc.h (Byte): Update comments.
231 (Word): Likewise.
232 (Dword): Likewise.
233 (Fword): Likewise.
234 (Qword): Likewise.
235 (Tbyte): Likewise.
236 (Xmmword): Likewise.
237 (Ymmword): Likewise.
238 (Zmmword): Likewise.
239 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
240 vcvttps2uqq.
241 * i386-tbl.h: Regenerated.
242
cde3679e
NC		 2432018-07-12 Sudakshina Das <sudi.das@arm.com>
244
245 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
246 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
247 * aarch64-asm-2.c: Regenerate.
248 * aarch64-dis-2.c: Regenerate.
249 * aarch64-opc-2.c: Regenerate.
250
45a28947
TC		 2512018-07-12 Tamar Christina <tamar.christina@arm.com>
252
253 PR binutils/23192
254 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
255 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
256 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
257 sqdmulh, sqrdmulh): Use Em16.
258
c597cc3d
SD		 2592018-07-11 Sudakshina Das <sudi.das@arm.com>
260
261 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
262 csdb together with them.
263 (thumb32_opcodes): Likewise.
264
a79eaed6
JB		 2652018-07-11 Jan Beulich <jbeulich@suse.com>
266
267 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
268 requiring 32-bit registers as operands 2 and 3. Improve
269 comments.
270 (mwait, mwaitx): Fold templates. Improve comments.
271 OPERAND_TYPE_INOUTPORTREG.
272 * i386-tbl.h: Re-generate.
273
2fb5be8d
JB		 2742018-07-11 Jan Beulich <jbeulich@suse.com>
275
276 * i386-gen.c (operand_type_init): Remove
277 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
278 OPERAND_TYPE_INOUTPORTREG.
279 * i386-init.h: Re-generate.
280
7f5cad30
JB		 2812018-07-11 Jan Beulich <jbeulich@suse.com>
282
283 * i386-opc.tbl (wrssd, wrussd): Add Dword.
284 (wrssq, wrussq): Add Qword.
285 * i386-tbl.h: Re-generate.
286
f0a85b07
JB		 2872018-07-11 Jan Beulich <jbeulich@suse.com>
288
289 * i386-opc.h: Rename OTMax to OTNum.
290 (OTNumOfUints): Adjust calculation.
291 (OTUnused): Directly alias to OTNum.
292
9dcb0ba4
MR		 2932018-07-09 Maciej W. Rozycki <macro@mips.com>
294
295 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
296 `reg_xys'.
297 (lea_reg_xys): Likewise.
298 (print_insn_loop_primitive): Rename `reg' local variable to
299 `reg_dxy'.
300
f311ba7e
TC		 3012018-07-06 Tamar Christina <tamar.christina@arm.com>
302
303 PR binutils/23242
304 * aarch64-tbl.h (ldarh): Fix disassembly mask.
305
cba05feb
TC		 3062018-07-06 Tamar Christina <tamar.christina@arm.com>
307
308 PR binutils/23369
309 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
310 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
311
471b9d15
MR		 3122018-07-02 Maciej W. Rozycki <macro@mips.com>
313
314 PR tdep/8282
315 * mips-dis.c (mips_option_arg_t): New enumeration.
316 (mips_options): New variable.
317 (disassembler_options_mips): New function.
318 (print_mips_disassembler_options): Reimplement in terms of
319 `disassembler_options_mips'.
320 * arm-dis.c (disassembler_options_arm): Adapt to using the
321 `disasm_options_and_args_t' structure.
322 * ppc-dis.c (disassembler_options_powerpc): Likewise.
323 * s390-dis.c (disassembler_options_s390): Likewise.
324
c0c468d5
TP		 3252018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
326
327 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
328 expected result.
329 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
330 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
331 * testsuite/ld-arm/tls-longplt.d: Likewise.
332
369c9167
TC		 3332018-06-29 Tamar Christina <tamar.christina@arm.com>
334
335 PR binutils/23192
336 * aarch64-asm-2.c: Regenerate.
337 * aarch64-dis-2.c: Likewise.
338 * aarch64-opc-2.c: Likewise.
339 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
340 * aarch64-opc.c (operand_general_constraint_met_p,
341 aarch64_print_operand): Likewise.
342 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
343 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
344 fmlal2, fmlsl2.
345 (AARCH64_OPERANDS): Add Em2.
346
30aa1306
NC		 3472018-06-26 Nick Clifton <nickc@redhat.com>
348
349 * po/uk.po: Updated Ukranian translation.
350 * po/de.po: Updated German translation.
351 * po/pt_BR.po: Updated Brazilian Portuguese translation.
352
eca4b721
NC		 3532018-06-26 Nick Clifton <nickc@redhat.com>
354
355 * nfp-dis.c: Fix spelling mistake.
356
71300e2c
NC		 3572018-06-24 Nick Clifton <nickc@redhat.com>
358
359 * configure: Regenerate.
360 * po/opcodes.pot: Regenerate.
361
719d8288
NC		 3622018-06-24 Nick Clifton <nickc@redhat.com>
363
364 2.31 branch created.
365
514cd3a0
TC		 3662018-06-19 Tamar Christina <tamar.christina@arm.com>
367
368 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
369 * aarch64-asm-2.c: Regenerate.
370 * aarch64-dis-2.c: Likewise.
371
385e4d0f
MR		 3722018-06-21 Maciej W. Rozycki <macro@mips.com>
373
374 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
375 `-M ginv' option description.
376
160d1b3d
SH		 3772018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
378
379 PR gas/23305
380 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
381 la and lla.
382
d0ac1c44
SM		 3832018-06-19 Simon Marchi <simon.marchi@ericsson.com>
384
385 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
386 * configure.ac: Remove AC_PREREQ.
387 * Makefile.in: Re-generate.
388 * aclocal.m4: Re-generate.
389 * configure: Re-generate.
390
6f20c942
FS		 3912018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
392
393 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
394 mips64r6 descriptors.
395 (parse_mips_ase_option): Handle -Mginv option.
396 (print_mips_disassembler_options): Document -Mginv.
397 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
398 (GINV): New macro.
399 (mips_opcodes): Define ginvi and ginvt.
400
730c3174
SE		 4012018-06-13 Scott Egerton <scott.egerton@imgtec.com>
402 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
403
404 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
405 * mips-opc.c (CRC, CRC64): New macros.
406 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
407 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
408 crc32cd for CRC64.
409
cb366992
EB		 4102018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
411
412 PR 20319
413 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
414 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
415
ce72cd46
AM		 4162018-06-06 Alan Modra <amodra@gmail.com>
417
418 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
419 setjmp. Move init for some other vars later too.
420
4b8e28c7
MF		 4212018-06-04 Max Filippov <jcmvbkbc@gmail.com>
422
423 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
424 (dis_private): Add new fields for property section tracking.
425 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
426 (xtensa_instruction_fits): New functions.
427 (fetch_data): Bump minimal fetch size to 4.
428 (print_insn_xtensa): Make struct dis_private static.
429 Load and prepare property table on section change.
430 Don't disassemble literals. Don't disassemble instructions that
431 cross property table boundaries.
432
55e99962
L		 4332018-06-01 H.J. Lu <hongjiu.lu@intel.com>
434
435 * configure: Regenerated.
436
733bd0ab
JB		 4372018-06-01 Jan Beulich <jbeulich@suse.com>
438
439 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
440 * i386-tbl.h: Re-generate.
441
dfd27d41
JB		 4422018-06-01 Jan Beulich <jbeulich@suse.com>
443
444 * i386-opc.tbl (sldt, str): Add NoRex64.
445 * i386-tbl.h: Re-generate.
446
64795710
JB		 4472018-06-01 Jan Beulich <jbeulich@suse.com>
448
449 * i386-opc.tbl (invpcid): Add Oword.
450 * i386-tbl.h: Re-generate.
451
030157d8
AM		 4522018-06-01 Alan Modra <amodra@gmail.com>
453
454 * sysdep.h (_bfd_error_handler): Don't declare.
455 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
456 * rl78-decode.opc: Likewise.
457 * msp430-decode.c: Regenerate.
458 * rl78-decode.c: Regenerate.
459
a9660a6f
AP		 4602018-05-30 Amit Pawar <Amit.Pawar@amd.com>
461
462 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
463 * i386-init.h : Regenerated.
464
277eb7f6
AM		 4652018-05-25 Alan Modra <amodra@gmail.com>
466
467 * Makefile.in: Regenerate.
468 * po/POTFILES.in: Regenerate.
469
98553ad3
PB		 4702018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
471
472 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
473 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
474 (insert_bab, extract_bab, insert_btab, extract_btab,
475 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
476 (BAT, BBA VBA RBS XB6S): Delete macros.
477 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
478 (BB, BD, RBX, XC6): Update for new macros.
479 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
480 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
481 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
482 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
483
7b4ae824
JD		 4842018-05-18 John Darrington <john@darrington.wattle.id.au>
485
486 * Makefile.am: Add support for s12z architecture.
487 * configure.ac: Likewise.
488 * disassemble.c: Likewise.
489 * disassemble.h: Likewise.
490 * Makefile.in: Regenerate.
491 * configure: Regenerate.
492 * s12z-dis.c: New file.
493 * s12z.h: New file.
494
29e0f0a1
AM		 4952018-05-18 Alan Modra <amodra@gmail.com>
496
497 * nfp-dis.c: Don't #include libbfd.h.
498 (init_nfp3200_priv): Use bfd_get_section_contents.
499 (nit_nfp6000_mecsr_sec): Likewise.
500
809276d2
NC		 5012018-05-17 Nick Clifton <nickc@redhat.com>
502
503 * po/zh_CN.po: Updated simplified Chinese translation.
504
ff329288
TC		 5052018-05-16 Tamar Christina <tamar.christina@arm.com>
506
507 PR binutils/23109
508 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
509 * aarch64-dis-2.c: Regenerate.
510
f9830ec1
TC		 5112018-05-15 Tamar Christina <tamar.christina@arm.com>
512
513 PR binutils/21446
514 * aarch64-asm.c (opintl.h): Include.
515 (aarch64_ins_sysreg): Enforce read/write constraints.
516 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
517 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
518 (F_REG_READ, F_REG_WRITE): New.
519 * aarch64-opc.c (aarch64_print_operand): Generate notes for
520 AARCH64_OPND_SYSREG.
521 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
522 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
523 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
524 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
525 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
526 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
527 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
528 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
529 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
530 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
531 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
532 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
533 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
534 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
535 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
536 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
537 msr (F_SYS_WRITE), mrs (F_SYS_READ).
538
7d02540a
TC		 5392018-05-15 Tamar Christina <tamar.christina@arm.com>
540
541 PR binutils/21446
542 * aarch64-dis.c (no_notes: New.
543 (parse_aarch64_dis_option): Support notes.
544 (aarch64_decode_insn, print_operands): Likewise.
545 (print_aarch64_disassembler_options): Document notes.
546 * aarch64-opc.c (aarch64_print_operand): Support notes.
547
561a72d4
TC		 5482018-05-15 Tamar Christina <tamar.christina@arm.com>
549
550 PR binutils/21446
551 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
552 and take error struct.
553 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
554 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
555 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
556 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
557 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
558 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
559 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
560 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
561 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
562 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
563 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
564 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
565 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
566 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
567 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
568 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
569 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
570 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
571 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
572 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
573 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
574 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
575 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
576 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
577 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
578 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
579 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
580 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
581 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
582 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
583 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
584 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
585 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
586 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
587 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
588 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
589 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
590 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
591 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
592 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
593 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
594 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
595 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
596 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
597 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
598 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
599 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
600 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
601 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
602 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
603 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
604 (determine_disassembling_preference, aarch64_decode_insn,
605 print_insn_aarch64_word, print_insn_data): Take errors struct.
606 (print_insn_aarch64): Use errors.
607 * aarch64-asm-2.c: Regenerate.
608 * aarch64-dis-2.c: Regenerate.
609 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
610 boolean in aarch64_insert_operan.
611 (print_operand_extractor): Likewise.
612 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
613
1678bd35
FT		 6142018-05-15 Francois H. Theron <francois.theron@netronome.com>
615
616 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
617
06cfb1c8
L		 6182018-05-09 H.J. Lu <hongjiu.lu@intel.com>
619
620 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
621
84f9f8c3
AM		 6222018-05-09 Sebastian Rasmussen <sebras@gmail.com>
623
624 * cr16-opc.c (cr16_instruction): Comment typo fix.
625 * hppa-dis.c (print_insn_hppa): Likewise.
626
e6f372ba
JW		 6272018-05-08 Jim Wilson <jimw@sifive.com>
628
629 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
630 (match_c_slli64, match_srxi_as_c_srxi): New.
631 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
632 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
633 <c.slli, c.srli, c.srai>: Use match_s_slli.
634 <c.slli64, c.srli64, c.srai64>: New.
635
f413a913
AM		 6362018-05-08 Alan Modra <amodra@gmail.com>
637
638 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
639 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
640 partition opcode space for index lookup.
641
a87a6478
PB		 6422018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
643
644 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
645 <insn_length>: ...with this. Update usage.
646 Remove duplicate call to *info->memory_error_func.
647
c0a30a9f
L		 6482018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
649 H.J. Lu <hongjiu.lu@intel.com>
650
651 * i386-dis.c (Gva): New.
652 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
653 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
654 (prefix_table): New instructions (see prefix above).
655 (mod_table): New instructions (see prefix above).
656 (OP_G): Handle va_mode.
657 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
658 CPU_MOVDIR64B_FLAGS.
659 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
660 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
661 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
662 * i386-opc.tbl: Add movidir{i,64b}.
663 * i386-init.h: Regenerated.
664 * i386-tbl.h: Likewise.
665
75c0a438
L		 6662018-05-07 H.J. Lu <hongjiu.lu@intel.com>
667
668 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
669 AddrPrefixOpReg.
670 * i386-opc.h (AddrPrefixOp0): Renamed to ...
671 (AddrPrefixOpReg): This.
672 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
673 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
674
2ceb7719
PB		 6752018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
676
677 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
678 (vle_num_opcodes): Likewise.
679 (spe2_num_opcodes): Likewise.
680 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
681 initialization loop.
682 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
683 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
684 only once.
685
b3ac5c6c
TC		 6862018-05-01 Tamar Christina <tamar.christina@arm.com>
687
688 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
689
fe944acf
FT		 6902018-04-30 Francois H. Theron <francois.theron@netronome.com>
691
692 Makefile.am: Added nfp-dis.c.
693 configure.ac: Added bfd_nfp_arch.
694 disassemble.h: Added print_insn_nfp prototype.
695 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
696 nfp-dis.c: New, for NFP support.
697 po/POTFILES.in: Added nfp-dis.c to the list.
698 Makefile.in: Regenerate.
699 configure: Regenerate.
700
e2195274
JB		 7012018-04-26 Jan Beulich <jbeulich@suse.com>
702
703 * i386-opc.tbl: Fold various non-memory operand AVX512VL
704 templates into their base ones.
705 * i386-tlb.h: Re-generate.
706
59ef5df4
JB		 7072018-04-26 Jan Beulich <jbeulich@suse.com>
708
709 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
710 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
711 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
712 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
713 * i386-init.h: Re-generate.
714
6e041cf4
JB		 7152018-04-26 Jan Beulich <jbeulich@suse.com>
716
717 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
718 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
719 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
720 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
721 comment.
722 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
723 and CpuRegMask.
724 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
725 CpuRegMask: Delete.
726 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
727 cpuregzmm, and cpuregmask.
728 * i386-init.h: Re-generate.
729 * i386-tbl.h: Re-generate.
730
0e0eea78
JB		 7312018-04-26 Jan Beulich <jbeulich@suse.com>
732
733 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
734 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
735 * i386-init.h: Re-generate.
736
2f1bada2
JB		 7372018-04-26 Jan Beulich <jbeulich@suse.com>
738
739 * i386-gen.c (VexImmExt): Delete.
740 * i386-opc.h (VexImmExt, veximmext): Delete.
741 * i386-opc.tbl: Drop all VexImmExt uses.
742 * i386-tlb.h: Re-generate.
743
bacd1457
JB		 7442018-04-25 Jan Beulich <jbeulich@suse.com>
745
746 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
747 register-only forms.
748 * i386-tlb.h: Re-generate.
749
10bba94b
TC		 7502018-04-25 Tamar Christina <tamar.christina@arm.com>
751
752 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
753
c48935d7
IT		 7542018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
755
756 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
757 PREFIX_0F1C.
758 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
759 (cpu_flags): Add CpuCLDEMOTE.
760 * i386-init.h: Regenerate.
761 * i386-opc.h (enum): Add CpuCLDEMOTE,
762 (i386_cpu_flags): Add cpucldemote.
763 * i386-opc.tbl: Add cldemote.
764 * i386-tbl.h: Regenerate.
765
211dc24b
AM		 7662018-04-16 Alan Modra <amodra@gmail.com>
767
768 * Makefile.am: Remove sh5 and sh64 support.
769 * configure.ac: Likewise.
770 * disassemble.c: Likewise.
771 * disassemble.h: Likewise.
772 * sh-dis.c: Likewise.
773 * sh64-dis.c: Delete.
774 * sh64-opc.c: Delete.
775 * sh64-opc.h: Delete.
776 * Makefile.in: Regenerate.
777 * configure: Regenerate.
778 * po/POTFILES.in: Regenerate.
779
a9a4b302
AM		 7802018-04-16 Alan Modra <amodra@gmail.com>
781
782 * Makefile.am: Remove w65 support.
783 * configure.ac: Likewise.
784 * disassemble.c: Likewise.
785 * disassemble.h: Likewise.
786 * w65-dis.c: Delete.
787 * w65-opc.h: Delete.
788 * Makefile.in: Regenerate.
789 * configure: Regenerate.
790 * po/POTFILES.in: Regenerate.
791
04cb01fd
AM		 7922018-04-16 Alan Modra <amodra@gmail.com>
793
794 * configure.ac: Remove we32k support.
795 * configure: Regenerate.
796
c2bf1eec
AM		 7972018-04-16 Alan Modra <amodra@gmail.com>
798
799 * Makefile.am: Remove m88k support.
800 * configure.ac: Likewise.
801 * disassemble.c: Likewise.
802 * disassemble.h: Likewise.
803 * m88k-dis.c: Delete.
804 * Makefile.in: Regenerate.
805 * configure: Regenerate.
806 * po/POTFILES.in: Regenerate.
807
6793974d
AM		 8082018-04-16 Alan Modra <amodra@gmail.com>
809
810 * Makefile.am: Remove i370 support.
811 * configure.ac: Likewise.
812 * disassemble.c: Likewise.
813 * disassemble.h: Likewise.
814 * i370-dis.c: Delete.
815 * i370-opc.c: Delete.
816 * Makefile.in: Regenerate.
817 * configure: Regenerate.
818 * po/POTFILES.in: Regenerate.
819
e82aa794
AM		 8202018-04-16 Alan Modra <amodra@gmail.com>
821
822 * Makefile.am: Remove h8500 support.
823 * configure.ac: Likewise.
824 * disassemble.c: Likewise.
825 * disassemble.h: Likewise.
826 * h8500-dis.c: Delete.
827 * h8500-opc.h: Delete.
828 * Makefile.in: Regenerate.
829 * configure: Regenerate.
830 * po/POTFILES.in: Regenerate.
831
fceadf09
AM		 8322018-04-16 Alan Modra <amodra@gmail.com>
833
834 * configure.ac: Remove tahoe support.
835 * configure: Regenerate.
836
ae1d3843
L		 8372018-04-15 H.J. Lu <hongjiu.lu@intel.com>
838
839 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
840 umwait.
841 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
842 64-bit mode.
843 * i386-tbl.h: Regenerated.
844
de89d0a3
IT		 8452018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
846
847 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
848 PREFIX_MOD_1_0FAE_REG_6.
849 (va_mode): New.
850 (OP_E_register): Use va_mode.
851 * i386-dis-evex.h (prefix_table):
852 New instructions (see prefixes above).
853 * i386-gen.c (cpu_flag_init): Add WAITPKG.
854 (cpu_flags): Likewise.
855 * i386-opc.h (enum): Likewise.
856 (i386_cpu_flags): Likewise.
857 * i386-opc.tbl: Add umonitor, umwait, tpause.
858 * i386-init.h: Regenerate.
859 * i386-tbl.h: Likewise.
860
a8eb42a8
AM		 8612018-04-11 Alan Modra <amodra@gmail.com>
862
863 * opcodes/i860-dis.c: Delete.
864 * opcodes/i960-dis.c: Delete.
865 * Makefile.am: Remove i860 and i960 support.
866 * configure.ac: Likewise.
867 * disassemble.c: Likewise.
868 * disassemble.h: Likewise.
869 * Makefile.in: Regenerate.
870 * configure: Regenerate.
871 * po/POTFILES.in: Regenerate.
872
caf0678c
L		 8732018-04-04 H.J. Lu <hongjiu.lu@intel.com>
874
875 PR binutils/23025
876 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
877 to 0.
878 (print_insn): Clear vex instead of vex.evex.
879
4fb0d2b9
NC		 8802018-04-04 Nick Clifton <nickc@redhat.com>
881
882 * po/es.po: Updated Spanish translation.
883
c39e5b26
JB		 8842018-03-28 Jan Beulich <jbeulich@suse.com>
885
886 * i386-gen.c (opcode_modifiers): Delete VecESize.
887 * i386-opc.h (VecESize): Delete.
888 (struct i386_opcode_modifier): Delete vecesize.
889 * i386-opc.tbl: Drop VecESize.
890 * i386-tlb.h: Re-generate.
891
8e6e0792
JB		 8922018-03-28 Jan Beulich <jbeulich@suse.com>
893
894 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
895 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
896 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
897 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
898 * i386-tlb.h: Re-generate.
899
9f123b91
JB		 9002018-03-28 Jan Beulich <jbeulich@suse.com>
901
902 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
903 Fold AVX512 forms
904 * i386-tlb.h: Re-generate.
905
9646c87b
JB		 9062018-03-28 Jan Beulich <jbeulich@suse.com>
907
908 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
909 (vex_len_table): Drop Y for vcvt*2si.
910 (putop): Replace plain 'Y' handling by abort().
911
c8d59609
NC		 9122018-03-28 Nick Clifton <nickc@redhat.com>
913
914 PR 22988
915 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
916 instructions with only a base address register.
917 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
918 handle AARHC64_OPND_SVE_ADDR_R.
919 (aarch64_print_operand): Likewise.
920 * aarch64-asm-2.c: Regenerate.
921 * aarch64_dis-2.c: Regenerate.
922 * aarch64-opc-2.c: Regenerate.
923
b8c169f3
JB		 9242018-03-22 Jan Beulich <jbeulich@suse.com>
925
926 * i386-opc.tbl: Drop VecESize from register only insn forms and
927 memory forms not allowing broadcast.
928 * i386-tlb.h: Re-generate.
929
96bc132a
JB		 9302018-03-22 Jan Beulich <jbeulich@suse.com>
931
932 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
933 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
934 sha256*): Drop Disp<N>.
935
9f79e886
JB		 9362018-03-22 Jan Beulich <jbeulich@suse.com>
937
938 * i386-dis.c (EbndS, bnd_swap_mode): New.
939 (prefix_table): Use EbndS.
940 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
941 * i386-opc.tbl (bndmov): Move misplaced Load.
942 * i386-tlb.h: Re-generate.
943
d6793fa1
JB		 9442018-03-22 Jan Beulich <jbeulich@suse.com>
945
946 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
947 templates allowing memory operands and folded ones for register
948 only flavors.
949 * i386-tlb.h: Re-generate.
950
f7768225
JB		 9512018-03-22 Jan Beulich <jbeulich@suse.com>
952
953 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
954 256-bit templates. Drop redundant leftover Disp<N>.
955 * i386-tlb.h: Re-generate.
956
0e35537d
JW		 9572018-03-14 Kito Cheng <kito.cheng@gmail.com>
958
959 * riscv-opc.c (riscv_insn_types): New.
960
b4a3689a
NC		 9612018-03-13 Nick Clifton <nickc@redhat.com>
962
963 * po/pt_BR.po: Updated Brazilian Portuguese translation.
964
d3d50934
L		 9652018-03-08 H.J. Lu <hongjiu.lu@intel.com>
966
967 * i386-opc.tbl: Add Optimize to clr.
968 * i386-tbl.h: Regenerated.
969
bd5dea88
L		 9702018-03-08 H.J. Lu <hongjiu.lu@intel.com>
971
972 * i386-gen.c (opcode_modifiers): Remove OldGcc.
973 * i386-opc.h (OldGcc): Removed.
974 (i386_opcode_modifier): Remove oldgcc.
975 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
976 instructions for old (<= 2.8.1) versions of gcc.
977 * i386-tbl.h: Regenerated.
978
e771e7c9
JB		 9792018-03-08 Jan Beulich <jbeulich@suse.com>
980
981 * i386-opc.h (EVEXDYN): New.
982 * i386-opc.tbl: Fold various AVX512VL templates.
983 * i386-tlb.h: Re-generate.
984
ed438a93
JB		 9852018-03-08 Jan Beulich <jbeulich@suse.com>
986
987 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
988 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
989 vpexpandd, vpexpandq): Fold AFX512VF templates.
990 * i386-tlb.h: Re-generate.
991
454172a9
JB		 9922018-03-08 Jan Beulich <jbeulich@suse.com>
993
994 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
995 Fold 128- and 256-bit VEX-encoded templates.
996 * i386-tlb.h: Re-generate.
997
36824150
JB		 9982018-03-08 Jan Beulich <jbeulich@suse.com>
999
1000 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1001 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1002 vpexpandd, vpexpandq): Fold AVX512F templates.
1003 * i386-tlb.h: Re-generate.
1004
e7f5c0a9
JB		 10052018-03-08 Jan Beulich <jbeulich@suse.com>
1006
1007 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1008 64-bit templates. Drop Disp<N>.
1009 * i386-tlb.h: Re-generate.
1010
25a4277f
JB		 10112018-03-08 Jan Beulich <jbeulich@suse.com>
1012
1013 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1014 and 256-bit templates.
1015 * i386-tlb.h: Re-generate.
1016
d2224064
JB		 10172018-03-08 Jan Beulich <jbeulich@suse.com>
1018
1019 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1020 * i386-tlb.h: Re-generate.
1021
1b193f0b
JB		 10222018-03-08 Jan Beulich <jbeulich@suse.com>
1023
1024 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1025 Drop NoAVX.
1026 * i386-tlb.h: Re-generate.
1027
f2f6a710
JB		 10282018-03-08 Jan Beulich <jbeulich@suse.com>
1029
1030 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1031 * i386-tlb.h: Re-generate.
1032
38e314eb
JB		 10332018-03-08 Jan Beulich <jbeulich@suse.com>
1034
1035 * i386-gen.c (opcode_modifiers): Delete FloatD.
1036 * i386-opc.h (FloatD): Delete.
1037 (struct i386_opcode_modifier): Delete floatd.
1038 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1039 FloatD by D.
1040 * i386-tlb.h: Re-generate.
1041
d53e6b98
JB		 10422018-03-08 Jan Beulich <jbeulich@suse.com>
1043
1044 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1045
2907c2f5
JB		 10462018-03-08 Jan Beulich <jbeulich@suse.com>
1047
1048 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1049 * i386-tlb.h: Re-generate.
1050
73053c1f
JB		 10512018-03-08 Jan Beulich <jbeulich@suse.com>
1052
1053 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1054 forms.
1055 * i386-tlb.h: Re-generate.
1056
52fe4420
AM		 10572018-03-07 Alan Modra <amodra@gmail.com>
1058
1059 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1060 bfd_arch_rs6000.
1061 * disassemble.h (print_insn_rs6000): Delete.
1062 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1063 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1064 (print_insn_rs6000): Delete.
1065
a6743a54
AM		 10662018-03-03 Alan Modra <amodra@gmail.com>
1067
1068 * sysdep.h (opcodes_error_handler): Define.
1069 (_bfd_error_handler): Declare.
1070 * Makefile.am: Remove stray #.
1071 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1072 EDIT" comment.
1073 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1074 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1075 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1076 opcodes_error_handler to print errors. Standardize error messages.
1077 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1078 and include opintl.h.
1079 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1080 * i386-gen.c: Standardize error messages.
1081 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1082 * Makefile.in: Regenerate.
1083 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1084 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1085 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1086 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1087 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1088 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1089 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1090 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1091 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1092 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1093 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1094 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1095 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1096
8305403a
L		 10972018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1098
1099 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1100 vpsub[bwdq] instructions.
1101 * i386-tbl.h: Regenerated.
1102
e184813f
AM		 11032018-03-01 Alan Modra <amodra@gmail.com>
1104
1105 * configure.ac (ALL_LINGUAS): Sort.
1106 * configure: Regenerate.
1107
5b616bef
TP		 11082018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1109
1110 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1111 macro by assignements.
1112
b6f8c7c4
L		 11132018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1114
1115 PR gas/22871
1116 * i386-gen.c (opcode_modifiers): Add Optimize.
1117 * i386-opc.h (Optimize): New enum.
1118 (i386_opcode_modifier): Add optimize.
1119 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1120 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1121 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1122 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1123 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1124 vpxord and vpxorq.
1125 * i386-tbl.h: Regenerated.
1126
e95b887f
AM		 11272018-02-26 Alan Modra <amodra@gmail.com>
1128
1129 * crx-dis.c (getregliststring): Allocate a large enough buffer
1130 to silence false positive gcc8 warning.
1131
0bccfb29
JW		 11322018-02-22 Shea Levy <shea@shealevy.com>
1133
1134 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1135
6b6b6807
L		 11362018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1137
1138 * i386-opc.tbl: Add {rex},
1139 * i386-tbl.h: Regenerated.
1140
75f31665
MR		 11412018-02-20 Maciej W. Rozycki <macro@mips.com>
1142
1143 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1144 (mips16_opcodes): Replace `M' with `m' for "restore".
1145
e207bc53
TP		 11462018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1147
1148 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1149
87993319
MR		 11502018-02-13 Maciej W. Rozycki <macro@mips.com>
1151
1152 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1153 variable to `function_index'.
1154
68d20676
NC		 11552018-02-13 Nick Clifton <nickc@redhat.com>
1156
1157 PR 22823
1158 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1159 about truncation of printing.
1160
d2159fdc
HW		 11612018-02-12 Henry Wong <henry@stuffedcow.net>
1162
1163 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1164
f174ef9f
NC		 11652018-02-05 Nick Clifton <nickc@redhat.com>
1166
1167 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1168
be3a8dca
IT		 11692018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1170
1171 * i386-dis.c (enum): Add pconfig.
1172 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1173 (cpu_flags): Add CpuPCONFIG.
1174 * i386-opc.h (enum): Add CpuPCONFIG.
1175 (i386_cpu_flags): Add cpupconfig.
1176 * i386-opc.tbl: Add PCONFIG instruction.
1177 * i386-init.h: Regenerate.
1178 * i386-tbl.h: Likewise.
1179
3233d7d0
IT		 11802018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1181
1182 * i386-dis.c (enum): Add PREFIX_0F09.
1183 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1184 (cpu_flags): Add CpuWBNOINVD.
1185 * i386-opc.h (enum): Add CpuWBNOINVD.
1186 (i386_cpu_flags): Add cpuwbnoinvd.
1187 * i386-opc.tbl: Add WBNOINVD instruction.
1188 * i386-init.h: Regenerate.
1189 * i386-tbl.h: Likewise.
1190
e925c834
JW		 11912018-01-17 Jim Wilson <jimw@sifive.com>
1192
1193 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1194
d777820b
IT		 11952018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1196
1197 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1198 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1199 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1200 (cpu_flags): Add CpuIBT, CpuSHSTK.
1201 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1202 (i386_cpu_flags): Add cpuibt, cpushstk.
1203 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1204 * i386-init.h: Regenerate.
1205 * i386-tbl.h: Likewise.
1206
f6efed01
NC		 12072018-01-16 Nick Clifton <nickc@redhat.com>
1208
1209 * po/pt_BR.po: Updated Brazilian Portugese translation.
1210 * po/de.po: Updated German translation.
1211
2721d702
JW		 12122018-01-15 Jim Wilson <jimw@sifive.com>
1213
1214 * riscv-opc.c (match_c_nop): New.
1215 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1216
616dcb87
NC		 12172018-01-15 Nick Clifton <nickc@redhat.com>
1218
1219 * po/uk.po: Updated Ukranian translation.
1220
3957a496
NC		 12212018-01-13 Nick Clifton <nickc@redhat.com>
1222
1223 * po/opcodes.pot: Regenerated.
1224
769c7ea5
NC		 12252018-01-13 Nick Clifton <nickc@redhat.com>
1226
1227 * configure: Regenerate.
1228
faf766e3
NC		 12292018-01-13 Nick Clifton <nickc@redhat.com>
1230
1231 2.30 branch created.
1232
888a89da
IT		 12332018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1234
1235 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1236 * i386-tbl.h: Regenerate.
1237
cbda583a
JB		 12382018-01-10 Jan Beulich <jbeulich@suse.com>
1239
1240 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1241 * i386-tbl.h: Re-generate.
1242
c9e92278
JB		 12432018-01-10 Jan Beulich <jbeulich@suse.com>
1244
1245 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1246 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1247 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1248 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1249 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1250 Disp8MemShift of AVX512VL forms.
1251 * i386-tbl.h: Re-generate.
1252
35fd2b2b
JW		 12532018-01-09 Jim Wilson <jimw@sifive.com>
1254
1255 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1256 then the hi_addr value is zero.
1257
91d8b670
JG		 12582018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1259
1260 * arm-dis.c (arm_opcodes): Add csdb.
1261 (thumb32_opcodes): Add csdb.
1262
be2e7d95
JG		 12632018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1264
1265 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1266 * aarch64-asm-2.c: Regenerate.
1267 * aarch64-dis-2.c: Regenerate.
1268 * aarch64-opc-2.c: Regenerate.
1269
704a705d
L		 12702018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1271
1272 PR gas/22681
1273 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1274 Remove AVX512 vmovd with 64-bit operands.
1275 * i386-tbl.h: Regenerated.
1276
35eeb78f
JW		 12772018-01-05 Jim Wilson <jimw@sifive.com>
1278
1279 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1280 jalr.
1281
219d1afa
AM		 12822018-01-03 Alan Modra <amodra@gmail.com>
1283
1284 Update year range in copyright notice of all files.
1285
1508bbf5
JB		 12862018-01-02 Jan Beulich <jbeulich@suse.com>
1287
1288 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1289 and OPERAND_TYPE_REGZMM entries.
1290
1e563868 1291For older changes see ChangeLog-2017
3499769a 1292\f
1e563868 1293Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1294
1295Copying and distribution of this file, with or without modification,
1296are permitted in any medium without royalty provided the copyright
1297notice and this notice are preserved.
1298
1299Local Variables:
1300mode: change-log
1301left-margin: 8
1302fill-column: 74
1303version-control: never
1304End:
GDB Binutils - Deliverables
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