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2005-02-23 Andrew Cagney <cagney@gnu.org>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
ec36c4a4
NC		 12005-02-23 Nick Clifton <nickc@redhat.com>
2
3 * crx-dis.c (make_instruction): Move argument structure into inner
4 scope and ensure that all of its fields are initialised before
5 they are used.
6
53c9ebc5
AM		 72005-02-22 Alan Modra <amodra@bigpond.net.au>
8
9 * arc-ext.c: Warning fixes.
10 * arc-ext.h: Likewise.
11 * cgen-opc.c: Likewise.
12 * ia64-gen.c: Likewise.
13 * maxq-dis.c: Likewise.
14 * ns32k-dis.c: Likewise.
15 * w65-dis.c: Likewise.
16 * ia64-asmtab.c: Regenerate.
17
610ad19b
AM		 182005-02-22 Alan Modra <amodra@bigpond.net.au>
19
20 * fr30-desc.c: Regenerate.
21 * fr30-desc.h: Regenerate.
22 * fr30-opc.c: Regenerate.
23 * fr30-opc.h: Regenerate.
24 * frv-desc.c: Regenerate.
25 * frv-desc.h: Regenerate.
26 * frv-opc.c: Regenerate.
27 * frv-opc.h: Regenerate.
28 * ip2k-desc.c: Regenerate.
29 * ip2k-desc.h: Regenerate.
30 * ip2k-opc.c: Regenerate.
31 * ip2k-opc.h: Regenerate.
32 * iq2000-desc.c: Regenerate.
33 * iq2000-desc.h: Regenerate.
34 * iq2000-opc.c: Regenerate.
35 * iq2000-opc.h: Regenerate.
36 * m32r-desc.c: Regenerate.
37 * m32r-desc.h: Regenerate.
38 * m32r-opc.c: Regenerate.
39 * m32r-opc.h: Regenerate.
40 * m32r-opinst.c: Regenerate.
41 * openrisc-desc.c: Regenerate.
42 * openrisc-desc.h: Regenerate.
43 * openrisc-opc.c: Regenerate.
44 * openrisc-opc.h: Regenerate.
45 * xstormy16-desc.c: Regenerate.
46 * xstormy16-desc.h: Regenerate.
47 * xstormy16-opc.c: Regenerate.
48 * xstormy16-opc.h: Regenerate.
49
db9db6f2
AM		 502005-02-21 Alan Modra <amodra@bigpond.net.au>
51
52 * Makefile.am: Run "make dep-am"
53 * Makefile.in: Regenerate.
54
bf143b25
NC		 552005-02-15 Nick Clifton <nickc@redhat.com>
56
57 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
58 compile time warnings.
59 (print_keyword): Likewise.
60 (default_print_insn): Likewise.
61
62 * fr30-desc.c: Regenerated.
63 * fr30-desc.h: Regenerated.
64 * fr30-dis.c: Regenerated.
65 * fr30-opc.c: Regenerated.
66 * fr30-opc.h: Regenerated.
67 * frv-desc.c: Regenerated.
68 * frv-dis.c: Regenerated.
69 * frv-opc.c: Regenerated.
70 * ip2k-asm.c: Regenerated.
71 * ip2k-desc.c: Regenerated.
72 * ip2k-desc.h: Regenerated.
73 * ip2k-dis.c: Regenerated.
74 * ip2k-opc.c: Regenerated.
75 * ip2k-opc.h: Regenerated.
76 * iq2000-desc.c: Regenerated.
77 * iq2000-dis.c: Regenerated.
78 * iq2000-opc.c: Regenerated.
79 * m32r-asm.c: Regenerated.
80 * m32r-desc.c: Regenerated.
81 * m32r-desc.h: Regenerated.
82 * m32r-dis.c: Regenerated.
83 * m32r-opc.c: Regenerated.
84 * m32r-opc.h: Regenerated.
85 * m32r-opinst.c: Regenerated.
86 * openrisc-desc.c: Regenerated.
87 * openrisc-desc.h: Regenerated.
88 * openrisc-dis.c: Regenerated.
89 * openrisc-opc.c: Regenerated.
90 * openrisc-opc.h: Regenerated.
91 * xstormy16-desc.c: Regenerated.
92 * xstormy16-desc.h: Regenerated.
93 * xstormy16-dis.c: Regenerated.
94 * xstormy16-opc.c: Regenerated.
95 * xstormy16-opc.h: Regenerated.
96
d6098898
L		 972005-02-14 H.J. Lu <hongjiu.lu@intel.com>
98
99 * dis-buf.c (perror_memory): Use sprintf_vma to print out
100 address.
101
5a84f3e0
NC		 1022005-02-11 Nick Clifton <nickc@redhat.com>
103
bc18c937
NC		 104 * iq2000-asm.c: Regenerate.
105
5a84f3e0
NC		 106 * frv-dis.c: Regenerate.
107
0a40490e
JB		 1082005-02-07 Jim Blandy <jimb@redhat.com>
109
110 * Makefile.am (CGEN): Load guile.scm before calling the main
111 application script.
112 * Makefile.in: Regenerated.
113 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
114 Simply pass the cgen-opc.scm path to ${cgen} as its first
115 argument; ${cgen} itself now contains the '-s', or whatever is
116 appropriate for the Scheme being used.
117
c46f8c51
AC		 1182005-01-31 Andrew Cagney <cagney@gnu.org>
119
120 * configure: Regenerate to track ../gettext.m4.
121
60b9a617
JB		 1222005-01-31 Jan Beulich <jbeulich@novell.com>
123
124 * ia64-gen.c (NELEMS): Define.
125 (shrink): Generate alias with missing second predicate register when
126 opcode has two outputs and these are both predicates.
127 * ia64-opc-i.c (FULL17): Define.
128 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
129 here to generate output template.
130 (TBITCM, TNATCM): Undefine after use.
131 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
132 first input. Add ld16 aliases without ar.csd as second output. Add
133 st16 aliases without ar.csd as second input. Add cmpxchg aliases
134 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
135 ar.ccv as third/fourth inputs. Consolidate through...
136 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
137 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
138 * ia64-asmtab.c: Regenerate.
139
a53bf506
AC		 1402005-01-27 Andrew Cagney <cagney@gnu.org>
141
142 * configure: Regenerate to track ../gettext.m4 change.
143
90219bd0
AO		 1442005-01-25 Alexandre Oliva <aoliva@redhat.com>
145
146 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
147 * frv-asm.c: Rebuilt.
148 * frv-desc.c: Rebuilt.
149 * frv-desc.h: Rebuilt.
150 * frv-dis.c: Rebuilt.
151 * frv-ibld.c: Rebuilt.
152 * frv-opc.c: Rebuilt.
153 * frv-opc.h: Rebuilt.
154
45181ed1
AC		 1552005-01-24 Andrew Cagney <cagney@gnu.org>
156
157 * configure: Regenerate, ../gettext.m4 was updated.
158
9e836e3d
FF		 1592005-01-21 Fred Fish <fnf@specifixinc.com>
160
161 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
162 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
163 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
164 * mips-dis.c: Ditto.
165
5e8cb021
AM		 1662005-01-20 Alan Modra <amodra@bigpond.net.au>
167
168 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
169
986e18a5
FF		 1702005-01-19 Fred Fish <fnf@specifixinc.com>
171
172 * mips-dis.c (no_aliases): New disassembly option flag.
173 (set_default_mips_dis_options): Init no_aliases to zero.
174 (parse_mips_dis_option): Handle no-aliases option.
175 (print_insn_mips): Ignore table entries that are aliases
176 if no_aliases is set.
177 (print_insn_mips16): Ditto.
178 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
179 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
180 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
181 * mips16-opc.c (mips16_opcodes): Ditto.
182
e38bc3b5
NC		 1832005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
184
185 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
186 (inheritance diagram): Add missing edge.
187 (arch_sh1_up): Rename arch_sh_up to match external name to make life
188 easier for the testsuite.
189 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
190 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
610ad19b 191 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
e38bc3b5
NC		 192 arch_sh2a_or_sh4_up child.
193 (sh_table): Do renaming as above.
194 Correct comment for ldc.l for gas testsuite to read.
195 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
196 Correct comments for movy.w and movy.l for gas testsuite to read.
197 Correct comments for fmov.d and fmov.s for gas testsuite to read.
198
9df48ba9
L		 1992005-01-12 H.J. Lu <hongjiu.lu@intel.com>
200
201 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
202
2033b4b9
L		 2032005-01-12 H.J. Lu <hongjiu.lu@intel.com>
204
205 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
206
0bcb06d2
AS		 2072005-01-10 Andreas Schwab <schwab@suse.de>
208
209 * disassemble.c (disassemble_init_for_target) <case
210 bfd_arch_ia64>: Set skip_zeroes to 16.
211 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
212
47add74d
TL		 2132004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
214
215 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
216
246f4c05
SS		 2172004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
218
219 * avr-dis.c: Prettyprint. Added printing of symbol names in all
220 memory references. Convert avr_operand() to C90 formatting.
221
0e1200e5
TL		 2222004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
223
224 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
225
89a649f7
TL		 2262004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
227
228 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
229 (no_op_insn): Initialize array with instructions that have no
230 operands.
231 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
232
6255809c
RE		 2332004-11-29 Richard Earnshaw <rearnsha@arm.com>
234
235 * arm-dis.c: Correct top-level comment.
236
2fbad815
RE		 2372004-11-27 Richard Earnshaw <rearnsha@arm.com>
238
239 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
240 architecuture defining the insn.
241 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 242 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
243 field.
2fbad815
RE		 244 Also include opcode/arm.h.
245 * Makefile.am (arm-dis.lo): Update dependency list.
246 * Makefile.in: Regenerate.
247
d81acc42
NC		 2482004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
249
250 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
251 reflect the change to the short immediate syntax.
252
ca4f2377
AM		 2532004-11-19 Alan Modra <amodra@bigpond.net.au>
254
5da8bf1b
AM		 255 * or32-opc.c (debug): Warning fix.
256 * po/POTFILES.in: Regenerate.
257
ca4f2377
AM		 258 * maxq-dis.c: Formatting.
259 (print_insn): Warning fix.
260
b7693d02
DJ		 2612004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
262
263 * arm-dis.c (WORD_ADDRESS): Define.
264 (print_insn): Use it. Correct big-endian end-of-section handling.
265
300dac7e
NC		 2662004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
267 Vineet Sharma <vineets@noida.hcltech.com>
268
269 * maxq-dis.c: New file.
270 * disassemble.c (ARCH_maxq): Define.
610ad19b 271 (disassembler): Add 'print_insn_maxq_little' for handling maxq
300dac7e
NC		 272 instructions..
273 * configure.in: Add case for bfd_maxq_arch.
274 * configure: Regenerate.
275 * Makefile.am: Add support for maxq-dis.c
276 * Makefile.in: Regenerate.
277 * aclocal.m4: Regenerate.
278
42048ee7
TL		 2792004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
280
281 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
282 mode.
283 * crx-dis.c: Likewise.
284
bd21e58e
HPN		 2852004-11-04 Hans-Peter Nilsson <hp@axis.com>
286
287 Generally, handle CRISv32.
288 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
289 (struct cris_disasm_data): New type.
290 (format_reg, format_hex, cris_constraint, print_flags)
291 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
292 callers changed.
293 (format_sup_reg, print_insn_crisv32_with_register_prefix)
294 (print_insn_crisv32_without_register_prefix)
295 (print_insn_crisv10_v32_with_register_prefix)
296 (print_insn_crisv10_v32_without_register_prefix)
297 (cris_parse_disassembler_options): New functions.
298 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
299 parameter. All callers changed.
300 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
301 failure.
302 (cris_constraint) <case 'Y', 'U'>: New cases.
303 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
304 for constraint 'n'.
305 (print_with_operands) <case 'Y'>: New case.
306 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
307 <case 'N', 'Y', 'Q'>: New cases.
308 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
309 (print_insn_cris_with_register_prefix)
310 (print_insn_cris_without_register_prefix): Call
311 cris_parse_disassembler_options.
312 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
313 for CRISv32 and the size of immediate operands. New v32-only
314 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
315 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
316 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
317 Change brp to be v3..v10.
318 (cris_support_regs): New vector.
319 (cris_opcodes): Update head comment. New format characters '[',
320 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
321 Add new opcodes for v32 and adjust existing opcodes to accommodate
322 differences to earlier variants.
323 (cris_cond15s): New vector.
324
9306ca4a
JB		 3252004-11-04 Jan Beulich <jbeulich@novell.com>
326
327 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
328 (indirEb): Remove.
329 (Mp): Use f_mode rather than none at all.
330 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
331 replaces what previously was x_mode; x_mode now means 128-bit SSE
332 operands.
333 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
334 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
335 pinsrw's second operand is Edqw.
336 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
337 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
338 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
339 mode when an operand size override is present or always suffixing.
340 More instructions will need to be added to this group.
341 (putop): Handle new macro chars 'C' (short/long suffix selector),
342 'I' (Intel mode override for following macro char), and 'J' (for
343 adding the 'l' prefix to far branches in AT&T mode). When an
344 alternative was specified in the template, honor macro character when
345 specified for Intel mode.
346 (OP_E): Handle new *_mode values. Correct pointer specifications for
347 memory operands. Consolidate output of index register.
348 (OP_G): Handle new *_mode values.
349 (OP_I): Handle const_1_mode.
350 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
351 respective opcode prefix bits have been consumed.
352 (OP_EM, OP_EX): Provide some default handling for generating pointer
353 specifications.
354
f39c96a9
TL		 3552004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
356
357 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
358 COP_INST macro.
359
812337be
TL		 3602004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
361
362 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
363 (getregliststring): Support HI/LO and user registers.
610ad19b 364 * crx-opc.c (crx_instruction): Update data structure according to the
812337be
TL		 365 rearrangement done in CRX opcode header file.
366 (crx_regtab): Likewise.
367 (crx_optab): Likewise.
610ad19b 368 (crx_instruction): Reorder load/stor instructions, remove unsupported
812337be
TL		 369 formats.
370 support new Co-Processor instruction 'cpi'.
371
4030fa5a
NC		 3722004-10-27 Nick Clifton <nickc@redhat.com>
373
374 * opcodes/iq2000-asm.c: Regenerate.
375 * opcodes/iq2000-desc.c: Regenerate.
376 * opcodes/iq2000-desc.h: Regenerate.
377 * opcodes/iq2000-dis.c: Regenerate.
378 * opcodes/iq2000-ibld.c: Regenerate.
379 * opcodes/iq2000-opc.c: Regenerate.
380 * opcodes/iq2000-opc.h: Regenerate.
381
fc3d45e8
TL		 3822004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
383
384 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
385 us4, us5 (respectively).
386 Remove unsupported 'popa' instruction.
387 Reverse operands order in store co-processor instructions.
388
3c55da70
AM		 3892004-10-15 Alan Modra <amodra@bigpond.net.au>
390
391 * Makefile.am: Run "make dep-am"
392 * Makefile.in: Regenerate.
393
7fa3d080
BW		 3942004-10-12 Bob Wilson <bob.wilson@acm.org>
395
396 * xtensa-dis.c: Use ISO C90 formatting.
397
e612bb4d
AM		 3982004-10-09 Alan Modra <amodra@bigpond.net.au>
399
400 * ppc-opc.c: Revert 2004-09-09 change.
401
43cd72b9
BW		 4022004-10-07 Bob Wilson <bob.wilson@acm.org>
403
404 * xtensa-dis.c (state_names): Delete.
405 (fetch_data): Use xtensa_isa_maxlength.
406 (print_xtensa_operand): Replace operand parameter with opcode/operand
407 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
408 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
409 instruction bundles. Use xmalloc instead of malloc.
410
bbac1f2a
NC		 4112004-10-07 David Gibson <david@gibson.dropbear.id.au>
412
413 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
414 initializers.
415
48c9f030
NC		 4162004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
417
418 * crx-opc.c (crx_instruction): Support Co-processor insns.
419 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
420 (getregliststring): Change function to use the above enum.
421 (print_arg): Handle CO-Processor insns.
422 (crx_cinvs): Add 'b' option to invalidate the branch-target
423 cache.
424
12c64a4e
AH		 4252004-10-06 Aldy Hernandez <aldyh@redhat.com>
426
427 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
428 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
429 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
430 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
431 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
432
14127cc4
NC		 4332004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
434
435 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
436 rather than add it.
437
0dd132b6
NC		 4382004-09-30 Paul Brook <paul@codesourcery.com>
439
440 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
441 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
442
3f85e526
L		 4432004-09-17 H.J. Lu <hongjiu.lu@intel.com>
444
445 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
446 (CONFIG_STATUS_DEPENDENCIES): New.
447 (Makefile): Removed.
448 (config.status): Likewise.
449 * Makefile.in: Regenerated.
450
8ae85421
AM		 4512004-09-17 Alan Modra <amodra@bigpond.net.au>
452
453 * Makefile.am: Run "make dep-am".
454 * Makefile.in: Regenerate.
455 * aclocal.m4: Regenerate.
456 * configure: Regenerate.
457 * po/POTFILES.in: Regenerate.
458 * po/opcodes.pot: Regenerate.
459
24443139
AS		 4602004-09-11 Andreas Schwab <schwab@suse.de>
461
462 * configure: Rebuild.
463
2a309db0
AM		 4642004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
465
466 * ppc-opc.c (L): Make this field not optional.
467
42851540
NC		 4682004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
469
470 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
471 Fix parameter to 'm[t|f]csr' insns.
472
979273e3
NN		 4732004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
474
475 * configure.in: Autoupdate to autoconf 2.59.
476 * aclocal.m4: Rebuild with aclocal 1.4p6.
477 * configure: Rebuild with autoconf 2.59.
478 * Makefile.in: Rebuild with automake 1.4p6 (picking up
479 bfd changes for autoconf 2.59 on the way).
480 * config.in: Rebuild with autoheader 2.59.
481
ac28a1cb
RS		 4822004-08-27 Richard Sandiford <rsandifo@redhat.com>
483
484 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
485
30d1c836
ML		 4862004-07-30 Michal Ludvig <mludvig@suse.cz>
487
488 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
489 (GRPPADLCK2): New define.
490 (twobyte_has_modrm): True for 0xA6.
491 (grps): GRPPADLCK2 for opcode 0xA6.
492
0b0ac059
AO		 4932004-07-29 Alexandre Oliva <aoliva@redhat.com>
494
495 Introduce SH2a support.
496 * sh-opc.h (arch_sh2a_base): Renumber.
497 (arch_sh2a_nofpu_base): Remove.
498 (arch_sh_base_mask): Adjust.
499 (arch_opann_mask): New.
500 (arch_sh2a, arch_sh2a_nofpu): Adjust.
501 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
502 (sh_table): Adjust whitespace.
503 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
504 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
505 instruction list throughout.
506 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
507 of arch_sh2a in instruction list throughout.
508 (arch_sh2e_up): Accomodate above changes.
509 (arch_sh2_up): Ditto.
510 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
511 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
512 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
513 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
514 * sh-opc.h (arch_sh2a_nofpu): New.
515 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
516 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
517 instruction.
518 2004-01-20 DJ Delorie <dj@redhat.com>
519 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
520 2003-12-29 DJ Delorie <dj@redhat.com>
521 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
522 sh_opcode_info, sh_table): Add sh2a support.
523 (arch_op32): New, to tag 32-bit opcodes.
524 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
525 2003-12-02 Michael Snyder <msnyder@redhat.com>
526 * sh-opc.h (arch_sh2a): Add.
527 * sh-dis.c (arch_sh2a): Handle.
528 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
529
670ec21d
NC		 5302004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
531
532 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
533
ed049af3
NC		 5342004-07-22 Nick Clifton <nickc@redhat.com>
535
536 PR/280
537 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
538 insns - this is done by objdump itself.
539 * h8500-dis.c (print_insn_h8500): Likewise.
540
20f0a1fc
NC		 5412004-07-21 Jan Beulich <jbeulich@novell.com>
542
543 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
544 regardless of address size prefix in effect.
545 (ptr_reg): Size or address registers does not depend on rex64, but
546 on the presence of an address size override.
547 (OP_MMX): Use rex.x only for xmm registers.
548 (OP_EM): Use rex.z only for xmm registers.
549
6f14957b
MR		 5502004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
551
552 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
553 move/branch operations to the bottom so that VR5400 multimedia
554 instructions take precedence in disassembly.
555
1586d91e
MR		 5562004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
557
558 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
559 ISA-specific "break" encoding.
560
982de27a
NC		 5612004-07-13 Elvis Chiang <elvisfb@gmail.com>
562
563 * arm-opc.h: Fix typo in comment.
564
4300ab10
AS		 5652004-07-11 Andreas Schwab <schwab@suse.de>
566
567 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
568
8577e690
AS		 5692004-07-09 Andreas Schwab <schwab@suse.de>
570
571 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
572
1fe1f39c
NC		 5732004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
574
575 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
576 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
577 (crx-dis.lo): New target.
578 (crx-opc.lo): Likewise.
579 * Makefile.in: Regenerate.
580 * configure.in: Handle bfd_crx_arch.
581 * configure: Regenerate.
582 * crx-dis.c: New file.
583 * crx-opc.c: New file.
584 * disassemble.c (ARCH_crx): Define.
585 (disassembler): Handle ARCH_crx.
586
7a33b495
JW		 5872004-06-29 James E Wilson <wilson@specifixinc.com>
588
589 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
590 * ia64-asmtab.c: Regnerate.
591
98e69875
AM		 5922004-06-28 Alan Modra <amodra@bigpond.net.au>
593
594 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
595 (extract_fxm): Don't test dialect.
596 (XFXFXM_MASK): Include the power4 bit.
597 (XFXM): Add p4 param.
598 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
599
a53b85e2
AO		 6002004-06-27 Alexandre Oliva <aoliva@redhat.com>
601
602 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
603 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
604
d0618d1c
AM		 6052004-06-26 Alan Modra <amodra@bigpond.net.au>
606
607 * ppc-opc.c (BH, XLBH_MASK): Define.
608 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
609
1d9f512f
AM		 6102004-06-24 Alan Modra <amodra@bigpond.net.au>
611
612 * i386-dis.c (x_mode): Comment.
613 (two_source_ops): File scope.
614 (float_mem): Correct fisttpll and fistpll.
615 (float_mem_mode): New table.
616 (dofloat): Use it.
617 (OP_E): Correct intel mode PTR output.
618 (ptr_reg): Use open_char and close_char.
619 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
620 operands. Set two_source_ops.
621
52886d70
AM		 6222004-06-15 Alan Modra <amodra@bigpond.net.au>
623
624 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
625 instead of _raw_size.
626
bad9ceea
JJ		 6272004-06-08 Jakub Jelinek <jakub@redhat.com>
628
629 * ia64-gen.c (in_iclass): Handle more postinc st
630 and ld variants.
631 * ia64-asmtab.c: Rebuilt.
632
0451f5df
MS		 6332004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
634
635 * s390-opc.txt: Correct architecture mask for some opcodes.
636 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
637 in the esa mode as well.
638
f6f9408f
JR		 6392004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
640
641 * sh-dis.c (target_arch): Make unsigned.
642 (print_insn_sh): Replace (most of) switch with a call to
643 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
644 * sh-opc.h: Redefine architecture flags values.
645 Add sh3-nommu architecture.
646 Reorganise <arch>_up macros so they make more visual sense.
647 (SH_MERGE_ARCH_SET): Define new macro.
648 (SH_VALID_BASE_ARCH_SET): Likewise.
649 (SH_VALID_MMU_ARCH_SET): Likewise.
650 (SH_VALID_CO_ARCH_SET): Likewise.
651 (SH_VALID_ARCH_SET): Likewise.
652 (SH_MERGE_ARCH_SET_VALID): Likewise.
653 (SH_ARCH_SET_HAS_FPU): Likewise.
654 (SH_ARCH_SET_HAS_DSP): Likewise.
655 (SH_ARCH_UNKNOWN_ARCH): Likewise.
656 (sh_get_arch_from_bfd_mach): Add prototype.
657 (sh_get_arch_up_from_bfd_mach): Likewise.
658 (sh_get_bfd_mach_from_arch_set): Likewise.
659 (sh_merge_bfd_arc): Likewise.
660
be8c092b
NC		 6612004-05-24 Peter Barada <peter@the-baradas.com>
662
663 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
610ad19b
AM		 664 into new match_insn_m68k function. Loop over canidate
665 matches and select first that completely matches.
be8c092b
NC		 666 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
667 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
610ad19b 668 to verify addressing for MAC/EMAC.
be8c092b
NC		 669 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
670 reigster halves since 'fpu' and 'spl' look misleading.
671 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
672 * m68k-opc.c: Rearragne mac/emac cases to use longest for
673 first, tighten up match masks.
674 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
675 'size' from special case code in print_insn_m68k to
676 determine decode size of insns.
677
a30e9cc4
AM		 6782004-05-19 Alan Modra <amodra@bigpond.net.au>
679
680 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
681 well as when -mpower4.
682
9598fbe5
NC		 6832004-05-13 Nick Clifton <nickc@redhat.com>
684
685 * po/fr.po: Updated French translation.
686
6b6e92f4
NC		 6872004-05-05 Peter Barada <peter@the-baradas.com>
688
689 * m68k-dis.c(print_insn_m68k): Add new chips, use core
690 variants in arch_mask. Only set m68881/68851 for 68k chips.
691 * m68k-op.c: Switch from ColdFire chips to core variants.
692
a404d431
AM		 6932004-05-05 Alan Modra <amodra@bigpond.net.au>
694
a30e9cc4 695 PR 147.
a404d431
AM		 696 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
697
f3806e43
BE		 6982004-04-29 Ben Elliston <bje@au.ibm.com>
699
520ceea4
BE		 700 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
701 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 702
1f1799d5
KK		 7032004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
704
705 * sh-dis.c (print_insn_sh): Print the value in constant pool
706 as a symbol if it looks like a symbol.
707
fd99574b
NC		 7082004-04-22 Peter Barada <peter@the-baradas.com>
709
710 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
711 appropriate ColdFire architectures.
712 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
713 mask addressing.
714 Add EMAC instructions, fix MAC instructions. Remove
715 macmw/macml/msacmw/msacml instructions since mask addressing now
716 supported.
717
b4781d44
JJ		 7182004-04-20 Jakub Jelinek <jakub@redhat.com>
719
720 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
721 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
722 suffix. Use fmov*x macros, create all 3 fpsize variants in one
723 macro. Adjust all users.
724
91809fda 7252004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
610ad19b 726
91809fda
NC		 727 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
728 separately.
729
f4453dfa
NC		 7302004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
731
732 * m32r-asm.c: Regenerate.
733
9b0de91a
SS		 7342004-03-29 Stan Shebs <shebs@apple.com>
735
736 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
737 used.
738
e20c0b3d
AM		 7392004-03-19 Alan Modra <amodra@bigpond.net.au>
740
741 * aclocal.m4: Regenerate.
742 * config.in: Regenerate.
743 * configure: Regenerate.
744 * po/POTFILES.in: Regenerate.
745 * po/opcodes.pot: Regenerate.
746
fdd12ef3
AM		 7472004-03-16 Alan Modra <amodra@bigpond.net.au>
748
749 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
750 PPC_OPERANDS_GPR_0.
751 * ppc-opc.c (RA0): Define.
752 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
753 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 754 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 755
2dc111b3 7562004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 757
758 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 759
7bfeee7b
AM		 7602004-03-15 Alan Modra <amodra@bigpond.net.au>
761
762 * sparc-dis.c (print_insn_sparc): Update getword prototype.
763
7ffdda93
ML		 7642004-03-12 Michal Ludvig <mludvig@suse.cz>
765
766 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 767 (grps): Delete GRPPLOCK entry.
7ffdda93 768
cc0ec051
AM		 7692004-03-12 Alan Modra <amodra@bigpond.net.au>
770
771 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
772 (M, Mp): Use OP_M.
773 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
774 (GRPPADLCK): Define.
775 (dis386): Use NOP_Fixup on "nop".
776 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
777 (twobyte_has_modrm): Set for 0xa7.
778 (padlock_table): Delete. Move to..
779 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
780 and clflush.
781 (print_insn): Revert PADLOCK_SPECIAL code.
782 (OP_E): Delete sfence, lfence, mfence checks.
783
4fd61dcb
JJ		 7842004-03-12 Jakub Jelinek <jakub@redhat.com>
785
786 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
787 (INVLPG_Fixup): New function.
788 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
789
0f10071e
ML		 7902004-03-12 Michal Ludvig <mludvig@suse.cz>
791
792 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
793 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
794 (padlock_table): New struct with PadLock instructions.
795 (print_insn): Handle PADLOCK_SPECIAL.
796
c02908d2
AM		 7972004-03-12 Alan Modra <amodra@bigpond.net.au>
798
799 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
800 (OP_E): Twiddle clflush to sfence here.
801
d5bb7600
NC		 8022004-03-08 Nick Clifton <nickc@redhat.com>
803
804 * po/de.po: Updated German translation.
805
ae51a426
JR		 8062003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
807
808 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
809 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
810 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
811 accordingly.
812
676a64f4
RS		 8132004-03-01 Richard Sandiford <rsandifo@redhat.com>
814
815 * frv-asm.c: Regenerate.
816 * frv-desc.c: Regenerate.
817 * frv-desc.h: Regenerate.
818 * frv-dis.c: Regenerate.
819 * frv-ibld.c: Regenerate.
820 * frv-opc.c: Regenerate.
821 * frv-opc.h: Regenerate.
822
c7a48b9a
RS		 8232004-03-01 Richard Sandiford <rsandifo@redhat.com>
824
825 * frv-desc.c, frv-opc.c: Regenerate.
826
8ae0baa2
RS		 8272004-03-01 Richard Sandiford <rsandifo@redhat.com>
828
829 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
830
ce11586c
JR		 8312004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
832
833 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
834 Also correct mistake in the comment.
835
6a5709a5
JR		 8362004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
837
838 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
839 ensure that double registers have even numbers.
840 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
841 that reserved instruction 0xfffd does not decode the same
842 as 0xfdfd (ftrv).
843 * sh-opc.h: Add REG_N_D nibble type and use it whereever
844 REG_N refers to a double register.
845 Add REG_N_B01 nibble type and use it instead of REG_NM
846 in ftrv.
847 Adjust the bit patterns in a few comments.
848
e5d2b64f 8492004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 850
851 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 852
1f04b05f
AH		 8532004-02-20 Aldy Hernandez <aldyh@redhat.com>
854
855 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
856
2f3b8700
AH		 8572004-02-20 Aldy Hernandez <aldyh@redhat.com>
858
859 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
860
f0b26da6 8612004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 862
863 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
864 mtivor32, mtivor33, mtivor34.
f0b26da6 865
23d59c56 8662004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 867
868 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 869
34920d91
NC		 8702004-02-10 Petko Manolov <petkan@nucleusys.com>
871
872 * arm-opc.h Maverick accumulator register opcode fixes.
873
44d86481
BE		 8742004-02-13 Ben Elliston <bje@wasabisystems.com>
875
876 * m32r-dis.c: Regenerate.
877
17707c23
MS		 8782004-01-27 Michael Snyder <msnyder@redhat.com>
879
880 * sh-opc.h (sh_table): "fsrra", not "fssra".
881
fe3a9bc4
NC		 8822004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
883
884 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
885 contraints.
886
ff24f124
JJ		 8872004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
888
889 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
890
a02a862a
AM		 8912004-01-19 Alan Modra <amodra@bigpond.net.au>
892
893 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
894 1. Don't print scale factor on AT&T mode when index missing.
895
d164ea7f
AO		 8962004-01-16 Alexandre Oliva <aoliva@redhat.com>
897
898 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
899 when loaded into XR registers.
900
cb10e79a
RS		 9012004-01-14 Richard Sandiford <rsandifo@redhat.com>
902
903 * frv-desc.h: Regenerate.
904 * frv-desc.c: Regenerate.
905 * frv-opc.c: Regenerate.
906
f532f3fa
MS		 9072004-01-13 Michael Snyder <msnyder@redhat.com>
908
909 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
910
e45d0630
PB		 9112004-01-09 Paul Brook <paul@codesourcery.com>
912
913 * arm-opc.h (arm_opcodes): Move generic mcrr after known
914 specific opcodes.
915
3ba7a1aa
DJ		 9162004-01-07 Daniel Jacobowitz <drow@mvista.com>
917
918 * Makefile.am (libopcodes_la_DEPENDENCIES)
919 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
920 comment about the problem.
921 * Makefile.in: Regenerate.
922
ba2d3f07
AO		 9232004-01-06 Alexandre Oliva <aoliva@redhat.com>
924
925 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
926 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
927 cut&paste errors in shifting/truncating numerical operands.
928 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
929 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
930 (parse_uslo16): Likewise.
931 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
932 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
933 (parse_s12): Likewise.
934 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
935 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
936 (parse_uslo16): Likewise.
937 (parse_uhi16): Parse gothi and gotfuncdeschi.
938 (parse_d12): Parse got12 and gotfuncdesc12.
939 (parse_s12): Likewise.
940
3ab48931
NC		 9412004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
942
943 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
944 instruction which looks similar to an 'rla' instruction.
a0bd404e 945
c9e214e5 946For older changes see ChangeLog-0203
252b5132
RH		 947\f
948Local Variables:
2f6d2f85
NC		 949mode: change-log
950left-margin: 8
951fill-column: 74
252b5132
RH		 952version-control: never
953End:
GDB Binutils - Deliverables
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