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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
3cac54d2
RW		 12010-09-27 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
2
3 * configure: Regenerate.
4
d9aee5d7
AK		 52010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
6
7 * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
8 (main): Recognize the new CPU string.
9 * s390-opc.c: Add new instruction formats and masks.
10 * s390-opc.txt: Add new z196 instructions.
11
02cbf767
AK		 122010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
13
14 * s390-dis.c (print_insn_s390): Pick instruction with most
15 specific mask.
16 * s390-opc.c: Add unused bits to the insn mask.
17 * s390-opc.txt: Reorder some instructions to prefer more recent
18 versions.
19
6844b2c2
MGD		 202010-09-27 Tejas Belagod <tejas.belagod@arm.com>
21
22 * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
23 correction to unaligned PCs while printing comment.
24
90ec0d68
MGD		 252010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
26
27 * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
28 (thumb32_opcodes): Likewise.
29 (banked_regname): New function.
30 (print_insn_arm): Add Virtualization Extensions support.
31 (print_insn_thumb32): Likewise.
32
eea54501
MGD		 332010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
34
35 * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
36 ARM state.
37
f4c65163
MGD		 382010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
39
40 * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
41 (thumb32_opcodes): Likewise.
42
60e5ef9f
MGD		 432010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
44
45 * arm-dis.c (arm_opcodes): Add support for pldw.
46 (thumb32_opcodes): Likewise.
47
7a360e83
MF		 482010-09-22 Robin Getz <robin.getz@analog.com>
49
50 * bfin-dis.c (fmtconst): Cast address to 32bits.
51
35fc57f3
MF		 522010-09-22 Mike Frysinger <vapier@gentoo.org>
53
54 * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
55
219b747a
MF		 562010-09-22 Robin Getz <robin.getz@analog.com>
57
58 * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
59 Reject P6/P7 to TESTSET.
60 (decode_PushPopReg_0): Check for parallel insns. Reject pushing
61 SP onto the stack.
62 (decode_PushPopMultiple_0): Check for parallel insns. Make sure
63 P/D fields match all the time.
64 (decode_CCflag_0): Check for parallel insns. Verify x/y fields
65 are 0 for accumulator compares.
66 (decode_CC2stat_0): Check for parallel insns. Reject CC<op>CC.
67 (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
68 decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
69 decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
70 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
71 decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
72 insns.
73 (decode_dagMODim_0): Verify br field for IREG ops.
74 (decode_LDST_0): Reject preg load into same preg.
75 (_print_insn_bfin): Handle returns for ILLEGAL decodes.
76 (print_insn_bfin): Likewise.
77
775f1cf0
MF		 782010-09-22 Mike Frysinger <vapier@gentoo.org>
79
80 * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
81
0b7691fd
MF		 822010-09-22 Robin Getz <robin.getz@analog.com>
83
84 * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
85
b2459327
MF		 862010-09-22 Mike Frysinger <vapier@gentoo.org>
87
88 * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
89
50e2162a
MF		 902010-09-22 Robin Getz <robin.getz@analog.com>
91
92 * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
93 register values greater than 8.
94 (IS_RESERVEDREG, allreg, mostreg): New helpers.
95 (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
96 (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
97 (decode_CC2dreg_0): Check valid CC register number.
98
a01eda85
MF		 992010-09-22 Robin Getz <robin.getz@analog.com>
100
101 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
102
22215ae0
MF		 1032010-09-22 Robin Getz <robin.getz@analog.com>
104
105 * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
106 (reg_names): Likewise.
107 (decode_statbits): Likewise; while reformatting to make manageable.
108
73a63ccf
MF		 1092010-09-22 Mike Frysinger <vapier@gentoo.org>
110
111 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
112 (decode_pseudoOChar_0): New function.
113 (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
114
59a82d23
MF		 1152010-09-22 Robin Getz <robin.getz@analog.com>
116
117 * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
118 LSHIFT instead of SHIFT.
119
528c6277
MF		 1202010-09-22 Mike Frysinger <vapier@gentoo.org>
121
122 * bfin-dis.c (constant_formats): Constify the whole structure.
123 (fmtconst): Add const to return value.
124 (reg_names): Mark const.
125 (decode_multfunc): Mark s0/s1 as const.
126 (decode_macfunc): Mark a/sop as const.
127
db472d6f
MGD		 1282010-09-17 Tejas Belagod <tejas.belagod@arm.com>
129
130 * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
131
f6690563
MR		 1322010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
133
134 * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
135 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
136
8901a3cd
PM		 1372010-09-10 Pierre Muller <muller@ics.u-strasbg.fr>
138
139 * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
140 dlx_insn_type array.
141
d9e3625e
L		 1422010-08-31 H.J. Lu <hongjiu.lu@intel.com>
143
144 PR binutils/11960
145 * i386-dis.c (sIv): New.
146 (dis386): Replace Iq with sIv on "pushT".
147 (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
148 (x86_64_table): Replace {T|}/{P|} with P.
149 (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
150 (OP_sI): Update v_mode. Remove w_mode.
151
f383de66
NF		 1522010-08-27 Nathan Froyd <froydnj@codesourcery.com>
153
154 * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
155 on E500 and E500MC.
156
1ab03f4b
L		 1572010-08-17 H.J. Lu <hongjiu.lu@intel.com>
158
159 * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
160 prefetchw.
161
22109423
L		 1622010-08-06 Quentin Neill <quentin.neill@amd.com>
163
164 * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
165 to processor flags for PENTIUMPRO processors and later.
166 * i386-opc.h (enum): Add CpuNop.
167 (i386_cpu_flags): Add cpunop bit.
168 * i386-opc.tbl: Change nop cpu_flags.
169 * i386-init.h: Regenerated.
170 * i386-tbl.h: Likewise.
171
b49dfb4a
L		 1722010-08-06 Quentin Neill <quentin.neill@amd.com>
173
174 * i386-opc.h (enum): Fix typos in comments.
175
6ca4eb77
AM		 1762010-08-06 Alan Modra <amodra@gmail.com>
177
178 * disassemble.c: Formatting.
179 (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
180
92d4d42e
L		 1812010-08-05 H.J. Lu <hongjiu.lu@intel.com>
182
183 * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
184 * i386-tbl.h: Regenerated.
185
b414985b
L		 1862010-08-05 H.J. Lu <hongjiu.lu@intel.com>
187
188 * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
189
190 * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b.
191 * i386-tbl.h: Regenerated.
192
f9c7014e
DD		 1932010-07-29 DJ Delorie <dj@redhat.com>
194
195 * rx-decode.opc (SRR): New.
196 (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
197 r0,r0) and NOP3 (max r0,r0) special cases.
198 * rx-decode.c: Regenerate.
6ca4eb77 199
592a252b
L		 2002010-07-28 H.J. Lu <hongjiu.lu@intel.com>
201
202 * i386-dis.c: Add 0F to VEX opcode enums.
203
3cf79a01
DD		 2042010-07-27 DJ Delorie <dj@redhat.com>
205
206 * rx-decode.opc (store_flags): Remove, replace with F_* macros.
207 (rx_decode_opcode): Likewise.
208 * rx-decode.c: Regenerate.
209
1cd986c5
NC		 2102010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
211 Ina Pandit <ina.pandit@kpitcummins.com>
212
213 * v850-dis.c (v850_sreg_names): Updated structure for system
214 registers.
215 (float_cc_names): new structure for condition codes.
216 (print_value): Update the function that prints value.
217 (get_operand_value): New function to get the operand value.
218 (disassemble): Updated to handle the disassembly of instructions.
219 (print_insn_v850): Updated function to print instruction for different
220 families.
221 * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
222 extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
223 extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
224 insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
225 extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
226 extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
227 extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
228 insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
229 (insert_d8_7, insert_d5_4, insert_i5div): Remove.
230 (v850_operands): Update with the relocation name. Also update
231 the instructions with specific set of processors.
232
52e7f43d
RE		 2332010-07-08 Tejas Belagod <tejas.belagod@arm.com>
234
235 * arm-dis.c (print_insn_arm): Add cases for printing more
236 symbolic operands.
237 (print_insn_thumb32): Likewise.
238
c680e7f6
MR		 2392010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
240
241 * mips-dis.c (print_insn_mips): Correct branch instruction type
242 determination.
243
9a2c7088
MR		 2442010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
245
246 * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
247 type and delay slot determination.
248 (print_insn_mips16): Extend branch instruction type and delay
249 slot determination to cover all instructions.
250 * mips16-opc.c (BR): Remove macro.
251 (UBR, CBR): New macros.
252 (mips16_opcodes): Update branch annotation for "b", "beqz",
253 "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
254 and "jrc".
255
d7d9a9f8
L		 2562010-07-05 H.J. Lu <hongjiu.lu@intel.com>
257
258 AVX Programming Reference (June, 2010)
259 * i386-dis.c (mod_table): Replace rdrnd with rdrand.
260 * i386-opc.tbl: Likewise.
261 * i386-tbl.h: Regenerated.
262
77321f53
L		 2632010-07-05 H.J. Lu <hongjiu.lu@intel.com>
264
265 * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
266
7102e95e
AS		 2672010-07-03 Andreas Schwab <schwab@linux-m68k.org>
268
269 * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
270 ppc_cpu_t before inverting.
3a5530ea
AS		 271 (ppc_parse_cpu): Likewise.
272 (print_insn_powerpc): Likewise.
7102e95e 273
bdc70b4a
AM		 2742010-07-03 Alan Modra <amodra@gmail.com>
275
276 * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
277 * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
278 (PPC64, MFDEC2): Update.
279 (NON32, NO371): Define.
280 (powerpc_opcode): Update to not use old opcode flags, and avoid
281 -m601 duplicates.
282
21375995
DD		 2832010-07-03 DJ Delorie <dj@delorie.com>
284
285 * m32c-ibld.c: Regenerate.
286
81a0b7e2
AM		 2872010-07-03 Alan Modra <amodra@gmail.com>
288
289 * ppc-opc.c (PWR2COM): Define.
290 (PPCPWR2): Add PPC_OPCODE_COMMON.
291 (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
292 "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst",
293 "rac" from -mcom.
294
c7b8aa3a
L		 2952010-07-01 H.J. Lu <hongjiu.lu@intel.com>
296
297 AVX Programming Reference (June, 2010)
298 * i386-dis.c (PREFIX_0FAE_REG_0): New.
299 (PREFIX_0FAE_REG_1): Likewise.
300 (PREFIX_0FAE_REG_2): Likewise.
301 (PREFIX_0FAE_REG_3): Likewise.
302 (PREFIX_VEX_3813): Likewise.
303 (PREFIX_VEX_3A1D): Likewise.
304 (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
305 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
306 PREFIX_VEX_3A1D.
307 (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
308 (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
309 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
310
311 * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
312 CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
313 (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
314
315 * i386-opc.h (CpuXsaveopt): New.
77321f53 316 (CpuFSGSBase): Likewise.
c7b8aa3a
L		 317 (CpuRdRnd): Likewise.
318 (CpuF16C): Likewise.
319 (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
320 cpuf16c.
321
322 * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
323 wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
a00eb5e8
L		 324 * i386-init.h: Regenerated.
325 * i386-tbl.h: Likewise.
c7b8aa3a 326
09a8ad8d
AM		 3272010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
328
329 * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
330 and mtocrf on EFS.
331
360cfc9c
AM		 3322010-06-29 Alan Modra <amodra@gmail.com>
333
334 * maxq-dis.c: Delete file.
335 * Makefile.am: Remove references to maxq.
336 * configure.in: Likewise.
337 * disassemble.c: Likewise.
338 * Makefile.in: Regenerate.
339 * configure: Regenerate.
340 * po/POTFILES.in: Regenerate.
341
dc898d5e
AM		 3422010-06-29 Alan Modra <amodra@gmail.com>
343
344 * mep-dis.c: Regenerate.
345
8e560766
MGD		 3462010-06-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
347
348 * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.
349
c7e2358a
AM		 3502010-06-27 Alan Modra <amodra@gmail.com>
351
352 * arc-dis.c (arc_sprintf): Delete set but unused variables.
353 (decodeInstr): Likewise.
354 * dlx-dis.c (print_insn_dlx): Likewise.
355 * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
356 * maxq-dis.c (check_move, print_insn): Likewise.
357 * mep-dis.c (mep_examine_ivc2_insns): Likewise.
358 * msp430-dis.c (msp430_branchinstr): Likewise.
359 * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
360 * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
361 * sparc-dis.c (print_insn_sparc): Likewise.
362 * fr30-asm.c: Regenerate.
363 * frv-asm.c: Regenerate.
364 * ip2k-asm.c: Regenerate.
365 * iq2000-asm.c: Regenerate.
366 * lm32-asm.c: Regenerate.
367 * m32c-asm.c: Regenerate.
368 * m32r-asm.c: Regenerate.
369 * mep-asm.c: Regenerate.
370 * mt-asm.c: Regenerate.
371 * openrisc-asm.c: Regenerate.
372 * xc16x-asm.c: Regenerate.
373 * xstormy16-asm.c: Regenerate.
374
6ffe3d99
NC		 3752010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
376
377 PR gas/11673
378 * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
379
09ec0d17
NC		 3802010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
381
382 PR binutils/11676
383 * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
384
e01d869a
AM		 3852010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
386
387 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
388 e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
389 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
390 touch floating point regs and are enabled by COM, PPC or PPCCOM.
391 Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
392 Treat lwsync as msync on e500.
393
1f4e4950
MGD		 3942010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
395
396 * arm-dis.c (thumb-opcodes): Add disassembly for movs.
397
9d82ec38
MGD		 3982010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
399
e01d869a 400 * arm-dis.c (print_insn_neon): Ensure disassembly of Neon
9d82ec38
MGD		 401 constants is the same on 32-bit and 64-bit hosts.
402
c3a6ea62 4032010-05-27 Jason Duerstock <jason.duerstock+binutils@gmail.com>
d8b24b95
NC		 404
405 * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
406 .short directives so that they can be reassembled.
407
9db8dccb
CM		 4082010-05-26 Catherine Moore <clm@codesourcery.com>
409 David Ung <davidu@mips.com>
410
411 * mips-opc.c: Change membership to I1 for instructions ssnop and
412 ehb.
413
dfc8cf43
L		 4142010-05-26 H.J. Lu <hongjiu.lu@intel.com>
415
416 * i386-dis.c (sib): New.
417 (get_sib): Likewise.
418 (print_insn): Call get_sib.
419 OP_E_memory): Use sib.
420
f79e2745
CM		 4212010-05-26 Catherine Moore <clm@codesoourcery.com>
422
423 * mips-dis.c (mips_arch): Remove INSN_MIPS16.
424 * mips-opc.c (I16): Remove.
425 (mips_builtin_op): Reclassify jalx.
426
51b5d4a8
AM		 4272010-05-19 Alan Modra <amodra@gmail.com>
428
429 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
430 divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
431
85d4ac0b
AM		 4322010-05-13 Alan Modra <amodra@gmail.com>
433
434 * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
435
4547cb56
NC		 4362010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
437
438 * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
439 format.
440 (print_insn_thumb16): Add support for new %W format.
441
6540b386
TG		 4422010-05-07 Tristan Gingold <gingold@adacore.com>
443
444 * Makefile.in: Regenerate with automake 1.11.1.
445 * aclocal.m4: Ditto.
446
3e01a7fd
NC		 4472010-05-05 Nick Clifton <nickc@redhat.com>
448
449 * po/es.po: Updated Spanish translation.
450
9c9c98a5
NC		 4512010-04-22 Nick Clifton <nickc@redhat.com>
452
453 * po/opcodes.pot: Updated by the Translation project.
454 * po/vi.po: Updated Vietnamese translation.
455
f07af43e
L		 4562010-04-16 H.J. Lu <hongjiu.lu@intel.com>
457
458 * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
459 bits in opcode.
460
3d540e93
NC		 4612010-04-09 Nick Clifton <nickc@redhat.com>
462
463 * i386-dis.c (print_insn): Remove unused variable op.
464 (OP_sI): Remove unused variable mask.
465
397841b5
AM		 4662010-04-07 Alan Modra <amodra@gmail.com>
467
468 * configure: Regenerate.
469
cee62821
PB		 4702010-04-06 Peter Bergner <bergner@vnet.ibm.com>
471
472 * ppc-opc.c (RBOPT): New define.
473 ("dccci"): Enable for PPCA2. Make operands optional.
474 ("iccci"): Likewise. Do not deprecate for PPC476.
475
accf4463
NC		 4762010-04-02 Masaki Muranaka <monaka@monami-software.com>
477
478 * cr16-opc.c (cr16_instruction): Fix typo in comment.
479
40b36596
JM		 4802010-03-25 Joseph Myers <joseph@codesourcery.com>
481
482 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
483 * Makefile.in: Regenerate.
484 * configure.in (bfd_tic6x_arch): New.
485 * configure: Regenerate.
486 * disassemble.c (ARCH_tic6x): Define if ARCH_all.
487 (disassembler): Handle TI C6X.
488 * tic6x-dis.c: New.
489
1985c81c
MF		 4902010-03-24 Mike Frysinger <vapier@gentoo.org>
491
492 * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
493
f66187fd
JM		 4942010-03-23 Joseph Myers <joseph@codesourcery.com>
495
496 * dis-buf.c (buffer_read_memory): Give error for reading just
497 before the start of memory.
498
ce7d077e
SP		 4992010-03-22 Sebastian Pop <sebastian.pop@amd.com>
500 Quentin Neill <quentin.neill@amd.com>
501
502 * i386-dis.c (OP_LWP_I): Removed.
503 (reg_table): Do not use OP_LWP_I, use Iq.
504 (OP_LWPCB_E): Remove use of names16.
505 (OP_LWP_E): Same.
506 * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
507 should not set the Vex.length bit.
508 * i386-tbl.h: Regenerated.
509
63d0fa4e
AM		 5102010-02-25 Edmar Wienskoski <edmar@freescale.com>
511
512 * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
513
c060226a
NC		 5142010-02-24 Nick Clifton <nickc@redhat.com>
515
516 PR binutils/6773
517 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
518 <prefix>asx. Replace <prefix>subaddx with <prefix>sax.
519 (thumb32_opcodes): Likewise.
520
ab7875de
NC		 5212010-02-15 Nick Clifton <nickc@redhat.com>
522
523 * po/vi.po: Updated Vietnamese translation.
524
fee1d3e8
DE		 5252010-02-12 Doug Evans <dje@sebabeach.org>
526
527 * lm32-opinst.c: Regenerate.
528
37ec9240
DE		 5292010-02-11 Doug Evans <dje@sebabeach.org>
530
9468ae89
DE		 531 * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
532 (print_address): Delete CGEN_PRINT_ADDRESS.
533 * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
534 * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
535 * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
536 * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
537
37ec9240
DE		 538 * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
539 * frv-desc.c, * frv-desc.h, * frv-opc.c,
540 * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
541 * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
542 * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
543 * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
544 * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
545 * mep-desc.c, * mep-desc.h, * mep-opc.c,
546 * mt-desc.c, * mt-desc.h, * mt-opc.c,
547 * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
548 * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
549 * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
550
c75ef631
L		 5512010-02-11 H.J. Lu <hongjiu.lu@intel.com>
552
553 * i386-dis.c: Update copyright.
554 * i386-gen.c: Likewise.
555 * i386-opc.h: Likewise.
556 * i386-opc.tbl: Likewise.
557
a683cc34
SP		 5582010-02-10 Quentin Neill <quentin.neill@amd.com>
559 Sebastian Pop <sebastian.pop@amd.com>
560
561 * i386-dis.c (OP_EX_VexImmW): Reintroduced
562 function to handle 5th imm8 operand.
563 (PREFIX_VEX_3A48): Added.
564 (PREFIX_VEX_3A49): Added.
565 (VEX_W_3A48_P_2): Added.
566 (VEX_W_3A49_P_2): Added.
567 (prefix table): Added entries for PREFIX_VEX_3A48
568 and PREFIX_VEX_3A49.
569 (vex table): Added entries for VEX_W_3A48_P_2 and
570 and VEX_W_3A49_P_2.
571 * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
572 for Vec_Imm4 operands.
573 * i386-opc.h (enum): Added Vec_Imm4.
574 (i386_operand_type): Added vec_imm4.
575 * i386-opc.tbl: Add entries for vpermilp[ds].
576 * i386-init.h: Regenerated.
577 * i386-tbl.h: Regenerated.
578
cdc51b07
RS		 5792010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
580
581 * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
582 and "pwr7". Move "a2" into alphabetical order.
583
ce3d2015
AM		 5842010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
585
586 * ppc-dis.c (ppc_opts): Add titan entry.
587 * ppc-opc.c (TITAN, MULHW): Define.
588 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
589
68339fdf
SP		 5902010-02-03 Quentin Neill <quentin.neill@amd.com>
591
592 * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
593 to CPU_BDVER1_FLAGS
594 * i386-init.h: Regenerated.
595
f3d55a94
AG		 5962010-02-03 Anthony Green <green@moxielogic.com>
597
598 * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
599 0x0f, and make 0x00 an illegal instruction.
600
b0e28b39
DJ		 6012010-01-29 Daniel Jacobowitz <dan@codesourcery.com>
602
603 * opcodes/arm-dis.c (struct arm_private_data): New.
604 (print_insn_coprocessor, print_insn_arm): Update to use struct
605 arm_private_data.
606 (is_mapping_symbol, get_map_sym_type): New functions.
607 (get_sym_code_type): Check the symbol's section. Do not check
608 mapping symbols.
609 (print_insn): Default to disassembling ARM mode code. Check
610 for mapping symbols separately from other symbols. Use
611 struct arm_private_data.
612
1c480963
L		 6132010-01-28 H.J. Lu <hongjiu.lu@intel.com>
614
615 * i386-dis.c (EXVexWdqScalar): New.
616 (vex_scalar_w_dq_mode): Likewise.
617 (prefix_table): Update entries for PREFIX_VEX_3899,
618 PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
619 PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
620 PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
621 PREFIX_VEX_38BD and PREFIX_VEX_38BF.
622 (intel_operand_size): Handle vex_scalar_w_dq_mode.
623 (OP_EX): Likewise.
624
539f890d
L		 6252010-01-27 H.J. Lu <hongjiu.lu@intel.com>
626
627 * i386-dis.c (XMScalar): New.
628 (EXdScalar): Likewise.
629 (EXqScalar): Likewise.
630 (EXqScalarS): Likewise.
631 (VexScalar): Likewise.
632 (EXdVexScalarS): Likewise.
633 (EXqVexScalarS): Likewise.
634 (XMVexScalar): Likewise.
635 (scalar_mode): Likewise.
636 (d_scalar_mode): Likewise.
637 (d_scalar_swap_mode): Likewise.
638 (q_scalar_mode): Likewise.
639 (q_scalar_swap_mode): Likewise.
640 (vex_scalar_mode): Likewise.
641 (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
642 VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
643 VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
644 VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
645 VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
646 VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
647 VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
648 VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
649 VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
650 VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
651 (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
652 VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
653 VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
654 VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
655 VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
656 VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
657 VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
658 VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
659 VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
660 (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
661 q_scalar_mode, q_scalar_swap_mode.
662 (OP_XMM): Handle scalar_mode.
663 (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
664 and q_scalar_swap_mode.
665 (OP_VEX): Handle vex_scalar_mode.
666
208b4d78
L		 6672010-01-24 H.J. Lu <hongjiu.lu@intel.com>
668
669 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
670
448b213a
L		 6712010-01-24 H.J. Lu <hongjiu.lu@intel.com>
672
673 * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
674
47cf8fa0
L		 6752010-01-24 H.J. Lu <hongjiu.lu@intel.com>
676
677 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
678
592d1631
L		 6792010-01-24 H.J. Lu <hongjiu.lu@intel.com>
680
681 * i386-dis.c (Bad_Opcode): New.
682 (bad_opcode): Likewise.
683 (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
684 (dis386_twobyte): Likewise.
685 (reg_table): Likewise.
686 (prefix_table): Likewise.
687 (x86_64_table): Likewise.
688 (vex_len_table): Likewise.
689 (vex_w_table): Likewise.
690 (mod_table): Likewise.
691 (rm_table): Likewise.
692 (float_reg): Likewise.
693 (reg_table): Remove trailing "(bad)" entries.
694 (prefix_table): Likewise.
695 (x86_64_table): Likewise.
696 (vex_len_table): Likewise.
697 (vex_w_table): Likewise.
698 (mod_table): Likewise.
699 (rm_table): Likewise.
700 (get_valid_dis386): Handle bytemode 0.
701
712366da
L		 7022010-01-23 H.J. Lu <hongjiu.lu@intel.com>
703
704 * i386-opc.h (VEXScalar): New.
705
706 * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
707 instructions.
708 * i386-tbl.h: Regenerated.
709
706e8205 7102010-01-21 H.J. Lu <hongjiu.lu@intel.com>
73bb6729
L		 711
712 * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
713
714 * i386-opc.tbl: Add xsave64 and xrstor64.
715 * i386-tbl.h: Regenerated.
716
99ea83aa
NC		 7172010-01-20 Nick Clifton <nickc@redhat.com>
718
719 PR 11170
720 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
721 based post-indexed addressing.
722
a6461c02
SP		 7232010-01-15 Sebastian Pop <sebastian.pop@amd.com>
724
725 * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
726 * i386-tbl.h: Regenerated.
727
a2a7d12c
L		 7282010-01-14 H.J. Lu <hongjiu.lu@intel.com>
729
730 * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
731 comments.
732
b9733481
L		 7332010-01-14 H.J. Lu <hongjiu.lu@intel.com>
734
735 * i386-dis.c (names_mm): New.
736 (intel_names_mm): Likewise.
737 (att_names_mm): Likewise.
738 (names_xmm): Likewise.
739 (intel_names_xmm): Likewise.
740 (att_names_xmm): Likewise.
741 (names_ymm): Likewise.
742 (intel_names_ymm): Likewise.
743 (att_names_ymm): Likewise.
744 (print_insn): Set names_mm, names_xmm and names_ymm.
745 (OP_MMX): Use names_mm, names_xmm and names_ymm.
746 (OP_XMM): Likewise.
747 (OP_EM): Likewise.
748 (OP_EMC): Likewise.
749 (OP_MXC): Likewise.
750 (OP_EX): Likewise.
751 (XMM_Fixup): Likewise.
752 (OP_VEX): Likewise.
753 (OP_EX_VexReg): Likewise.
754 (OP_Vex_2src): Likewise.
755 (OP_Vex_2src_1): Likewise.
756 (OP_Vex_2src_2): Likewise.
757 (OP_REG_VexI4): Likewise.
758
5e6718e4
L		 7592010-01-13 H.J. Lu <hongjiu.lu@intel.com>
760
761 * i386-dis.c (print_insn): Update comments.
762
d869730d
L		 7632010-01-12 H.J. Lu <hongjiu.lu@intel.com>
764
765 * i386-dis.c (rex_original): Removed.
766 (ckprefix): Remove rex_original.
767 (print_insn): Update comments.
768
3725885a
RW		 7692010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
770
771 * Makefile.in: Regenerate.
772 * configure: Regenerate.
773
b7cd1872
DE		 7742010-01-07 Doug Evans <dje@sebabeach.org>
775
776 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
777 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
778 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
779 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
780 * xstormy16-ibld.c: Regenerate.
781
69dd9865
SP		 7822010-01-06 Quentin Neill <quentin.neill@amd.com>
783
784 * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
785 * i386-init.h: Regenerated.
786
e3e535bc
NC		 7872010-01-06 Daniel Gutson <dgutson@codesourcery.com>
788
789 * arm-dis.c (print_insn): Fixed search for next symbol and data
790 dumping condition, and the initial mapping symbol state.
791
fe8afbc4
DE		 7922010-01-05 Doug Evans <dje@sebabeach.org>
793
794 * cgen-ibld.in: #include "cgen/basic-modes.h".
795 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
796 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
797 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
798 * xstormy16-ibld.c: Regenerate.
799
2edcd244
NC		 8002010-01-04 Nick Clifton <nickc@redhat.com>
801
802 PR 11123
803 * arm-dis.c (print_insn_coprocessor): Initialise value.
804
0dc93057
AM		 8052010-01-04 Edmar Wienskoski <edmar@freescale.com>
806
807 * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
808
05994f45
DE		 8092010-01-02 Doug Evans <dje@sebabeach.org>
810
811 * cgen-asm.in: Update copyright year.
812 * cgen-dis.in: Update copyright year.
813 * cgen-ibld.in: Update copyright year.
814 * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
815 * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
816 * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
817 * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
818 * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
819 * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
820 * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
821 * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
822 * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
823 * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
824 * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
825 * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
826 * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
827 * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
828 * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
829 * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
830 * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
831 * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
832 * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
833 * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
834 * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
2426c15f 835
43ecc30f 836For older changes see ChangeLog-2009
252b5132
RH		 837\f
838Local Variables:
2f6d2f85
NC		 839mode: change-log
840left-margin: 8
841fill-column: 74
252b5132
RH		 842version-control: never
843End:
GDB Binutils - Deliverables
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