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[AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
ea2deeec
MW		 12015-12-10 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
4 with aarch64_sys_ins_reg_has_xt.
5 (aarch64_ext_sysins_op): Likewise.
6 * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
7 (F_HASXT): New.
8 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
9 (aarch64_sys_regs_dc): Likewise.
10 (aarch64_sys_regs_at): Likewise.
11 (aarch64_sys_regs_tlbi): Likewise.
12 (aarch64_sys_ins_reg_has_xt): New.
13
6479e48e
MW		 142015-12-10 Matthew Wahab <matthew.wahab@arm.com>
15
16 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
17 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
18 (aarch64_pstatefields): Add "uao".
19 (aarch64_pstatefield_supported_p): Add checks for "uao".
20
47f81142
MW		 212015-12-10 Matthew Wahab <matthew.wahab@arm.com>
22
23 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
24 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
25 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
26 (aarch64_sys_reg_supported_p): Add architecture feature tests for
27 new registers.
28
c8a6db6f
MW		 292015-12-10 Matthew Wahab <matthew.wahab@arm.com>
30
31 * aarch64-asm-2.c: Regenerate.
32 * aarch64-dis-2.c: Regenerate.
33 * aarch64-tbl.h (aarch64_feature_ras): New.
34 (RAS): New.
35 (aarch64_opcode_table): Add "esb".
36
8eab4136
L		 372015-12-09 H.J. Lu <hongjiu.lu@intel.com>
38
39 * i386-dis.c (MOD_0F01_REG_5): New.
40 (RM_0F01_REG_5): Likewise.
41 (reg_table): Use MOD_0F01_REG_5.
42 (mod_table): Add MOD_0F01_REG_5.
43 (rm_table): Add RM_0F01_REG_5.
44 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
45 (cpu_flags): Add CpuOSPKE.
46 * i386-opc.h (CpuOSPKE): New.
47 (i386_cpu_flags): Add cpuospke.
48 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
49 * i386-init.h: Regenerated.
50 * i386-tbl.h: Likewise.
51
1eac08cc
DD		 522015-12-07 DJ Delorie <dj@redhat.com>
53
54 * rl78-decode.opc: Enable MULU for all ISAs.
55 * rl78-decode.c: Regenerate.
56
dd2887fc
AM		 572015-12-07 Alan Modra <amodra@gmail.com>
58
59 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
60 major opcode/xop.
61
24b368f8
CZ		 622015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
63
64 * arc-dis.c (special_flag_p): Match full mnemonic.
65 * arc-opc.c (print_insn_arc): Check section size to read
66 appropriate number of bytes. Fix printing.
67 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
68 arguments.
69
3395762e
AV		 702015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
71
72 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
73 <ldah>: ... to this.
74
622b9eb1
MW		 752015-11-27 Matthew Wahab <matthew.wahab@arm.com>
76
77 * aarch64-asm-2.c: Regenerate.
78 * aarch64-dis-2.c: Regenerate.
79 * aarch64-opc-2.c: Regenerate.
80 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
81 (QL_INT2FP_H, QL_FP2INT_H): New.
82 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
83 (QL_DST_H): New.
84 (QL_FCCMP_H): New.
85 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
86 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
87 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
88 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
89 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
90 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
91 fcsel.
92
cf86120b
MW		 932015-11-27 Matthew Wahab <matthew.wahab@arm.com>
94
95 * aarch64-opc.c (half_conv_t): New.
96 (expand_fp_imm): Replace is_dp flag with the parameter size to
97 specify the number of bytes for the required expansion. Treat
98 a 16-bit expansion like a 32-bit expansion. Add check for an
99 unsupported size request. Update comment.
100 (aarch64_print_operand): Update to support 16-bit floating point
101 values. Update for changes to expand_fp_imm.
102
3bd894a7
MW		 1032015-11-27 Matthew Wahab <matthew.wahab@arm.com>
104
105 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
106 (FP_F16): New.
107
64357d2e
MW		 1082015-11-27 Matthew Wahab <matthew.wahab@arm.com>
109
110 * aarch64-asm-2.c: Regenerate.
111 * aarch64-dis-2.c: Regenerate.
112 * aarch64-opc-2.c: Regenerate.
113 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
114 "rev64".
115
d685192a
MW		 1162015-11-27 Matthew Wahab <matthew.wahab@arm.com>
117
118 * aarch64-asm-2.c: Regenerate.
119 * aarch64-asm.c (convert_bfc_to_bfm): New.
120 (convert_to_real): Add case for OP_BFC.
121 * aarch64-dis-2.c: Regenerate.
122 * aarch64-dis.c: (convert_bfm_to_bfc): New.
123 (convert_to_alias): Add case for OP_BFC.
124 * aarch64-opc-2.c: Regenerate.
125 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
126 to allow width operand in three-operand instructions.
127 * aarch64-tbl.h (QL_BF1): New.
128 (aarch64_feature_v8_2): New.
129 (ARMV8_2): New.
130 (aarch64_opcode_table): Add "bfc".
131
35822b38
MW		 1322015-11-27 Matthew Wahab <matthew.wahab@arm.com>
133
134 * aarch64-asm-2.c: Regenerate.
135 * aarch64-dis-2.c: Regenerate.
136 * aarch64-dis.c: Weaken assert.
137 * aarch64-gen.c: Include the instruction in the list of its
138 possible aliases.
139
1a04d1a7
MW		 1402015-11-27 Matthew Wahab <matthew.wahab@arm.com>
141
142 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
143 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
144 feature test.
145
e49d43ff
TG		 1462015-11-23 Tristan Gingold <gingold@adacore.com>
147
148 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
149
250aafa4
MW		 1502015-11-20 Matthew Wahab <matthew.wahab@arm.com>
151
152 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
153 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
154 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
155 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
156 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
157 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
158 cnthv_ctl_el2, cnthv_cval_el2.
159 (aarch64_sys_reg_supported_p): Update for the new system
160 registers.
161
a915c10f
NC		 1622015-11-20 Nick Clifton <nickc@redhat.com>
163
164 PR binutils/19224
165 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
166
f8c2a965
NC		 1672015-11-20 Nick Clifton <nickc@redhat.com>
168
169 * po/zh_CN.po: Updated simplified Chinese translation.
170
c2825638
MW		 1712015-11-19 Matthew Wahab <matthew.wahab@arm.com>
172
173 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
174 of MSR PAN immediate operand.
175
e7286c56
NC		 1762015-11-16 Nick Clifton <nickc@redhat.com>
177
178 * rx-dis.c (condition_names): Replace always and never with
179 invalid, since the always/never conditions can never be legal.
180
d8bd95ef
TG		 1812015-11-13 Tristan Gingold <gingold@adacore.com>
182
183 * configure: Regenerate.
184
a680de9a
PB		 1852015-11-11 Alan Modra <amodra@gmail.com>
186 Peter Bergner <bergner@vnet.ibm.com>
187
188 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
189 Add PPC_OPCODE_VSX3 to the vsx entry.
190 (powerpc_init_dialect): Set default dialect to power9.
191 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
192 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
193 extract_l1 insert_xtq6, extract_xtq6): New static functions.
194 (insert_esync): Test for illegal L operand value.
195 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
196 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
197 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
198 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
199 PPCVSX3): New defines.
200 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
201 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
202 <mcrxr>: Use XBFRARB_MASK.
203 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
204 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
205 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
206 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
207 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
208 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
209 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
210 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
211 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
212 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
213 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
214 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
215 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
216 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
217 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
218 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
219 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
220 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
221 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
222 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
223 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
224 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
225 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
226 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
227 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
228 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
229 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
230 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
231 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
232 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
233 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
234 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
235
854eb72b
NC		 2362015-11-02 Nick Clifton <nickc@redhat.com>
237
238 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
239 instructions.
240 * rx-decode.c: Regenerate.
241
e292aa7a
NC		 2422015-11-02 Nick Clifton <nickc@redhat.com>
243
244 * rx-decode.opc (rx_disp): If the displacement is zero, set the
245 type to RX_Operand_Zero_Indirect.
246 * rx-decode.c: Regenerate.
247 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
248
43cdf5ae
YQ		 2492015-10-28 Yao Qi <yao.qi@linaro.org>
250
251 * aarch64-dis.c (aarch64_decode_insn): Add one argument
252 noaliases_p. Update comments. Pass noaliases_p rather than
253 no_aliases to aarch64_opcode_decode.
254 (print_insn_aarch64_word): Pass no_aliases to
255 aarch64_decode_insn.
256
c2f28758
VK		 2572015-10-27 Vinay <Vinay.G@kpit.com>
258
259 PR binutils/19159
260 * rl78-decode.opc (MOV): Added offset to DE register in index
261 addressing mode.
262 * rl78-decode.c: Regenerate.
263
46662804
VK		 2642015-10-27 Vinay Kumar <vinay.g@kpit.com>
265
266 PR binutils/19158
267 * rl78-decode.opc: Add 's' print operator to instructions that
268 access system registers.
269 * rl78-decode.c: Regenerate.
270 * rl78-dis.c (print_insn_rl78_common): Decode all system
271 registers.
272
02f12cd4
VK		 2732015-10-27 Vinay Kumar <vinay.g@kpit.com>
274
275 PR binutils/19157
276 * rl78-decode.opc: Add 'a' print operator to mov instructions
277 using stack pointer plus index addressing.
278 * rl78-decode.c: Regenerate.
279
485f23cf
AK		 2802015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
281
282 * s390-opc.c: Fix comment.
283 * s390-opc.txt: Change instruction type for troo, trot, trto, and
284 trtt to RRF_U0RER since the second parameter does not need to be a
285 register pair.
286
3f94e60d
NC		 2872015-10-08 Nick Clifton <nickc@redhat.com>
288
289 * arc-dis.c (print_insn_arc): Initiallise insn array.
290
875880c6
YQ		 2912015-10-07 Yao Qi <yao.qi@linaro.org>
292
293 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
294 'name' rather than 'template'.
295 * aarch64-opc.c (aarch64_print_operand): Likewise.
296
886a2506
NC		 2972015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
298
299 * arc-dis.c: Revamped file for ARC support
300 * arc-dis.h: Likewise.
301 * arc-ext.c: Likewise.
302 * arc-ext.h: Likewise.
303 * arc-opc.c: Likewise.
304 * arc-fxi.h: New file.
305 * arc-regs.h: Likewise.
306 * arc-tbl.h: Likewise.
307
36f4aab1
YQ		 3082015-10-02 Yao Qi <yao.qi@linaro.org>
309
310 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
311 argument insn type to aarch64_insn. Rename to ...
312 (aarch64_decode_insn): ... it.
313 (print_insn_aarch64_word): Caller updated.
314
7232d389
YQ		 3152015-10-02 Yao Qi <yao.qi@linaro.org>
316
317 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
318 (print_insn_aarch64_word): Caller updated.
319
7ecc513a
DV		 3202015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
321
322 * s390-mkopc.c (main): Parse htm and vx flag.
323 * s390-opc.txt: Mark instructions from the hardware transactional
324 memory and vector facilities with the "htm"/"vx" flag.
325
b08b78e7
NC		 3262015-09-28 Nick Clifton <nickc@redhat.com>
327
328 * po/de.po: Updated German translation.
329
36f7a941
TR		 3302015-09-28 Tom Rix <tom@bumblecow.com>
331
332 * ppc-opc.c (PPC500): Mark some opcodes as invalid
333
b6518b38
NC		 3342015-09-23 Nick Clifton <nickc@redhat.com>
335
336 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
337 function.
338 * tic30-dis.c (print_branch): Likewise.
339 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
340 value before left shifting.
341 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
342 * hppa-dis.c (print_insn_hppa): Likewise.
343 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
344 array.
345 * msp430-dis.c (msp430_singleoperand): Likewise.
346 (msp430_doubleoperand): Likewise.
347 (print_insn_msp430): Likewise.
348 * nds32-asm.c (parse_operand): Likewise.
349 * sh-opc.h (MASK): Likewise.
350 * v850-dis.c (get_operand_value): Likewise.
351
f04265ec
NC		 3522015-09-22 Nick Clifton <nickc@redhat.com>
353
354 * rx-decode.opc (bwl): Use RX_Bad_Size.
355 (sbwl): Likewise.
356 (ubwl): Likewise. Rename to ubw.
357 (uBWL): Rename to uBW.
358 Replace all references to uBWL with uBW.
359 * rx-decode.c: Regenerate.
360 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
361 (opsize_names): Likewise.
362 (print_insn_rx): Detect and report RX_Bad_Size.
363
6dca4fd1
AB		 3642015-09-22 Anton Blanchard <anton@samba.org>
365
366 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
367
38074311
JM		 3682015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
369
370 * sparc-dis.c (print_insn_sparc): Handle the privileged register
371 %pmcdper.
372
5f40e14d
JS		 3732015-08-24 Jan Stancek <jstancek@redhat.com>
374
375 * i386-dis.c (print_insn): Fix decoding of three byte operands.
376
ab4e4ed5
AF		 3772015-08-21 Alexander Fomin <alexander.fomin@intel.com>
378
379 PR binutils/18257
380 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
381 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
382 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
383 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
384 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
385 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
386 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
387 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
388 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
389 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
390 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
391 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
392 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
393 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
394 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
395 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
396 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
397 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
398 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
399 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
400 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
401 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
402 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
403 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
404 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
405 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
406 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
407 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
408 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
409 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
410 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
411 (vex_w_table): Replace terminals with MOD_TABLE entries for
412 most of mask instructions.
413
919b75f7
AM		 4142015-08-17 Alan Modra <amodra@gmail.com>
415
416 * cgen.sh: Trim trailing space from cgen output.
417 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
418 (print_dis_table): Likewise.
419 * opc2c.c (dump_lines): Likewise.
420 (orig_filename): Warning fix.
421 * ia64-asmtab.c: Regenerate.
422
4ab90a7a
AV		 4232015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
424
425 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
426 and higher with ARM instruction set will now mark the 26-bit
427 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
428 (arm_opcodes): Fix for unpredictable nop being recognized as a
429 teq.
430
40fc1451
SD		 4312015-08-12 Simon Dardis <simon.dardis@imgtec.com>
432
433 * micromips-opc.c (micromips_opcodes): Re-order table so that move
434 based on 'or' is first.
435 * mips-opc.c (mips_builtin_opcodes): Ditto.
436
922c5db5
NC		 4372015-08-11 Nick Clifton <nickc@redhat.com>
438
439 PR 18800
440 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
441 instruction.
442
75fb7498
RS		 4432015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
444
445 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
446
36aed29d
AP		 4472015-08-07 Amit Pawar <Amit.Pawar@amd.com>
448
449 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
450 * i386-init.h: Regenerated.
451
a8484f96
L		 4522015-07-30 H.J. Lu <hongjiu.lu@intel.com>
453
454 PR binutils/13571
455 * i386-dis.c (MOD_0FC3): New.
456 (PREFIX_0FC3): Renamed to ...
457 (PREFIX_MOD_0_0FC3): This.
458 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
459 (prefix_table): Replace Ma with Ev on movntiS.
460 (mod_table): Add MOD_0FC3.
461
37a42ee9
L		 4622015-07-27 H.J. Lu <hongjiu.lu@intel.com>
463
464 * configure: Regenerated.
465
070fe95d
AM		 4662015-07-23 Alan Modra <amodra@gmail.com>
467
468 PR 18708
469 * i386-dis.c (get64): Avoid signed integer overflow.
470
20c2a615
L		 4712015-07-22 Alexander Fomin <alexander.fomin@intel.com>
472
473 PR binutils/18631
474 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
475 "EXEvexHalfBcstXmmq" for the second operand.
476 (EVEX_W_0F79_P_2): Likewise.
477 (EVEX_W_0F7A_P_2): Likewise.
478 (EVEX_W_0F7B_P_2): Likewise.
479
6f1c2142
AM		 4802015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
481
482 * arm-dis.c (print_insn_coprocessor): Added support for quarter
483 float bitfield format.
484 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
485 quarter float bitfield format.
486
8a643cc3
L		 4872015-07-14 H.J. Lu <hongjiu.lu@intel.com>
488
489 * configure: Regenerated.
490
ef5a96d5
AM		 4912015-07-03 Alan Modra <amodra@gmail.com>
492
493 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
494 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
495 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
496
c8c8175b
SL		 4972015-07-01 Sandra Loosemore <sandra@codesourcery.com>
498 Cesar Philippidis <cesar@codesourcery.com>
499
500 * nios2-dis.c (nios2_extract_opcode): New.
501 (nios2_disassembler_state): New.
502 (nios2_find_opcode_hash): Use mach parameter to select correct
503 disassembler state.
504 (nios2_print_insn_arg): Extend to support new R2 argument letters
505 and formats.
506 (print_insn_nios2): Check for 16-bit instruction at end of memory.
507 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
508 (NIOS2_NUM_OPCODES): Rename to...
509 (NIOS2_NUM_R1_OPCODES): This.
510 (nios2_r2_opcodes): New.
511 (NIOS2_NUM_R2_OPCODES): New.
512 (nios2_num_r2_opcodes): New.
513 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
514 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
515 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
516 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
517 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
518
9916071f
AP		 5192015-06-30 Amit Pawar <Amit.Pawar@amd.com>
520
521 * i386-dis.c (OP_Mwaitx): New.
522 (rm_table): Add monitorx/mwaitx.
523 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
524 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
525 (operand_type_init): Add CpuMWAITX.
526 * i386-opc.h (CpuMWAITX): New.
527 (i386_cpu_flags): Add cpumwaitx.
528 * i386-opc.tbl: Add monitorx and mwaitx.
529 * i386-init.h: Regenerated.
530 * i386-tbl.h: Likewise.
531
7b934113
PB		 5322015-06-22 Peter Bergner <bergner@vnet.ibm.com>
533
534 * ppc-opc.c (insert_ls): Test for invalid LS operands.
535 (insert_esync): New function.
536 (LS, WC): Use insert_ls.
537 (ESYNC): Use insert_esync.
538
bdc4de1b
NC		 5392015-06-22 Nick Clifton <nickc@redhat.com>
540
541 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
542 requested region lies beyond it.
543 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
544 looking for 32-bit insns.
545 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
546 data.
547 * sh-dis.c (print_insn_sh): Likewise.
548 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
549 blocks of instructions.
550 * vax-dis.c (print_insn_vax): Check that the requested address
551 does not clash with the stop_vma.
552
11a0cf2e
PB		 5532015-06-19 Peter Bergner <bergner@vnet.ibm.com>
554
070fe95d 555 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 556 * ppc-opc.c (FXM4): Add non-zero optional value.
557 (TBR): Likewise.
558 (SXL): Likewise.
559 (insert_fxm): Handle new default operand value.
560 (extract_fxm): Likewise.
561 (insert_tbr): Likewise.
562 (extract_tbr): Likewise.
563
bdfa8b95
MW		 5642015-06-16 Matthew Wahab <matthew.wahab@arm.com>
565
566 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
567
24b4cf66
SN		 5682015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
569
570 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
571
99a2c561
PB		 5722015-06-12 Peter Bergner <bergner@vnet.ibm.com>
573
574 * ppc-opc.c: Add comment accidentally removed by old commit.
575 (MTMSRD_L): Delete.
576
40f77f82
AM		 5772015-06-04 Peter Bergner <bergner@vnet.ibm.com>
578
579 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
580
13be46a2
NC		 5812015-06-04 Nick Clifton <nickc@redhat.com>
582
583 PR 18474
584 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
585
ddfded2f
MW		 5862015-06-02 Matthew Wahab <matthew.wahab@arm.com>
587
588 * arm-dis.c (arm_opcodes): Add "setpan".
589 (thumb_opcodes): Add "setpan".
590
1af1dd51
MW		 5912015-06-02 Matthew Wahab <matthew.wahab@arm.com>
592
593 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
594 macros.
595
9e1f0fa7
MW		 5962015-06-02 Matthew Wahab <matthew.wahab@arm.com>
597
598 * aarch64-tbl.h (aarch64_feature_rdma): New.
599 (RDMA): New.
600 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
601 * aarch64-asm-2.c: Regenerate.
602 * aarch64-dis-2.c: Regenerate.
603 * aarch64-opc-2.c: Regenerate.
604
290806fd
MW		 6052015-06-02 Matthew Wahab <matthew.wahab@arm.com>
606
607 * aarch64-tbl.h (aarch64_feature_lor): New.
608 (LOR): New.
609 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
610 "stllrb", "stllrh".
611 * aarch64-asm-2.c: Regenerate.
612 * aarch64-dis-2.c: Regenerate.
613 * aarch64-opc-2.c: Regenerate.
614
f21cce2c
MW		 6152015-06-01 Matthew Wahab <matthew.wahab@arm.com>
616
617 * aarch64-opc.c (F_ARCHEXT): New.
618 (aarch64_sys_regs): Add "pan".
619 (aarch64_sys_reg_supported_p): New.
620 (aarch64_pstatefields): Add "pan".
621 (aarch64_pstatefield_supported_p): New.
622
d194d186
JB		 6232015-06-01 Jan Beulich <jbeulich@suse.com>
624
625 * i386-tbl.h: Regenerate.
626
3a8547d2
JB		 6272015-06-01 Jan Beulich <jbeulich@suse.com>
628
629 * i386-dis.c (print_insn): Swap rounding mode specifier and
630 general purpose register in Intel mode.
631
015c54d5
JB		 6322015-06-01 Jan Beulich <jbeulich@suse.com>
633
634 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
635 * i386-tbl.h: Regenerate.
636
071f0063
L		 6372015-05-18 H.J. Lu <hongjiu.lu@intel.com>
638
639 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
640 * i386-init.h: Regenerated.
641
5db04b09
L		 6422015-05-15 H.J. Lu <hongjiu.lu@intel.com>
643
644 PR binutis/18386
645 * i386-dis.c: Add comments for '@'.
646 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
647 (enum x86_64_isa): New.
648 (isa64): Likewise.
649 (print_i386_disassembler_options): Add amd64 and intel64.
650 (print_insn): Handle amd64 and intel64.
651 (putop): Handle '@'.
652 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
653 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
654 * i386-opc.h (AMD64): New.
655 (CpuIntel64): Likewise.
656 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
657 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
658 Mark direct call/jmp without Disp16|Disp32 as Intel64.
659 * i386-init.h: Regenerated.
660 * i386-tbl.h: Likewise.
661
4bc0608a
PB		 6622015-05-14 Peter Bergner <bergner@vnet.ibm.com>
663
664 * ppc-opc.c (IH) New define.
665 (powerpc_opcodes) <wait>: Do not enable for POWER7.
666 <tlbie>: Add RS operand for POWER7.
667 <slbia>: Add IH operand for POWER6.
668
70cead07
L		 6692015-05-11 H.J. Lu <hongjiu.lu@intel.com>
670
671 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
672 direct branch.
673 (jmp): Likewise.
674 * i386-tbl.h: Regenerated.
675
7b6d09fb
L		 6762015-05-11 H.J. Lu <hongjiu.lu@intel.com>
677
678 * configure.ac: Support bfd_iamcu_arch.
679 * disassemble.c (disassembler): Support bfd_iamcu_arch.
680 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
681 CPU_IAMCU_COMPAT_FLAGS.
682 (cpu_flags): Add CpuIAMCU.
683 * i386-opc.h (CpuIAMCU): New.
684 (i386_cpu_flags): Add cpuiamcu.
685 * configure: Regenerated.
686 * i386-init.h: Likewise.
687 * i386-tbl.h: Likewise.
688
31955f99
L		 6892015-05-08 H.J. Lu <hongjiu.lu@intel.com>
690
691 PR binutis/18386
692 * i386-dis.c (X86_64_E8): New.
693 (X86_64_E9): Likewise.
694 Update comments on 'T', 'U', 'V'. Add comments for '^'.
695 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
696 (x86_64_table): Add X86_64_E8 and X86_64_E9.
697 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
698 (putop): Handle '^'.
699 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
700 REX_W.
701
0952813b
DD		 7022015-04-30 DJ Delorie <dj@redhat.com>
703
704 * disassemble.c (disassembler): Choose suitable disassembler based
705 on E_ABI.
706 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
707 it to decode mul/div insns.
708 * rl78-decode.c: Regenerate.
709 * rl78-dis.c (print_insn_rl78): Rename to...
710 (print_insn_rl78_common): ...this, take ISA parameter.
711 (print_insn_rl78): New.
712 (print_insn_rl78_g10): New.
713 (print_insn_rl78_g13): New.
714 (print_insn_rl78_g14): New.
715 (rl78_get_disassembler): New.
716
f9d3ecaa
NC		 7172015-04-29 Nick Clifton <nickc@redhat.com>
718
719 * po/fr.po: Updated French translation.
720
4fff86c5
PB		 7212015-04-27 Peter Bergner <bergner@vnet.ibm.com>
722
723 * ppc-opc.c (DCBT_EO): New define.
724 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
725 <lharx>: Likewise.
726 <stbcx.>: Likewise.
727 <sthcx.>: Likewise.
728 <waitrsv>: Do not enable for POWER7 and later.
729 <waitimpl>: Likewise.
730 <dcbt>: Default to the two operand form of the instruction for all
731 "old" cpus. For "new" cpus, use the operand ordering that matches
732 whether the cpu is server or embedded.
733 <dcbtst>: Likewise.
734
3b78cfe1
AK		 7352015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
736
737 * s390-opc.c: New instruction type VV0UU2.
738 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
739 and WFC.
740
04d824a4
JB		 7412015-04-23 Jan Beulich <jbeulich@suse.com>
742
743 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
744 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
745 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
746 (vfpclasspd, vfpclassps): Add %XZ.
747
09708981
L		 7482015-04-15 H.J. Lu <hongjiu.lu@intel.com>
749
750 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
751 (PREFIX_UD_REPZ): Likewise.
752 (PREFIX_UD_REPNZ): Likewise.
753 (PREFIX_UD_DATA): Likewise.
754 (PREFIX_UD_ADDR): Likewise.
755 (PREFIX_UD_LOCK): Likewise.
756
3888916d
L		 7572015-04-15 H.J. Lu <hongjiu.lu@intel.com>
758
759 * i386-dis.c (prefix_requirement): Removed.
760 (print_insn): Don't set prefix_requirement. Check
761 dp->prefix_requirement instead of prefix_requirement.
762
f24bcbaa
L		 7632015-04-15 H.J. Lu <hongjiu.lu@intel.com>
764
765 PR binutils/17898
766 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
767 (PREFIX_MOD_0_0FC7_REG_6): This.
768 (PREFIX_MOD_3_0FC7_REG_6): New.
769 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
770 (prefix_table): Replace PREFIX_0FC7_REG_6 with
771 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
772 PREFIX_MOD_3_0FC7_REG_7.
773 (mod_table): Replace PREFIX_0FC7_REG_6 with
774 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
775 PREFIX_MOD_3_0FC7_REG_7.
776
507bd325
L		 7772015-04-15 H.J. Lu <hongjiu.lu@intel.com>
778
779 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
780 (PREFIX_MANDATORY_REPNZ): Likewise.
781 (PREFIX_MANDATORY_DATA): Likewise.
782 (PREFIX_MANDATORY_ADDR): Likewise.
783 (PREFIX_MANDATORY_LOCK): Likewise.
784 (PREFIX_MANDATORY): Likewise.
785 (PREFIX_UD_SHIFT): Set to 8
786 (PREFIX_UD_REPZ): Updated.
787 (PREFIX_UD_REPNZ): Likewise.
788 (PREFIX_UD_DATA): Likewise.
789 (PREFIX_UD_ADDR): Likewise.
790 (PREFIX_UD_LOCK): Likewise.
791 (PREFIX_IGNORED_SHIFT): New.
792 (PREFIX_IGNORED_REPZ): Likewise.
793 (PREFIX_IGNORED_REPNZ): Likewise.
794 (PREFIX_IGNORED_DATA): Likewise.
795 (PREFIX_IGNORED_ADDR): Likewise.
796 (PREFIX_IGNORED_LOCK): Likewise.
797 (PREFIX_OPCODE): Likewise.
798 (PREFIX_IGNORED): Likewise.
799 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
800 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
801 (three_byte_table): Likewise.
802 (mod_table): Likewise.
803 (mandatory_prefix): Renamed to ...
804 (prefix_requirement): This.
805 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
806 Update PREFIX_90 entry.
807 (get_valid_dis386): Check prefix_requirement to see if a prefix
808 should be ignored.
809 (print_insn): Replace mandatory_prefix with prefix_requirement.
810
f0fba320
RL		 8112015-04-15 Renlin Li <renlin.li@arm.com>
812
813 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
814 use it for ssat and ssat16.
815 (print_insn_thumb32): Add handle case for 'D' control code.
816
bf890a93
IT		 8172015-04-06 Ilya Tocar <ilya.tocar@intel.com>
818 H.J. Lu <hongjiu.lu@intel.com>
819
820 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
821 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
822 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
823 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
824 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
825 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
826 Fill prefix_requirement field.
827 (struct dis386): Add prefix_requirement field.
828 (dis386): Fill prefix_requirement field.
829 (dis386_twobyte): Ditto.
830 (twobyte_has_mandatory_prefix_: Remove.
831 (reg_table): Fill prefix_requirement field.
832 (prefix_table): Ditto.
833 (x86_64_table): Ditto.
834 (three_byte_table): Ditto.
835 (xop_table): Ditto.
836 (vex_table): Ditto.
837 (vex_len_table): Ditto.
838 (vex_w_table): Ditto.
839 (mod_table): Ditto.
840 (bad_opcode): Ditto.
841 (print_insn): Use prefix_requirement.
842 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
843 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
844 (float_reg): Ditto.
845
2f783c1f
MF		 8462015-03-30 Mike Frysinger <vapier@gentoo.org>
847
848 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
849
b9d94d62
L		 8502015-03-29 H.J. Lu <hongjiu.lu@intel.com>
851
852 * Makefile.in: Regenerated.
853
27c49e9a
AB		 8542015-03-25 Anton Blanchard <anton@samba.org>
855
856 * ppc-dis.c (disassemble_init_powerpc): Only initialise
857 powerpc_opcd_indices and vle_opcd_indices once.
858
c4e676f1
AB		 8592015-03-25 Anton Blanchard <anton@samba.org>
860
861 * ppc-opc.c (powerpc_opcodes): Add slbfee.
862
823d2571
TG		 8632015-03-24 Terry Guo <terry.guo@arm.com>
864
865 * arm-dis.c (opcode32): Updated to use new arm feature struct.
866 (opcode16): Likewise.
867 (coprocessor_opcodes): Replace bit with feature struct.
868 (neon_opcodes): Likewise.
869 (arm_opcodes): Likewise.
870 (thumb_opcodes): Likewise.
871 (thumb32_opcodes): Likewise.
872 (print_insn_coprocessor): Likewise.
873 (print_insn_arm): Likewise.
874 (select_arm_features): Follow new feature struct.
875
029f3522
GG		 8762015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
877
878 * i386-dis.c (rm_table): Add clzero.
879 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
880 Add CPU_CLZERO_FLAGS.
881 (cpu_flags): Add CpuCLZERO.
882 * i386-opc.h: Add CpuCLZERO.
883 * i386-opc.tbl: Add clzero.
884 * i386-init.h: Re-generated.
885 * i386-tbl.h: Re-generated.
886
6914869a
AB		 8872015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
888
889 * mips-opc.c (decode_mips_operand): Fix constraint issues
890 with u and y operands.
891
21e20815
AB		 8922015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
893
894 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
895
6b1d7593
AK		 8962015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
897
898 * s390-opc.c: Add new IBM z13 instructions.
899 * s390-opc.txt: Likewise.
900
c8f89a34
JW		 9012015-03-10 Renlin Li <renlin.li@arm.com>
902
903 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
904 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
905 related alias.
906 * aarch64-asm-2.c: Regenerate.
907 * aarch64-dis-2.c: Likewise.
908 * aarch64-opc-2.c: Likewise.
909
d8282f0e
JW		 9102015-03-03 Jiong Wang <jiong.wang@arm.com>
911
912 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
913
ac994365
OE		 9142015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
915
916 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
917 arch_sh_up.
918 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
919 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
920
fd63f640
V		 9212015-02-23 Vinay <Vinay.G@kpit.com>
922
923 * rl78-decode.opc (MOV): Added space between two operands for
924 'mov' instruction in index addressing mode.
925 * rl78-decode.c: Regenerate.
926
f63c1776
PA		 9272015-02-19 Pedro Alves <palves@redhat.com>
928
929 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
930
07774fcc
PA		 9312015-02-10 Pedro Alves <palves@redhat.com>
932 Tom Tromey <tromey@redhat.com>
933
934 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
935 microblaze_and, microblaze_xor.
936 * microblaze-opc.h (opcodes): Adjust.
937
3f8107ab
AM		 9382015-01-28 James Bowman <james.bowman@ftdichip.com>
939
940 * Makefile.am: Add FT32 files.
941 * configure.ac: Handle FT32.
942 * disassemble.c (disassembler): Call print_insn_ft32.
943 * ft32-dis.c: New file.
944 * ft32-opc.c: New file.
945 * Makefile.in: Regenerate.
946 * configure: Regenerate.
947 * po/POTFILES.in: Regenerate.
948
e5fe4957
KLC		 9492015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
950
951 * nds32-asm.c (keyword_sr): Add new system registers.
952
1e2e8c52
AK		 9532015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
954
955 * s390-dis.c (s390_extract_operand): Support vector register
956 operands.
957 (s390_print_insn_with_opcode): Support new operands types and add
958 new handling of optional operands.
959 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
960 and include opcode/s390.h instead.
961 (struct op_struct): New field `flags'.
962 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
963 (dumpTable): Dump flags.
964 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
965 string.
966 * s390-opc.c: Add new operands types, instruction formats, and
967 instruction masks.
968 (s390_opformats): Add new formats for .insn.
969 * s390-opc.txt: Add new instructions.
970
b90efa5b 9712015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 972
b90efa5b 973 Update year range in copyright notice of all files.
bffb6004 974
b90efa5b 975For older changes see ChangeLog-2014
252b5132 976\f
b90efa5b 977Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 978
979Copying and distribution of this file, with or without modification,
980are permitted in any medium without royalty provided the copyright
981notice and this notice are preserved.
982
252b5132 983Local Variables:
2f6d2f85
NC		 984mode: change-log
985left-margin: 8
986fill-column: 74
252b5132
RH		 987version-control: never
988End:
GDB Binutils - Deliverables
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