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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
ea783ef3
DM		 12011-08-05 David S. Miller <davem@davemloft.net>
2
3 * sparc-dis.c (v9a_ast_reg_names): Add "cps".
4 (X_RS3): New macro.
5 (print_insn_sparc): Handle '4', '5', and '(' format codes.
6 Accept %asr numbers below 28.
7 * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
8 instructions.
9
3929df09
QN		 102011-08-02 Quentin Neill <quentin.neill@amd.com>
11
12 * i386-dis.c (xop_table): Remove spurious bextr insn.
13
d7921315
L		 142011-08-01 H.J. Lu <hongjiu.lu@intel.com>
15
16 PR ld/13048
17 * i386-dis.c (print_insn): Optimize info->mach check.
18
00f51a41
L		 192011-08-01 H.J. Lu <hongjiu.lu@intel.com>
20
21 PR gas/13046
22 * i386-opc.tbl: Add Disp32S to 64bit call.
23 * i386-tbl.h: Regenerated.
24
df58fc94
RS		 252011-07-24 Chao-ying Fu <fu@mips.com>
26 Maciej W. Rozycki <macro@codesourcery.com>
27
28 * micromips-opc.c: New file.
29 * mips-dis.c (micromips_to_32_reg_b_map): New array.
30 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
31 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
32 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
33 (micromips_to_32_reg_q_map): Likewise.
34 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
35 (micromips_ase): New variable.
36 (is_micromips): New function.
37 (set_default_mips_dis_options): Handle microMIPS ASE.
38 (print_insn_micromips): New function.
39 (is_compressed_mode_p): Likewise.
40 (_print_insn_mips): Handle microMIPS instructions.
41 * Makefile.am (CFILES): Add micromips-opc.c.
42 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
43 * Makefile.in: Regenerate.
44 * configure: Regenerate.
45
46 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
47 (micromips_to_32_reg_i_map): Likewise.
48 (micromips_to_32_reg_m_map): Likewise.
49 (micromips_to_32_reg_n_map): New macro.
50
bcd530a7
RS		 512011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
52
53 * mips-opc.c (NODS): New macro.
54 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
55 (DSP_VOLA): Likewise.
56 (mips_builtin_opcodes): Add NODS annotation to "deret" and
57 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
58 place of TRAP for "wait", "waiti" and "yield".
59 * mips16-opc.c (NODS): New macro.
60 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
61 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
62 "restore" and "save".
63
7a9068fe
L		 642011-07-22 H.J. Lu <hongjiu.lu@intel.com>
65
66 * configure.in: Handle bfd_k1om_arch.
67 * configure: Regenerated.
68
69 * disassemble.c (disassembler): Handle bfd_k1om_arch.
70
71 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
72 bfd_mach_k1om_intel_syntax.
73
74 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
75 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
76 (cpu_flags): Add CpuK1OM.
77
78 * i386-opc.h (CpuK1OM): New.
79 (i386_cpu_flags): Add cpuk1om.
80
81 * i386-init.h: Regenerated.
82 * i386-tbl.h: Likewise.
83
1b93226d
NC		 842011-07-12 Nick Clifton <nickc@redhat.com>
85
86 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
87 accidental change.
88
5d73b1f1
NC		 892011-07-01 Nick Clifton <nickc@redhat.com>
90
91 PR binutils/12329
92 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
93 insns using post-increment addressing.
94
182ae480
L		 952011-06-30 H.J. Lu <hongjiu.lu@intel.com>
96
97 * i386-dis.c (vex_len_table): Update rorxS.
98
4cb0953d
L		 992011-06-30 H.J. Lu <hongjiu.lu@intel.com>
100
101 AVX Programming Reference (June, 2011)
102 * i386-dis.c (vex_len_table): Correct rorxS.
103
104 * i386-opc.tbl: Correct rorx.
105 * i386-tbl.h: Regenerated.
106
906efcbc
L		 1072011-06-29 H.J. Lu <hongjiu.lu@intel.com>
108
109 * tilegx-opc.c (find_opcode): Replace "index" with "i".
110 * tilepro-opc.c (find_opcode): Likewise.
111
ceb94aa5
RS		 1122011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
113
114 * mips16-opc.c (jalrc, jrc): Move earlier in file.
115
f7002f42
L		 1162011-06-21 H.J. Lu <hongjiu.lu@intel.com>
117
118 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
119 PREFIX_VEX_0F388E.
120
56300268
AS		 1212011-06-17 Andreas Schwab <schwab@redhat.com>
122
123 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
124 (MOSTLYCLEANFILES): ... here.
125 * Makefile.in: Regenerate.
126
bcf2cf9f
AM		 1272011-06-14 Alan Modra <amodra@gmail.com>
128
129 * Makefile.in: Regenerate.
130
aa137e4d
NC		 1312011-06-13 Walter Lee <walt@tilera.com>
132
133 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
134 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
135 * Makefile.in: Regenerate.
136 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
137 * configure: Regenerate.
138 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
139 * po/POTFILES.in: Regenerate.
140 * tilegx-dis.c: New file.
141 * tilegx-opc.c: New file.
142 * tilepro-dis.c: New file.
143 * tilepro-opc.c: New file.
144
6c30d220
L		 1452011-06-10 H.J. Lu <hongjiu.lu@intel.com>
146
147 AVX Programming Reference (June, 2011)
148 * i386-dis.c (XMGatherQ): New.
149 * i386-dis.c (EXxmm_mb): New.
150 (EXxmm_mb): Likewise.
151 (EXxmm_mw): Likewise.
152 (EXxmm_md): Likewise.
153 (EXxmm_mq): Likewise.
154 (EXxmmdw): Likewise.
155 (EXxmmqd): Likewise.
156 (VexGatherQ): Likewise.
157 (MVexVSIBDWpX): Likewise.
158 (MVexVSIBQWpX): Likewise.
159 (xmm_mb_mode): Likewise.
160 (xmm_mw_mode): Likewise.
161 (xmm_md_mode): Likewise.
162 (xmm_mq_mode): Likewise.
163 (xmmdw_mode): Likewise.
164 (xmmqd_mode): Likewise.
165 (ymmxmm_mode): Likewise.
166 (vex_vsib_d_w_dq_mode): Likewise.
167 (vex_vsib_q_w_dq_mode): Likewise.
168 (MOD_VEX_0F385A_PREFIX_2): Likewise.
169 (MOD_VEX_0F388C_PREFIX_2): Likewise.
170 (MOD_VEX_0F388E_PREFIX_2): Likewise.
171 (PREFIX_0F3882): Likewise.
172 (PREFIX_VEX_0F3816): Likewise.
173 (PREFIX_VEX_0F3836): Likewise.
174 (PREFIX_VEX_0F3845): Likewise.
175 (PREFIX_VEX_0F3846): Likewise.
176 (PREFIX_VEX_0F3847): Likewise.
177 (PREFIX_VEX_0F3858): Likewise.
178 (PREFIX_VEX_0F3859): Likewise.
179 (PREFIX_VEX_0F385A): Likewise.
180 (PREFIX_VEX_0F3878): Likewise.
181 (PREFIX_VEX_0F3879): Likewise.
182 (PREFIX_VEX_0F388C): Likewise.
183 (PREFIX_VEX_0F388E): Likewise.
184 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
185 (PREFIX_VEX_0F38F5): Likewise.
186 (PREFIX_VEX_0F38F6): Likewise.
187 (PREFIX_VEX_0F3A00): Likewise.
188 (PREFIX_VEX_0F3A01): Likewise.
189 (PREFIX_VEX_0F3A02): Likewise.
190 (PREFIX_VEX_0F3A38): Likewise.
191 (PREFIX_VEX_0F3A39): Likewise.
192 (PREFIX_VEX_0F3A46): Likewise.
193 (PREFIX_VEX_0F3AF0): Likewise.
194 (VEX_LEN_0F3816_P_2): Likewise.
195 (VEX_LEN_0F3819_P_2): Likewise.
196 (VEX_LEN_0F3836_P_2): Likewise.
197 (VEX_LEN_0F385A_P_2_M_0): Likewise.
198 (VEX_LEN_0F38F5_P_0): Likewise.
199 (VEX_LEN_0F38F5_P_1): Likewise.
200 (VEX_LEN_0F38F5_P_3): Likewise.
201 (VEX_LEN_0F38F6_P_3): Likewise.
202 (VEX_LEN_0F38F7_P_1): Likewise.
203 (VEX_LEN_0F38F7_P_2): Likewise.
204 (VEX_LEN_0F38F7_P_3): Likewise.
205 (VEX_LEN_0F3A00_P_2): Likewise.
206 (VEX_LEN_0F3A01_P_2): Likewise.
207 (VEX_LEN_0F3A38_P_2): Likewise.
208 (VEX_LEN_0F3A39_P_2): Likewise.
209 (VEX_LEN_0F3A46_P_2): Likewise.
210 (VEX_LEN_0F3AF0_P_3): Likewise.
211 (VEX_W_0F3816_P_2): Likewise.
212 (VEX_W_0F3818_P_2): Likewise.
213 (VEX_W_0F3819_P_2): Likewise.
214 (VEX_W_0F3836_P_2): Likewise.
215 (VEX_W_0F3846_P_2): Likewise.
216 (VEX_W_0F3858_P_2): Likewise.
217 (VEX_W_0F3859_P_2): Likewise.
218 (VEX_W_0F385A_P_2_M_0): Likewise.
219 (VEX_W_0F3878_P_2): Likewise.
220 (VEX_W_0F3879_P_2): Likewise.
221 (VEX_W_0F3A00_P_2): Likewise.
222 (VEX_W_0F3A01_P_2): Likewise.
223 (VEX_W_0F3A02_P_2): Likewise.
224 (VEX_W_0F3A38_P_2): Likewise.
225 (VEX_W_0F3A39_P_2): Likewise.
226 (VEX_W_0F3A46_P_2): Likewise.
227 (MOD_VEX_0F3818_PREFIX_2): Removed.
228 (MOD_VEX_0F3819_PREFIX_2): Likewise.
229 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
230 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
231 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
232 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
233 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
234 (VEX_LEN_0F3A0E_P_2): Likewise.
235 (VEX_LEN_0F3A0F_P_2): Likewise.
236 (VEX_LEN_0F3A42_P_2): Likewise.
237 (VEX_LEN_0F3A4C_P_2): Likewise.
238 (VEX_W_0F3818_P_2_M_0): Likewise.
239 (VEX_W_0F3819_P_2_M_0): Likewise.
240 (prefix_table): Updated.
241 (three_byte_table): Likewise.
242 (vex_table): Likewise.
243 (vex_len_table): Likewise.
244 (vex_w_table): Likewise.
245 (mod_table): Likewise.
246 (putop): Handle "LW".
247 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
248 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
249 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
250 (OP_EX): Likewise.
251 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
252 vex_vsib_q_w_dq_mode.
253 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
254 (OP_VEX): Likewise.
255
256 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
257 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
258 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
259 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
260 (opcode_modifiers): Add VecSIB.
261
262 * i386-opc.h (CpuAVX2): New.
263 (CpuBMI2): Likewise.
264 (CpuLZCNT): Likewise.
265 (CpuINVPCID): Likewise.
266 (VecSIB128): Likewise.
267 (VecSIB256): Likewise.
268 (VecSIB): Likewise.
269 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
270 (i386_opcode_modifier): Add vecsib.
271
272 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
273 * i386-init.h: Regenerated.
274 * i386-tbl.h: Likewise.
275
d535accd
QN		 2762011-06-03 Quentin Neill <quentin.neill@amd.com>
277
278 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
279 * i386-init.h: Regenerated.
280
f8b960bc
NC		 2812011-06-03 Nick Clifton <nickc@redhat.com>
282
283 PR binutils/12752
284 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
285 computing address offsets.
286 (print_arm_address): Likewise.
287 (print_insn_arm): Likewise.
288 (print_insn_thumb16): Likewise.
289 (print_insn_thumb32): Likewise.
290
26d97720
NS		 2912011-06-02 Jie Zhang <jie@codesourcery.com>
292 Nathan Sidwell <nathan@codesourcery.com>
293 Maciej Rozycki <macro@codesourcery.com>
294
295 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
296 as address offset.
297 (print_arm_address): Likewise. Elide positive #0 appropriately.
298 (print_insn_arm): Likewise.
299
f8b960bc
NC		 3002011-06-02 Nick Clifton <nickc@redhat.com>
301
302 PR gas/12752
303 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
304 passed to print_address_func.
305
cc643b88
NC		 3062011-06-02 Nick Clifton <nickc@redhat.com>
307
308 * arm-dis.c: Fix spelling mistakes.
309 * op/opcodes.pot: Regenerate.
310
c8fa16ed
AK		 3112011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
312
313 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
314 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
315 * s390-opc.txt: Fix cxr instruction type.
316
5e4b319c
AK		 3172011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
318
319 * s390-opc.c: Add new instruction types marking register pair
320 operands.
321 * s390-opc.txt: Match instructions having register pair operands
322 to the new instruction types.
323
fda544a2
NC		 3242011-05-19 Nick Clifton <nickc@redhat.com>
325
326 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
327 operands.
328
4cab4add
QN		 3292011-05-10 Quentin Neill <quentin.neill@amd.com>
330
331 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
332 * i386-init.h: Regenerated.
333
b4e7b885
NC		 3342011-04-27 Nick Clifton <nickc@redhat.com>
335
336 * po/da.po: Updated Danish translation.
337
2f7f7710
AM		 3382011-04-26 Anton Blanchard <anton@samba.org>
339
340 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
341
9887672f
DD		 3422011-04-21 DJ Delorie <dj@redhat.com>
343
344 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
345 * rx-decode.c: Regenerate.
346
3251b375
L		 3472011-04-20 H.J. Lu <hongjiu.lu@intel.com>
348
349 * i386-init.h: Regenerated.
350
b13a3ca6
QN		 3512011-04-19 Quentin Neill <quentin.neill@amd.com>
352
353 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
354 from bdver1 flags.
355
7d063384
NC		 3562011-04-13 Nick Clifton <nickc@redhat.com>
357
358 * v850-dis.c (disassemble): Always print a closing square brace if
359 an opening square brace was printed.
360
32a94698
NC		 3612011-04-12 Nick Clifton <nickc@redhat.com>
362
363 PR binutils/12534
364 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
365 patterns.
366 (print_insn_thumb32): Handle %L.
367
d2cd1205
JB		 3682011-04-11 Julian Brown <julian@codesourcery.com>
369
370 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
371 (print_insn_thumb32): Add APSR bitmask support.
372
1fbaefec
PB		 3732011-04-07 Paul Carroll<pcarroll@codesourcery.com>
374
375 * arm-dis.c (print_insn): init vars moved into private_data structure.
376
67171547
MF		 3772011-03-24 Mike Frysinger <vapier@gentoo.org>
378
379 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
380
8cc66334
EW		 3812011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
382
383 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
384 post-increment to support LPM Z+ instruction. Add support for 'E'
385 constraint for DES instruction.
386 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
387
34e77a92
RS		 3882011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
389
390 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
391
35fc36a8
RS		 3922011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
393
394 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
395 Use branch types instead.
396 (print_insn): Likewise.
397
0067d8fc
MR		 3982011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
399
400 * mips-opc.c (mips_builtin_opcodes): Correct register use
401 annotation of "alnv.ps".
402
3eebd5eb
MR		 4032011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
404
405 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
406
500cccad
MF		 4072011-02-22 Mike Frysinger <vapier@gentoo.org>
408
409 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
410
f5caf9f4
MF		 4112011-02-22 Mike Frysinger <vapier@gentoo.org>
412
413 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
414
e5bc4265
MF		 4152011-02-19 Mike Frysinger <vapier@gentoo.org>
416
417 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
418 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
419 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
420 exception, end_of_registers, msize, memory, bfd_mach.
421 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
422 LB0REG, LC1REG, LT1REG, LB1REG): Delete
423 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
424 (get_allreg): Change to new defines. Fallback to abort().
425
602427c4
MF		 4262011-02-14 Mike Frysinger <vapier@gentoo.org>
427
428 * bfin-dis.c: Add whitespace/parenthesis where needed.
429
298c1ec2
MF		 4302011-02-14 Mike Frysinger <vapier@gentoo.org>
431
432 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
433 than 7.
434
822ce8ee
RW		 4352011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
436
437 * configure: Regenerate.
438
13c02f06
MF		 4392011-02-13 Mike Frysinger <vapier@gentoo.org>
440
441 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
442
4db66394
MF		 4432011-02-13 Mike Frysinger <vapier@gentoo.org>
444
445 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
446 dregs only when P is set, and dregs_lo otherwise.
447
36f44611
MF		 4482011-02-13 Mike Frysinger <vapier@gentoo.org>
449
450 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
451
9805c0a5
MF		 4522011-02-12 Mike Frysinger <vapier@gentoo.org>
453
454 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
455
43a6aa65
MF		 4562011-02-12 Mike Frysinger <vapier@gentoo.org>
457
458 * bfin-dis.c (machine_registers): Delete REG_GP.
459 (reg_names): Delete "GP".
460 (decode_allregs): Change REG_GP to REG_LASTREG.
461
26bb3ddd
MF		 4622011-02-12 Mike Frysinger <vapier@gentoo.org>
463
89c0d58c
MR		 464 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
465 M_IH, M_IU): Delete.
26bb3ddd 466
69b8ea4a
MF		 4672011-02-11 Mike Frysinger <vapier@gentoo.org>
468
469 * bfin-dis.c (reg_names): Add const.
470 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
471 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
472 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
473 decode_counters, decode_allregs): Likewise.
474
42d5f9c6
MS		 4752011-02-09 Michael Snyder <msnyder@vmware.com>
476
56300268 477 * i386-dis.c (OP_J): Parenthesize expression to prevent
42d5f9c6
MS		 478 truncated addresses.
479 (print_insn): Fix indentation off-by-one.
480
4be0c941
NC		 4812011-02-01 Nick Clifton <nickc@redhat.com>
482
483 * po/da.po: Updated Danish translation.
484
6b069ee7
AM		 4852011-01-21 Dave Murphy <davem@devkitpro.org>
486
487 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
488
e3949f17
L		 4892011-01-18 H.J. Lu <hongjiu.lu@intel.com>
490
491 * i386-dis.c (sIbT): New.
492 (b_T_mode): Likewise.
493 (dis386): Replace sIb with sIbT on "pushT".
494 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
495 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
496
752573b2
JK		 4972011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
498
499 * i386-init.h: Regenerated.
500 * i386-tbl.h: Regenerated
501
2a2a0f38
QN		 5022011-01-17 Quentin Neill <quentin.neill@amd.com>
503
504 * i386-dis.c (REG_XOP_TBM_01): New.
505 (REG_XOP_TBM_02): New.
506 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
507 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
508 entries, and add bextr instruction.
509
510 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
511 (cpu_flags): Add CpuTBM.
512
513 * i386-opc.h (CpuTBM) New.
514 (i386_cpu_flags): Add bit cputbm.
515
516 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
517 blcs, blsfill, blsic, t1mskc, and tzmsk.
518
90d6ff62
DD		 5192011-01-12 DJ Delorie <dj@redhat.com>
520
521 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
522
c95354ed
MX		 5232011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
524
525 * mips-dis.c (print_insn_args): Adjust the value to print the real
526 offset for "+c" argument.
527
f7465604
NC		 5282011-01-10 Nick Clifton <nickc@redhat.com>
529
530 * po/da.po: Updated Danish translation.
531
639e30d2
NS		 5322011-01-05 Nathan Sidwell <nathan@codesourcery.com>
533
534 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
535
f12dc422
L		 5362011-01-04 H.J. Lu <hongjiu.lu@intel.com>
537
538 * i386-dis.c (REG_VEX_38F3): New.
539 (PREFIX_0FBC): Likewise.
540 (PREFIX_VEX_38F2): Likewise.
541 (PREFIX_VEX_38F3_REG_1): Likewise.
542 (PREFIX_VEX_38F3_REG_2): Likewise.
543 (PREFIX_VEX_38F3_REG_3): Likewise.
544 (PREFIX_VEX_38F7): Likewise.
545 (VEX_LEN_38F2_P_0): Likewise.
546 (VEX_LEN_38F3_R_1_P_0): Likewise.
547 (VEX_LEN_38F3_R_2_P_0): Likewise.
548 (VEX_LEN_38F3_R_3_P_0): Likewise.
549 (VEX_LEN_38F7_P_0): Likewise.
550 (dis386_twobyte): Use PREFIX_0FBC.
551 (reg_table): Add REG_VEX_38F3.
552 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
553 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
554 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
555 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
556 PREFIX_VEX_38F7.
557 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
558 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
559 VEX_LEN_38F7_P_0.
560
561 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
562 (cpu_flags): Add CpuBMI.
563
564 * i386-opc.h (CpuBMI): New.
565 (i386_cpu_flags): Add cpubmi.
566
567 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
568 * i386-init.h: Regenerated.
569 * i386-tbl.h: Likewise.
570
cb21baef
L		 5712011-01-04 H.J. Lu <hongjiu.lu@intel.com>
572
573 * i386-dis.c (VexGdq): New.
574 (OP_VEX): Handle dq_mode.
575
0db46eb4
L		 5762011-01-01 H.J. Lu <hongjiu.lu@intel.com>
577
578 * i386-gen.c (process_copyright): Update copyright to 2011.
579
9e9e0820 580For older changes see ChangeLog-2010
252b5132
RH		 581\f
582Local Variables:
2f6d2f85
NC		 583mode: change-log
584left-margin: 8
585fill-column: 74
252b5132
RH		 586version-control: never
587End:
GDB Binutils - Deliverables
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