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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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6128c599
JB		 12005-04-01 Jan Beulich <jbeulich@novell.com>
2
3 * i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any
4 visible operands in Intel mode. The first operand of monitor is
5 %rax in 64-bit mode.
6
373ff435
JB		 72005-04-01 Jan Beulich <jbeulich@novell.com>
8
9 * i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for
10 easier future additions.
11
4bd60896
JG		 122005-03-31 Jerome Guitton <guitton@gnat.com>
13
14 * configure.in: Check for basename.
15 * configure: Regenerate.
16 * config.in: Ditto.
17
4cc91dba
L		 182005-03-29 H.J. Lu <hongjiu.lu@intel.com>
19
20 * i386-dis.c (SEG_Fixup): New.
21 (Sv): New.
22 (dis386): Use "Sv" for 0x8c and 0x8e.
23
ec72cfe5
NC		 242005-03-21 Jan-Benedict Glaw <jbglaw@lug-owl.de>
25 Nick Clifton <nickc@redhat.com>
26
27 * vax-dis.c: (entry_addr): New varible: An array of user supplied
28 function entry mask addresses.
29 (entry_addr_occupied_slots): New variable: The number of occupied
30 elements in entry_addr.
31 (entry_addr_total_slots): New variable: The total number of
32 elements in entry_addr.
33 (parse_disassembler_options): New function. Fills in the entry_addr
34 array.
35 (free_entry_array): New function. Release the memory used by the
36 entry addr array. Suppressed because there is no way to call it.
37 (is_function_entry): Check if a given address is a function's
38 start address by looking at supplied entry mask addresses and
39 symbol information, if available.
40 (print_insn_vax): Use parse_disassembler_options and is_function_entry.
41
85064c79
L		 422005-03-23 H.J. Lu <hongjiu.lu@intel.com>
43
44 * cris-dis.c (print_with_operands): Use ~31L for long instead
45 of ~31.
46
de7141c7
L		 472005-03-20 H.J. Lu <hongjiu.lu@intel.com>
48
49 * mmix-opc.c (O): Revert the last change.
50 (Z): Likewise.
51
e493ab45
L		 522005-03-19 H.J. Lu <hongjiu.lu@intel.com>
53
54 * mmix-opc.c (O): Use 24UL instead of 24 for unsigned long.
55 (Z): Likewise.
56
d8d7c459
HPN		 572005-03-19 Hans-Peter Nilsson <hp@bitrange.com>
58
59 * mmix-opc.c (O, Z): Force expression as unsigned long.
60
ebdb0383
NC		 612005-03-18 Nick Clifton <nickc@redhat.com>
62
63 * ip2k-asm.c: Regenerate.
64 * op/opcodes.pot: Regenerate.
65
1ad12f97
NC		 662005-03-16 Nick Clifton <nickc@redhat.com>
67 Ben Elliston <bje@au.ibm.com>
68
569acd2c 69 * configure.in (werror): New switch: Add -Werror to the
1ad12f97 70 compiler command line. Enabled by default. Disable via
569acd2c 71 --disable-werror.
1ad12f97
NC		 72 * configure: Regenerate.
73
4eb30afc
AM		 742005-03-16 Alan Modra <amodra@bigpond.net.au>
75
76 * ppc-dis.c (powerpc_dialect): Don't set PPC_OPCODE_ALTIVEC when
77 BOOKE.
78
ea8409f7
AM		 792005-03-15 Alan Modra <amodra@bigpond.net.au>
80
729ae8d2
AM		 81 * po/es.po: Commit new Spanish translation.
82
ea8409f7
AM		 83 * po/fr.po: Commit new French translation.
84
4f495e61
NC		 852005-03-14 Jan-Benedict Glaw <jbglaw@lug-owl.de>
86
87 * vax-dis.c: Fix spelling error
88 (print_insn_vax): Use ".word 0x0012 # Entry mask: r1 r2 >" instead
89 of just "Entry mask: < r1 ... >"
90
0a003adc
ZW		 912005-03-12 Zack Weinberg <zack@codesourcery.com>
92
93 * arm-dis.c (arm_opcodes): Document %E and %V.
94 Add entries for v6T2 ARM instructions:
95 bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
96 (print_insn_arm): Add support for %E and %V.
885fc257 97 (thumb_opcodes): Add ARMv6K instructions nop, sev, wfe, wfi, yield.
0a003adc 98
da99ee72
AM		 992005-03-10 Jeff Baker <jbaker@qnx.com>
100 Alan Modra <amodra@bigpond.net.au>
101
102 * ppc-opc.c (insert_sprg, extract_sprg): New Functions.
103 (powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
104 (SPRG_MASK): Delete.
105 (XSPRG_MASK): Mask off extra bits now part of sprg field.
0a003adc 106 (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
da99ee72
AM		 107 mfsprg4..7 after msprg and consolidate.
108
220abb21
AM		 1092005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
110
111 * vax-dis.c (entry_mask_bit): New array.
112 (print_insn_vax): Decode function entry mask.
113
0e06657a
AH		 1142005-03-07 Aldy Hernandez <aldyh@redhat.com>
115
116 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
117
06647dfd
AM		 1182005-03-05 Alan Modra <amodra@bigpond.net.au>
119
120 * po/opcodes.pot: Regenerate.
121
82b829a7
RR		 1222005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
123
220abb21 124 * arc-dis.c (a4_decoding_class): New enum.
06647dfd
AM		 125 (dsmOneArcInst): Use the enum values for the decoding class.
126 Remove redundant case in the switch for decodingClass value 11.
82b829a7 127
c4a530c5
JB		 1282005-03-02 Jan Beulich <jbeulich@novell.com>
129
130 * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
131 accesses.
132 (OP_C): Consider lock prefix in non-64-bit modes.
133
47d8304e
AM		 1342005-02-24 Alan Modra <amodra@bigpond.net.au>
135
136 * cris-dis.c (format_hex): Remove ineffective warning fix.
137 * crx-dis.c (make_instruction): Warning fix.
138 * frv-asm.c: Regenerate.
139
ec36c4a4
NC		 1402005-02-23 Nick Clifton <nickc@redhat.com>
141
33b71eeb
NC		 142 * cgen-dis.in: Use bfd_byte for buffers that are passed to
143 read_memory.
06647dfd 144
33b71eeb 145 * ia64-opc.c (locate_opcode_ent): Initialise opval array.
06647dfd 146
ec36c4a4
NC		 147 * crx-dis.c (make_instruction): Move argument structure into inner
148 scope and ensure that all of its fields are initialised before
149 they are used.
150
33b71eeb
NC		 151 * fr30-asm.c: Regenerate.
152 * fr30-dis.c: Regenerate.
153 * frv-asm.c: Regenerate.
154 * frv-dis.c: Regenerate.
155 * ip2k-asm.c: Regenerate.
156 * ip2k-dis.c: Regenerate.
157 * iq2000-asm.c: Regenerate.
158 * iq2000-dis.c: Regenerate.
159 * m32r-asm.c: Regenerate.
160 * m32r-dis.c: Regenerate.
161 * openrisc-asm.c: Regenerate.
162 * openrisc-dis.c: Regenerate.
163 * xstormy16-asm.c: Regenerate.
164 * xstormy16-dis.c: Regenerate.
165
53c9ebc5
AM		 1662005-02-22 Alan Modra <amodra@bigpond.net.au>
167
168 * arc-ext.c: Warning fixes.
169 * arc-ext.h: Likewise.
170 * cgen-opc.c: Likewise.
171 * ia64-gen.c: Likewise.
172 * maxq-dis.c: Likewise.
173 * ns32k-dis.c: Likewise.
174 * w65-dis.c: Likewise.
175 * ia64-asmtab.c: Regenerate.
176
610ad19b
AM		 1772005-02-22 Alan Modra <amodra@bigpond.net.au>
178
179 * fr30-desc.c: Regenerate.
180 * fr30-desc.h: Regenerate.
181 * fr30-opc.c: Regenerate.
182 * fr30-opc.h: Regenerate.
183 * frv-desc.c: Regenerate.
184 * frv-desc.h: Regenerate.
185 * frv-opc.c: Regenerate.
186 * frv-opc.h: Regenerate.
187 * ip2k-desc.c: Regenerate.
188 * ip2k-desc.h: Regenerate.
189 * ip2k-opc.c: Regenerate.
190 * ip2k-opc.h: Regenerate.
191 * iq2000-desc.c: Regenerate.
192 * iq2000-desc.h: Regenerate.
193 * iq2000-opc.c: Regenerate.
194 * iq2000-opc.h: Regenerate.
195 * m32r-desc.c: Regenerate.
196 * m32r-desc.h: Regenerate.
197 * m32r-opc.c: Regenerate.
198 * m32r-opc.h: Regenerate.
199 * m32r-opinst.c: Regenerate.
200 * openrisc-desc.c: Regenerate.
201 * openrisc-desc.h: Regenerate.
202 * openrisc-opc.c: Regenerate.
203 * openrisc-opc.h: Regenerate.
204 * xstormy16-desc.c: Regenerate.
205 * xstormy16-desc.h: Regenerate.
206 * xstormy16-opc.c: Regenerate.
207 * xstormy16-opc.h: Regenerate.
208
db9db6f2
AM		 2092005-02-21 Alan Modra <amodra@bigpond.net.au>
210
211 * Makefile.am: Run "make dep-am"
212 * Makefile.in: Regenerate.
213
bf143b25
NC		 2142005-02-15 Nick Clifton <nickc@redhat.com>
215
216 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
217 compile time warnings.
218 (print_keyword): Likewise.
219 (default_print_insn): Likewise.
220
221 * fr30-desc.c: Regenerated.
222 * fr30-desc.h: Regenerated.
223 * fr30-dis.c: Regenerated.
224 * fr30-opc.c: Regenerated.
225 * fr30-opc.h: Regenerated.
226 * frv-desc.c: Regenerated.
227 * frv-dis.c: Regenerated.
228 * frv-opc.c: Regenerated.
229 * ip2k-asm.c: Regenerated.
230 * ip2k-desc.c: Regenerated.
231 * ip2k-desc.h: Regenerated.
232 * ip2k-dis.c: Regenerated.
233 * ip2k-opc.c: Regenerated.
234 * ip2k-opc.h: Regenerated.
235 * iq2000-desc.c: Regenerated.
236 * iq2000-dis.c: Regenerated.
237 * iq2000-opc.c: Regenerated.
238 * m32r-asm.c: Regenerated.
239 * m32r-desc.c: Regenerated.
240 * m32r-desc.h: Regenerated.
241 * m32r-dis.c: Regenerated.
242 * m32r-opc.c: Regenerated.
243 * m32r-opc.h: Regenerated.
244 * m32r-opinst.c: Regenerated.
245 * openrisc-desc.c: Regenerated.
246 * openrisc-desc.h: Regenerated.
247 * openrisc-dis.c: Regenerated.
248 * openrisc-opc.c: Regenerated.
249 * openrisc-opc.h: Regenerated.
250 * xstormy16-desc.c: Regenerated.
251 * xstormy16-desc.h: Regenerated.
252 * xstormy16-dis.c: Regenerated.
253 * xstormy16-opc.c: Regenerated.
254 * xstormy16-opc.h: Regenerated.
255
d6098898
L		 2562005-02-14 H.J. Lu <hongjiu.lu@intel.com>
257
258 * dis-buf.c (perror_memory): Use sprintf_vma to print out
259 address.
260
5a84f3e0
NC		 2612005-02-11 Nick Clifton <nickc@redhat.com>
262
bc18c937
NC		 263 * iq2000-asm.c: Regenerate.
264
5a84f3e0
NC		 265 * frv-dis.c: Regenerate.
266
0a40490e
JB		 2672005-02-07 Jim Blandy <jimb@redhat.com>
268
269 * Makefile.am (CGEN): Load guile.scm before calling the main
270 application script.
271 * Makefile.in: Regenerated.
272 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
273 Simply pass the cgen-opc.scm path to ${cgen} as its first
274 argument; ${cgen} itself now contains the '-s', or whatever is
275 appropriate for the Scheme being used.
276
c46f8c51
AC		 2772005-01-31 Andrew Cagney <cagney@gnu.org>
278
279 * configure: Regenerate to track ../gettext.m4.
280
60b9a617
JB		 2812005-01-31 Jan Beulich <jbeulich@novell.com>
282
283 * ia64-gen.c (NELEMS): Define.
284 (shrink): Generate alias with missing second predicate register when
285 opcode has two outputs and these are both predicates.
286 * ia64-opc-i.c (FULL17): Define.
287 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
288 here to generate output template.
289 (TBITCM, TNATCM): Undefine after use.
290 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
291 first input. Add ld16 aliases without ar.csd as second output. Add
292 st16 aliases without ar.csd as second input. Add cmpxchg aliases
293 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
294 ar.ccv as third/fourth inputs. Consolidate through...
295 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
296 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
297 * ia64-asmtab.c: Regenerate.
298
a53bf506
AC		 2992005-01-27 Andrew Cagney <cagney@gnu.org>
300
301 * configure: Regenerate to track ../gettext.m4 change.
302
90219bd0
AO		 3032005-01-25 Alexandre Oliva <aoliva@redhat.com>
304
305 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
306 * frv-asm.c: Rebuilt.
307 * frv-desc.c: Rebuilt.
308 * frv-desc.h: Rebuilt.
309 * frv-dis.c: Rebuilt.
310 * frv-ibld.c: Rebuilt.
311 * frv-opc.c: Rebuilt.
312 * frv-opc.h: Rebuilt.
313
45181ed1
AC		 3142005-01-24 Andrew Cagney <cagney@gnu.org>
315
316 * configure: Regenerate, ../gettext.m4 was updated.
317
9e836e3d
FF		 3182005-01-21 Fred Fish <fnf@specifixinc.com>
319
320 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
321 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
322 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
323 * mips-dis.c: Ditto.
324
5e8cb021
AM		 3252005-01-20 Alan Modra <amodra@bigpond.net.au>
326
327 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
328
986e18a5
FF		 3292005-01-19 Fred Fish <fnf@specifixinc.com>
330
331 * mips-dis.c (no_aliases): New disassembly option flag.
332 (set_default_mips_dis_options): Init no_aliases to zero.
333 (parse_mips_dis_option): Handle no-aliases option.
334 (print_insn_mips): Ignore table entries that are aliases
335 if no_aliases is set.
336 (print_insn_mips16): Ditto.
337 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
338 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
339 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
340 * mips16-opc.c (mips16_opcodes): Ditto.
341
e38bc3b5
NC		 3422005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
343
344 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
345 (inheritance diagram): Add missing edge.
346 (arch_sh1_up): Rename arch_sh_up to match external name to make life
347 easier for the testsuite.
348 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
349 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
610ad19b 350 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
e38bc3b5
NC		 351 arch_sh2a_or_sh4_up child.
352 (sh_table): Do renaming as above.
353 Correct comment for ldc.l for gas testsuite to read.
354 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
355 Correct comments for movy.w and movy.l for gas testsuite to read.
356 Correct comments for fmov.d and fmov.s for gas testsuite to read.
357
9df48ba9
L		 3582005-01-12 H.J. Lu <hongjiu.lu@intel.com>
359
360 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
361
2033b4b9
L		 3622005-01-12 H.J. Lu <hongjiu.lu@intel.com>
363
364 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
365
0bcb06d2
AS		 3662005-01-10 Andreas Schwab <schwab@suse.de>
367
368 * disassemble.c (disassemble_init_for_target) <case
369 bfd_arch_ia64>: Set skip_zeroes to 16.
370 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
371
47add74d
TL		 3722004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
373
374 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
375
246f4c05
SS		 3762004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
377
378 * avr-dis.c: Prettyprint. Added printing of symbol names in all
379 memory references. Convert avr_operand() to C90 formatting.
380
0e1200e5
TL		 3812004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
382
383 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
384
89a649f7
TL		 3852004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
386
387 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
388 (no_op_insn): Initialize array with instructions that have no
389 operands.
390 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
391
6255809c
RE		 3922004-11-29 Richard Earnshaw <rearnsha@arm.com>
393
394 * arm-dis.c: Correct top-level comment.
395
2fbad815
RE		 3962004-11-27 Richard Earnshaw <rearnsha@arm.com>
397
398 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
399 architecuture defining the insn.
400 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 401 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
402 field.
2fbad815
RE		 403 Also include opcode/arm.h.
404 * Makefile.am (arm-dis.lo): Update dependency list.
405 * Makefile.in: Regenerate.
406
d81acc42
NC		 4072004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
408
409 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
410 reflect the change to the short immediate syntax.
411
ca4f2377
AM		 4122004-11-19 Alan Modra <amodra@bigpond.net.au>
413
5da8bf1b
AM		 414 * or32-opc.c (debug): Warning fix.
415 * po/POTFILES.in: Regenerate.
416
ca4f2377
AM		 417 * maxq-dis.c: Formatting.
418 (print_insn): Warning fix.
419
b7693d02
DJ		 4202004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
421
422 * arm-dis.c (WORD_ADDRESS): Define.
423 (print_insn): Use it. Correct big-endian end-of-section handling.
424
300dac7e
NC		 4252004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
426 Vineet Sharma <vineets@noida.hcltech.com>
427
428 * maxq-dis.c: New file.
429 * disassemble.c (ARCH_maxq): Define.
610ad19b 430 (disassembler): Add 'print_insn_maxq_little' for handling maxq
300dac7e
NC		 431 instructions..
432 * configure.in: Add case for bfd_maxq_arch.
433 * configure: Regenerate.
434 * Makefile.am: Add support for maxq-dis.c
435 * Makefile.in: Regenerate.
436 * aclocal.m4: Regenerate.
437
42048ee7
TL		 4382004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
439
440 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
441 mode.
442 * crx-dis.c: Likewise.
443
bd21e58e
HPN		 4442004-11-04 Hans-Peter Nilsson <hp@axis.com>
445
446 Generally, handle CRISv32.
447 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
448 (struct cris_disasm_data): New type.
449 (format_reg, format_hex, cris_constraint, print_flags)
450 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
451 callers changed.
452 (format_sup_reg, print_insn_crisv32_with_register_prefix)
453 (print_insn_crisv32_without_register_prefix)
454 (print_insn_crisv10_v32_with_register_prefix)
455 (print_insn_crisv10_v32_without_register_prefix)
456 (cris_parse_disassembler_options): New functions.
457 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
458 parameter. All callers changed.
459 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
460 failure.
461 (cris_constraint) <case 'Y', 'U'>: New cases.
462 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
463 for constraint 'n'.
464 (print_with_operands) <case 'Y'>: New case.
465 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
466 <case 'N', 'Y', 'Q'>: New cases.
467 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
468 (print_insn_cris_with_register_prefix)
469 (print_insn_cris_without_register_prefix): Call
470 cris_parse_disassembler_options.
471 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
472 for CRISv32 and the size of immediate operands. New v32-only
473 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
474 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
475 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
476 Change brp to be v3..v10.
477 (cris_support_regs): New vector.
478 (cris_opcodes): Update head comment. New format characters '[',
479 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
480 Add new opcodes for v32 and adjust existing opcodes to accommodate
481 differences to earlier variants.
482 (cris_cond15s): New vector.
483
9306ca4a
JB		 4842004-11-04 Jan Beulich <jbeulich@novell.com>
485
486 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
487 (indirEb): Remove.
488 (Mp): Use f_mode rather than none at all.
489 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
490 replaces what previously was x_mode; x_mode now means 128-bit SSE
491 operands.
492 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
493 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
494 pinsrw's second operand is Edqw.
495 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
496 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
497 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
498 mode when an operand size override is present or always suffixing.
499 More instructions will need to be added to this group.
500 (putop): Handle new macro chars 'C' (short/long suffix selector),
501 'I' (Intel mode override for following macro char), and 'J' (for
502 adding the 'l' prefix to far branches in AT&T mode). When an
503 alternative was specified in the template, honor macro character when
504 specified for Intel mode.
505 (OP_E): Handle new *_mode values. Correct pointer specifications for
506 memory operands. Consolidate output of index register.
507 (OP_G): Handle new *_mode values.
508 (OP_I): Handle const_1_mode.
509 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
510 respective opcode prefix bits have been consumed.
511 (OP_EM, OP_EX): Provide some default handling for generating pointer
512 specifications.
513
f39c96a9
TL		 5142004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
515
516 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
517 COP_INST macro.
518
812337be
TL		 5192004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
520
521 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
522 (getregliststring): Support HI/LO and user registers.
610ad19b 523 * crx-opc.c (crx_instruction): Update data structure according to the
812337be
TL		 524 rearrangement done in CRX opcode header file.
525 (crx_regtab): Likewise.
526 (crx_optab): Likewise.
610ad19b 527 (crx_instruction): Reorder load/stor instructions, remove unsupported
812337be
TL		 528 formats.
529 support new Co-Processor instruction 'cpi'.
530
4030fa5a
NC		 5312004-10-27 Nick Clifton <nickc@redhat.com>
532
533 * opcodes/iq2000-asm.c: Regenerate.
534 * opcodes/iq2000-desc.c: Regenerate.
535 * opcodes/iq2000-desc.h: Regenerate.
536 * opcodes/iq2000-dis.c: Regenerate.
537 * opcodes/iq2000-ibld.c: Regenerate.
538 * opcodes/iq2000-opc.c: Regenerate.
539 * opcodes/iq2000-opc.h: Regenerate.
540
fc3d45e8
TL		 5412004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
542
543 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
544 us4, us5 (respectively).
545 Remove unsupported 'popa' instruction.
546 Reverse operands order in store co-processor instructions.
547
3c55da70
AM		 5482004-10-15 Alan Modra <amodra@bigpond.net.au>
549
550 * Makefile.am: Run "make dep-am"
551 * Makefile.in: Regenerate.
552
7fa3d080
BW		 5532004-10-12 Bob Wilson <bob.wilson@acm.org>
554
555 * xtensa-dis.c: Use ISO C90 formatting.
556
e612bb4d
AM		 5572004-10-09 Alan Modra <amodra@bigpond.net.au>
558
559 * ppc-opc.c: Revert 2004-09-09 change.
560
43cd72b9
BW		 5612004-10-07 Bob Wilson <bob.wilson@acm.org>
562
563 * xtensa-dis.c (state_names): Delete.
564 (fetch_data): Use xtensa_isa_maxlength.
565 (print_xtensa_operand): Replace operand parameter with opcode/operand
566 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
567 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
568 instruction bundles. Use xmalloc instead of malloc.
569
bbac1f2a
NC		 5702004-10-07 David Gibson <david@gibson.dropbear.id.au>
571
572 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
573 initializers.
574
48c9f030
NC		 5752004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
576
577 * crx-opc.c (crx_instruction): Support Co-processor insns.
578 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
579 (getregliststring): Change function to use the above enum.
580 (print_arg): Handle CO-Processor insns.
581 (crx_cinvs): Add 'b' option to invalidate the branch-target
582 cache.
583
12c64a4e
AH		 5842004-10-06 Aldy Hernandez <aldyh@redhat.com>
585
586 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
587 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
588 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
589 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
590 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
591
14127cc4
NC		 5922004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
593
594 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
595 rather than add it.
596
0dd132b6
NC		 5972004-09-30 Paul Brook <paul@codesourcery.com>
598
599 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
600 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
601
3f85e526
L		 6022004-09-17 H.J. Lu <hongjiu.lu@intel.com>
603
604 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
605 (CONFIG_STATUS_DEPENDENCIES): New.
606 (Makefile): Removed.
607 (config.status): Likewise.
608 * Makefile.in: Regenerated.
609
8ae85421
AM		 6102004-09-17 Alan Modra <amodra@bigpond.net.au>
611
612 * Makefile.am: Run "make dep-am".
613 * Makefile.in: Regenerate.
614 * aclocal.m4: Regenerate.
615 * configure: Regenerate.
616 * po/POTFILES.in: Regenerate.
617 * po/opcodes.pot: Regenerate.
618
24443139
AS		 6192004-09-11 Andreas Schwab <schwab@suse.de>
620
621 * configure: Rebuild.
622
2a309db0
AM		 6232004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
624
625 * ppc-opc.c (L): Make this field not optional.
626
42851540
NC		 6272004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
628
629 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
630 Fix parameter to 'm[t|f]csr' insns.
631
979273e3
NN		 6322004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
633
634 * configure.in: Autoupdate to autoconf 2.59.
635 * aclocal.m4: Rebuild with aclocal 1.4p6.
636 * configure: Rebuild with autoconf 2.59.
637 * Makefile.in: Rebuild with automake 1.4p6 (picking up
638 bfd changes for autoconf 2.59 on the way).
639 * config.in: Rebuild with autoheader 2.59.
640
ac28a1cb
RS		 6412004-08-27 Richard Sandiford <rsandifo@redhat.com>
642
643 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
644
30d1c836
ML		 6452004-07-30 Michal Ludvig <mludvig@suse.cz>
646
647 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
648 (GRPPADLCK2): New define.
649 (twobyte_has_modrm): True for 0xA6.
650 (grps): GRPPADLCK2 for opcode 0xA6.
651
0b0ac059
AO		 6522004-07-29 Alexandre Oliva <aoliva@redhat.com>
653
654 Introduce SH2a support.
655 * sh-opc.h (arch_sh2a_base): Renumber.
656 (arch_sh2a_nofpu_base): Remove.
657 (arch_sh_base_mask): Adjust.
658 (arch_opann_mask): New.
659 (arch_sh2a, arch_sh2a_nofpu): Adjust.
660 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
661 (sh_table): Adjust whitespace.
662 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
663 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
664 instruction list throughout.
665 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
666 of arch_sh2a in instruction list throughout.
667 (arch_sh2e_up): Accomodate above changes.
668 (arch_sh2_up): Ditto.
669 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
670 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
671 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
672 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
673 * sh-opc.h (arch_sh2a_nofpu): New.
674 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
675 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
676 instruction.
677 2004-01-20 DJ Delorie <dj@redhat.com>
678 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
679 2003-12-29 DJ Delorie <dj@redhat.com>
680 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
681 sh_opcode_info, sh_table): Add sh2a support.
682 (arch_op32): New, to tag 32-bit opcodes.
683 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
684 2003-12-02 Michael Snyder <msnyder@redhat.com>
685 * sh-opc.h (arch_sh2a): Add.
686 * sh-dis.c (arch_sh2a): Handle.
687 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
688
670ec21d
NC		 6892004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
690
691 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
692
ed049af3
NC		 6932004-07-22 Nick Clifton <nickc@redhat.com>
694
695 PR/280
696 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
697 insns - this is done by objdump itself.
698 * h8500-dis.c (print_insn_h8500): Likewise.
699
20f0a1fc
NC		 7002004-07-21 Jan Beulich <jbeulich@novell.com>
701
702 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
703 regardless of address size prefix in effect.
704 (ptr_reg): Size or address registers does not depend on rex64, but
705 on the presence of an address size override.
706 (OP_MMX): Use rex.x only for xmm registers.
707 (OP_EM): Use rex.z only for xmm registers.
708
6f14957b
MR		 7092004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
710
711 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
712 move/branch operations to the bottom so that VR5400 multimedia
713 instructions take precedence in disassembly.
714
1586d91e
MR		 7152004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
716
717 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
718 ISA-specific "break" encoding.
719
982de27a
NC		 7202004-07-13 Elvis Chiang <elvisfb@gmail.com>
721
722 * arm-opc.h: Fix typo in comment.
723
4300ab10
AS		 7242004-07-11 Andreas Schwab <schwab@suse.de>
725
726 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
727
8577e690
AS		 7282004-07-09 Andreas Schwab <schwab@suse.de>
729
730 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
731
1fe1f39c
NC		 7322004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
733
734 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
735 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
736 (crx-dis.lo): New target.
737 (crx-opc.lo): Likewise.
738 * Makefile.in: Regenerate.
739 * configure.in: Handle bfd_crx_arch.
740 * configure: Regenerate.
741 * crx-dis.c: New file.
742 * crx-opc.c: New file.
743 * disassemble.c (ARCH_crx): Define.
744 (disassembler): Handle ARCH_crx.
745
7a33b495
JW		 7462004-06-29 James E Wilson <wilson@specifixinc.com>
747
748 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
749 * ia64-asmtab.c: Regnerate.
750
98e69875
AM		 7512004-06-28 Alan Modra <amodra@bigpond.net.au>
752
753 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
754 (extract_fxm): Don't test dialect.
755 (XFXFXM_MASK): Include the power4 bit.
756 (XFXM): Add p4 param.
757 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
758
a53b85e2
AO		 7592004-06-27 Alexandre Oliva <aoliva@redhat.com>
760
761 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
762 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
763
d0618d1c
AM		 7642004-06-26 Alan Modra <amodra@bigpond.net.au>
765
766 * ppc-opc.c (BH, XLBH_MASK): Define.
767 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
768
1d9f512f
AM		 7692004-06-24 Alan Modra <amodra@bigpond.net.au>
770
771 * i386-dis.c (x_mode): Comment.
772 (two_source_ops): File scope.
773 (float_mem): Correct fisttpll and fistpll.
774 (float_mem_mode): New table.
775 (dofloat): Use it.
776 (OP_E): Correct intel mode PTR output.
777 (ptr_reg): Use open_char and close_char.
778 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
779 operands. Set two_source_ops.
780
52886d70
AM		 7812004-06-15 Alan Modra <amodra@bigpond.net.au>
782
783 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
784 instead of _raw_size.
785
bad9ceea
JJ		 7862004-06-08 Jakub Jelinek <jakub@redhat.com>
787
788 * ia64-gen.c (in_iclass): Handle more postinc st
789 and ld variants.
790 * ia64-asmtab.c: Rebuilt.
791
0451f5df
MS		 7922004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
793
794 * s390-opc.txt: Correct architecture mask for some opcodes.
795 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
796 in the esa mode as well.
797
f6f9408f
JR		 7982004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
799
800 * sh-dis.c (target_arch): Make unsigned.
801 (print_insn_sh): Replace (most of) switch with a call to
802 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
803 * sh-opc.h: Redefine architecture flags values.
804 Add sh3-nommu architecture.
805 Reorganise <arch>_up macros so they make more visual sense.
806 (SH_MERGE_ARCH_SET): Define new macro.
807 (SH_VALID_BASE_ARCH_SET): Likewise.
808 (SH_VALID_MMU_ARCH_SET): Likewise.
809 (SH_VALID_CO_ARCH_SET): Likewise.
810 (SH_VALID_ARCH_SET): Likewise.
811 (SH_MERGE_ARCH_SET_VALID): Likewise.
812 (SH_ARCH_SET_HAS_FPU): Likewise.
813 (SH_ARCH_SET_HAS_DSP): Likewise.
814 (SH_ARCH_UNKNOWN_ARCH): Likewise.
815 (sh_get_arch_from_bfd_mach): Add prototype.
816 (sh_get_arch_up_from_bfd_mach): Likewise.
817 (sh_get_bfd_mach_from_arch_set): Likewise.
818 (sh_merge_bfd_arc): Likewise.
819
be8c092b
NC		 8202004-05-24 Peter Barada <peter@the-baradas.com>
821
822 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
610ad19b
AM		 823 into new match_insn_m68k function. Loop over canidate
824 matches and select first that completely matches.
be8c092b
NC		 825 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
826 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
610ad19b 827 to verify addressing for MAC/EMAC.
be8c092b
NC		 828 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
829 reigster halves since 'fpu' and 'spl' look misleading.
830 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
831 * m68k-opc.c: Rearragne mac/emac cases to use longest for
832 first, tighten up match masks.
833 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
834 'size' from special case code in print_insn_m68k to
835 determine decode size of insns.
836
a30e9cc4
AM		 8372004-05-19 Alan Modra <amodra@bigpond.net.au>
838
839 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
840 well as when -mpower4.
841
9598fbe5
NC		 8422004-05-13 Nick Clifton <nickc@redhat.com>
843
844 * po/fr.po: Updated French translation.
845
6b6e92f4
NC		 8462004-05-05 Peter Barada <peter@the-baradas.com>
847
848 * m68k-dis.c(print_insn_m68k): Add new chips, use core
849 variants in arch_mask. Only set m68881/68851 for 68k chips.
850 * m68k-op.c: Switch from ColdFire chips to core variants.
851
a404d431
AM		 8522004-05-05 Alan Modra <amodra@bigpond.net.au>
853
a30e9cc4 854 PR 147.
a404d431
AM		 855 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
856
f3806e43
BE		 8572004-04-29 Ben Elliston <bje@au.ibm.com>
858
520ceea4
BE		 859 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
860 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 861
1f1799d5
KK		 8622004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
863
864 * sh-dis.c (print_insn_sh): Print the value in constant pool
865 as a symbol if it looks like a symbol.
866
fd99574b
NC		 8672004-04-22 Peter Barada <peter@the-baradas.com>
868
869 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
870 appropriate ColdFire architectures.
871 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
872 mask addressing.
873 Add EMAC instructions, fix MAC instructions. Remove
874 macmw/macml/msacmw/msacml instructions since mask addressing now
875 supported.
876
b4781d44
JJ		 8772004-04-20 Jakub Jelinek <jakub@redhat.com>
878
879 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
880 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
881 suffix. Use fmov*x macros, create all 3 fpsize variants in one
882 macro. Adjust all users.
883
91809fda 8842004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
610ad19b 885
91809fda
NC		 886 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
887 separately.
888
f4453dfa
NC		 8892004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
890
891 * m32r-asm.c: Regenerate.
892
9b0de91a
SS		 8932004-03-29 Stan Shebs <shebs@apple.com>
894
895 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
896 used.
897
e20c0b3d
AM		 8982004-03-19 Alan Modra <amodra@bigpond.net.au>
899
900 * aclocal.m4: Regenerate.
901 * config.in: Regenerate.
902 * configure: Regenerate.
903 * po/POTFILES.in: Regenerate.
904 * po/opcodes.pot: Regenerate.
905
fdd12ef3
AM		 9062004-03-16 Alan Modra <amodra@bigpond.net.au>
907
908 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
909 PPC_OPERANDS_GPR_0.
910 * ppc-opc.c (RA0): Define.
911 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
912 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 913 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 914
2dc111b3 9152004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 916
917 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 918
7bfeee7b
AM		 9192004-03-15 Alan Modra <amodra@bigpond.net.au>
920
921 * sparc-dis.c (print_insn_sparc): Update getword prototype.
922
7ffdda93
ML		 9232004-03-12 Michal Ludvig <mludvig@suse.cz>
924
925 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 926 (grps): Delete GRPPLOCK entry.
7ffdda93 927
cc0ec051
AM		 9282004-03-12 Alan Modra <amodra@bigpond.net.au>
929
930 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
931 (M, Mp): Use OP_M.
932 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
933 (GRPPADLCK): Define.
934 (dis386): Use NOP_Fixup on "nop".
935 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
936 (twobyte_has_modrm): Set for 0xa7.
937 (padlock_table): Delete. Move to..
938 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
939 and clflush.
940 (print_insn): Revert PADLOCK_SPECIAL code.
941 (OP_E): Delete sfence, lfence, mfence checks.
942
4fd61dcb
JJ		 9432004-03-12 Jakub Jelinek <jakub@redhat.com>
944
945 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
946 (INVLPG_Fixup): New function.
947 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
948
0f10071e
ML		 9492004-03-12 Michal Ludvig <mludvig@suse.cz>
950
951 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
952 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
953 (padlock_table): New struct with PadLock instructions.
954 (print_insn): Handle PADLOCK_SPECIAL.
955
c02908d2
AM		 9562004-03-12 Alan Modra <amodra@bigpond.net.au>
957
958 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
959 (OP_E): Twiddle clflush to sfence here.
960
d5bb7600
NC		 9612004-03-08 Nick Clifton <nickc@redhat.com>
962
963 * po/de.po: Updated German translation.
964
ae51a426
JR		 9652003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
966
967 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
968 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
969 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
970 accordingly.
971
676a64f4
RS		 9722004-03-01 Richard Sandiford <rsandifo@redhat.com>
973
974 * frv-asm.c: Regenerate.
975 * frv-desc.c: Regenerate.
976 * frv-desc.h: Regenerate.
977 * frv-dis.c: Regenerate.
978 * frv-ibld.c: Regenerate.
979 * frv-opc.c: Regenerate.
980 * frv-opc.h: Regenerate.
981
c7a48b9a
RS		 9822004-03-01 Richard Sandiford <rsandifo@redhat.com>
983
984 * frv-desc.c, frv-opc.c: Regenerate.
985
8ae0baa2
RS		 9862004-03-01 Richard Sandiford <rsandifo@redhat.com>
987
988 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
989
ce11586c
JR		 9902004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
991
992 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
993 Also correct mistake in the comment.
994
6a5709a5
JR		 9952004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
996
997 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
998 ensure that double registers have even numbers.
999 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
1000 that reserved instruction 0xfffd does not decode the same
1001 as 0xfdfd (ftrv).
1002 * sh-opc.h: Add REG_N_D nibble type and use it whereever
1003 REG_N refers to a double register.
1004 Add REG_N_B01 nibble type and use it instead of REG_NM
1005 in ftrv.
1006 Adjust the bit patterns in a few comments.
1007
e5d2b64f 10082004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1009
1010 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 1011
1f04b05f
AH		 10122004-02-20 Aldy Hernandez <aldyh@redhat.com>
1013
1014 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
1015
2f3b8700
AH		 10162004-02-20 Aldy Hernandez <aldyh@redhat.com>
1017
1018 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
1019
f0b26da6 10202004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1021
1022 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
1023 mtivor32, mtivor33, mtivor34.
f0b26da6 1024
23d59c56 10252004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1026
1027 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 1028
34920d91
NC		 10292004-02-10 Petko Manolov <petkan@nucleusys.com>
1030
1031 * arm-opc.h Maverick accumulator register opcode fixes.
1032
44d86481
BE		 10332004-02-13 Ben Elliston <bje@wasabisystems.com>
1034
1035 * m32r-dis.c: Regenerate.
1036
17707c23
MS		 10372004-01-27 Michael Snyder <msnyder@redhat.com>
1038
1039 * sh-opc.h (sh_table): "fsrra", not "fssra".
1040
fe3a9bc4
NC		 10412004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
1042
1043 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
1044 contraints.
1045
ff24f124
JJ		 10462004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
1047
1048 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
1049
a02a862a
AM		 10502004-01-19 Alan Modra <amodra@bigpond.net.au>
1051
1052 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
1053 1. Don't print scale factor on AT&T mode when index missing.
1054
d164ea7f
AO		 10552004-01-16 Alexandre Oliva <aoliva@redhat.com>
1056
1057 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
1058 when loaded into XR registers.
1059
cb10e79a
RS		 10602004-01-14 Richard Sandiford <rsandifo@redhat.com>
1061
1062 * frv-desc.h: Regenerate.
1063 * frv-desc.c: Regenerate.
1064 * frv-opc.c: Regenerate.
1065
f532f3fa
MS		 10662004-01-13 Michael Snyder <msnyder@redhat.com>
1067
1068 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
1069
e45d0630
PB		 10702004-01-09 Paul Brook <paul@codesourcery.com>
1071
1072 * arm-opc.h (arm_opcodes): Move generic mcrr after known
1073 specific opcodes.
1074
3ba7a1aa
DJ		 10752004-01-07 Daniel Jacobowitz <drow@mvista.com>
1076
1077 * Makefile.am (libopcodes_la_DEPENDENCIES)
1078 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
1079 comment about the problem.
1080 * Makefile.in: Regenerate.
1081
ba2d3f07
AO		 10822004-01-06 Alexandre Oliva <aoliva@redhat.com>
1083
1084 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
1085 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
1086 cut&paste errors in shifting/truncating numerical operands.
1087 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1088 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
1089 (parse_uslo16): Likewise.
1090 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
1091 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
1092 (parse_s12): Likewise.
1093 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1094 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
1095 (parse_uslo16): Likewise.
1096 (parse_uhi16): Parse gothi and gotfuncdeschi.
1097 (parse_d12): Parse got12 and gotfuncdesc12.
1098 (parse_s12): Likewise.
1099
3ab48931
NC		 11002004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
1101
1102 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
1103 instruction which looks similar to an 'rla' instruction.
a0bd404e 1104
c9e214e5 1105For older changes see ChangeLog-0203
252b5132
RH		 1106\f
1107Local Variables:
2f6d2f85
NC		 1108mode: change-log
1109left-margin: 8
1110fill-column: 74
252b5132
RH		 1111version-control: never
1112End:
GDB Binutils - Deliverables
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