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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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ed7841b3
JB		 12006-11-30 Jan Beulich <jbeulich@novell.com>
2
3 * i386-dis.c (SEG_Fixup): Delete.
4 (Sv): Use OP_SEG.
5 (putop): New suffix character 'D'.
6 (dis386): Use it.
7 (grps): Likewise.
8 (OP_SEG): Handle bytemode other than w_mode.
9
52fd6d94
JB		 102006-11-30 Jan Beulich <jbeulich@novell.com>
11
12 * i386-dis.c (zAX): New.
13 (Xz): New.
14 (Yzr): New.
15 (z_mode): New.
16 (z_mode_ax_reg): New.
17 (putop): New suffix character 'G'.
18 (dis386): Use it for in, out, ins, and outs.
19 (intel_operand_size): Handle z_mode.
20 (OP_REG): Delete unreachable case indir_dx_reg.
21 (OP_IMREG): Fix Intel syntax output for case indir_dx_reg. Handle
22 z_mode_ax_reg.
23 (OP_ESreg): Fix Intel syntax operand size handling.
24 (OP_DSreg): Likewise.
25
a35ca55a
JB		 262006-11-30 Jan Beulich <jbeulich@novell.com>
27
28 * i386-dis.c (dis386): Use 'R' and 'O' for cbw/cwd unconditionally.
29 (putop): For 'O' suffix, print 'q' in Intel mode, and mark data prefix
30 used. For 'R' and 'W' suffix, simplify and fix Intel mode.
31
00249aaa
PB		 322006-11-29 Paul Brook <paul@codesourcery.com>
33
34 * arm-dis.c (coprocessor_opcodes): Fix bitfields for fconstd/fconstd.
35
e821645d
DJ		 362006-11-22 Daniel Jacobowitz <dan@codesourcery.com>
37
38 * arm-dis.c (last_is_thumb): Delete.
39 (enum map_type, last_type): New.
40 (print_insn_data): New.
41 (get_sym_code_type): Take MAP_TYPE argument. Check the type of
42 the right symbol. Handle $d.
43 (print_insn): Check for mapping symbols even without a normal
44 symbol. Adjust searching. If $d is found see how much data
45 to print. Handle data.
46
869ddf2a
NS		 472006-11-16 Nathan Sidwell <nathan@codesourcery.com>
48
49 * m68k-opc.c (m68k_opcodes): Place trap instructions before set
50 conditionals. Add tpf coldfire instruction as alias for trapf.
51
d81afd0c
L		 522006-11-09 H.J. Lu <hongjiu.lu@intel.com>
53
54 * i386-dis.c (print_insn): Check PREFIX_REPNZ before
55 PREFIX_DATA when prefix user table is used.
56
eec0f4ca
L		 572006-11-09 H.J. Lu <hongjiu.lu@intel.com>
58
59 * i386-dis.c (twobyte_uses_SSE_prefix): Renamed to ...
60 (twobyte_uses_DATA_prefix): This.
61 (twobyte_uses_REPNZ_prefix): New.
62 (twobyte_uses_REPZ_prefix): Likewise.
63 (threebyte_0x38_uses_DATA_prefix): Likewise.
64 (threebyte_0x38_uses_REPNZ_prefix): Likewise.
65 (threebyte_0x38_uses_REPZ_prefix): Likewise.
66 (threebyte_0x3a_uses_DATA_prefix): Likewise.
67 (threebyte_0x3a_uses_REPNZ_prefix): Likewise.
68 (threebyte_0x3a_uses_REPZ_prefix): Likewise.
69 (print_insn): Updated checking usages of DATA/REPNZ/REPZ
70 prefixes.
71
a9353e60
AM		 722006-11-06 Troy Rollo <troy@corvu.com.au>
73
74 * ppc-opc.c: Restore COM to mfcr wrongly removed 2003-07-04.
75
06d2da93
NC		 762006-11-01 Mei Ligang <ligang@sunnorth.com.cn>
77
78 * score-opc.h (score_opcodes): Delete modifier '0x'.
79
2087ad84
PB		 802006-10-30 Paul Brook <paul@codesourcery.com>
81
82 * arm-dis.c (last_is_thumb, last_mapping_sym, last_mapping_addr): New.
83 (get_sym_code_type): New function.
84 (print_insn): Search for mapping symbols.
85
b138abaa
NC		 862006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
87
88 * score-dis.c (print_insn): Correct the error code to print
89 correct PCE instruction disassembly.
90
702f0fb4
PB		 912006-10-26 Ben Elliston <bje@au.ibm.com>
92 Anton Blanchard <anton@samba.org>
93 Peter Bergner <bergner@vnet.ibm.com>
94
95 * ppc-opc.c (A_L, DCM, DGM, TE, RMC, R, SP, S, SH16, XRT_L, EH,
96 AFRALFRC_MASK, Z, ZRC, Z_MASK, XLRT_MASK, XEH_MASK): Define.
97 (POWER6): Define.
98 (powerpc_opcodes): Extend "lwarx", "ldarx", "dcbf", "fres", "fres.",
99 "frsqrtes", "frsqrtes." "fre", "fre.", "frsqrte" and "frsqrte.".
100 Add "doze", "nap", "sleep", "rvwinkle", "dcbfl", "prtyw", "prtyd",
101 "mfcfar", "cmpb", "lfdpx", "stfdpx", "mtcfar", "mffgpr", "mftgpr",
102 "lwzcix", "lhzcix", "lbzcix", "ldcix", "lfiwax", "stwcix", "sthcix",
103 "stbcix", "stdcix", "lfdp", "dadd", "dadd.", "dqua", "dqua.", "dmul",
104 "dmul.", "drrnd", "drrnd.", "dscli", "dscli.", "dquai", "dquai.",
105 "dscri", "dscri.", "drintx", "drintx.", "dcmpo", "dtstex", "dtstdc",
106 "dtstdg", "dtstsf", "drintn", "drintn.", "dctdp", "dctdp.", "dctfix",
107 "dctfix.", "ddedpd", "ddedpd.", "dxex", "dxex.", "dsub", "dsub.",
108 "ddiv", "ddiv.", "dcmpu", "drsp", "drsp.", "dcffix", "dcffix.",
109 "denbcd", "denbcd.", "diex", "diex.", "stfdp", "daddq", "daddq.",
110 "dquaq", "dquaq.", "fcpsgn", "fcpsgn.", "dmulq", "dmulq.",
111 "drrndq", "drrndq.", "dscliq", "dscliq.", "dquaiq", "dquaiq.",
112 "dscriq", "dscriq.", "drintxq", "drintxq.", "dcmpoq", "dtstexq",
113 "dtstdcq", "dtstdgq", "dtstsfq", "drintnq", "drintnq.",
114 "dctqpq", "dctqpq.", "dctfixq", "dctfixq.", "ddedpdq", "ddedpdq.",
115 "dxexq", "dxexq.", "dsubq", "dsubq.", "ddivq", "ddivq.", "dcmpuq",
116 "drdpq", "drdpq.", "dcffixq", "dcffixq.", "denbcdq", "denbcdq.",
117 "diexq" and "diexq." opcodes.
118
a3202ebb
DJ		 1192006-10-26 Daniel Jacobowitz <dan@codesourcery.com>
120
121 * h8300-dis.c (bfd_h8_disassemble): Add missing consts.
122
e9f53129
AM		 1232006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
124 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
125 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
126 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
127 Alan Modra <amodra@bigpond.net.au>
128
129 * spu-dis.c: New file.
130 * spu-opc.c: New file.
131 * configure.in: Add SPU support.
132 * disassemble.c: Likewise.
133 * Makefile.am: Likewise. Run "make dep-am".
134 * Makefile.in: Regenerate.
135 * configure: Regenerate.
136 * po/POTFILES.in: Regenerate.
137
ede602d7
AM		 1382006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
139
140 * ppc-opc.c (CELL): New define.
141 (powerpc_opcodes): Enable hrfid for Cell. Add ldbrx and stdbrx,
142 cell specific instructions. Add {st,l}x{r,l}{,l} cell specific
143 VMX instructions.
144 * ppc-dis.c (powerpc_dialect): Handle cell.
145
7918206c
MM		 1462006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
147
148 * i386-dis.c (dis386): Add support for the change in POPCNT opcode in
149 amdfam10 architecture.
150 (PREGRP37): NEW.
151 (print_insn): Disallow REP prefix for POPCNT.
152
f3b8f628
AS		 1532006-10-20 Andrew Stubbs <andrew.stubbs@st.com>
154
155 * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB
156 duplicating it.
157
d3f1a427
DB		 1582006-10-18 Dave Brolley <brolley@redhat.com>
159
160 * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch.
161 * configure: Regenerated.
162
3bb0c887
AM		 1632006-09-29 Alan Modra <amodra@bigpond.net.au>
164
165 * po/POTFILES.in: Regenerate.
166
2d447fca
JM		 1672006-09-26 Mark Shinwell <shinwell@codesourcery.com>
168 Joseph Myers <joseph@codesourcery.com>
169 Ian Lance Taylor <ian@wasabisystems.com>
170 Ben Elliston <bje@wasabisystems.com>
171
172 * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
173 only be used with the default multiply-add operation, so if N is
174 set, don't bother printing X. Add new iwmmxt instructions.
175 (IWMMXT_INSN_COUNT): Update.
176 (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
177 with a 'c' suffix.
178 (print_insn_coprocessor): Check for iWMMXt2. Handle format
179 specifiers 'r', 'i'.
180
c4b5fff9
L		 1812006-09-24 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
182
183 PR binutils/3100
184 * i386-dis.c (prefix_user_table): Fix the second operand of
185 maskmovdqu instruction to allow only %xmm register instead of
186 both %xmm register and memory.
187
539e75ad
L		 1882006-09-23 H.J. Lu <hongjiu.lu@intel.com>
189
190 PR binutils/3235
191 * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
192 address size prefix.
193
1c0d3aa6
NC		 1942006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
195
196 * score-dis.c: New file.
197 * score-opc.h: New file.
198 * Makefile.am: Add Score files.
199 * Makefile.in: Regenerate.
200 * configure.in: Add support for Score target.
201 * configure: Regenerate.
202 * disassemble.c: Add support for Score target.
203
0112cd26
NC		 2042006-09-16 Nick Clifton <nickc@redhat.com>
205 Pedro Alves <pedro_alves@portugalmail.pt>
206
207 * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
208 macros defined in bfd.h.
209 * cris-dis.c: Likewise.
210 * h8300-dis.c: Likewise.
211 * i386-dis.c: Likewise.
212 * ia64-gen.c: Likewise.
213 * mips-dis: Likewise.
214
428e3f1f
PB		 2152006-09-04 Paul Brook <paul@codesourcery.com>
216
217 * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
218
96fbad73
L		 2192006-08-23 H.J. Lu <hongjiu.lu@intel.com>
220
221 * i386-dis.c (three_byte_table): Expand to 256 elements.
222
2232006-08-04 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
4d9567e0 224
a7a8d8e5 225 PR binutils/3000
4d9567e0
MM		 226 * i386-dis.c (MXC,EMC): Define.
227 (OP_MXC): New function to handle cvt* (convert instructions) between
228 %xmm and %mm register correctly.
229 (OP_EMC): ditto.
96fbad73 230 (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
4d9567e0
MM		 231 instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
232 with EMC/MXC.
233
777b13b9
RS		 2342006-07-29 Richard Sandiford <richard@codesourcery.com>
235
236 * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
237 "fdaddl" entry.
238
401a54cf
PB		 2392006-07-19 Paul Brook <paul@codesourcery.com>
240
241 * armd-dis.c (arm_opcodes): Fix rbit opcode.
242
2b516b72
L		 2432006-07-18 H.J. Lu <hongjiu.lu@intel.com>
244
245 * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
246 "sldt", "str" and "smsw".
247
10505f38
L		 2482006-07-15 H.J. Lu <hongjiu.lu@intel.com>
249
250 PR binutils/2829
251 * i386-dis.c (GRP11_C6): NEW.
252 (GRP11_C7): Likewise.
253 (GRP12): Updated.
254 (GRP13): Likewise.
255 (GRP14): Likewise.
256 (GRP15): Likewise.
257 (GRP16): Likewise.
258 (GRPAMD): Likewise.
259 (GRPPADLCK1): Likewise.
260 (GRPPADLCK2): Likewise.
261 (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
262 respectively.
263 (grps): Add entries for GRP11_C6 and GRP11_C7.
264
050dfa73
MM		 2652006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
266 Michael Meissner <michael.meissner@amd.com>
267
268 * i386-dis.c (dis386): Add support for 4 operand instructions. Add
269 support for amdfam10 SSE4a/ABM instructions. Modify all
270 initializer macros to have additional arguments. Disallow REP
271 prefix for non-string instructions.
272 (print_insn): Ditto.
273
e8b42ce4
JB		 2742006-07-05 Julian Brown <julian@codesourcery.com>
275
276 * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
277
15965411
L		 2782006-06-12 H.J. Lu <hongjiu.lu@intel.com>
279
280 * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
281 (twobyte_has_modrm): Set 1 for 0x1f.
282
46e883c5
L		 2832006-06-12 H.J. Lu <hongjiu.lu@intel.com>
284
285 * i386-dis.c (NOP_Fixup): Removed.
286 (NOP_Fixup1): New.
287 (NOP_Fixup2): Likewise.
288 (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
289
4e9d3b81
JB		 2902006-06-12 Julian Brown <julian@codesourcery.com>
291
292 * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
293 on 64-bit hosts.
294
b3882df9
L		 2952006-06-10 H.J. Lu <hongjiu.lu@intel.com>
296
297 * i386.c (GRP10): Renamed to ...
298 (GRP12): This.
299 (GRP11): Renamed to ...
300 (GRP13): This.
301 (GRP12): Renamed to ...
302 (GRP14): This.
303 (GRP13): Renamed to ...
304 (GRP15): This.
305 (GRP14): Renamed to ...
306 (GRP16): This.
307 (dis386_twobyte): Updated.
308 (grps): Likewise.
309
5f4df3dd
NC		 3102006-06-09 Nick Clifton <nickc@redhat.com>
311
312 * po/fi.po: Updated Finnish translation.
313
6648b7cf
JM		 3142006-06-07 Joseph S. Myers <joseph@codesourcery.com>
315
316 * po/Make-in (pdf, ps): New dummy targets.
317
c22aaad1
PB		 3182006-06-06 Paul Brook <paul@codesourcery.com>
319
320 * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
321 instructions.
322 (neon_opcodes): Add conditional execution specifiers.
323 (thumb_opcodes): Ditto.
324 (thumb32_opcodes): Ditto.
325 (arm_conditional): Change 0xe to "al" and add "" to end.
326 (ifthen_state, ifthen_next_state, ifthen_address): New.
327 (IFTHEN_COND): Define.
328 (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
329 (print_insn_arm): Change %c to use new values of arm_conditional.
330 (print_insn_thumb16): Print thumb conditions. Add %I.
331 (print_insn_thumb32): Print thumb conditions.
332 (find_ifthen_state): New function.
333 (print_insn): Track IT block state.
334
9622b051
AM		 3352006-06-06 Ben Elliston <bje@au.ibm.com>
336 Anton Blanchard <anton@samba.org>
337 Peter Bergner <bergner@vnet.ibm.com>
338
339 * ppc-dis.c (powerpc_dialect): Handle power6 option.
340 (print_ppc_disassembler_options): Mention power6.
341
65263ce3
TS		 3422006-06-06 Thiemo Seufer <ths@mips.com>
343 Chao-ying Fu <fu@mips.com>
344
345 * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
346 * mips-opc.c: Add DSP64 instructions.
347
92ce91bb
AM		 3482006-06-06 Alan Modra <amodra@bigpond.net.au>
349
350 * m68hc11-dis.c (print_insn): Warning fix.
351
4cfe2c59
DJ		 3522006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
353
354 * po/Make-in (top_builddir): Define.
355
7ff1a5b5
AM		 3562006-06-05 Alan Modra <amodra@bigpond.net.au>
357
358 * Makefile.am: Run "make dep-am".
359 * Makefile.in: Regenerate.
360 * config.in: Regenerate.
361
20e95c23
DJ		 3622006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
363
364 * Makefile.am (INCLUDES): Use @INCINTL@.
365 * acinclude.m4: Include new gettext macros.
366 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
367 Remove local code for po/Makefile.
368 * Makefile.in, aclocal.m4, configure: Regenerated.
369
eebf07fb
NC		 3702006-05-30 Nick Clifton <nickc@redhat.com>
371
372 * po/es.po: Updated Spanish translation.
373
a596001e
RS		 3742006-05-25 Richard Sandiford <richard@codesourcery.com>
375
376 * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
377 and fmovem entries. Put register list entries before immediate
378 mask entries. Use "l" rather than "L" in the fmovem entries.
379 * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
380 out from INFO.
381 (m68k_scan_mask): New function, split out from...
382 (print_insn_m68k): ...here. If no architecture has been set,
383 first try printing an m680x0 instruction, then try a Coldfire one.
384
4a4d496a
NC		 3852006-05-24 Nick Clifton <nickc@redhat.com>
386
387 * po/ga.po: Updated Irish translation.
388
a854efa3
NC		 3892006-05-22 Nick Clifton <nickc@redhat.com>
390
391 * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
392
0bd79061
NC		 3932006-05-22 Nick Clifton <nickc@redhat.com>
394
395 * po/nl.po: Updated translation.
396
00988f49
AM		 3972006-05-18 Alan Modra <amodra@bigpond.net.au>
398
399 * avr-dis.c: Formatting fix.
400
9b3f89ee
TS		 4012006-05-14 Thiemo Seufer <ths@mips.com>
402
403 * mips16-opc.c (I1, I32, I64): New shortcut defines.
404 (mips16_opcodes): Change membership of instructions to their
405 lowest baseline ISA.
406
cb6d3433
L		 4072006-05-09 H.J. Lu <hongjiu.lu@intel.com>
408
409 * i386-dis.c (grps): Update sgdt/sidt for 64bit.
410
1f3c39b9
JB		 4112006-05-05 Julian Brown <julian@codesourcery.com>
412
413 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
414 vldm/vstm.
415
d43b4baf
TS		 4162006-05-05 Thiemo Seufer <ths@mips.com>
417 David Ung <davidu@mips.com>
418
419 * mips-opc.c: Add macro for cache instruction.
420
39a7806d
TS		 4212006-05-04 Thiemo Seufer <ths@mips.com>
422 Nigel Stephens <nigel@mips.com>
423 David Ung <davidu@mips.com>
424
425 * mips-dis.c (mips_arch_choices): Add smartmips instruction
426 decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
427 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
428 MIPS64R2.
429 * mips-opc.c: fix random typos in comments.
430 (INSN_SMARTMIPS): New defines.
431 (mips_builtin_opcodes): Add paired single support for MIPS32R2.
432 Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
433 flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
434 FP_S and FP_D flags to denote single and double register
435 accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
436 Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
437 for MIPS32R2. Add SmartMIPS instructions. Add two-argument
438 variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
439 release 2 ISAs.
440 * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
441
104b4fab
TS		 4422006-05-03 Thiemo Seufer <ths@mips.com>
443
444 * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
445
022fac6d
TS		 4462006-05-02 Thiemo Seufer <ths@mips.com>
447 Nigel Stephens <nigel@mips.com>
448 David Ung <davidu@mips.com>
449
450 * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
451 (print_mips16_insn_arg): Force mips16 to odd addresses.
452
9bcd4f99
TS		 4532006-04-30 Thiemo Seufer <ths@mips.com>
454 David Ung <davidu@mips.com>
455
456 * mips-opc.c (mips_builtin_opcodes): Add udi instructions
457 "udi0" to "udi15".
458 * mips-dis.c (print_insn_args): Adds udi argument handling.
459
f095b97b
JW		 4602006-04-28 James E Wilson <wilson@specifix.com>
461
462 * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
463 error message.
464
59c455b3
TS		 4652006-04-28 Thiemo Seufer <ths@mips.com>
466 David Ung <davidu@mips.com>
bdb09db1 467 Nigel Stephens <nigel@mips.com>
59c455b3
TS		 468
469 * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
470 names.
471
cc0ca239 4722006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1 473 Nigel Stephens <nigel@mips.com>
cc0ca239
TS		 474 David Ung <davidu@mips.com>
475
476 * mips-dis.c (print_insn_args): Add mips_opcode argument.
477 (print_insn_mips): Adjust print_insn_args call.
478
0d09bfe6 4792006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1 480 Nigel Stephens <nigel@mips.com>
0d09bfe6
TS		 481
482 * mips-dis.c (print_insn_args): Print $fcc only for FP
483 instructions, use $cc elsewise.
484
654c225a 4852006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1 486 Nigel Stephens <nigel@mips.com>
654c225a
TS		 487
488 * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
489 Map MIPS16 registers to O32 names.
490 (print_mips16_insn_arg): Use mips16_reg_names.
491
0dbde4cf
JB		 4922006-04-26 Julian Brown <julian@codesourcery.com>
493
494 * arm-dis.c (print_insn_neon): Disassemble floating-point constant
495 VMOV.
496
16980d0b
JB		 4972006-04-26 Nathan Sidwell <nathan@codesourcery.com>
498 Julian Brown <julian@codesourcery.com>
499
500 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
501 %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
502 Add unified load/store instruction names.
503 (neon_opcode_table): New.
504 (arm_opcodes): Expand meaning of %<bitfield>['`?].
505 (arm_decode_bitfield): New.
506 (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
507 Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
508 (print_insn_neon): New.
509 (print_insn_arm): Adjust print_insn_coprocessor call. Call
510 print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
511 (print_insn_thumb32): Likewise.
512
ec3fcc56
AM		 5132006-04-19 Alan Modra <amodra@bigpond.net.au>
514
515 * Makefile.am: Run "make dep-am".
516 * Makefile.in: Regenerate.
517
241a6c40
AM		 5182006-04-19 Alan Modra <amodra@bigpond.net.au>
519
7c6646cd
AM		 520 * avr-dis.c (avr_operand): Warning fix.
521
241a6c40
AM		 522 * configure: Regenerate.
523
e7403566
DJ		 5242006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
525
526 * po/POTFILES.in: Regenerated.
527
52f16a0e
NC		 5282006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
529
530 PR binutils/2454
531 * avr-dis.c (avr_operand): Arrange for a comment to appear before
532 the symolic form of an address, so that the output of objdump -d
533 can be reassembled.
534
e78efa90
DD		 5352006-04-10 DJ Delorie <dj@redhat.com>
536
537 * m32c-asm.c: Regenerate.
538
108a6f8e
CD		 5392006-04-06 Carlos O'Donell <carlos@codesourcery.com>
540
541 * Makefile.am: Add install-html target.
542 * Makefile.in: Regenerate.
543
a135cb2c
NC		 5442006-04-06 Nick Clifton <nickc@redhat.com>
545
546 * po/vi/po: Updated Vietnamese translation.
547
47426b41
AM		 5482006-03-31 Paul Koning <ni1d@arrl.net>
549
550 * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
551
331f1cbe
BS		 5522006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
553
554 * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
555 logic to identify halfword shifts.
556
c16d2bf0
PB		 5572006-03-16 Paul Brook <paul@codesourcery.com>
558
559 * arm-dis.c (arm_opcodes): Rename swi to svc.
560 (thumb_opcodes): Ditto.
561
5348b81e
DD		 5622006-03-13 DJ Delorie <dj@redhat.com>
563
5398310a
DD		 564 * m32c-asm.c: Regenerate.
565 * m32c-desc.c: Likewise.
566 * m32c-desc.h: Likewise.
567 * m32c-dis.c: Likewise.
568 * m32c-ibld.c: Likewise.
5348b81e
DD		 569 * m32c-opc.c: Likewise.
570 * m32c-opc.h: Likewise.
571
253d272c
DD		 5722006-03-10 DJ Delorie <dj@redhat.com>
573
574 * m32c-desc.c: Regenerate with mul.l, mulu.l.
575 * m32c-opc.c: Likewise.
576 * m32c-opc.h: Likewise.
577
578
f530741d
NC		 5792006-03-09 Nick Clifton <nickc@redhat.com>
580
581 * po/sv.po: Updated Swedish translation.
582
35c52694
L		 5832006-03-07 H.J. Lu <hongjiu.lu@intel.com>
584
585 PR binutils/2428
586 * i386-dis.c (REP_Fixup): New function.
587 (AL): Remove duplicate.
588 (Xbr): New.
589 (Xvr): Likewise.
590 (Ybr): Likewise.
591 (Yvr): Likewise.
592 (indirDXr): Likewise.
593 (ALr): Likewise.
594 (eAXr): Likewise.
595 (dis386): Updated entries of ins, outs, movs, lods and stos.
596
ed963e2d
NC		 5972006-03-05 Nick Clifton <nickc@redhat.com>
598
599 * cgen-ibld.in (insert_normal): Cope with attempts to insert a
600 signed 32-bit value into an unsigned 32-bit field when the host is
601 a 64-bit machine.
602 * fr30-ibld.c: Regenerate.
603 * frv-ibld.c: Regenerate.
604 * ip2k-ibld.c: Regenerate.
605 * iq2000-asm.c: Regenerate.
606 * iq2000-ibld.c: Regenerate.
607 * m32c-ibld.c: Regenerate.
608 * m32r-ibld.c: Regenerate.
609 * openrisc-ibld.c: Regenerate.
610 * xc16x-ibld.c: Regenerate.
611 * xstormy16-ibld.c: Regenerate.
612
c7d41dc5
NC		 6132006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
614
615 * xc16x-asm.c: Regenerate.
616 * xc16x-dis.c: Regenerate.
c7d41dc5 617
f7d9e5c3
CD		 6182006-02-27 Carlos O'Donell <carlos@codesourcery.com>
619
620 * po/Make-in: Add html target.
621
331d2d0d
L		 6222006-02-27 H.J. Lu <hongjiu.lu@intel.com>
623
624 * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
625 Intel Merom New Instructions.
626 (THREE_BYTE_0): Likewise.
627 (THREE_BYTE_1): Likewise.
628 (three_byte_table): Likewise.
629 (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
630 THREE_BYTE_1 for entry 0x3a.
631 (twobyte_has_modrm): Updated.
632 (twobyte_uses_SSE_prefix): Likewise.
633 (print_insn): Handle 3-byte opcodes used by Intel Merom New
634 Instructions.
635
ff3f9d5b
DM		 6362006-02-24 David S. Miller <davem@sunset.davemloft.net>
637
638 * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
639 (v9_hpriv_reg_names): New table.
640 (print_insn_sparc): Allow values up to 16 for '?' and '!'.
641 New cases '$' and '%' for read/write hyperprivileged register.
642 * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
643 window handling and rdhpr/wrhpr instructions.
644
6772dd07
DD		 6452006-02-24 DJ Delorie <dj@redhat.com>
646
647 * m32c-desc.c: Regenerate with linker relaxation attributes.
648 * m32c-desc.h: Likewise.
649 * m32c-dis.c: Likewise.
650 * m32c-opc.c: Likewise.
651
62b3e311
PB		 6522006-02-24 Paul Brook <paul@codesourcery.com>
653
654 * arm-dis.c (arm_opcodes): Add V7 instructions.
655 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
656 (print_arm_address): New function.
657 (print_insn_arm): Use it. Add 'P' and 'U' cases.
658 (psr_name): New function.
659 (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
660
59cf82fe
L		 6612006-02-23 H.J. Lu <hongjiu.lu@intel.com>
662
663 * ia64-opc-i.c (bXc): New.
664 (mXc): Likewise.
665 (OpX2TaTbYaXcC): Likewise.
666 (TF). Likewise.
667 (TFCM). Likewise.
668 (ia64_opcodes_i): Add instructions for tf.
669
670 * ia64-opc.h (IMMU5b): New.
671
672 * ia64-asmtab.c: Regenerated.
673
19a7219f
L		 6742006-02-23 H.J. Lu <hongjiu.lu@intel.com>
675
676 * ia64-gen.c: Update copyright years.
677 * ia64-opc-b.c: Likewise.
678
7f3dfb9c
L		 6792006-02-22 H.J. Lu <hongjiu.lu@intel.com>
680
681 * ia64-gen.c (lookup_regindex): Handle ".vm".
682 (print_dependency_table): Handle '\"'.
683
684 * ia64-ic.tbl: Updated from SDM 2.2.
685 * ia64-raw.tbl: Likewise.
686 * ia64-waw.tbl: Likewise.
687 * ia64-asmtab.c: Regenerated.
688
689 * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
690
d70c5fc7
NC		 6912006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
692 Anil Paranjape <anilp1@kpitcummins.com>
693 Shilin Shakti <shilins@kpitcummins.com>
694
695 * xc16x-desc.h: New file
696 * xc16x-desc.c: New file
697 * xc16x-opc.h: New file
698 * xc16x-opc.c: New file
699 * xc16x-ibld.c: New file
700 * xc16x-asm.c: New file
701 * xc16x-dis.c: New file
702 * Makefile.am: Entries for xc16x
703 * Makefile.in: Regenerate
704 * cofigure.in: Add xc16x target information.
705 * configure: Regenerate.
706 * disassemble.c: Add xc16x target information.
707
a1cfb73e
L		 7082006-02-11 H.J. Lu <hongjiu.lu@intel.com>
709
710 * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
711 moves.
712
6dd5059a
L		 7132006-02-11 H.J. Lu <hongjiu.lu@intel.com>
714
715 * i386-dis.c ('Z'): Add a new macro.
716 (dis386_twobyte): Use "movZ" for control register moves.
717
8536c657
NC		 7182006-02-10 Nick Clifton <nickc@redhat.com>
719
720 * iq2000-asm.c: Regenerate.
721
266abb8f
NS		 7222006-02-07 Nathan Sidwell <nathan@codesourcery.com>
723
724 * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
725
f1a64f49
DU		 7262006-01-26 David Ung <davidu@mips.com>
727
728 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
729 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
730 floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
731 nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
732 rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
733
9e919b5f
AM		 7342006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
735
736 * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
737 ld_d_r, pref_xd_cb): Use signed char to hold data to be
738 disassembled.
739 * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
740 buffer overflows when disassembling instructions like
741 ld (ix+123),0x23
742 * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
743 operand, if the offset is negative.
744
c9021189
AM		 7452006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
746
747 * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
748 unsigned char to hold data to be disassembled.
749
d99b6465
AS		 7502006-01-17 Andreas Schwab <schwab@suse.de>
751
752 PR binutils/1486
753 * disassemble.c (disassemble_init_for_target): Set
754 disassembler_needs_relocs for bfd_arch_arm.
755
c2fe9327
PB		 7562006-01-16 Paul Brook <paul@codesourcery.com>
757
e88d958a 758 * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
c2fe9327
PB		 759 f?add?, and f?sub? instructions.
760
32fba81d
NC		 7612006-01-16 Nick Clifton <nickc@redhat.com>
762
763 * po/zh_CN.po: New Chinese (simplified) translation.
764 * configure.in (ALL_LINGUAS): Add "zh_CH".
765 * configure: Regenerate.
766
1b3a26b5
PB		 7672006-01-05 Paul Brook <paul@codesourcery.com>
768
769 * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
770
db313fa6
DD		 7712006-01-06 DJ Delorie <dj@redhat.com>
772
773 * m32c-desc.c: Regenerate.
774 * m32c-opc.c: Regenerate.
775 * m32c-opc.h: Regenerate.
776
54d46aca
DD		 7772006-01-03 DJ Delorie <dj@redhat.com>
778
779 * cgen-ibld.in (extract_normal): Avoid memory range errors.
780 * m32c-ibld.c: Regenerated.
781
e88d958a 782For older changes see ChangeLog-2005
252b5132
RH		 783\f
784Local Variables:
2f6d2f85
NC		 785mode: change-log
786left-margin: 8
787fill-column: 74
252b5132
RH		 788version-control: never
789End:
GDB Binutils - Deliverables
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