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Updated German translation.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
ec72cfe5
NC		 12005-03-21 Jan-Benedict Glaw <jbglaw@lug-owl.de>
2 Nick Clifton <nickc@redhat.com>
3
4 * vax-dis.c: (entry_addr): New varible: An array of user supplied
5 function entry mask addresses.
6 (entry_addr_occupied_slots): New variable: The number of occupied
7 elements in entry_addr.
8 (entry_addr_total_slots): New variable: The total number of
9 elements in entry_addr.
10 (parse_disassembler_options): New function. Fills in the entry_addr
11 array.
12 (free_entry_array): New function. Release the memory used by the
13 entry addr array. Suppressed because there is no way to call it.
14 (is_function_entry): Check if a given address is a function's
15 start address by looking at supplied entry mask addresses and
16 symbol information, if available.
17 (print_insn_vax): Use parse_disassembler_options and is_function_entry.
18
85064c79
L		 192005-03-23 H.J. Lu <hongjiu.lu@intel.com>
20
21 * cris-dis.c (print_with_operands): Use ~31L for long instead
22 of ~31.
23
de7141c7
L		 242005-03-20 H.J. Lu <hongjiu.lu@intel.com>
25
26 * mmix-opc.c (O): Revert the last change.
27 (Z): Likewise.
28
e493ab45
L		 292005-03-19 H.J. Lu <hongjiu.lu@intel.com>
30
31 * mmix-opc.c (O): Use 24UL instead of 24 for unsigned long.
32 (Z): Likewise.
33
d8d7c459
HPN		 342005-03-19 Hans-Peter Nilsson <hp@bitrange.com>
35
36 * mmix-opc.c (O, Z): Force expression as unsigned long.
37
ebdb0383
NC		 382005-03-18 Nick Clifton <nickc@redhat.com>
39
40 * ip2k-asm.c: Regenerate.
41 * op/opcodes.pot: Regenerate.
42
1ad12f97
NC		 432005-03-16 Nick Clifton <nickc@redhat.com>
44 Ben Elliston <bje@au.ibm.com>
45
569acd2c 46 * configure.in (werror): New switch: Add -Werror to the
1ad12f97 47 compiler command line. Enabled by default. Disable via
569acd2c 48 --disable-werror.
1ad12f97
NC		 49 * configure: Regenerate.
50
4eb30afc
AM		 512005-03-16 Alan Modra <amodra@bigpond.net.au>
52
53 * ppc-dis.c (powerpc_dialect): Don't set PPC_OPCODE_ALTIVEC when
54 BOOKE.
55
ea8409f7
AM		 562005-03-15 Alan Modra <amodra@bigpond.net.au>
57
729ae8d2
AM		 58 * po/es.po: Commit new Spanish translation.
59
ea8409f7
AM		 60 * po/fr.po: Commit new French translation.
61
4f495e61
NC		 622005-03-14 Jan-Benedict Glaw <jbglaw@lug-owl.de>
63
64 * vax-dis.c: Fix spelling error
65 (print_insn_vax): Use ".word 0x0012 # Entry mask: r1 r2 >" instead
66 of just "Entry mask: < r1 ... >"
67
0a003adc
ZW		 682005-03-12 Zack Weinberg <zack@codesourcery.com>
69
70 * arm-dis.c (arm_opcodes): Document %E and %V.
71 Add entries for v6T2 ARM instructions:
72 bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
73 (print_insn_arm): Add support for %E and %V.
885fc257 74 (thumb_opcodes): Add ARMv6K instructions nop, sev, wfe, wfi, yield.
0a003adc 75
da99ee72
AM		 762005-03-10 Jeff Baker <jbaker@qnx.com>
77 Alan Modra <amodra@bigpond.net.au>
78
79 * ppc-opc.c (insert_sprg, extract_sprg): New Functions.
80 (powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
81 (SPRG_MASK): Delete.
82 (XSPRG_MASK): Mask off extra bits now part of sprg field.
0a003adc 83 (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
da99ee72
AM		 84 mfsprg4..7 after msprg and consolidate.
85
220abb21
AM		 862005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
87
88 * vax-dis.c (entry_mask_bit): New array.
89 (print_insn_vax): Decode function entry mask.
90
0e06657a
AH		 912005-03-07 Aldy Hernandez <aldyh@redhat.com>
92
93 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
94
06647dfd
AM		 952005-03-05 Alan Modra <amodra@bigpond.net.au>
96
97 * po/opcodes.pot: Regenerate.
98
82b829a7
RR		 992005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
100
220abb21 101 * arc-dis.c (a4_decoding_class): New enum.
06647dfd
AM		 102 (dsmOneArcInst): Use the enum values for the decoding class.
103 Remove redundant case in the switch for decodingClass value 11.
82b829a7 104
c4a530c5
JB		 1052005-03-02 Jan Beulich <jbeulich@novell.com>
106
107 * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
108 accesses.
109 (OP_C): Consider lock prefix in non-64-bit modes.
110
47d8304e
AM		 1112005-02-24 Alan Modra <amodra@bigpond.net.au>
112
113 * cris-dis.c (format_hex): Remove ineffective warning fix.
114 * crx-dis.c (make_instruction): Warning fix.
115 * frv-asm.c: Regenerate.
116
ec36c4a4
NC		 1172005-02-23 Nick Clifton <nickc@redhat.com>
118
33b71eeb
NC		 119 * cgen-dis.in: Use bfd_byte for buffers that are passed to
120 read_memory.
06647dfd 121
33b71eeb 122 * ia64-opc.c (locate_opcode_ent): Initialise opval array.
06647dfd 123
ec36c4a4
NC		 124 * crx-dis.c (make_instruction): Move argument structure into inner
125 scope and ensure that all of its fields are initialised before
126 they are used.
127
33b71eeb
NC		 128 * fr30-asm.c: Regenerate.
129 * fr30-dis.c: Regenerate.
130 * frv-asm.c: Regenerate.
131 * frv-dis.c: Regenerate.
132 * ip2k-asm.c: Regenerate.
133 * ip2k-dis.c: Regenerate.
134 * iq2000-asm.c: Regenerate.
135 * iq2000-dis.c: Regenerate.
136 * m32r-asm.c: Regenerate.
137 * m32r-dis.c: Regenerate.
138 * openrisc-asm.c: Regenerate.
139 * openrisc-dis.c: Regenerate.
140 * xstormy16-asm.c: Regenerate.
141 * xstormy16-dis.c: Regenerate.
142
53c9ebc5
AM		 1432005-02-22 Alan Modra <amodra@bigpond.net.au>
144
145 * arc-ext.c: Warning fixes.
146 * arc-ext.h: Likewise.
147 * cgen-opc.c: Likewise.
148 * ia64-gen.c: Likewise.
149 * maxq-dis.c: Likewise.
150 * ns32k-dis.c: Likewise.
151 * w65-dis.c: Likewise.
152 * ia64-asmtab.c: Regenerate.
153
610ad19b
AM		 1542005-02-22 Alan Modra <amodra@bigpond.net.au>
155
156 * fr30-desc.c: Regenerate.
157 * fr30-desc.h: Regenerate.
158 * fr30-opc.c: Regenerate.
159 * fr30-opc.h: Regenerate.
160 * frv-desc.c: Regenerate.
161 * frv-desc.h: Regenerate.
162 * frv-opc.c: Regenerate.
163 * frv-opc.h: Regenerate.
164 * ip2k-desc.c: Regenerate.
165 * ip2k-desc.h: Regenerate.
166 * ip2k-opc.c: Regenerate.
167 * ip2k-opc.h: Regenerate.
168 * iq2000-desc.c: Regenerate.
169 * iq2000-desc.h: Regenerate.
170 * iq2000-opc.c: Regenerate.
171 * iq2000-opc.h: Regenerate.
172 * m32r-desc.c: Regenerate.
173 * m32r-desc.h: Regenerate.
174 * m32r-opc.c: Regenerate.
175 * m32r-opc.h: Regenerate.
176 * m32r-opinst.c: Regenerate.
177 * openrisc-desc.c: Regenerate.
178 * openrisc-desc.h: Regenerate.
179 * openrisc-opc.c: Regenerate.
180 * openrisc-opc.h: Regenerate.
181 * xstormy16-desc.c: Regenerate.
182 * xstormy16-desc.h: Regenerate.
183 * xstormy16-opc.c: Regenerate.
184 * xstormy16-opc.h: Regenerate.
185
db9db6f2
AM		 1862005-02-21 Alan Modra <amodra@bigpond.net.au>
187
188 * Makefile.am: Run "make dep-am"
189 * Makefile.in: Regenerate.
190
bf143b25
NC		 1912005-02-15 Nick Clifton <nickc@redhat.com>
192
193 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
194 compile time warnings.
195 (print_keyword): Likewise.
196 (default_print_insn): Likewise.
197
198 * fr30-desc.c: Regenerated.
199 * fr30-desc.h: Regenerated.
200 * fr30-dis.c: Regenerated.
201 * fr30-opc.c: Regenerated.
202 * fr30-opc.h: Regenerated.
203 * frv-desc.c: Regenerated.
204 * frv-dis.c: Regenerated.
205 * frv-opc.c: Regenerated.
206 * ip2k-asm.c: Regenerated.
207 * ip2k-desc.c: Regenerated.
208 * ip2k-desc.h: Regenerated.
209 * ip2k-dis.c: Regenerated.
210 * ip2k-opc.c: Regenerated.
211 * ip2k-opc.h: Regenerated.
212 * iq2000-desc.c: Regenerated.
213 * iq2000-dis.c: Regenerated.
214 * iq2000-opc.c: Regenerated.
215 * m32r-asm.c: Regenerated.
216 * m32r-desc.c: Regenerated.
217 * m32r-desc.h: Regenerated.
218 * m32r-dis.c: Regenerated.
219 * m32r-opc.c: Regenerated.
220 * m32r-opc.h: Regenerated.
221 * m32r-opinst.c: Regenerated.
222 * openrisc-desc.c: Regenerated.
223 * openrisc-desc.h: Regenerated.
224 * openrisc-dis.c: Regenerated.
225 * openrisc-opc.c: Regenerated.
226 * openrisc-opc.h: Regenerated.
227 * xstormy16-desc.c: Regenerated.
228 * xstormy16-desc.h: Regenerated.
229 * xstormy16-dis.c: Regenerated.
230 * xstormy16-opc.c: Regenerated.
231 * xstormy16-opc.h: Regenerated.
232
d6098898
L		 2332005-02-14 H.J. Lu <hongjiu.lu@intel.com>
234
235 * dis-buf.c (perror_memory): Use sprintf_vma to print out
236 address.
237
5a84f3e0
NC		 2382005-02-11 Nick Clifton <nickc@redhat.com>
239
bc18c937
NC		 240 * iq2000-asm.c: Regenerate.
241
5a84f3e0
NC		 242 * frv-dis.c: Regenerate.
243
0a40490e
JB		 2442005-02-07 Jim Blandy <jimb@redhat.com>
245
246 * Makefile.am (CGEN): Load guile.scm before calling the main
247 application script.
248 * Makefile.in: Regenerated.
249 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
250 Simply pass the cgen-opc.scm path to ${cgen} as its first
251 argument; ${cgen} itself now contains the '-s', or whatever is
252 appropriate for the Scheme being used.
253
c46f8c51
AC		 2542005-01-31 Andrew Cagney <cagney@gnu.org>
255
256 * configure: Regenerate to track ../gettext.m4.
257
60b9a617
JB		 2582005-01-31 Jan Beulich <jbeulich@novell.com>
259
260 * ia64-gen.c (NELEMS): Define.
261 (shrink): Generate alias with missing second predicate register when
262 opcode has two outputs and these are both predicates.
263 * ia64-opc-i.c (FULL17): Define.
264 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
265 here to generate output template.
266 (TBITCM, TNATCM): Undefine after use.
267 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
268 first input. Add ld16 aliases without ar.csd as second output. Add
269 st16 aliases without ar.csd as second input. Add cmpxchg aliases
270 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
271 ar.ccv as third/fourth inputs. Consolidate through...
272 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
273 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
274 * ia64-asmtab.c: Regenerate.
275
a53bf506
AC		 2762005-01-27 Andrew Cagney <cagney@gnu.org>
277
278 * configure: Regenerate to track ../gettext.m4 change.
279
90219bd0
AO		 2802005-01-25 Alexandre Oliva <aoliva@redhat.com>
281
282 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
283 * frv-asm.c: Rebuilt.
284 * frv-desc.c: Rebuilt.
285 * frv-desc.h: Rebuilt.
286 * frv-dis.c: Rebuilt.
287 * frv-ibld.c: Rebuilt.
288 * frv-opc.c: Rebuilt.
289 * frv-opc.h: Rebuilt.
290
45181ed1
AC		 2912005-01-24 Andrew Cagney <cagney@gnu.org>
292
293 * configure: Regenerate, ../gettext.m4 was updated.
294
9e836e3d
FF		 2952005-01-21 Fred Fish <fnf@specifixinc.com>
296
297 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
298 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
299 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
300 * mips-dis.c: Ditto.
301
5e8cb021
AM		 3022005-01-20 Alan Modra <amodra@bigpond.net.au>
303
304 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
305
986e18a5
FF		 3062005-01-19 Fred Fish <fnf@specifixinc.com>
307
308 * mips-dis.c (no_aliases): New disassembly option flag.
309 (set_default_mips_dis_options): Init no_aliases to zero.
310 (parse_mips_dis_option): Handle no-aliases option.
311 (print_insn_mips): Ignore table entries that are aliases
312 if no_aliases is set.
313 (print_insn_mips16): Ditto.
314 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
315 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
316 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
317 * mips16-opc.c (mips16_opcodes): Ditto.
318
e38bc3b5
NC		 3192005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
320
321 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
322 (inheritance diagram): Add missing edge.
323 (arch_sh1_up): Rename arch_sh_up to match external name to make life
324 easier for the testsuite.
325 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
326 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
610ad19b 327 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
e38bc3b5
NC		 328 arch_sh2a_or_sh4_up child.
329 (sh_table): Do renaming as above.
330 Correct comment for ldc.l for gas testsuite to read.
331 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
332 Correct comments for movy.w and movy.l for gas testsuite to read.
333 Correct comments for fmov.d and fmov.s for gas testsuite to read.
334
9df48ba9
L		 3352005-01-12 H.J. Lu <hongjiu.lu@intel.com>
336
337 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
338
2033b4b9
L		 3392005-01-12 H.J. Lu <hongjiu.lu@intel.com>
340
341 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
342
0bcb06d2
AS		 3432005-01-10 Andreas Schwab <schwab@suse.de>
344
345 * disassemble.c (disassemble_init_for_target) <case
346 bfd_arch_ia64>: Set skip_zeroes to 16.
347 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
348
47add74d
TL		 3492004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
350
351 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
352
246f4c05
SS		 3532004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
354
355 * avr-dis.c: Prettyprint. Added printing of symbol names in all
356 memory references. Convert avr_operand() to C90 formatting.
357
0e1200e5
TL		 3582004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
359
360 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
361
89a649f7
TL		 3622004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
363
364 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
365 (no_op_insn): Initialize array with instructions that have no
366 operands.
367 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
368
6255809c
RE		 3692004-11-29 Richard Earnshaw <rearnsha@arm.com>
370
371 * arm-dis.c: Correct top-level comment.
372
2fbad815
RE		 3732004-11-27 Richard Earnshaw <rearnsha@arm.com>
374
375 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
376 architecuture defining the insn.
377 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 378 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
379 field.
2fbad815
RE		 380 Also include opcode/arm.h.
381 * Makefile.am (arm-dis.lo): Update dependency list.
382 * Makefile.in: Regenerate.
383
d81acc42
NC		 3842004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
385
386 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
387 reflect the change to the short immediate syntax.
388
ca4f2377
AM		 3892004-11-19 Alan Modra <amodra@bigpond.net.au>
390
5da8bf1b
AM		 391 * or32-opc.c (debug): Warning fix.
392 * po/POTFILES.in: Regenerate.
393
ca4f2377
AM		 394 * maxq-dis.c: Formatting.
395 (print_insn): Warning fix.
396
b7693d02
DJ		 3972004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
398
399 * arm-dis.c (WORD_ADDRESS): Define.
400 (print_insn): Use it. Correct big-endian end-of-section handling.
401
300dac7e
NC		 4022004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
403 Vineet Sharma <vineets@noida.hcltech.com>
404
405 * maxq-dis.c: New file.
406 * disassemble.c (ARCH_maxq): Define.
610ad19b 407 (disassembler): Add 'print_insn_maxq_little' for handling maxq
300dac7e
NC		 408 instructions..
409 * configure.in: Add case for bfd_maxq_arch.
410 * configure: Regenerate.
411 * Makefile.am: Add support for maxq-dis.c
412 * Makefile.in: Regenerate.
413 * aclocal.m4: Regenerate.
414
42048ee7
TL		 4152004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
416
417 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
418 mode.
419 * crx-dis.c: Likewise.
420
bd21e58e
HPN		 4212004-11-04 Hans-Peter Nilsson <hp@axis.com>
422
423 Generally, handle CRISv32.
424 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
425 (struct cris_disasm_data): New type.
426 (format_reg, format_hex, cris_constraint, print_flags)
427 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
428 callers changed.
429 (format_sup_reg, print_insn_crisv32_with_register_prefix)
430 (print_insn_crisv32_without_register_prefix)
431 (print_insn_crisv10_v32_with_register_prefix)
432 (print_insn_crisv10_v32_without_register_prefix)
433 (cris_parse_disassembler_options): New functions.
434 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
435 parameter. All callers changed.
436 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
437 failure.
438 (cris_constraint) <case 'Y', 'U'>: New cases.
439 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
440 for constraint 'n'.
441 (print_with_operands) <case 'Y'>: New case.
442 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
443 <case 'N', 'Y', 'Q'>: New cases.
444 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
445 (print_insn_cris_with_register_prefix)
446 (print_insn_cris_without_register_prefix): Call
447 cris_parse_disassembler_options.
448 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
449 for CRISv32 and the size of immediate operands. New v32-only
450 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
451 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
452 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
453 Change brp to be v3..v10.
454 (cris_support_regs): New vector.
455 (cris_opcodes): Update head comment. New format characters '[',
456 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
457 Add new opcodes for v32 and adjust existing opcodes to accommodate
458 differences to earlier variants.
459 (cris_cond15s): New vector.
460
9306ca4a
JB		 4612004-11-04 Jan Beulich <jbeulich@novell.com>
462
463 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
464 (indirEb): Remove.
465 (Mp): Use f_mode rather than none at all.
466 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
467 replaces what previously was x_mode; x_mode now means 128-bit SSE
468 operands.
469 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
470 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
471 pinsrw's second operand is Edqw.
472 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
473 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
474 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
475 mode when an operand size override is present or always suffixing.
476 More instructions will need to be added to this group.
477 (putop): Handle new macro chars 'C' (short/long suffix selector),
478 'I' (Intel mode override for following macro char), and 'J' (for
479 adding the 'l' prefix to far branches in AT&T mode). When an
480 alternative was specified in the template, honor macro character when
481 specified for Intel mode.
482 (OP_E): Handle new *_mode values. Correct pointer specifications for
483 memory operands. Consolidate output of index register.
484 (OP_G): Handle new *_mode values.
485 (OP_I): Handle const_1_mode.
486 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
487 respective opcode prefix bits have been consumed.
488 (OP_EM, OP_EX): Provide some default handling for generating pointer
489 specifications.
490
f39c96a9
TL		 4912004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
492
493 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
494 COP_INST macro.
495
812337be
TL		 4962004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
497
498 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
499 (getregliststring): Support HI/LO and user registers.
610ad19b 500 * crx-opc.c (crx_instruction): Update data structure according to the
812337be
TL		 501 rearrangement done in CRX opcode header file.
502 (crx_regtab): Likewise.
503 (crx_optab): Likewise.
610ad19b 504 (crx_instruction): Reorder load/stor instructions, remove unsupported
812337be
TL		 505 formats.
506 support new Co-Processor instruction 'cpi'.
507
4030fa5a
NC		 5082004-10-27 Nick Clifton <nickc@redhat.com>
509
510 * opcodes/iq2000-asm.c: Regenerate.
511 * opcodes/iq2000-desc.c: Regenerate.
512 * opcodes/iq2000-desc.h: Regenerate.
513 * opcodes/iq2000-dis.c: Regenerate.
514 * opcodes/iq2000-ibld.c: Regenerate.
515 * opcodes/iq2000-opc.c: Regenerate.
516 * opcodes/iq2000-opc.h: Regenerate.
517
fc3d45e8
TL		 5182004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
519
520 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
521 us4, us5 (respectively).
522 Remove unsupported 'popa' instruction.
523 Reverse operands order in store co-processor instructions.
524
3c55da70
AM		 5252004-10-15 Alan Modra <amodra@bigpond.net.au>
526
527 * Makefile.am: Run "make dep-am"
528 * Makefile.in: Regenerate.
529
7fa3d080
BW		 5302004-10-12 Bob Wilson <bob.wilson@acm.org>
531
532 * xtensa-dis.c: Use ISO C90 formatting.
533
e612bb4d
AM		 5342004-10-09 Alan Modra <amodra@bigpond.net.au>
535
536 * ppc-opc.c: Revert 2004-09-09 change.
537
43cd72b9
BW		 5382004-10-07 Bob Wilson <bob.wilson@acm.org>
539
540 * xtensa-dis.c (state_names): Delete.
541 (fetch_data): Use xtensa_isa_maxlength.
542 (print_xtensa_operand): Replace operand parameter with opcode/operand
543 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
544 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
545 instruction bundles. Use xmalloc instead of malloc.
546
bbac1f2a
NC		 5472004-10-07 David Gibson <david@gibson.dropbear.id.au>
548
549 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
550 initializers.
551
48c9f030
NC		 5522004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
553
554 * crx-opc.c (crx_instruction): Support Co-processor insns.
555 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
556 (getregliststring): Change function to use the above enum.
557 (print_arg): Handle CO-Processor insns.
558 (crx_cinvs): Add 'b' option to invalidate the branch-target
559 cache.
560
12c64a4e
AH		 5612004-10-06 Aldy Hernandez <aldyh@redhat.com>
562
563 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
564 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
565 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
566 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
567 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
568
14127cc4
NC		 5692004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
570
571 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
572 rather than add it.
573
0dd132b6
NC		 5742004-09-30 Paul Brook <paul@codesourcery.com>
575
576 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
577 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
578
3f85e526
L		 5792004-09-17 H.J. Lu <hongjiu.lu@intel.com>
580
581 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
582 (CONFIG_STATUS_DEPENDENCIES): New.
583 (Makefile): Removed.
584 (config.status): Likewise.
585 * Makefile.in: Regenerated.
586
8ae85421
AM		 5872004-09-17 Alan Modra <amodra@bigpond.net.au>
588
589 * Makefile.am: Run "make dep-am".
590 * Makefile.in: Regenerate.
591 * aclocal.m4: Regenerate.
592 * configure: Regenerate.
593 * po/POTFILES.in: Regenerate.
594 * po/opcodes.pot: Regenerate.
595
24443139
AS		 5962004-09-11 Andreas Schwab <schwab@suse.de>
597
598 * configure: Rebuild.
599
2a309db0
AM		 6002004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
601
602 * ppc-opc.c (L): Make this field not optional.
603
42851540
NC		 6042004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
605
606 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
607 Fix parameter to 'm[t|f]csr' insns.
608
979273e3
NN		 6092004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
610
611 * configure.in: Autoupdate to autoconf 2.59.
612 * aclocal.m4: Rebuild with aclocal 1.4p6.
613 * configure: Rebuild with autoconf 2.59.
614 * Makefile.in: Rebuild with automake 1.4p6 (picking up
615 bfd changes for autoconf 2.59 on the way).
616 * config.in: Rebuild with autoheader 2.59.
617
ac28a1cb
RS		 6182004-08-27 Richard Sandiford <rsandifo@redhat.com>
619
620 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
621
30d1c836
ML		 6222004-07-30 Michal Ludvig <mludvig@suse.cz>
623
624 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
625 (GRPPADLCK2): New define.
626 (twobyte_has_modrm): True for 0xA6.
627 (grps): GRPPADLCK2 for opcode 0xA6.
628
0b0ac059
AO		 6292004-07-29 Alexandre Oliva <aoliva@redhat.com>
630
631 Introduce SH2a support.
632 * sh-opc.h (arch_sh2a_base): Renumber.
633 (arch_sh2a_nofpu_base): Remove.
634 (arch_sh_base_mask): Adjust.
635 (arch_opann_mask): New.
636 (arch_sh2a, arch_sh2a_nofpu): Adjust.
637 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
638 (sh_table): Adjust whitespace.
639 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
640 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
641 instruction list throughout.
642 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
643 of arch_sh2a in instruction list throughout.
644 (arch_sh2e_up): Accomodate above changes.
645 (arch_sh2_up): Ditto.
646 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
647 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
648 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
649 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
650 * sh-opc.h (arch_sh2a_nofpu): New.
651 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
652 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
653 instruction.
654 2004-01-20 DJ Delorie <dj@redhat.com>
655 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
656 2003-12-29 DJ Delorie <dj@redhat.com>
657 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
658 sh_opcode_info, sh_table): Add sh2a support.
659 (arch_op32): New, to tag 32-bit opcodes.
660 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
661 2003-12-02 Michael Snyder <msnyder@redhat.com>
662 * sh-opc.h (arch_sh2a): Add.
663 * sh-dis.c (arch_sh2a): Handle.
664 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
665
670ec21d
NC		 6662004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
667
668 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
669
ed049af3
NC		 6702004-07-22 Nick Clifton <nickc@redhat.com>
671
672 PR/280
673 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
674 insns - this is done by objdump itself.
675 * h8500-dis.c (print_insn_h8500): Likewise.
676
20f0a1fc
NC		 6772004-07-21 Jan Beulich <jbeulich@novell.com>
678
679 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
680 regardless of address size prefix in effect.
681 (ptr_reg): Size or address registers does not depend on rex64, but
682 on the presence of an address size override.
683 (OP_MMX): Use rex.x only for xmm registers.
684 (OP_EM): Use rex.z only for xmm registers.
685
6f14957b
MR		 6862004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
687
688 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
689 move/branch operations to the bottom so that VR5400 multimedia
690 instructions take precedence in disassembly.
691
1586d91e
MR		 6922004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
693
694 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
695 ISA-specific "break" encoding.
696
982de27a
NC		 6972004-07-13 Elvis Chiang <elvisfb@gmail.com>
698
699 * arm-opc.h: Fix typo in comment.
700
4300ab10
AS		 7012004-07-11 Andreas Schwab <schwab@suse.de>
702
703 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
704
8577e690
AS		 7052004-07-09 Andreas Schwab <schwab@suse.de>
706
707 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
708
1fe1f39c
NC		 7092004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
710
711 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
712 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
713 (crx-dis.lo): New target.
714 (crx-opc.lo): Likewise.
715 * Makefile.in: Regenerate.
716 * configure.in: Handle bfd_crx_arch.
717 * configure: Regenerate.
718 * crx-dis.c: New file.
719 * crx-opc.c: New file.
720 * disassemble.c (ARCH_crx): Define.
721 (disassembler): Handle ARCH_crx.
722
7a33b495
JW		 7232004-06-29 James E Wilson <wilson@specifixinc.com>
724
725 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
726 * ia64-asmtab.c: Regnerate.
727
98e69875
AM		 7282004-06-28 Alan Modra <amodra@bigpond.net.au>
729
730 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
731 (extract_fxm): Don't test dialect.
732 (XFXFXM_MASK): Include the power4 bit.
733 (XFXM): Add p4 param.
734 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
735
a53b85e2
AO		 7362004-06-27 Alexandre Oliva <aoliva@redhat.com>
737
738 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
739 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
740
d0618d1c
AM		 7412004-06-26 Alan Modra <amodra@bigpond.net.au>
742
743 * ppc-opc.c (BH, XLBH_MASK): Define.
744 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
745
1d9f512f
AM		 7462004-06-24 Alan Modra <amodra@bigpond.net.au>
747
748 * i386-dis.c (x_mode): Comment.
749 (two_source_ops): File scope.
750 (float_mem): Correct fisttpll and fistpll.
751 (float_mem_mode): New table.
752 (dofloat): Use it.
753 (OP_E): Correct intel mode PTR output.
754 (ptr_reg): Use open_char and close_char.
755 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
756 operands. Set two_source_ops.
757
52886d70
AM		 7582004-06-15 Alan Modra <amodra@bigpond.net.au>
759
760 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
761 instead of _raw_size.
762
bad9ceea
JJ		 7632004-06-08 Jakub Jelinek <jakub@redhat.com>
764
765 * ia64-gen.c (in_iclass): Handle more postinc st
766 and ld variants.
767 * ia64-asmtab.c: Rebuilt.
768
0451f5df
MS		 7692004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
770
771 * s390-opc.txt: Correct architecture mask for some opcodes.
772 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
773 in the esa mode as well.
774
f6f9408f
JR		 7752004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
776
777 * sh-dis.c (target_arch): Make unsigned.
778 (print_insn_sh): Replace (most of) switch with a call to
779 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
780 * sh-opc.h: Redefine architecture flags values.
781 Add sh3-nommu architecture.
782 Reorganise <arch>_up macros so they make more visual sense.
783 (SH_MERGE_ARCH_SET): Define new macro.
784 (SH_VALID_BASE_ARCH_SET): Likewise.
785 (SH_VALID_MMU_ARCH_SET): Likewise.
786 (SH_VALID_CO_ARCH_SET): Likewise.
787 (SH_VALID_ARCH_SET): Likewise.
788 (SH_MERGE_ARCH_SET_VALID): Likewise.
789 (SH_ARCH_SET_HAS_FPU): Likewise.
790 (SH_ARCH_SET_HAS_DSP): Likewise.
791 (SH_ARCH_UNKNOWN_ARCH): Likewise.
792 (sh_get_arch_from_bfd_mach): Add prototype.
793 (sh_get_arch_up_from_bfd_mach): Likewise.
794 (sh_get_bfd_mach_from_arch_set): Likewise.
795 (sh_merge_bfd_arc): Likewise.
796
be8c092b
NC		 7972004-05-24 Peter Barada <peter@the-baradas.com>
798
799 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
610ad19b
AM		 800 into new match_insn_m68k function. Loop over canidate
801 matches and select first that completely matches.
be8c092b
NC		 802 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
803 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
610ad19b 804 to verify addressing for MAC/EMAC.
be8c092b
NC		 805 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
806 reigster halves since 'fpu' and 'spl' look misleading.
807 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
808 * m68k-opc.c: Rearragne mac/emac cases to use longest for
809 first, tighten up match masks.
810 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
811 'size' from special case code in print_insn_m68k to
812 determine decode size of insns.
813
a30e9cc4
AM		 8142004-05-19 Alan Modra <amodra@bigpond.net.au>
815
816 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
817 well as when -mpower4.
818
9598fbe5
NC		 8192004-05-13 Nick Clifton <nickc@redhat.com>
820
821 * po/fr.po: Updated French translation.
822
6b6e92f4
NC		 8232004-05-05 Peter Barada <peter@the-baradas.com>
824
825 * m68k-dis.c(print_insn_m68k): Add new chips, use core
826 variants in arch_mask. Only set m68881/68851 for 68k chips.
827 * m68k-op.c: Switch from ColdFire chips to core variants.
828
a404d431
AM		 8292004-05-05 Alan Modra <amodra@bigpond.net.au>
830
a30e9cc4 831 PR 147.
a404d431
AM		 832 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
833
f3806e43
BE		 8342004-04-29 Ben Elliston <bje@au.ibm.com>
835
520ceea4
BE		 836 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
837 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 838
1f1799d5
KK		 8392004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
840
841 * sh-dis.c (print_insn_sh): Print the value in constant pool
842 as a symbol if it looks like a symbol.
843
fd99574b
NC		 8442004-04-22 Peter Barada <peter@the-baradas.com>
845
846 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
847 appropriate ColdFire architectures.
848 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
849 mask addressing.
850 Add EMAC instructions, fix MAC instructions. Remove
851 macmw/macml/msacmw/msacml instructions since mask addressing now
852 supported.
853
b4781d44
JJ		 8542004-04-20 Jakub Jelinek <jakub@redhat.com>
855
856 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
857 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
858 suffix. Use fmov*x macros, create all 3 fpsize variants in one
859 macro. Adjust all users.
860
91809fda 8612004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
610ad19b 862
91809fda
NC		 863 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
864 separately.
865
f4453dfa
NC		 8662004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
867
868 * m32r-asm.c: Regenerate.
869
9b0de91a
SS		 8702004-03-29 Stan Shebs <shebs@apple.com>
871
872 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
873 used.
874
e20c0b3d
AM		 8752004-03-19 Alan Modra <amodra@bigpond.net.au>
876
877 * aclocal.m4: Regenerate.
878 * config.in: Regenerate.
879 * configure: Regenerate.
880 * po/POTFILES.in: Regenerate.
881 * po/opcodes.pot: Regenerate.
882
fdd12ef3
AM		 8832004-03-16 Alan Modra <amodra@bigpond.net.au>
884
885 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
886 PPC_OPERANDS_GPR_0.
887 * ppc-opc.c (RA0): Define.
888 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
889 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 890 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 891
2dc111b3 8922004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 893
894 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 895
7bfeee7b
AM		 8962004-03-15 Alan Modra <amodra@bigpond.net.au>
897
898 * sparc-dis.c (print_insn_sparc): Update getword prototype.
899
7ffdda93
ML		 9002004-03-12 Michal Ludvig <mludvig@suse.cz>
901
902 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 903 (grps): Delete GRPPLOCK entry.
7ffdda93 904
cc0ec051
AM		 9052004-03-12 Alan Modra <amodra@bigpond.net.au>
906
907 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
908 (M, Mp): Use OP_M.
909 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
910 (GRPPADLCK): Define.
911 (dis386): Use NOP_Fixup on "nop".
912 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
913 (twobyte_has_modrm): Set for 0xa7.
914 (padlock_table): Delete. Move to..
915 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
916 and clflush.
917 (print_insn): Revert PADLOCK_SPECIAL code.
918 (OP_E): Delete sfence, lfence, mfence checks.
919
4fd61dcb
JJ		 9202004-03-12 Jakub Jelinek <jakub@redhat.com>
921
922 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
923 (INVLPG_Fixup): New function.
924 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
925
0f10071e
ML		 9262004-03-12 Michal Ludvig <mludvig@suse.cz>
927
928 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
929 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
930 (padlock_table): New struct with PadLock instructions.
931 (print_insn): Handle PADLOCK_SPECIAL.
932
c02908d2
AM		 9332004-03-12 Alan Modra <amodra@bigpond.net.au>
934
935 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
936 (OP_E): Twiddle clflush to sfence here.
937
d5bb7600
NC		 9382004-03-08 Nick Clifton <nickc@redhat.com>
939
940 * po/de.po: Updated German translation.
941
ae51a426
JR		 9422003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
943
944 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
945 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
946 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
947 accordingly.
948
676a64f4
RS		 9492004-03-01 Richard Sandiford <rsandifo@redhat.com>
950
951 * frv-asm.c: Regenerate.
952 * frv-desc.c: Regenerate.
953 * frv-desc.h: Regenerate.
954 * frv-dis.c: Regenerate.
955 * frv-ibld.c: Regenerate.
956 * frv-opc.c: Regenerate.
957 * frv-opc.h: Regenerate.
958
c7a48b9a
RS		 9592004-03-01 Richard Sandiford <rsandifo@redhat.com>
960
961 * frv-desc.c, frv-opc.c: Regenerate.
962
8ae0baa2
RS		 9632004-03-01 Richard Sandiford <rsandifo@redhat.com>
964
965 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
966
ce11586c
JR		 9672004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
968
969 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
970 Also correct mistake in the comment.
971
6a5709a5
JR		 9722004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
973
974 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
975 ensure that double registers have even numbers.
976 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
977 that reserved instruction 0xfffd does not decode the same
978 as 0xfdfd (ftrv).
979 * sh-opc.h: Add REG_N_D nibble type and use it whereever
980 REG_N refers to a double register.
981 Add REG_N_B01 nibble type and use it instead of REG_NM
982 in ftrv.
983 Adjust the bit patterns in a few comments.
984
e5d2b64f 9852004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 986
987 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 988
1f04b05f
AH		 9892004-02-20 Aldy Hernandez <aldyh@redhat.com>
990
991 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
992
2f3b8700
AH		 9932004-02-20 Aldy Hernandez <aldyh@redhat.com>
994
995 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
996
f0b26da6 9972004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 998
999 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
1000 mtivor32, mtivor33, mtivor34.
f0b26da6 1001
23d59c56 10022004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1003
1004 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 1005
34920d91
NC		 10062004-02-10 Petko Manolov <petkan@nucleusys.com>
1007
1008 * arm-opc.h Maverick accumulator register opcode fixes.
1009
44d86481
BE		 10102004-02-13 Ben Elliston <bje@wasabisystems.com>
1011
1012 * m32r-dis.c: Regenerate.
1013
17707c23
MS		 10142004-01-27 Michael Snyder <msnyder@redhat.com>
1015
1016 * sh-opc.h (sh_table): "fsrra", not "fssra".
1017
fe3a9bc4
NC		 10182004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
1019
1020 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
1021 contraints.
1022
ff24f124
JJ		 10232004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
1024
1025 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
1026
a02a862a
AM		 10272004-01-19 Alan Modra <amodra@bigpond.net.au>
1028
1029 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
1030 1. Don't print scale factor on AT&T mode when index missing.
1031
d164ea7f
AO		 10322004-01-16 Alexandre Oliva <aoliva@redhat.com>
1033
1034 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
1035 when loaded into XR registers.
1036
cb10e79a
RS		 10372004-01-14 Richard Sandiford <rsandifo@redhat.com>
1038
1039 * frv-desc.h: Regenerate.
1040 * frv-desc.c: Regenerate.
1041 * frv-opc.c: Regenerate.
1042
f532f3fa
MS		 10432004-01-13 Michael Snyder <msnyder@redhat.com>
1044
1045 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
1046
e45d0630
PB		 10472004-01-09 Paul Brook <paul@codesourcery.com>
1048
1049 * arm-opc.h (arm_opcodes): Move generic mcrr after known
1050 specific opcodes.
1051
3ba7a1aa
DJ		 10522004-01-07 Daniel Jacobowitz <drow@mvista.com>
1053
1054 * Makefile.am (libopcodes_la_DEPENDENCIES)
1055 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
1056 comment about the problem.
1057 * Makefile.in: Regenerate.
1058
ba2d3f07
AO		 10592004-01-06 Alexandre Oliva <aoliva@redhat.com>
1060
1061 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
1062 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
1063 cut&paste errors in shifting/truncating numerical operands.
1064 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1065 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
1066 (parse_uslo16): Likewise.
1067 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
1068 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
1069 (parse_s12): Likewise.
1070 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1071 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
1072 (parse_uslo16): Likewise.
1073 (parse_uhi16): Parse gothi and gotfuncdeschi.
1074 (parse_d12): Parse got12 and gotfuncdesc12.
1075 (parse_s12): Likewise.
1076
3ab48931
NC		 10772004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
1078
1079 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
1080 instruction which looks similar to an 'rla' instruction.
a0bd404e 1081
c9e214e5 1082For older changes see ChangeLog-0203
252b5132
RH		 1083\f
1084Local Variables:
2f6d2f85
NC		 1085mode: change-log
1086left-margin: 8
1087fill-column: 74
252b5132
RH		 1088version-control: never
1089End:
GDB Binutils - Deliverables
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