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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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da99ee72
AM		 12005-03-10 Jeff Baker <jbaker@qnx.com>
2 Alan Modra <amodra@bigpond.net.au>
3
4 * ppc-opc.c (insert_sprg, extract_sprg): New Functions.
5 (powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
6 (SPRG_MASK): Delete.
7 (XSPRG_MASK): Mask off extra bits now part of sprg field.
8 (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
9 mfsprg4..7 after msprg and consolidate.
10
220abb21
AM		 112005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
12
13 * vax-dis.c (entry_mask_bit): New array.
14 (print_insn_vax): Decode function entry mask.
15
0e06657a
AH		 162005-03-07 Aldy Hernandez <aldyh@redhat.com>
17
18 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
19
06647dfd
AM		 202005-03-05 Alan Modra <amodra@bigpond.net.au>
21
22 * po/opcodes.pot: Regenerate.
23
82b829a7
RR		 242005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
25
220abb21 26 * arc-dis.c (a4_decoding_class): New enum.
06647dfd
AM		 27 (dsmOneArcInst): Use the enum values for the decoding class.
28 Remove redundant case in the switch for decodingClass value 11.
82b829a7 29
c4a530c5
JB		 302005-03-02 Jan Beulich <jbeulich@novell.com>
31
32 * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
33 accesses.
34 (OP_C): Consider lock prefix in non-64-bit modes.
35
47d8304e
AM		 362005-02-24 Alan Modra <amodra@bigpond.net.au>
37
38 * cris-dis.c (format_hex): Remove ineffective warning fix.
39 * crx-dis.c (make_instruction): Warning fix.
40 * frv-asm.c: Regenerate.
41
ec36c4a4
NC		 422005-02-23 Nick Clifton <nickc@redhat.com>
43
33b71eeb
NC		 44 * cgen-dis.in: Use bfd_byte for buffers that are passed to
45 read_memory.
06647dfd 46
33b71eeb 47 * ia64-opc.c (locate_opcode_ent): Initialise opval array.
06647dfd 48
ec36c4a4
NC		 49 * crx-dis.c (make_instruction): Move argument structure into inner
50 scope and ensure that all of its fields are initialised before
51 they are used.
52
33b71eeb
NC		 53 * fr30-asm.c: Regenerate.
54 * fr30-dis.c: Regenerate.
55 * frv-asm.c: Regenerate.
56 * frv-dis.c: Regenerate.
57 * ip2k-asm.c: Regenerate.
58 * ip2k-dis.c: Regenerate.
59 * iq2000-asm.c: Regenerate.
60 * iq2000-dis.c: Regenerate.
61 * m32r-asm.c: Regenerate.
62 * m32r-dis.c: Regenerate.
63 * openrisc-asm.c: Regenerate.
64 * openrisc-dis.c: Regenerate.
65 * xstormy16-asm.c: Regenerate.
66 * xstormy16-dis.c: Regenerate.
67
53c9ebc5
AM		 682005-02-22 Alan Modra <amodra@bigpond.net.au>
69
70 * arc-ext.c: Warning fixes.
71 * arc-ext.h: Likewise.
72 * cgen-opc.c: Likewise.
73 * ia64-gen.c: Likewise.
74 * maxq-dis.c: Likewise.
75 * ns32k-dis.c: Likewise.
76 * w65-dis.c: Likewise.
77 * ia64-asmtab.c: Regenerate.
78
610ad19b
AM		 792005-02-22 Alan Modra <amodra@bigpond.net.au>
80
81 * fr30-desc.c: Regenerate.
82 * fr30-desc.h: Regenerate.
83 * fr30-opc.c: Regenerate.
84 * fr30-opc.h: Regenerate.
85 * frv-desc.c: Regenerate.
86 * frv-desc.h: Regenerate.
87 * frv-opc.c: Regenerate.
88 * frv-opc.h: Regenerate.
89 * ip2k-desc.c: Regenerate.
90 * ip2k-desc.h: Regenerate.
91 * ip2k-opc.c: Regenerate.
92 * ip2k-opc.h: Regenerate.
93 * iq2000-desc.c: Regenerate.
94 * iq2000-desc.h: Regenerate.
95 * iq2000-opc.c: Regenerate.
96 * iq2000-opc.h: Regenerate.
97 * m32r-desc.c: Regenerate.
98 * m32r-desc.h: Regenerate.
99 * m32r-opc.c: Regenerate.
100 * m32r-opc.h: Regenerate.
101 * m32r-opinst.c: Regenerate.
102 * openrisc-desc.c: Regenerate.
103 * openrisc-desc.h: Regenerate.
104 * openrisc-opc.c: Regenerate.
105 * openrisc-opc.h: Regenerate.
106 * xstormy16-desc.c: Regenerate.
107 * xstormy16-desc.h: Regenerate.
108 * xstormy16-opc.c: Regenerate.
109 * xstormy16-opc.h: Regenerate.
110
db9db6f2
AM		 1112005-02-21 Alan Modra <amodra@bigpond.net.au>
112
113 * Makefile.am: Run "make dep-am"
114 * Makefile.in: Regenerate.
115
bf143b25
NC		 1162005-02-15 Nick Clifton <nickc@redhat.com>
117
118 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
119 compile time warnings.
120 (print_keyword): Likewise.
121 (default_print_insn): Likewise.
122
123 * fr30-desc.c: Regenerated.
124 * fr30-desc.h: Regenerated.
125 * fr30-dis.c: Regenerated.
126 * fr30-opc.c: Regenerated.
127 * fr30-opc.h: Regenerated.
128 * frv-desc.c: Regenerated.
129 * frv-dis.c: Regenerated.
130 * frv-opc.c: Regenerated.
131 * ip2k-asm.c: Regenerated.
132 * ip2k-desc.c: Regenerated.
133 * ip2k-desc.h: Regenerated.
134 * ip2k-dis.c: Regenerated.
135 * ip2k-opc.c: Regenerated.
136 * ip2k-opc.h: Regenerated.
137 * iq2000-desc.c: Regenerated.
138 * iq2000-dis.c: Regenerated.
139 * iq2000-opc.c: Regenerated.
140 * m32r-asm.c: Regenerated.
141 * m32r-desc.c: Regenerated.
142 * m32r-desc.h: Regenerated.
143 * m32r-dis.c: Regenerated.
144 * m32r-opc.c: Regenerated.
145 * m32r-opc.h: Regenerated.
146 * m32r-opinst.c: Regenerated.
147 * openrisc-desc.c: Regenerated.
148 * openrisc-desc.h: Regenerated.
149 * openrisc-dis.c: Regenerated.
150 * openrisc-opc.c: Regenerated.
151 * openrisc-opc.h: Regenerated.
152 * xstormy16-desc.c: Regenerated.
153 * xstormy16-desc.h: Regenerated.
154 * xstormy16-dis.c: Regenerated.
155 * xstormy16-opc.c: Regenerated.
156 * xstormy16-opc.h: Regenerated.
157
d6098898
L		 1582005-02-14 H.J. Lu <hongjiu.lu@intel.com>
159
160 * dis-buf.c (perror_memory): Use sprintf_vma to print out
161 address.
162
5a84f3e0
NC		 1632005-02-11 Nick Clifton <nickc@redhat.com>
164
bc18c937
NC		 165 * iq2000-asm.c: Regenerate.
166
5a84f3e0
NC		 167 * frv-dis.c: Regenerate.
168
0a40490e
JB		 1692005-02-07 Jim Blandy <jimb@redhat.com>
170
171 * Makefile.am (CGEN): Load guile.scm before calling the main
172 application script.
173 * Makefile.in: Regenerated.
174 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
175 Simply pass the cgen-opc.scm path to ${cgen} as its first
176 argument; ${cgen} itself now contains the '-s', or whatever is
177 appropriate for the Scheme being used.
178
c46f8c51
AC		 1792005-01-31 Andrew Cagney <cagney@gnu.org>
180
181 * configure: Regenerate to track ../gettext.m4.
182
60b9a617
JB		 1832005-01-31 Jan Beulich <jbeulich@novell.com>
184
185 * ia64-gen.c (NELEMS): Define.
186 (shrink): Generate alias with missing second predicate register when
187 opcode has two outputs and these are both predicates.
188 * ia64-opc-i.c (FULL17): Define.
189 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
190 here to generate output template.
191 (TBITCM, TNATCM): Undefine after use.
192 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
193 first input. Add ld16 aliases without ar.csd as second output. Add
194 st16 aliases without ar.csd as second input. Add cmpxchg aliases
195 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
196 ar.ccv as third/fourth inputs. Consolidate through...
197 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
198 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
199 * ia64-asmtab.c: Regenerate.
200
a53bf506
AC		 2012005-01-27 Andrew Cagney <cagney@gnu.org>
202
203 * configure: Regenerate to track ../gettext.m4 change.
204
90219bd0
AO		 2052005-01-25 Alexandre Oliva <aoliva@redhat.com>
206
207 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
208 * frv-asm.c: Rebuilt.
209 * frv-desc.c: Rebuilt.
210 * frv-desc.h: Rebuilt.
211 * frv-dis.c: Rebuilt.
212 * frv-ibld.c: Rebuilt.
213 * frv-opc.c: Rebuilt.
214 * frv-opc.h: Rebuilt.
215
45181ed1
AC		 2162005-01-24 Andrew Cagney <cagney@gnu.org>
217
218 * configure: Regenerate, ../gettext.m4 was updated.
219
9e836e3d
FF		 2202005-01-21 Fred Fish <fnf@specifixinc.com>
221
222 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
223 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
224 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
225 * mips-dis.c: Ditto.
226
5e8cb021
AM		 2272005-01-20 Alan Modra <amodra@bigpond.net.au>
228
229 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
230
986e18a5
FF		 2312005-01-19 Fred Fish <fnf@specifixinc.com>
232
233 * mips-dis.c (no_aliases): New disassembly option flag.
234 (set_default_mips_dis_options): Init no_aliases to zero.
235 (parse_mips_dis_option): Handle no-aliases option.
236 (print_insn_mips): Ignore table entries that are aliases
237 if no_aliases is set.
238 (print_insn_mips16): Ditto.
239 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
240 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
241 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
242 * mips16-opc.c (mips16_opcodes): Ditto.
243
e38bc3b5
NC		 2442005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
245
246 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
247 (inheritance diagram): Add missing edge.
248 (arch_sh1_up): Rename arch_sh_up to match external name to make life
249 easier for the testsuite.
250 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
251 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
610ad19b 252 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
e38bc3b5
NC		 253 arch_sh2a_or_sh4_up child.
254 (sh_table): Do renaming as above.
255 Correct comment for ldc.l for gas testsuite to read.
256 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
257 Correct comments for movy.w and movy.l for gas testsuite to read.
258 Correct comments for fmov.d and fmov.s for gas testsuite to read.
259
9df48ba9
L		 2602005-01-12 H.J. Lu <hongjiu.lu@intel.com>
261
262 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
263
2033b4b9
L		 2642005-01-12 H.J. Lu <hongjiu.lu@intel.com>
265
266 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
267
0bcb06d2
AS		 2682005-01-10 Andreas Schwab <schwab@suse.de>
269
270 * disassemble.c (disassemble_init_for_target) <case
271 bfd_arch_ia64>: Set skip_zeroes to 16.
272 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
273
47add74d
TL		 2742004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
275
276 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
277
246f4c05
SS		 2782004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
279
280 * avr-dis.c: Prettyprint. Added printing of symbol names in all
281 memory references. Convert avr_operand() to C90 formatting.
282
0e1200e5
TL		 2832004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
284
285 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
286
89a649f7
TL		 2872004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
288
289 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
290 (no_op_insn): Initialize array with instructions that have no
291 operands.
292 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
293
6255809c
RE		 2942004-11-29 Richard Earnshaw <rearnsha@arm.com>
295
296 * arm-dis.c: Correct top-level comment.
297
2fbad815
RE		 2982004-11-27 Richard Earnshaw <rearnsha@arm.com>
299
300 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
301 architecuture defining the insn.
302 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 303 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
304 field.
2fbad815
RE		 305 Also include opcode/arm.h.
306 * Makefile.am (arm-dis.lo): Update dependency list.
307 * Makefile.in: Regenerate.
308
d81acc42
NC		 3092004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
310
311 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
312 reflect the change to the short immediate syntax.
313
ca4f2377
AM		 3142004-11-19 Alan Modra <amodra@bigpond.net.au>
315
5da8bf1b
AM		 316 * or32-opc.c (debug): Warning fix.
317 * po/POTFILES.in: Regenerate.
318
ca4f2377
AM		 319 * maxq-dis.c: Formatting.
320 (print_insn): Warning fix.
321
b7693d02
DJ		 3222004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
323
324 * arm-dis.c (WORD_ADDRESS): Define.
325 (print_insn): Use it. Correct big-endian end-of-section handling.
326
300dac7e
NC		 3272004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
328 Vineet Sharma <vineets@noida.hcltech.com>
329
330 * maxq-dis.c: New file.
331 * disassemble.c (ARCH_maxq): Define.
610ad19b 332 (disassembler): Add 'print_insn_maxq_little' for handling maxq
300dac7e
NC		 333 instructions..
334 * configure.in: Add case for bfd_maxq_arch.
335 * configure: Regenerate.
336 * Makefile.am: Add support for maxq-dis.c
337 * Makefile.in: Regenerate.
338 * aclocal.m4: Regenerate.
339
42048ee7
TL		 3402004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
341
342 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
343 mode.
344 * crx-dis.c: Likewise.
345
bd21e58e
HPN		 3462004-11-04 Hans-Peter Nilsson <hp@axis.com>
347
348 Generally, handle CRISv32.
349 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
350 (struct cris_disasm_data): New type.
351 (format_reg, format_hex, cris_constraint, print_flags)
352 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
353 callers changed.
354 (format_sup_reg, print_insn_crisv32_with_register_prefix)
355 (print_insn_crisv32_without_register_prefix)
356 (print_insn_crisv10_v32_with_register_prefix)
357 (print_insn_crisv10_v32_without_register_prefix)
358 (cris_parse_disassembler_options): New functions.
359 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
360 parameter. All callers changed.
361 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
362 failure.
363 (cris_constraint) <case 'Y', 'U'>: New cases.
364 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
365 for constraint 'n'.
366 (print_with_operands) <case 'Y'>: New case.
367 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
368 <case 'N', 'Y', 'Q'>: New cases.
369 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
370 (print_insn_cris_with_register_prefix)
371 (print_insn_cris_without_register_prefix): Call
372 cris_parse_disassembler_options.
373 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
374 for CRISv32 and the size of immediate operands. New v32-only
375 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
376 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
377 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
378 Change brp to be v3..v10.
379 (cris_support_regs): New vector.
380 (cris_opcodes): Update head comment. New format characters '[',
381 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
382 Add new opcodes for v32 and adjust existing opcodes to accommodate
383 differences to earlier variants.
384 (cris_cond15s): New vector.
385
9306ca4a
JB		 3862004-11-04 Jan Beulich <jbeulich@novell.com>
387
388 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
389 (indirEb): Remove.
390 (Mp): Use f_mode rather than none at all.
391 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
392 replaces what previously was x_mode; x_mode now means 128-bit SSE
393 operands.
394 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
395 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
396 pinsrw's second operand is Edqw.
397 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
398 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
399 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
400 mode when an operand size override is present or always suffixing.
401 More instructions will need to be added to this group.
402 (putop): Handle new macro chars 'C' (short/long suffix selector),
403 'I' (Intel mode override for following macro char), and 'J' (for
404 adding the 'l' prefix to far branches in AT&T mode). When an
405 alternative was specified in the template, honor macro character when
406 specified for Intel mode.
407 (OP_E): Handle new *_mode values. Correct pointer specifications for
408 memory operands. Consolidate output of index register.
409 (OP_G): Handle new *_mode values.
410 (OP_I): Handle const_1_mode.
411 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
412 respective opcode prefix bits have been consumed.
413 (OP_EM, OP_EX): Provide some default handling for generating pointer
414 specifications.
415
f39c96a9
TL		 4162004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
417
418 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
419 COP_INST macro.
420
812337be
TL		 4212004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
422
423 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
424 (getregliststring): Support HI/LO and user registers.
610ad19b 425 * crx-opc.c (crx_instruction): Update data structure according to the
812337be
TL		 426 rearrangement done in CRX opcode header file.
427 (crx_regtab): Likewise.
428 (crx_optab): Likewise.
610ad19b 429 (crx_instruction): Reorder load/stor instructions, remove unsupported
812337be
TL		 430 formats.
431 support new Co-Processor instruction 'cpi'.
432
4030fa5a
NC		 4332004-10-27 Nick Clifton <nickc@redhat.com>
434
435 * opcodes/iq2000-asm.c: Regenerate.
436 * opcodes/iq2000-desc.c: Regenerate.
437 * opcodes/iq2000-desc.h: Regenerate.
438 * opcodes/iq2000-dis.c: Regenerate.
439 * opcodes/iq2000-ibld.c: Regenerate.
440 * opcodes/iq2000-opc.c: Regenerate.
441 * opcodes/iq2000-opc.h: Regenerate.
442
fc3d45e8
TL		 4432004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
444
445 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
446 us4, us5 (respectively).
447 Remove unsupported 'popa' instruction.
448 Reverse operands order in store co-processor instructions.
449
3c55da70
AM		 4502004-10-15 Alan Modra <amodra@bigpond.net.au>
451
452 * Makefile.am: Run "make dep-am"
453 * Makefile.in: Regenerate.
454
7fa3d080
BW		 4552004-10-12 Bob Wilson <bob.wilson@acm.org>
456
457 * xtensa-dis.c: Use ISO C90 formatting.
458
e612bb4d
AM		 4592004-10-09 Alan Modra <amodra@bigpond.net.au>
460
461 * ppc-opc.c: Revert 2004-09-09 change.
462
43cd72b9
BW		 4632004-10-07 Bob Wilson <bob.wilson@acm.org>
464
465 * xtensa-dis.c (state_names): Delete.
466 (fetch_data): Use xtensa_isa_maxlength.
467 (print_xtensa_operand): Replace operand parameter with opcode/operand
468 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
469 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
470 instruction bundles. Use xmalloc instead of malloc.
471
bbac1f2a
NC		 4722004-10-07 David Gibson <david@gibson.dropbear.id.au>
473
474 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
475 initializers.
476
48c9f030
NC		 4772004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
478
479 * crx-opc.c (crx_instruction): Support Co-processor insns.
480 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
481 (getregliststring): Change function to use the above enum.
482 (print_arg): Handle CO-Processor insns.
483 (crx_cinvs): Add 'b' option to invalidate the branch-target
484 cache.
485
12c64a4e
AH		 4862004-10-06 Aldy Hernandez <aldyh@redhat.com>
487
488 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
489 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
490 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
491 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
492 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
493
14127cc4
NC		 4942004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
495
496 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
497 rather than add it.
498
0dd132b6
NC		 4992004-09-30 Paul Brook <paul@codesourcery.com>
500
501 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
502 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
503
3f85e526
L		 5042004-09-17 H.J. Lu <hongjiu.lu@intel.com>
505
506 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
507 (CONFIG_STATUS_DEPENDENCIES): New.
508 (Makefile): Removed.
509 (config.status): Likewise.
510 * Makefile.in: Regenerated.
511
8ae85421
AM		 5122004-09-17 Alan Modra <amodra@bigpond.net.au>
513
514 * Makefile.am: Run "make dep-am".
515 * Makefile.in: Regenerate.
516 * aclocal.m4: Regenerate.
517 * configure: Regenerate.
518 * po/POTFILES.in: Regenerate.
519 * po/opcodes.pot: Regenerate.
520
24443139
AS		 5212004-09-11 Andreas Schwab <schwab@suse.de>
522
523 * configure: Rebuild.
524
2a309db0
AM		 5252004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
526
527 * ppc-opc.c (L): Make this field not optional.
528
42851540
NC		 5292004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
530
531 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
532 Fix parameter to 'm[t|f]csr' insns.
533
979273e3
NN		 5342004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
535
536 * configure.in: Autoupdate to autoconf 2.59.
537 * aclocal.m4: Rebuild with aclocal 1.4p6.
538 * configure: Rebuild with autoconf 2.59.
539 * Makefile.in: Rebuild with automake 1.4p6 (picking up
540 bfd changes for autoconf 2.59 on the way).
541 * config.in: Rebuild with autoheader 2.59.
542
ac28a1cb
RS		 5432004-08-27 Richard Sandiford <rsandifo@redhat.com>
544
545 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
546
30d1c836
ML		 5472004-07-30 Michal Ludvig <mludvig@suse.cz>
548
549 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
550 (GRPPADLCK2): New define.
551 (twobyte_has_modrm): True for 0xA6.
552 (grps): GRPPADLCK2 for opcode 0xA6.
553
0b0ac059
AO		 5542004-07-29 Alexandre Oliva <aoliva@redhat.com>
555
556 Introduce SH2a support.
557 * sh-opc.h (arch_sh2a_base): Renumber.
558 (arch_sh2a_nofpu_base): Remove.
559 (arch_sh_base_mask): Adjust.
560 (arch_opann_mask): New.
561 (arch_sh2a, arch_sh2a_nofpu): Adjust.
562 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
563 (sh_table): Adjust whitespace.
564 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
565 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
566 instruction list throughout.
567 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
568 of arch_sh2a in instruction list throughout.
569 (arch_sh2e_up): Accomodate above changes.
570 (arch_sh2_up): Ditto.
571 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
572 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
573 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
574 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
575 * sh-opc.h (arch_sh2a_nofpu): New.
576 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
577 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
578 instruction.
579 2004-01-20 DJ Delorie <dj@redhat.com>
580 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
581 2003-12-29 DJ Delorie <dj@redhat.com>
582 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
583 sh_opcode_info, sh_table): Add sh2a support.
584 (arch_op32): New, to tag 32-bit opcodes.
585 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
586 2003-12-02 Michael Snyder <msnyder@redhat.com>
587 * sh-opc.h (arch_sh2a): Add.
588 * sh-dis.c (arch_sh2a): Handle.
589 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
590
670ec21d
NC		 5912004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
592
593 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
594
ed049af3
NC		 5952004-07-22 Nick Clifton <nickc@redhat.com>
596
597 PR/280
598 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
599 insns - this is done by objdump itself.
600 * h8500-dis.c (print_insn_h8500): Likewise.
601
20f0a1fc
NC		 6022004-07-21 Jan Beulich <jbeulich@novell.com>
603
604 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
605 regardless of address size prefix in effect.
606 (ptr_reg): Size or address registers does not depend on rex64, but
607 on the presence of an address size override.
608 (OP_MMX): Use rex.x only for xmm registers.
609 (OP_EM): Use rex.z only for xmm registers.
610
6f14957b
MR		 6112004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
612
613 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
614 move/branch operations to the bottom so that VR5400 multimedia
615 instructions take precedence in disassembly.
616
1586d91e
MR		 6172004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
618
619 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
620 ISA-specific "break" encoding.
621
982de27a
NC		 6222004-07-13 Elvis Chiang <elvisfb@gmail.com>
623
624 * arm-opc.h: Fix typo in comment.
625
4300ab10
AS		 6262004-07-11 Andreas Schwab <schwab@suse.de>
627
628 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
629
8577e690
AS		 6302004-07-09 Andreas Schwab <schwab@suse.de>
631
632 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
633
1fe1f39c
NC		 6342004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
635
636 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
637 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
638 (crx-dis.lo): New target.
639 (crx-opc.lo): Likewise.
640 * Makefile.in: Regenerate.
641 * configure.in: Handle bfd_crx_arch.
642 * configure: Regenerate.
643 * crx-dis.c: New file.
644 * crx-opc.c: New file.
645 * disassemble.c (ARCH_crx): Define.
646 (disassembler): Handle ARCH_crx.
647
7a33b495
JW		 6482004-06-29 James E Wilson <wilson@specifixinc.com>
649
650 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
651 * ia64-asmtab.c: Regnerate.
652
98e69875
AM		 6532004-06-28 Alan Modra <amodra@bigpond.net.au>
654
655 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
656 (extract_fxm): Don't test dialect.
657 (XFXFXM_MASK): Include the power4 bit.
658 (XFXM): Add p4 param.
659 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
660
a53b85e2
AO		 6612004-06-27 Alexandre Oliva <aoliva@redhat.com>
662
663 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
664 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
665
d0618d1c
AM		 6662004-06-26 Alan Modra <amodra@bigpond.net.au>
667
668 * ppc-opc.c (BH, XLBH_MASK): Define.
669 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
670
1d9f512f
AM		 6712004-06-24 Alan Modra <amodra@bigpond.net.au>
672
673 * i386-dis.c (x_mode): Comment.
674 (two_source_ops): File scope.
675 (float_mem): Correct fisttpll and fistpll.
676 (float_mem_mode): New table.
677 (dofloat): Use it.
678 (OP_E): Correct intel mode PTR output.
679 (ptr_reg): Use open_char and close_char.
680 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
681 operands. Set two_source_ops.
682
52886d70
AM		 6832004-06-15 Alan Modra <amodra@bigpond.net.au>
684
685 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
686 instead of _raw_size.
687
bad9ceea
JJ		 6882004-06-08 Jakub Jelinek <jakub@redhat.com>
689
690 * ia64-gen.c (in_iclass): Handle more postinc st
691 and ld variants.
692 * ia64-asmtab.c: Rebuilt.
693
0451f5df
MS		 6942004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
695
696 * s390-opc.txt: Correct architecture mask for some opcodes.
697 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
698 in the esa mode as well.
699
f6f9408f
JR		 7002004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
701
702 * sh-dis.c (target_arch): Make unsigned.
703 (print_insn_sh): Replace (most of) switch with a call to
704 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
705 * sh-opc.h: Redefine architecture flags values.
706 Add sh3-nommu architecture.
707 Reorganise <arch>_up macros so they make more visual sense.
708 (SH_MERGE_ARCH_SET): Define new macro.
709 (SH_VALID_BASE_ARCH_SET): Likewise.
710 (SH_VALID_MMU_ARCH_SET): Likewise.
711 (SH_VALID_CO_ARCH_SET): Likewise.
712 (SH_VALID_ARCH_SET): Likewise.
713 (SH_MERGE_ARCH_SET_VALID): Likewise.
714 (SH_ARCH_SET_HAS_FPU): Likewise.
715 (SH_ARCH_SET_HAS_DSP): Likewise.
716 (SH_ARCH_UNKNOWN_ARCH): Likewise.
717 (sh_get_arch_from_bfd_mach): Add prototype.
718 (sh_get_arch_up_from_bfd_mach): Likewise.
719 (sh_get_bfd_mach_from_arch_set): Likewise.
720 (sh_merge_bfd_arc): Likewise.
721
be8c092b
NC		 7222004-05-24 Peter Barada <peter@the-baradas.com>
723
724 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
610ad19b
AM		 725 into new match_insn_m68k function. Loop over canidate
726 matches and select first that completely matches.
be8c092b
NC		 727 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
728 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
610ad19b 729 to verify addressing for MAC/EMAC.
be8c092b
NC		 730 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
731 reigster halves since 'fpu' and 'spl' look misleading.
732 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
733 * m68k-opc.c: Rearragne mac/emac cases to use longest for
734 first, tighten up match masks.
735 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
736 'size' from special case code in print_insn_m68k to
737 determine decode size of insns.
738
a30e9cc4
AM		 7392004-05-19 Alan Modra <amodra@bigpond.net.au>
740
741 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
742 well as when -mpower4.
743
9598fbe5
NC		 7442004-05-13 Nick Clifton <nickc@redhat.com>
745
746 * po/fr.po: Updated French translation.
747
6b6e92f4
NC		 7482004-05-05 Peter Barada <peter@the-baradas.com>
749
750 * m68k-dis.c(print_insn_m68k): Add new chips, use core
751 variants in arch_mask. Only set m68881/68851 for 68k chips.
752 * m68k-op.c: Switch from ColdFire chips to core variants.
753
a404d431
AM		 7542004-05-05 Alan Modra <amodra@bigpond.net.au>
755
a30e9cc4 756 PR 147.
a404d431
AM		 757 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
758
f3806e43
BE		 7592004-04-29 Ben Elliston <bje@au.ibm.com>
760
520ceea4
BE		 761 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
762 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 763
1f1799d5
KK		 7642004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
765
766 * sh-dis.c (print_insn_sh): Print the value in constant pool
767 as a symbol if it looks like a symbol.
768
fd99574b
NC		 7692004-04-22 Peter Barada <peter@the-baradas.com>
770
771 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
772 appropriate ColdFire architectures.
773 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
774 mask addressing.
775 Add EMAC instructions, fix MAC instructions. Remove
776 macmw/macml/msacmw/msacml instructions since mask addressing now
777 supported.
778
b4781d44
JJ		 7792004-04-20 Jakub Jelinek <jakub@redhat.com>
780
781 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
782 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
783 suffix. Use fmov*x macros, create all 3 fpsize variants in one
784 macro. Adjust all users.
785
91809fda 7862004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
610ad19b 787
91809fda
NC		 788 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
789 separately.
790
f4453dfa
NC		 7912004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
792
793 * m32r-asm.c: Regenerate.
794
9b0de91a
SS		 7952004-03-29 Stan Shebs <shebs@apple.com>
796
797 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
798 used.
799
e20c0b3d
AM		 8002004-03-19 Alan Modra <amodra@bigpond.net.au>
801
802 * aclocal.m4: Regenerate.
803 * config.in: Regenerate.
804 * configure: Regenerate.
805 * po/POTFILES.in: Regenerate.
806 * po/opcodes.pot: Regenerate.
807
fdd12ef3
AM		 8082004-03-16 Alan Modra <amodra@bigpond.net.au>
809
810 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
811 PPC_OPERANDS_GPR_0.
812 * ppc-opc.c (RA0): Define.
813 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
814 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 815 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 816
2dc111b3 8172004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 818
819 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 820
7bfeee7b
AM		 8212004-03-15 Alan Modra <amodra@bigpond.net.au>
822
823 * sparc-dis.c (print_insn_sparc): Update getword prototype.
824
7ffdda93
ML		 8252004-03-12 Michal Ludvig <mludvig@suse.cz>
826
827 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 828 (grps): Delete GRPPLOCK entry.
7ffdda93 829
cc0ec051
AM		 8302004-03-12 Alan Modra <amodra@bigpond.net.au>
831
832 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
833 (M, Mp): Use OP_M.
834 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
835 (GRPPADLCK): Define.
836 (dis386): Use NOP_Fixup on "nop".
837 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
838 (twobyte_has_modrm): Set for 0xa7.
839 (padlock_table): Delete. Move to..
840 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
841 and clflush.
842 (print_insn): Revert PADLOCK_SPECIAL code.
843 (OP_E): Delete sfence, lfence, mfence checks.
844
4fd61dcb
JJ		 8452004-03-12 Jakub Jelinek <jakub@redhat.com>
846
847 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
848 (INVLPG_Fixup): New function.
849 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
850
0f10071e
ML		 8512004-03-12 Michal Ludvig <mludvig@suse.cz>
852
853 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
854 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
855 (padlock_table): New struct with PadLock instructions.
856 (print_insn): Handle PADLOCK_SPECIAL.
857
c02908d2
AM		 8582004-03-12 Alan Modra <amodra@bigpond.net.au>
859
860 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
861 (OP_E): Twiddle clflush to sfence here.
862
d5bb7600
NC		 8632004-03-08 Nick Clifton <nickc@redhat.com>
864
865 * po/de.po: Updated German translation.
866
ae51a426
JR		 8672003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
868
869 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
870 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
871 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
872 accordingly.
873
676a64f4
RS		 8742004-03-01 Richard Sandiford <rsandifo@redhat.com>
875
876 * frv-asm.c: Regenerate.
877 * frv-desc.c: Regenerate.
878 * frv-desc.h: Regenerate.
879 * frv-dis.c: Regenerate.
880 * frv-ibld.c: Regenerate.
881 * frv-opc.c: Regenerate.
882 * frv-opc.h: Regenerate.
883
c7a48b9a
RS		 8842004-03-01 Richard Sandiford <rsandifo@redhat.com>
885
886 * frv-desc.c, frv-opc.c: Regenerate.
887
8ae0baa2
RS		 8882004-03-01 Richard Sandiford <rsandifo@redhat.com>
889
890 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
891
ce11586c
JR		 8922004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
893
894 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
895 Also correct mistake in the comment.
896
6a5709a5
JR		 8972004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
898
899 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
900 ensure that double registers have even numbers.
901 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
902 that reserved instruction 0xfffd does not decode the same
903 as 0xfdfd (ftrv).
904 * sh-opc.h: Add REG_N_D nibble type and use it whereever
905 REG_N refers to a double register.
906 Add REG_N_B01 nibble type and use it instead of REG_NM
907 in ftrv.
908 Adjust the bit patterns in a few comments.
909
e5d2b64f 9102004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 911
912 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 913
1f04b05f
AH		 9142004-02-20 Aldy Hernandez <aldyh@redhat.com>
915
916 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
917
2f3b8700
AH		 9182004-02-20 Aldy Hernandez <aldyh@redhat.com>
919
920 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
921
f0b26da6 9222004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 923
924 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
925 mtivor32, mtivor33, mtivor34.
f0b26da6 926
23d59c56 9272004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 928
929 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 930
34920d91
NC		 9312004-02-10 Petko Manolov <petkan@nucleusys.com>
932
933 * arm-opc.h Maverick accumulator register opcode fixes.
934
44d86481
BE		 9352004-02-13 Ben Elliston <bje@wasabisystems.com>
936
937 * m32r-dis.c: Regenerate.
938
17707c23
MS		 9392004-01-27 Michael Snyder <msnyder@redhat.com>
940
941 * sh-opc.h (sh_table): "fsrra", not "fssra".
942
fe3a9bc4
NC		 9432004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
944
945 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
946 contraints.
947
ff24f124
JJ		 9482004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
949
950 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
951
a02a862a
AM		 9522004-01-19 Alan Modra <amodra@bigpond.net.au>
953
954 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
955 1. Don't print scale factor on AT&T mode when index missing.
956
d164ea7f
AO		 9572004-01-16 Alexandre Oliva <aoliva@redhat.com>
958
959 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
960 when loaded into XR registers.
961
cb10e79a
RS		 9622004-01-14 Richard Sandiford <rsandifo@redhat.com>
963
964 * frv-desc.h: Regenerate.
965 * frv-desc.c: Regenerate.
966 * frv-opc.c: Regenerate.
967
f532f3fa
MS		 9682004-01-13 Michael Snyder <msnyder@redhat.com>
969
970 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
971
e45d0630
PB		 9722004-01-09 Paul Brook <paul@codesourcery.com>
973
974 * arm-opc.h (arm_opcodes): Move generic mcrr after known
975 specific opcodes.
976
3ba7a1aa
DJ		 9772004-01-07 Daniel Jacobowitz <drow@mvista.com>
978
979 * Makefile.am (libopcodes_la_DEPENDENCIES)
980 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
981 comment about the problem.
982 * Makefile.in: Regenerate.
983
ba2d3f07
AO		 9842004-01-06 Alexandre Oliva <aoliva@redhat.com>
985
986 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
987 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
988 cut&paste errors in shifting/truncating numerical operands.
989 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
990 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
991 (parse_uslo16): Likewise.
992 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
993 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
994 (parse_s12): Likewise.
995 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
996 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
997 (parse_uslo16): Likewise.
998 (parse_uhi16): Parse gothi and gotfuncdeschi.
999 (parse_d12): Parse got12 and gotfuncdesc12.
1000 (parse_s12): Likewise.
1001
3ab48931
NC		 10022004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
1003
1004 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
1005 instruction which looks similar to an 'rla' instruction.
a0bd404e 1006
c9e214e5 1007For older changes see ChangeLog-0203
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1009Local Variables:
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NC		 1010mode: change-log
1011left-margin: 8
1012fill-column: 74
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RH		 1013version-control: never
1014End:
GDB Binutils - Deliverables
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