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b6518b38
NC		 12015-09-23 Nick Clifton <nickc@redhat.com>
2
3 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
4 function.
5 * tic30-dis.c (print_branch): Likewise.
6 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
7 value before left shifting.
8 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
9 * hppa-dis.c (print_insn_hppa): Likewise.
10 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
11 array.
12 * msp430-dis.c (msp430_singleoperand): Likewise.
13 (msp430_doubleoperand): Likewise.
14 (print_insn_msp430): Likewise.
15 * nds32-asm.c (parse_operand): Likewise.
16 * sh-opc.h (MASK): Likewise.
17 * v850-dis.c (get_operand_value): Likewise.
18
f04265ec
NC		 192015-09-22 Nick Clifton <nickc@redhat.com>
20
21 * rx-decode.opc (bwl): Use RX_Bad_Size.
22 (sbwl): Likewise.
23 (ubwl): Likewise. Rename to ubw.
24 (uBWL): Rename to uBW.
25 Replace all references to uBWL with uBW.
26 * rx-decode.c: Regenerate.
27 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
28 (opsize_names): Likewise.
29 (print_insn_rx): Detect and report RX_Bad_Size.
30
6dca4fd1
AB		 312015-09-22 Anton Blanchard <anton@samba.org>
32
33 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
34
38074311
JM		 352015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
36
37 * sparc-dis.c (print_insn_sparc): Handle the privileged register
38 %pmcdper.
39
5f40e14d
JS		 402015-08-24 Jan Stancek <jstancek@redhat.com>
41
42 * i386-dis.c (print_insn): Fix decoding of three byte operands.
43
ab4e4ed5
AF		 442015-08-21 Alexander Fomin <alexander.fomin@intel.com>
45
46 PR binutils/18257
47 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
48 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
49 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
50 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
51 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
52 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
53 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
54 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
55 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
56 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
57 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
58 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
59 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
60 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
61 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
62 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
63 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
64 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
65 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
66 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
67 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
68 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
69 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
70 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
71 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
72 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
73 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
74 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
75 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
76 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
77 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
78 (vex_w_table): Replace terminals with MOD_TABLE entries for
79 most of mask instructions.
80
919b75f7
AM		 812015-08-17 Alan Modra <amodra@gmail.com>
82
83 * cgen.sh: Trim trailing space from cgen output.
84 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
85 (print_dis_table): Likewise.
86 * opc2c.c (dump_lines): Likewise.
87 (orig_filename): Warning fix.
88 * ia64-asmtab.c: Regenerate.
89
4ab90a7a
AV		 902015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
91
92 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
93 and higher with ARM instruction set will now mark the 26-bit
94 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
95 (arm_opcodes): Fix for unpredictable nop being recognized as a
96 teq.
97
40fc1451
SD		 982015-08-12 Simon Dardis <simon.dardis@imgtec.com>
99
100 * micromips-opc.c (micromips_opcodes): Re-order table so that move
101 based on 'or' is first.
102 * mips-opc.c (mips_builtin_opcodes): Ditto.
103
922c5db5
NC		 1042015-08-11 Nick Clifton <nickc@redhat.com>
105
106 PR 18800
107 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
108 instruction.
109
75fb7498
RS		 1102015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
111
112 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
113
36aed29d
AP		 1142015-08-07 Amit Pawar <Amit.Pawar@amd.com>
115
116 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
117 * i386-init.h: Regenerated.
118
a8484f96
L		 1192015-07-30 H.J. Lu <hongjiu.lu@intel.com>
120
121 PR binutils/13571
122 * i386-dis.c (MOD_0FC3): New.
123 (PREFIX_0FC3): Renamed to ...
124 (PREFIX_MOD_0_0FC3): This.
125 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
126 (prefix_table): Replace Ma with Ev on movntiS.
127 (mod_table): Add MOD_0FC3.
128
37a42ee9
L		 1292015-07-27 H.J. Lu <hongjiu.lu@intel.com>
130
131 * configure: Regenerated.
132
070fe95d
AM		 1332015-07-23 Alan Modra <amodra@gmail.com>
134
135 PR 18708
136 * i386-dis.c (get64): Avoid signed integer overflow.
137
20c2a615
L		 1382015-07-22 Alexander Fomin <alexander.fomin@intel.com>
139
140 PR binutils/18631
141 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
142 "EXEvexHalfBcstXmmq" for the second operand.
143 (EVEX_W_0F79_P_2): Likewise.
144 (EVEX_W_0F7A_P_2): Likewise.
145 (EVEX_W_0F7B_P_2): Likewise.
146
6f1c2142
AM		 1472015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
148
149 * arm-dis.c (print_insn_coprocessor): Added support for quarter
150 float bitfield format.
151 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
152 quarter float bitfield format.
153
8a643cc3
L		 1542015-07-14 H.J. Lu <hongjiu.lu@intel.com>
155
156 * configure: Regenerated.
157
ef5a96d5
AM		 1582015-07-03 Alan Modra <amodra@gmail.com>
159
160 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
161 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
162 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
163
c8c8175b
SL		 1642015-07-01 Sandra Loosemore <sandra@codesourcery.com>
165 Cesar Philippidis <cesar@codesourcery.com>
166
167 * nios2-dis.c (nios2_extract_opcode): New.
168 (nios2_disassembler_state): New.
169 (nios2_find_opcode_hash): Use mach parameter to select correct
170 disassembler state.
171 (nios2_print_insn_arg): Extend to support new R2 argument letters
172 and formats.
173 (print_insn_nios2): Check for 16-bit instruction at end of memory.
174 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
175 (NIOS2_NUM_OPCODES): Rename to...
176 (NIOS2_NUM_R1_OPCODES): This.
177 (nios2_r2_opcodes): New.
178 (NIOS2_NUM_R2_OPCODES): New.
179 (nios2_num_r2_opcodes): New.
180 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
181 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
182 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
183 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
184 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
185
9916071f
AP		 1862015-06-30 Amit Pawar <Amit.Pawar@amd.com>
187
188 * i386-dis.c (OP_Mwaitx): New.
189 (rm_table): Add monitorx/mwaitx.
190 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
191 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
192 (operand_type_init): Add CpuMWAITX.
193 * i386-opc.h (CpuMWAITX): New.
194 (i386_cpu_flags): Add cpumwaitx.
195 * i386-opc.tbl: Add monitorx and mwaitx.
196 * i386-init.h: Regenerated.
197 * i386-tbl.h: Likewise.
198
7b934113
PB		 1992015-06-22 Peter Bergner <bergner@vnet.ibm.com>
200
201 * ppc-opc.c (insert_ls): Test for invalid LS operands.
202 (insert_esync): New function.
203 (LS, WC): Use insert_ls.
204 (ESYNC): Use insert_esync.
205
bdc4de1b
NC		 2062015-06-22 Nick Clifton <nickc@redhat.com>
207
208 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
209 requested region lies beyond it.
210 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
211 looking for 32-bit insns.
212 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
213 data.
214 * sh-dis.c (print_insn_sh): Likewise.
215 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
216 blocks of instructions.
217 * vax-dis.c (print_insn_vax): Check that the requested address
218 does not clash with the stop_vma.
219
11a0cf2e
PB		 2202015-06-19 Peter Bergner <bergner@vnet.ibm.com>
221
070fe95d 222 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 223 * ppc-opc.c (FXM4): Add non-zero optional value.
224 (TBR): Likewise.
225 (SXL): Likewise.
226 (insert_fxm): Handle new default operand value.
227 (extract_fxm): Likewise.
228 (insert_tbr): Likewise.
229 (extract_tbr): Likewise.
230
bdfa8b95
MW		 2312015-06-16 Matthew Wahab <matthew.wahab@arm.com>
232
233 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
234
24b4cf66
SN		 2352015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
236
237 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
238
99a2c561
PB		 2392015-06-12 Peter Bergner <bergner@vnet.ibm.com>
240
241 * ppc-opc.c: Add comment accidentally removed by old commit.
242 (MTMSRD_L): Delete.
243
40f77f82
AM		 2442015-06-04 Peter Bergner <bergner@vnet.ibm.com>
245
246 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
247
13be46a2
NC		 2482015-06-04 Nick Clifton <nickc@redhat.com>
249
250 PR 18474
251 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
252
ddfded2f
MW		 2532015-06-02 Matthew Wahab <matthew.wahab@arm.com>
254
255 * arm-dis.c (arm_opcodes): Add "setpan".
256 (thumb_opcodes): Add "setpan".
257
1af1dd51
MW		 2582015-06-02 Matthew Wahab <matthew.wahab@arm.com>
259
260 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
261 macros.
262
9e1f0fa7
MW		 2632015-06-02 Matthew Wahab <matthew.wahab@arm.com>
264
265 * aarch64-tbl.h (aarch64_feature_rdma): New.
266 (RDMA): New.
267 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
268 * aarch64-asm-2.c: Regenerate.
269 * aarch64-dis-2.c: Regenerate.
270 * aarch64-opc-2.c: Regenerate.
271
290806fd
MW		 2722015-06-02 Matthew Wahab <matthew.wahab@arm.com>
273
274 * aarch64-tbl.h (aarch64_feature_lor): New.
275 (LOR): New.
276 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
277 "stllrb", "stllrh".
278 * aarch64-asm-2.c: Regenerate.
279 * aarch64-dis-2.c: Regenerate.
280 * aarch64-opc-2.c: Regenerate.
281
f21cce2c
MW		 2822015-06-01 Matthew Wahab <matthew.wahab@arm.com>
283
284 * aarch64-opc.c (F_ARCHEXT): New.
285 (aarch64_sys_regs): Add "pan".
286 (aarch64_sys_reg_supported_p): New.
287 (aarch64_pstatefields): Add "pan".
288 (aarch64_pstatefield_supported_p): New.
289
d194d186
JB		 2902015-06-01 Jan Beulich <jbeulich@suse.com>
291
292 * i386-tbl.h: Regenerate.
293
3a8547d2
JB		 2942015-06-01 Jan Beulich <jbeulich@suse.com>
295
296 * i386-dis.c (print_insn): Swap rounding mode specifier and
297 general purpose register in Intel mode.
298
015c54d5
JB		 2992015-06-01 Jan Beulich <jbeulich@suse.com>
300
301 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
302 * i386-tbl.h: Regenerate.
303
071f0063
L		 3042015-05-18 H.J. Lu <hongjiu.lu@intel.com>
305
306 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
307 * i386-init.h: Regenerated.
308
5db04b09
L		 3092015-05-15 H.J. Lu <hongjiu.lu@intel.com>
310
311 PR binutis/18386
312 * i386-dis.c: Add comments for '@'.
313 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
314 (enum x86_64_isa): New.
315 (isa64): Likewise.
316 (print_i386_disassembler_options): Add amd64 and intel64.
317 (print_insn): Handle amd64 and intel64.
318 (putop): Handle '@'.
319 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
320 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
321 * i386-opc.h (AMD64): New.
322 (CpuIntel64): Likewise.
323 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
324 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
325 Mark direct call/jmp without Disp16|Disp32 as Intel64.
326 * i386-init.h: Regenerated.
327 * i386-tbl.h: Likewise.
328
4bc0608a
PB		 3292015-05-14 Peter Bergner <bergner@vnet.ibm.com>
330
331 * ppc-opc.c (IH) New define.
332 (powerpc_opcodes) <wait>: Do not enable for POWER7.
333 <tlbie>: Add RS operand for POWER7.
334 <slbia>: Add IH operand for POWER6.
335
70cead07
L		 3362015-05-11 H.J. Lu <hongjiu.lu@intel.com>
337
338 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
339 direct branch.
340 (jmp): Likewise.
341 * i386-tbl.h: Regenerated.
342
7b6d09fb
L		 3432015-05-11 H.J. Lu <hongjiu.lu@intel.com>
344
345 * configure.ac: Support bfd_iamcu_arch.
346 * disassemble.c (disassembler): Support bfd_iamcu_arch.
347 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
348 CPU_IAMCU_COMPAT_FLAGS.
349 (cpu_flags): Add CpuIAMCU.
350 * i386-opc.h (CpuIAMCU): New.
351 (i386_cpu_flags): Add cpuiamcu.
352 * configure: Regenerated.
353 * i386-init.h: Likewise.
354 * i386-tbl.h: Likewise.
355
31955f99
L		 3562015-05-08 H.J. Lu <hongjiu.lu@intel.com>
357
358 PR binutis/18386
359 * i386-dis.c (X86_64_E8): New.
360 (X86_64_E9): Likewise.
361 Update comments on 'T', 'U', 'V'. Add comments for '^'.
362 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
363 (x86_64_table): Add X86_64_E8 and X86_64_E9.
364 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
365 (putop): Handle '^'.
366 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
367 REX_W.
368
0952813b
DD		 3692015-04-30 DJ Delorie <dj@redhat.com>
370
371 * disassemble.c (disassembler): Choose suitable disassembler based
372 on E_ABI.
373 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
374 it to decode mul/div insns.
375 * rl78-decode.c: Regenerate.
376 * rl78-dis.c (print_insn_rl78): Rename to...
377 (print_insn_rl78_common): ...this, take ISA parameter.
378 (print_insn_rl78): New.
379 (print_insn_rl78_g10): New.
380 (print_insn_rl78_g13): New.
381 (print_insn_rl78_g14): New.
382 (rl78_get_disassembler): New.
383
f9d3ecaa
NC		 3842015-04-29 Nick Clifton <nickc@redhat.com>
385
386 * po/fr.po: Updated French translation.
387
4fff86c5
PB		 3882015-04-27 Peter Bergner <bergner@vnet.ibm.com>
389
390 * ppc-opc.c (DCBT_EO): New define.
391 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
392 <lharx>: Likewise.
393 <stbcx.>: Likewise.
394 <sthcx.>: Likewise.
395 <waitrsv>: Do not enable for POWER7 and later.
396 <waitimpl>: Likewise.
397 <dcbt>: Default to the two operand form of the instruction for all
398 "old" cpus. For "new" cpus, use the operand ordering that matches
399 whether the cpu is server or embedded.
400 <dcbtst>: Likewise.
401
3b78cfe1
AK		 4022015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
403
404 * s390-opc.c: New instruction type VV0UU2.
405 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
406 and WFC.
407
04d824a4
JB		 4082015-04-23 Jan Beulich <jbeulich@suse.com>
409
410 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
411 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
412 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
413 (vfpclasspd, vfpclassps): Add %XZ.
414
09708981
L		 4152015-04-15 H.J. Lu <hongjiu.lu@intel.com>
416
417 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
418 (PREFIX_UD_REPZ): Likewise.
419 (PREFIX_UD_REPNZ): Likewise.
420 (PREFIX_UD_DATA): Likewise.
421 (PREFIX_UD_ADDR): Likewise.
422 (PREFIX_UD_LOCK): Likewise.
423
3888916d
L		 4242015-04-15 H.J. Lu <hongjiu.lu@intel.com>
425
426 * i386-dis.c (prefix_requirement): Removed.
427 (print_insn): Don't set prefix_requirement. Check
428 dp->prefix_requirement instead of prefix_requirement.
429
f24bcbaa
L		 4302015-04-15 H.J. Lu <hongjiu.lu@intel.com>
431
432 PR binutils/17898
433 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
434 (PREFIX_MOD_0_0FC7_REG_6): This.
435 (PREFIX_MOD_3_0FC7_REG_6): New.
436 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
437 (prefix_table): Replace PREFIX_0FC7_REG_6 with
438 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
439 PREFIX_MOD_3_0FC7_REG_7.
440 (mod_table): Replace PREFIX_0FC7_REG_6 with
441 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
442 PREFIX_MOD_3_0FC7_REG_7.
443
507bd325
L		 4442015-04-15 H.J. Lu <hongjiu.lu@intel.com>
445
446 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
447 (PREFIX_MANDATORY_REPNZ): Likewise.
448 (PREFIX_MANDATORY_DATA): Likewise.
449 (PREFIX_MANDATORY_ADDR): Likewise.
450 (PREFIX_MANDATORY_LOCK): Likewise.
451 (PREFIX_MANDATORY): Likewise.
452 (PREFIX_UD_SHIFT): Set to 8
453 (PREFIX_UD_REPZ): Updated.
454 (PREFIX_UD_REPNZ): Likewise.
455 (PREFIX_UD_DATA): Likewise.
456 (PREFIX_UD_ADDR): Likewise.
457 (PREFIX_UD_LOCK): Likewise.
458 (PREFIX_IGNORED_SHIFT): New.
459 (PREFIX_IGNORED_REPZ): Likewise.
460 (PREFIX_IGNORED_REPNZ): Likewise.
461 (PREFIX_IGNORED_DATA): Likewise.
462 (PREFIX_IGNORED_ADDR): Likewise.
463 (PREFIX_IGNORED_LOCK): Likewise.
464 (PREFIX_OPCODE): Likewise.
465 (PREFIX_IGNORED): Likewise.
466 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
467 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
468 (three_byte_table): Likewise.
469 (mod_table): Likewise.
470 (mandatory_prefix): Renamed to ...
471 (prefix_requirement): This.
472 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
473 Update PREFIX_90 entry.
474 (get_valid_dis386): Check prefix_requirement to see if a prefix
475 should be ignored.
476 (print_insn): Replace mandatory_prefix with prefix_requirement.
477
f0fba320
RL		 4782015-04-15 Renlin Li <renlin.li@arm.com>
479
480 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
481 use it for ssat and ssat16.
482 (print_insn_thumb32): Add handle case for 'D' control code.
483
bf890a93
IT		 4842015-04-06 Ilya Tocar <ilya.tocar@intel.com>
485 H.J. Lu <hongjiu.lu@intel.com>
486
487 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
488 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
489 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
490 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
491 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
492 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
493 Fill prefix_requirement field.
494 (struct dis386): Add prefix_requirement field.
495 (dis386): Fill prefix_requirement field.
496 (dis386_twobyte): Ditto.
497 (twobyte_has_mandatory_prefix_: Remove.
498 (reg_table): Fill prefix_requirement field.
499 (prefix_table): Ditto.
500 (x86_64_table): Ditto.
501 (three_byte_table): Ditto.
502 (xop_table): Ditto.
503 (vex_table): Ditto.
504 (vex_len_table): Ditto.
505 (vex_w_table): Ditto.
506 (mod_table): Ditto.
507 (bad_opcode): Ditto.
508 (print_insn): Use prefix_requirement.
509 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
510 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
511 (float_reg): Ditto.
512
2f783c1f
MF		 5132015-03-30 Mike Frysinger <vapier@gentoo.org>
514
515 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
516
b9d94d62
L		 5172015-03-29 H.J. Lu <hongjiu.lu@intel.com>
518
519 * Makefile.in: Regenerated.
520
27c49e9a
AB		 5212015-03-25 Anton Blanchard <anton@samba.org>
522
523 * ppc-dis.c (disassemble_init_powerpc): Only initialise
524 powerpc_opcd_indices and vle_opcd_indices once.
525
c4e676f1
AB		 5262015-03-25 Anton Blanchard <anton@samba.org>
527
528 * ppc-opc.c (powerpc_opcodes): Add slbfee.
529
823d2571
TG		 5302015-03-24 Terry Guo <terry.guo@arm.com>
531
532 * arm-dis.c (opcode32): Updated to use new arm feature struct.
533 (opcode16): Likewise.
534 (coprocessor_opcodes): Replace bit with feature struct.
535 (neon_opcodes): Likewise.
536 (arm_opcodes): Likewise.
537 (thumb_opcodes): Likewise.
538 (thumb32_opcodes): Likewise.
539 (print_insn_coprocessor): Likewise.
540 (print_insn_arm): Likewise.
541 (select_arm_features): Follow new feature struct.
542
029f3522
GG		 5432015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
544
545 * i386-dis.c (rm_table): Add clzero.
546 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
547 Add CPU_CLZERO_FLAGS.
548 (cpu_flags): Add CpuCLZERO.
549 * i386-opc.h: Add CpuCLZERO.
550 * i386-opc.tbl: Add clzero.
551 * i386-init.h: Re-generated.
552 * i386-tbl.h: Re-generated.
553
6914869a
AB		 5542015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
555
556 * mips-opc.c (decode_mips_operand): Fix constraint issues
557 with u and y operands.
558
21e20815
AB		 5592015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
560
561 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
562
6b1d7593
AK		 5632015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
564
565 * s390-opc.c: Add new IBM z13 instructions.
566 * s390-opc.txt: Likewise.
567
c8f89a34
JW		 5682015-03-10 Renlin Li <renlin.li@arm.com>
569
570 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
571 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
572 related alias.
573 * aarch64-asm-2.c: Regenerate.
574 * aarch64-dis-2.c: Likewise.
575 * aarch64-opc-2.c: Likewise.
576
d8282f0e
JW		 5772015-03-03 Jiong Wang <jiong.wang@arm.com>
578
579 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
580
ac994365
OE		 5812015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
582
583 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
584 arch_sh_up.
585 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
586 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
587
fd63f640
V		 5882015-02-23 Vinay <Vinay.G@kpit.com>
589
590 * rl78-decode.opc (MOV): Added space between two operands for
591 'mov' instruction in index addressing mode.
592 * rl78-decode.c: Regenerate.
593
f63c1776
PA		 5942015-02-19 Pedro Alves <palves@redhat.com>
595
596 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
597
07774fcc
PA		 5982015-02-10 Pedro Alves <palves@redhat.com>
599 Tom Tromey <tromey@redhat.com>
600
601 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
602 microblaze_and, microblaze_xor.
603 * microblaze-opc.h (opcodes): Adjust.
604
3f8107ab
AM		 6052015-01-28 James Bowman <james.bowman@ftdichip.com>
606
607 * Makefile.am: Add FT32 files.
608 * configure.ac: Handle FT32.
609 * disassemble.c (disassembler): Call print_insn_ft32.
610 * ft32-dis.c: New file.
611 * ft32-opc.c: New file.
612 * Makefile.in: Regenerate.
613 * configure: Regenerate.
614 * po/POTFILES.in: Regenerate.
615
e5fe4957
KLC		 6162015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
617
618 * nds32-asm.c (keyword_sr): Add new system registers.
619
1e2e8c52
AK		 6202015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
621
622 * s390-dis.c (s390_extract_operand): Support vector register
623 operands.
624 (s390_print_insn_with_opcode): Support new operands types and add
625 new handling of optional operands.
626 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
627 and include opcode/s390.h instead.
628 (struct op_struct): New field `flags'.
629 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
630 (dumpTable): Dump flags.
631 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
632 string.
633 * s390-opc.c: Add new operands types, instruction formats, and
634 instruction masks.
635 (s390_opformats): Add new formats for .insn.
636 * s390-opc.txt: Add new instructions.
637
b90efa5b 6382015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 639
b90efa5b 640 Update year range in copyright notice of all files.
bffb6004 641
b90efa5b 642For older changes see ChangeLog-2014
252b5132 643\f
b90efa5b 644Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 645
646Copying and distribution of this file, with or without modification,
647are permitted in any medium without royalty provided the copyright
648notice and this notice are preserved.
649
252b5132 650Local Variables:
2f6d2f85
NC		 651mode: change-log
652left-margin: 8
653fill-column: 74
252b5132
RH		 654version-control: never
655End:
GDB Binutils - Deliverables
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