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6fd3a02d
PB		 12016-06-22 Peter Bergner <bergner@vnet.ibm.com>
2
3 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
4 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
5 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
6 xor3>: New mnemonics.
7 <setb>: Change to a VX form instruction.
8 (insert_sh6): Add support for rldixor.
9 (extract_sh6): Likewise.
10
6b477896
TS		 112016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
12
13 * arc-ext.h: Wrap in extern C.
14
bdd582db
GM		 152016-06-21 Graham Markall <graham.markall@embecosm.com>
16
17 * arc-dis.c (arc_insn_length): Add comment on instruction length.
18 Use same method for determining instruction length on ARC700 and
19 NPS-400.
20 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
21 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
22 with the NPS400 subclass.
23 * arc-opc.c: Likewise.
24
96074adc
JM		 252016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
26
27 * sparc-opc.c (rdasr): New macro.
28 (wrasr): Likewise.
29 (rdpr): Likewise.
30 (wrpr): Likewise.
31 (rdhpr): Likewise.
32 (wrhpr): Likewise.
33 (sparc_opcodes): Use the macros above to fix and expand the
34 definition of read/write instructions from/to
35 asr/privileged/hyperprivileged instructions.
36 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
37 %hva_mask_nz. Prefer softint_set and softint_clear over
38 set_softint and clear_softint.
39 (print_insn_sparc): Support %ver in Rd.
40
7a10c22f
JM		 412016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
42
43 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
44 architecture according to the hardware capabilities they require.
45
4f26fb3a
JM		 462016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
47
48 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
49 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
50 bfd_mach_sparc_v9{c,d,e,v,m}.
51 * sparc-opc.c (MASK_V9C): Define.
52 (MASK_V9D): Likewise.
53 (MASK_V9E): Likewise.
54 (MASK_V9V): Likewise.
55 (MASK_V9M): Likewise.
56 (v6): Add MASK_V9{C,D,E,V,M}.
57 (v6notlet): Likewise.
58 (v7): Likewise.
59 (v8): Likewise.
60 (v9): Likewise.
61 (v9andleon): Likewise.
62 (v9a): Likewise.
63 (v9b): Likewise.
64 (v9c): Define.
65 (v9d): Likewise.
66 (v9e): Likewise.
67 (v9v): Likewise.
68 (v9m): Likewise.
69 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
70
3ee6e4fb
NC		 712016-06-15 Nick Clifton <nickc@redhat.com>
72
73 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
74 constants to match expected behaviour.
75 (nds32_parse_opcode): Likewise. Also for whitespace.
76
02f3be19
AB		 772016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
78
79 * arc-opc.c (extract_rhv1): Extract value from insn.
80
6f9f37ed 812016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 82
83 * arc-nps400-tbl.h: Add ldbit instruction.
84 * arc-opc.c: Add flag classes required for ldbit.
85
6f9f37ed 862016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 87
88 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
89 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
90 support the above instructions.
91
6f9f37ed 922016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 93
94 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
95 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
96 csma, cbba, zncv, and hofs.
97 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
98 support the above instructions.
99
1002016-06-06 Graham Markall <graham.markall@embecosm.com>
101
102 * arc-nps400-tbl.h: Add andab and orab instructions.
103
1042016-06-06 Graham Markall <graham.markall@embecosm.com>
105
106 * arc-nps400-tbl.h: Add addl-like instructions.
107
1082016-06-06 Graham Markall <graham.markall@embecosm.com>
109
110 * arc-nps400-tbl.h: Add mxb and imxb instructions.
111
1122016-06-06 Graham Markall <graham.markall@embecosm.com>
113
114 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
115 instructions.
116
b2cc3f6f
AK		 1172016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
118
119 * s390-dis.c (option_use_insn_len_bits_p): New file scope
120 variable.
121 (init_disasm): Handle new command line option "insnlength".
122 (print_s390_disassembler_options): Mention new option in help
123 output.
124 (print_insn_s390): Use the encoded insn length when dumping
125 unknown instructions.
126
1857fe72
DC		 1272016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
128
129 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
130 to the address and set as symbol address for LDS/ STS immediate operands.
131
14b57c7c
AM		 1322016-06-07 Alan Modra <amodra@gmail.com>
133
134 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
135 cpu for "vle" to e500.
136 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
137 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
138 (PPCNONE): Delete, substitute throughout.
139 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
140 except for major opcode 4 and 31.
141 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
142
4d1464f2
MW		 1432016-06-07 Matthew Wahab <matthew.wahab@arm.com>
144
145 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
146 ARM_EXT_RAS in relevant entries.
147
026122a6
PB		 1482016-06-03 Peter Bergner <bergner@vnet.ibm.com>
149
150 PR binutils/20196
151 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
152 opcodes for E6500.
153
07f5af7d
L		 1542016-06-03 H.J. Lu <hongjiu.lu@intel.com>
155
156 PR binutis/18386
157 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
158 (indir_v_mode): New.
159 Add comments for '&'.
160 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
161 (putop): Handle '&'.
162 (intel_operand_size): Handle indir_v_mode.
163 (OP_E_register): Likewise.
164 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
165 64-bit indirect call/jmp for AMD64.
166 * i386-tbl.h: Regenerated
167
4eb6f892
AB		 1682016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
169
170 * arc-dis.c (struct arc_operand_iterator): New structure.
171 (find_format_from_table): All the old content from find_format,
172 with some minor adjustments, and parameter renaming.
173 (find_format_long_instructions): New function.
174 (find_format): Rewritten.
175 (arc_insn_length): Add LSB parameter.
176 (extract_operand_value): New function.
177 (operand_iterator_next): New function.
178 (print_insn_arc): Use new functions to find opcode, and iterator
179 over operands.
180 * arc-opc.c (insert_nps_3bit_dst_short): New function.
181 (extract_nps_3bit_dst_short): New function.
182 (insert_nps_3bit_src2_short): New function.
183 (extract_nps_3bit_src2_short): New function.
184 (insert_nps_bitop1_size): New function.
185 (extract_nps_bitop1_size): New function.
186 (insert_nps_bitop2_size): New function.
187 (extract_nps_bitop2_size): New function.
188 (insert_nps_bitop_mod4_msb): New function.
189 (extract_nps_bitop_mod4_msb): New function.
190 (insert_nps_bitop_mod4_lsb): New function.
191 (extract_nps_bitop_mod4_lsb): New function.
192 (insert_nps_bitop_dst_pos3_pos4): New function.
193 (extract_nps_bitop_dst_pos3_pos4): New function.
194 (insert_nps_bitop_ins_ext): New function.
195 (extract_nps_bitop_ins_ext): New function.
196 (arc_operands): Add new operands.
197 (arc_long_opcodes): New global array.
198 (arc_num_long_opcodes): New global.
199 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
200
1fe0971e
TS		 2012016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
202
203 * nds32-asm.h: Add extern "C".
204 * sh-opc.h: Likewise.
205
315f180f
GM		 2062016-06-01 Graham Markall <graham.markall@embecosm.com>
207
208 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
209 0,b,limm to the rflt instruction.
210
a2b5fccc
TS		 2112016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
212
213 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
214 constant.
215
0cbd0046
L		 2162016-05-29 H.J. Lu <hongjiu.lu@intel.com>
217
218 PR gas/20145
219 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
220 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
221 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
222 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
223 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
224 * i386-init.h: Regenerated.
225
1848e567
L		 2262016-05-27 H.J. Lu <hongjiu.lu@intel.com>
227
228 PR gas/20145
229 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
230 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
231 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
232 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
233 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
234 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
235 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
236 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
237 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
238 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
239 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
240 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
241 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
242 CpuRegMask for AVX512.
243 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
244 and CpuRegMask.
245 (set_bitfield_from_cpu_flag_init): New function.
246 (set_bitfield): Remove const on f. Call
247 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
248 * i386-opc.h (CpuRegMMX): New.
249 (CpuRegXMM): Likewise.
250 (CpuRegYMM): Likewise.
251 (CpuRegZMM): Likewise.
252 (CpuRegMask): Likewise.
253 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
254 and cpuregmask.
255 * i386-init.h: Regenerated.
256 * i386-tbl.h: Likewise.
257
e92bae62
L		 2582016-05-27 H.J. Lu <hongjiu.lu@intel.com>
259
260 PR gas/20154
261 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
262 (opcode_modifiers): Add AMD64 and Intel64.
263 (main): Properly verify CpuMax.
264 * i386-opc.h (CpuAMD64): Removed.
265 (CpuIntel64): Likewise.
266 (CpuMax): Set to CpuNo64.
267 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
268 (AMD64): New.
269 (Intel64): Likewise.
270 (i386_opcode_modifier): Add amd64 and intel64.
271 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
272 on call and jmp.
273 * i386-init.h: Regenerated.
274 * i386-tbl.h: Likewise.
275
e89c5eaa
L		 2762016-05-27 H.J. Lu <hongjiu.lu@intel.com>
277
278 PR gas/20154
279 * i386-gen.c (main): Fail if CpuMax is incorrect.
280 * i386-opc.h (CpuMax): Set to CpuIntel64.
281 * i386-tbl.h: Regenerated.
282
77d66e7b
NC		 2832016-05-27 Nick Clifton <nickc@redhat.com>
284
285 PR target/20150
286 * msp430-dis.c (msp430dis_read_two_bytes): New function.
287 (msp430dis_opcode_unsigned): New function.
288 (msp430dis_opcode_signed): New function.
289 (msp430_singleoperand): Use the new opcode reading functions.
290 Only disassenmble bytes if they were successfully read.
291 (msp430_doubleoperand): Likewise.
292 (msp430_branchinstr): Likewise.
293 (msp430x_callx_instr): Likewise.
294 (print_insn_msp430): Check that it is safe to read bytes before
295 attempting disassembly. Use the new opcode reading functions.
296
19dfcc89
PB		 2972016-05-26 Peter Bergner <bergner@vnet.ibm.com>
298
299 * ppc-opc.c (CY): New define. Document it.
300 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
301
f3ad7637
L		 3022016-05-25 H.J. Lu <hongjiu.lu@intel.com>
303
304 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
305 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
306 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
307 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
308 CPU_ANY_AVX_FLAGS.
309 * i386-init.h: Regenerated.
310
f1360d58
L		 3112016-05-25 H.J. Lu <hongjiu.lu@intel.com>
312
313 PR gas/20141
314 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
315 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
316 * i386-init.h: Regenerated.
317
293f5f65
L		 3182016-05-25 H.J. Lu <hongjiu.lu@intel.com>
319
320 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
321 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
322 * i386-init.h: Regenerated.
323
d9eca1df
CZ		 3242016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
325
326 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
327 information.
328 (print_insn_arc): Set insn_type information.
329 * arc-opc.c (C_CC): Add F_CLASS_COND.
330 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
331 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
332 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
333 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
334 (brne, brne_s, jeq_s, jne_s): Likewise.
335
87789e08
CZ		 3362016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
337
338 * arc-tbl.h (neg): New instruction variant.
339
c810e0b8
CZ		 3402016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
341
342 * arc-dis.c (find_format, find_format, get_auxreg)
343 (print_insn_arc): Changed.
344 * arc-ext.h (INSERT_XOP): Likewise.
345
3d207518
TS		 3462016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
347
348 * tic54x-dis.c (sprint_mmr): Adjust.
349 * tic54x-opc.c: Likewise.
350
514e58b7
AM		 3512016-05-19 Alan Modra <amodra@gmail.com>
352
353 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
354
e43de63c
AM		 3552016-05-19 Alan Modra <amodra@gmail.com>
356
357 * ppc-opc.c: Formatting.
358 (NSISIGNOPT): Define.
359 (powerpc_opcodes <subis>): Use NSISIGNOPT.
360
1401d2fe
MR		 3612016-05-18 Maciej W. Rozycki <macro@imgtec.com>
362
363 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
364 replacing references to `micromips_ase' throughout.
365 (_print_insn_mips): Don't use file-level microMIPS annotation to
366 determine the disassembly mode with the symbol table.
367
1178da44
PB		 3682016-05-13 Peter Bergner <bergner@vnet.ibm.com>
369
370 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
371
8f4f9071
MF		 3722016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
373
374 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
375 mips64r6.
376 * mips-opc.c (D34): New macro.
377 (mips_builtin_opcodes): Define bposge32c for DSPr3.
378
8bc52696
AF		 3792016-05-10 Alexander Fomin <alexander.fomin@intel.com>
380
381 * i386-dis.c (prefix_table): Add RDPID instruction.
382 * i386-gen.c (cpu_flag_init): Add RDPID flag.
383 (cpu_flags): Add RDPID bitfield.
384 * i386-opc.h (enum): Add RDPID element.
385 (i386_cpu_flags): Add RDPID field.
386 * i386-opc.tbl: Add RDPID instruction.
387 * i386-init.h: Regenerate.
388 * i386-tbl.h: Regenerate.
389
39d911fc
TP		 3902016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
391
392 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
393 branch type of a symbol.
394 (print_insn): Likewise.
395
16a1fa25
TP		 3962016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
397
398 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
399 Mainline Security Extensions instructions.
400 (thumb_opcodes): Add entries for narrow ARMv8-M Security
401 Extensions instructions.
402 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
403 instructions.
404 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
405 special registers.
406
d751b79e
JM		 4072016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
408
409 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
410
945e0f82
CZ		 4112016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
412
413 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
414 (arcExtMap_genOpcode): Likewise.
415 * arc-opc.c (arg_32bit_rc): Define new variable.
416 (arg_32bit_u6): Likewise.
417 (arg_32bit_limm): Likewise.
418
20f55f38
SN		 4192016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
420
421 * aarch64-gen.c (VERIFIER): Define.
422 * aarch64-opc.c (VERIFIER): Define.
423 (verify_ldpsw): Use static linkage.
424 * aarch64-opc.h (verify_ldpsw): Remove.
425 * aarch64-tbl.h: Use VERIFIER for verifiers.
426
4bd13cde
NC		 4272016-04-28 Nick Clifton <nickc@redhat.com>
428
429 PR target/19722
430 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
431 * aarch64-opc.c (verify_ldpsw): New function.
432 * aarch64-opc.h (verify_ldpsw): New prototype.
433 * aarch64-tbl.h: Add initialiser for verifier field.
434 (LDPSW): Set verifier to verify_ldpsw.
435
c0f92bf9
L		 4362016-04-23 H.J. Lu <hongjiu.lu@intel.com>
437
438 PR binutils/19983
439 PR binutils/19984
440 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
441 smaller than address size.
442
e6c7cdec
TS		 4432016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
444
445 * alpha-dis.c: Regenerate.
446 * crx-dis.c: Likewise.
447 * disassemble.c: Likewise.
448 * epiphany-opc.c: Likewise.
449 * fr30-opc.c: Likewise.
450 * frv-opc.c: Likewise.
451 * ip2k-opc.c: Likewise.
452 * iq2000-opc.c: Likewise.
453 * lm32-opc.c: Likewise.
454 * lm32-opinst.c: Likewise.
455 * m32c-opc.c: Likewise.
456 * m32r-opc.c: Likewise.
457 * m32r-opinst.c: Likewise.
458 * mep-opc.c: Likewise.
459 * mt-opc.c: Likewise.
460 * or1k-opc.c: Likewise.
461 * or1k-opinst.c: Likewise.
462 * tic80-opc.c: Likewise.
463 * xc16x-opc.c: Likewise.
464 * xstormy16-opc.c: Likewise.
465
537aefaf
AB		 4662016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
467
468 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
469 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
470 calcsd, and calcxd instructions.
471 * arc-opc.c (insert_nps_bitop_size): Delete.
472 (extract_nps_bitop_size): Delete.
473 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
474 (extract_nps_qcmp_m3): Define.
475 (extract_nps_qcmp_m2): Define.
476 (extract_nps_qcmp_m1): Define.
477 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
478 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
479 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
480 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
481 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
482 NPS_QCMP_M3.
483
c8f785f2
AB		 4842016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
485
486 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
487
6fd8e7c2
L		 4882016-04-15 H.J. Lu <hongjiu.lu@intel.com>
489
490 * Makefile.in: Regenerated with automake 1.11.6.
491 * aclocal.m4: Likewise.
492
4b0c052e
AB		 4932016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
494
495 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
496 instructions.
497 * arc-opc.c (insert_nps_cmem_uimm16): New function.
498 (extract_nps_cmem_uimm16): New function.
499 (arc_operands): Add NPS_XLDST_UIMM16 operand.
500
cb040366
AB		 5012016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
502
503 * arc-dis.c (arc_insn_length): New function.
504 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
505 (find_format): Change insnLen parameter to unsigned.
506
accc0180
NC		 5072016-04-13 Nick Clifton <nickc@redhat.com>
508
509 PR target/19937
510 * v850-opc.c (v850_opcodes): Correct masks for long versions of
511 the LD.B and LD.BU instructions.
512
f36e33da
CZ		 5132016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
514
515 * arc-dis.c (find_format): Check for extension flags.
516 (print_flags): New function.
517 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
518 .extAuxRegister.
519 * arc-ext.c (arcExtMap_coreRegName): Use
520 LAST_EXTENSION_CORE_REGISTER.
521 (arcExtMap_coreReadWrite): Likewise.
522 (dump_ARC_extmap): Update printing.
523 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
524 (arc_aux_regs): Add cpu field.
525 * arc-regs.h: Add cpu field, lower case name aux registers.
526
1c2e355e
CZ		 5272016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
528
529 * arc-tbl.h: Add rtsc, sleep with no arguments.
530
b99747ae
CZ		 5312016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
532
533 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
534 Initialize.
535 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
536 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
537 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
538 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
539 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
540 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
541 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
542 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
543 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
544 (arc_opcode arc_opcodes): Null terminate the array.
545 (arc_num_opcodes): Remove.
546 * arc-ext.h (INSERT_XOP): Define.
547 (extInstruction_t): Likewise.
548 (arcExtMap_instName): Delete.
549 (arcExtMap_insn): New function.
550 (arcExtMap_genOpcode): Likewise.
551 * arc-ext.c (ExtInstruction): Remove.
552 (create_map): Zero initialize instruction fields.
553 (arcExtMap_instName): Remove.
554 (arcExtMap_insn): New function.
555 (dump_ARC_extmap): More info while debuging.
556 (arcExtMap_genOpcode): New function.
557 * arc-dis.c (find_format): New function.
558 (print_insn_arc): Use find_format.
559 (arc_get_disassembler): Enable dump_ARC_extmap only when
560 debugging.
561
92708cec
MR		 5622016-04-11 Maciej W. Rozycki <macro@imgtec.com>
563
564 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
565 instruction bits out.
566
a42a4f84
AB		 5672016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
568
569 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
570 * arc-opc.c (arc_flag_operands): Add new flags.
571 (arc_flag_classes): Add new classes.
572
1328504b
AB		 5732016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
574
575 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
576
820f03ff
AB		 5772016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
578
579 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
580 encode1, rflt, crc16, and crc32 instructions.
581 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
582 (arc_flag_classes): Add C_NPS_R.
583 (insert_nps_bitop_size_2b): New function.
584 (extract_nps_bitop_size_2b): Likewise.
585 (insert_nps_bitop_uimm8): Likewise.
586 (extract_nps_bitop_uimm8): Likewise.
587 (arc_operands): Add new operand entries.
588
8ddf6b2a
CZ		 5892016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
590
b99747ae
CZ		 591 * arc-regs.h: Add a new subclass field. Add double assist
592 accumulator register values.
593 * arc-tbl.h: Use DPA subclass to mark the double assist
594 instructions. Use DPX/SPX subclas to mark the FPX instructions.
595 * arc-opc.c (RSP): Define instead of SP.
596 (arc_aux_regs): Add the subclass field.
8ddf6b2a 597
589a7d88
JW		 5982016-04-05 Jiong Wang <jiong.wang@arm.com>
599
600 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
601
0a191de9 6022016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 603
604 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
605 NPS_R_SRC1.
606
0a106562
AB		 6072016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
608
609 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
610 issues. No functional changes.
611
bd05ac5f
CZ		 6122016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
613
b99747ae
CZ		 614 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
615 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
616 (RTT): Remove duplicate.
617 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
618 (PCT_CONFIG*): Remove.
619 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 620
9885948f
CZ		 6212016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
622
b99747ae 623 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 624
f2dd8838
CZ		 6252016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
626
b99747ae
CZ		 627 * arc-tbl.h (invld07): Remove.
628 * arc-ext-tbl.h: New file.
629 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
630 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 631
0d2f91fe
JK		 6322016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
633
634 Fix -Wstack-usage warnings.
635 * aarch64-dis.c (print_operands): Substitute size.
636 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
637
a6b71f42
JM		 6382016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
639
640 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
641 to get a proper diagnostic when an invalid ASR register is used.
642
9780e045
NC		 6432016-03-22 Nick Clifton <nickc@redhat.com>
644
645 * configure: Regenerate.
646
e23e8ebe
AB		 6472016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
648
649 * arc-nps400-tbl.h: New file.
650 * arc-opc.c: Add top level comment.
651 (insert_nps_3bit_dst): New function.
652 (extract_nps_3bit_dst): New function.
653 (insert_nps_3bit_src2): New function.
654 (extract_nps_3bit_src2): New function.
655 (insert_nps_bitop_size): New function.
656 (extract_nps_bitop_size): New function.
657 (arc_flag_operands): Add nps400 entries.
658 (arc_flag_classes): Add nps400 entries.
659 (arc_operands): Add nps400 entries.
660 (arc_opcodes): Add nps400 include.
661
1ae8ab47
AB		 6622016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
663
664 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
665 the new class enum values.
666
8699fc3e
AB		 6672016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
668
669 * arc-dis.c (print_insn_arc): Handle nps400.
670
24740d83
AB		 6712016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
672
673 * arc-opc.c (BASE): Delete.
674
8678914f
NC		 6752016-03-18 Nick Clifton <nickc@redhat.com>
676
677 PR target/19721
678 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
679 of MOV insn that aliases an ORR insn.
680
cc933301
JW		 6812016-03-16 Jiong Wang <jiong.wang@arm.com>
682
683 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
684
f86f5863
TS		 6852016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
686
687 * mcore-opc.h: Add const qualifiers.
688 * microblaze-opc.h (struct op_code_struct): Likewise.
689 * sh-opc.h: Likewise.
690 * tic4x-dis.c (tic4x_print_indirect): Likewise.
691 (tic4x_print_op): Likewise.
692
62de1c63
AM		 6932016-03-02 Alan Modra <amodra@gmail.com>
694
d11698cd 695 * or1k-desc.h: Regenerate.
62de1c63 696 * fr30-ibld.c: Regenerate.
c697cf0b 697 * rl78-decode.c: Regenerate.
62de1c63 698
020efce5
NC		 6992016-03-01 Nick Clifton <nickc@redhat.com>
700
701 PR target/19747
702 * rl78-dis.c (print_insn_rl78_common): Fix typo.
703
b0c11777
RL		 7042016-02-24 Renlin Li <renlin.li@arm.com>
705
706 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
707 (print_insn_coprocessor): Support fp16 instructions.
708
3e309328
RL		 7092016-02-24 Renlin Li <renlin.li@arm.com>
710
711 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
712 vminnm, vrint(mpna).
713
8afc7bea
RL		 7142016-02-24 Renlin Li <renlin.li@arm.com>
715
716 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
717 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
718
4fd7268a
L		 7192016-02-15 H.J. Lu <hongjiu.lu@intel.com>
720
721 * i386-dis.c (print_insn): Parenthesize expression to prevent
722 truncated addresses.
723 (OP_J): Likewise.
724
4670103e
CZ		 7252016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
726 Janek van Oirschot <jvanoirs@synopsys.com>
727
b99747ae
CZ		 728 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
729 variable.
4670103e 730
c1d9289f
NC		 7312016-02-04 Nick Clifton <nickc@redhat.com>
732
733 PR target/19561
734 * msp430-dis.c (print_insn_msp430): Add a special case for
735 decoding an RRC instruction with the ZC bit set in the extension
736 word.
737
a143b004
AB		 7382016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
739
740 * cgen-ibld.in (insert_normal): Rework calculation of shift.
741 * epiphany-ibld.c: Regenerate.
742 * fr30-ibld.c: Regenerate.
743 * frv-ibld.c: Regenerate.
744 * ip2k-ibld.c: Regenerate.
745 * iq2000-ibld.c: Regenerate.
746 * lm32-ibld.c: Regenerate.
747 * m32c-ibld.c: Regenerate.
748 * m32r-ibld.c: Regenerate.
749 * mep-ibld.c: Regenerate.
750 * mt-ibld.c: Regenerate.
751 * or1k-ibld.c: Regenerate.
752 * xc16x-ibld.c: Regenerate.
753 * xstormy16-ibld.c: Regenerate.
754
b89807c6
AB		 7552016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
756
757 * epiphany-dis.c: Regenerated from latest cpu files.
758
d8c823c8
MM		 7592016-02-01 Michael McConville <mmcco@mykolab.com>
760
761 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
762 test bit.
763
5bc5ae88
RL		 7642016-01-25 Renlin Li <renlin.li@arm.com>
765
766 * arm-dis.c (mapping_symbol_for_insn): New function.
767 (find_ifthen_state): Call mapping_symbol_for_insn().
768
0bff6e2d
MW		 7692016-01-20 Matthew Wahab <matthew.wahab@arm.com>
770
771 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
772 of MSR UAO immediate operand.
773
100b4f2e
MR		 7742016-01-18 Maciej W. Rozycki <macro@imgtec.com>
775
776 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
777 instruction support.
778
5c14705f
AM		 7792016-01-17 Alan Modra <amodra@gmail.com>
780
781 * configure: Regenerate.
782
4d82fe66
NC		 7832016-01-14 Nick Clifton <nickc@redhat.com>
784
785 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
786 instructions that can support stack pointer operations.
787 * rl78-decode.c: Regenerate.
788 * rl78-dis.c: Fix display of stack pointer in MOVW based
789 instructions.
790
651657fa
MW		 7912016-01-14 Matthew Wahab <matthew.wahab@arm.com>
792
793 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
794 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
795 erxtatus_el1 and erxaddr_el1.
796
105bde57
MW		 7972016-01-12 Matthew Wahab <matthew.wahab@arm.com>
798
799 * arm-dis.c (arm_opcodes): Add "esb".
800 (thumb_opcodes): Likewise.
801
afa8d405
PB		 8022016-01-11 Peter Bergner <bergner@vnet.ibm.com>
803
804 * ppc-opc.c <xscmpnedp>: Delete.
805 <xvcmpnedp>: Likewise.
806 <xvcmpnedp.>: Likewise.
807 <xvcmpnesp>: Likewise.
808 <xvcmpnesp.>: Likewise.
809
83c3256e
AS		 8102016-01-08 Andreas Schwab <schwab@linux-m68k.org>
811
812 PR gas/13050
813 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
814 addition to ISA_A.
815
6f2750fe
AM		 8162016-01-01 Alan Modra <amodra@gmail.com>
817
818 Update year range in copyright notice of all files.
819
3499769a
AM		 820For older changes see ChangeLog-2015
821\f
822Copyright (C) 2016 Free Software Foundation, Inc.
823
824Copying and distribution of this file, with or without modification,
825are permitted in any medium without royalty provided the copyright
826notice and this notice are preserved.
827
828Local Variables:
829mode: change-log
830left-margin: 8
831fill-column: 74
832version-control: never
833End:
GDB Binutils - Deliverables
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