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GENERATE_SHLIB_SCRIPT vs. EMBEDDED.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
5103274f
NC		 12019-11-04 Nick Clifton <nickc@redhat.com>
2
3 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
4 of a v850 system register. Move the v850_sreg_names array into
5 this function.
6 (get_v850_reg_name): Likewise for ordinary register names.
7 (get_v850_vreg_name): Likewise for vector register names.
8 (get_v850_cc_name): Likewise for condition codes.
9 * get_v850_float_cc_name): Likewise for floating point condition
10 codes.
11 (get_v850_cacheop_name): Likewise for cache-ops.
12 (get_v850_prefop_name): Likewise for pref-ops.
13 (disassemble): Use the new accessor functions.
14
1820262b
DB		 152019-10-30 Delia Burduv <delia.burduv@arm.com>
16
17 * aarch64-opc.c (print_immediate_offset_address): Don't print the
18 immediate for the writeback form of ldraa/ldrab if it is 0.
19 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
20 * aarch64-opc-2.c: Regenerated.
21
3cc17af5
JB		 222019-10-30 Jan Beulich <jbeulich@suse.com>
23
24 * i386-gen.c (operand_type_shorthands): Delete.
25 (operand_type_init): Expand previous shorthands.
26 (set_bitfield_from_shorthand): Rename back to ...
27 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
28 of operand_type_init[].
29 (set_bitfield): Adjust call to the above function.
30 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
31 RegXMM, RegYMM, RegZMM): Define.
32 * i386-reg.tbl: Expand prior shorthands.
33
a2cebd03
JB		 342019-10-30 Jan Beulich <jbeulich@suse.com>
35
36 * i386-gen.c (output_i386_opcode): Change order of fields
37 emitted to output.
38 * i386-opc.h (struct insn_template): Move operands field.
39 Convert extension_opcode field to unsigned short.
40 * i386-tbl.h: Re-generate.
41
507916b8
JB		 422019-10-30 Jan Beulich <jbeulich@suse.com>
43
44 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
45 of W.
46 * i386-opc.h (W): Extend comment.
47 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
48 general purpose variants not allowing for byte operands.
49 * i386-tbl.h: Re-generate.
50
efea62b4
NC		 512019-10-29 Nick Clifton <nickc@redhat.com>
52
53 * tic30-dis.c (print_branch): Correct size of operand array.
54
9adb2591
NC		 552019-10-29 Nick Clifton <nickc@redhat.com>
56
57 * d30v-dis.c (print_insn): Check that operand index is valid
58 before attempting to access the operands array.
59
993a00a9
NC		 602019-10-29 Nick Clifton <nickc@redhat.com>
61
62 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
63 locating the bit to be tested.
64
66a66a17
NC		 652019-10-29 Nick Clifton <nickc@redhat.com>
66
67 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
68 values.
69 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
70 (print_insn_s12z): Check for illegal size values.
71
1ee3542c
NC		 722019-10-28 Nick Clifton <nickc@redhat.com>
73
74 * csky-dis.c (csky_chars_to_number): Check for a negative
75 count. Use an unsigned integer to construct the return value.
76
bbf9a0b5
NC		 772019-10-28 Nick Clifton <nickc@redhat.com>
78
79 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
80 operand buffer. Set value to 15 not 13.
81 (get_register_operand): Use OPERAND_BUFFER_LEN.
82 (get_indirect_operand): Likewise.
83 (print_two_operand): Likewise.
84 (print_three_operand): Likewise.
85 (print_oar_insn): Likewise.
86
d1e304bc
NC		 872019-10-28 Nick Clifton <nickc@redhat.com>
88
89 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
90 (bit_extract_simple): Likewise.
91 (bit_copy): Likewise.
92 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
93 index_offset array are not accessed.
94
dee33451
NC		 952019-10-28 Nick Clifton <nickc@redhat.com>
96
97 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
98 operand.
99
27cee81d
NC		 1002019-10-25 Nick Clifton <nickc@redhat.com>
101
102 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
103 access to opcodes.op array element.
104
de6d8dc2
NC		 1052019-10-23 Nick Clifton <nickc@redhat.com>
106
107 * rx-dis.c (get_register_name): Fix spelling typo in error
108 message.
109 (get_condition_name, get_flag_name, get_double_register_name)
110 (get_double_register_high_name, get_double_register_low_name)
111 (get_double_control_register_name, get_double_condition_name)
112 (get_opsize_name, get_size_name): Likewise.
113
6207ed28
NC		 1142019-10-22 Nick Clifton <nickc@redhat.com>
115
116 * rx-dis.c (get_size_name): New function. Provides safe
117 access to name array.
118 (get_opsize_name): Likewise.
119 (print_insn_rx): Use the accessor functions.
120
12234dfd
NC		 1212019-10-16 Nick Clifton <nickc@redhat.com>
122
123 * rx-dis.c (get_register_name): New function. Provides safe
124 access to name array.
125 (get_condition_name, get_flag_name, get_double_register_name)
126 (get_double_register_high_name, get_double_register_low_name)
127 (get_double_control_register_name, get_double_condition_name):
128 Likewise.
129 (print_insn_rx): Use the accessor functions.
130
1d378749
NC		 1312019-10-09 Nick Clifton <nickc@redhat.com>
132
133 PR 25041
134 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
135 instructions.
136
d241b910
JB		 1372019-10-07 Jan Beulich <jbeulich@suse.com>
138
139 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
140 (cmpsd): Likewise. Move EsSeg to other operand.
141 * opcodes/i386-tbl.h: Re-generate.
142
f5c5b7c1
AM		 1432019-09-23 Alan Modra <amodra@gmail.com>
144
145 * m68k-dis.c: Include cpu-m68k.h
146
7beeaeb8
AM		 1472019-09-23 Alan Modra <amodra@gmail.com>
148
149 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
150 "elf/mips.h" earlier.
151
3f9aad11
JB		 1522018-09-20 Jan Beulich <jbeulich@suse.com>
153
154 PR gas/25012
155 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
156 with SReg operand.
157 * i386-tbl.h: Re-generate.
158
fd361982
AM		 1592019-09-18 Alan Modra <amodra@gmail.com>
160
161 * arc-ext.c: Update throughout for bfd section macro changes.
162
e0b2a78c
SM		 1632019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
164
165 * Makefile.in: Re-generate.
166 * configure: Re-generate.
167
7e9ad3a3
JW		 1682019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
169
170 * riscv-opc.c (riscv_opcodes): Change subset field
171 to insn_class field for all instructions.
172 (riscv_insn_types): Likewise.
173
bb695960
PB		 1742019-09-16 Phil Blundell <pb@pbcl.net>
175
176 * configure: Regenerated.
177
8063ab7e
MV		 1782019-09-10 Miod Vallat <miod@online.fr>
179
180 PR 24982
181 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
182
60391a25
PB		 1832019-09-09 Phil Blundell <pb@pbcl.net>
184
185 binutils 2.33 branch created.
186
f44b758d
NC		 1872019-09-03 Nick Clifton <nickc@redhat.com>
188
189 PR 24961
190 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
191 greater than zero before indexing via (bufcnt -1).
192
1e4b5e7d
NC		 1932019-09-03 Nick Clifton <nickc@redhat.com>
194
195 PR 24958
196 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
197 (MAX_SPEC_REG_NAME_LEN): Define.
198 (struct mmix_dis_info): Use defined constants for array lengths.
199 (get_reg_name): New function.
200 (get_sprec_reg_name): New function.
201 (print_insn_mmix): Use new functions.
202
c4a23bf8
SP		 2032019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
204
205 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
206 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
207 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
208
a051e2f3
KT		 2092019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
210
211 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
212 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
213 (aarch64_sys_reg_supported_p): Update checks for the above.
214
08132bdd
SP		 2152019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
216
217 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
218 cases MVE_SQRSHRL and MVE_UQRSHLL.
219 (print_insn_mve): Add case for specifier 'k' to check
220 specific bit of the instruction.
221
d88bdcb4
PA		 2222019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
223
224 PR 24854
225 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
226 encountering an unknown machine type.
227 (print_insn_arc): Handle arc_insn_length returning 0. In error
228 cases return -1 rather than calling abort.
229
bc750500
JB		 2302019-08-07 Jan Beulich <jbeulich@suse.com>
231
232 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
233 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
234 IgnoreSize.
235 * i386-tbl.h: Re-generate.
236
23d188c7
BW		 2372019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
238
239 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
240 instructions.
241
c0d6f62f
JW		 2422019-07-30 Mel Chen <mel.chen@sifive.com>
243
244 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
245 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
246
247 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
248 fscsr.
249
0f3f7167
CZ		 2502019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
251
252 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
253 and MPY class instructions.
254 (parse_option): Add nps400 option.
255 (print_arc_disassembler_options): Add nps400 info.
256
7e126ba3
CZ		 2572019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
258
259 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
260 (bspop): Likewise.
261 (modapp): Likewise.
262 * arc-opc.c (RAD_CHK): Add.
263 * arc-tbl.h: Regenerate.
264
a028026d
KT		 2652019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
266
267 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
268 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
269
ac79ff9e
NC		 2702019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
271
272 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
273 instructions as UNPREDICTABLE.
274
231097b0
JM		 2752019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
276
277 * bpf-desc.c: Regenerated.
278
1d942ae9
JB		 2792019-07-17 Jan Beulich <jbeulich@suse.com>
280
281 * i386-gen.c (static_assert): Define.
282 (main): Use it.
283 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
284 (Opcode_Modifier_Num): ... this.
285 (Mem): Delete.
286
dfd69174
JB		 2872019-07-16 Jan Beulich <jbeulich@suse.com>
288
289 * i386-gen.c (operand_types): Move RegMem ...
290 (opcode_modifiers): ... here.
291 * i386-opc.h (RegMem): Move to opcode modifer enum.
292 (union i386_operand_type): Move regmem field ...
293 (struct i386_opcode_modifier): ... here.
294 * i386-opc.tbl (RegMem): Define.
295 (mov, movq): Move RegMem on segment, control, debug, and test
296 register flavors.
297 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
298 to non-SSE2AVX flavor.
299 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
300 Move RegMem on register only flavors. Drop IgnoreSize from
301 legacy encoding flavors.
302 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
303 flavors.
304 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
305 register only flavors.
306 (vmovd): Move RegMem and drop IgnoreSize on register only
307 flavor. Change opcode and operand order to store form.
308 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
309
21df382b
JB		 3102019-07-16 Jan Beulich <jbeulich@suse.com>
311
312 * i386-gen.c (operand_type_init, operand_types): Replace SReg
313 entries.
314 * i386-opc.h (SReg2, SReg3): Replace by ...
315 (SReg): ... this.
316 (union i386_operand_type): Replace sreg fields.
317 * i386-opc.tbl (mov, ): Use SReg.
318 (push, pop): Likewies. Drop i386 and x86-64 specific segment
319 register flavors.
320 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
321 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
322
3719fd55
JM		 3232019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
324
325 * bpf-desc.c: Regenerate.
326 * bpf-opc.c: Likewise.
327 * bpf-opc.h: Likewise.
328
92434a14
JM		 3292019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
330
331 * bpf-desc.c: Regenerate.
332 * bpf-opc.c: Likewise.
333
43dd7626
HPN		 3342019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
335
336 * arm-dis.c (print_insn_coprocessor): Rename index to
337 index_operand.
338
98602811
JW		 3392019-07-05 Kito Cheng <kito.cheng@sifive.com>
340
341 * riscv-opc.c (riscv_insn_types): Add r4 type.
342
343 * riscv-opc.c (riscv_insn_types): Add b and j type.
344
345 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
346 format for sb type and correct s type.
347
01c1ee4a
RS		 3482019-07-02 Richard Sandiford <richard.sandiford@arm.com>
349
350 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
351 SVE FMOV alias of FCPY.
352
83adff69
RS		 3532019-07-02 Richard Sandiford <richard.sandiford@arm.com>
354
355 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
356 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
357
89418844
RS		 3582019-07-02 Richard Sandiford <richard.sandiford@arm.com>
359
360 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
361 registers in an instruction prefixed by MOVPRFX.
362
41be57ca
MM		 3632019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
364
365 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
366 sve_size_13 icode to account for variant behaviour of
367 pmull{t,b}.
368 * aarch64-dis-2.c: Regenerate.
369 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
370 sve_size_13 icode to account for variant behaviour of
371 pmull{t,b}.
372 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
373 (OP_SVE_VVV_Q_D): Add new qualifier.
374 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
375 (struct aarch64_opcode): Split pmull{t,b} into those requiring
376 AES and those not.
377
9d3bf266
JB		 3782019-07-01 Jan Beulich <jbeulich@suse.com>
379
380 * opcodes/i386-gen.c (operand_type_init): Remove
381 OPERAND_TYPE_VEC_IMM4 entry.
382 (operand_types): Remove Vec_Imm4.
383 * opcodes/i386-opc.h (Vec_Imm4): Delete.
384 (union i386_operand_type): Remove vec_imm4.
385 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
386 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
387
c3949f43
JB		 3882019-07-01 Jan Beulich <jbeulich@suse.com>
389
390 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
391 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
392 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
393 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
394 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
395 monitorx, mwaitx): Drop ImmExt from operand-less forms.
396 * i386-tbl.h: Re-generate.
397
5641ec01
JB		 3982019-07-01 Jan Beulich <jbeulich@suse.com>
399
400 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
401 register operands.
402 * i386-tbl.h: Re-generate.
403
79dec6b7
JB		 4042019-07-01 Jan Beulich <jbeulich@suse.com>
405
406 * i386-opc.tbl (C): New.
407 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
408 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
409 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
410 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
411 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
412 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
413 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
414 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
415 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
416 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
417 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
418 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
419 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
420 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
421 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
422 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
423 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
424 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
425 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
426 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
427 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
428 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
429 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
430 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
431 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
432 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
433 flavors.
434 * i386-tbl.h: Re-generate.
435
a0a1771e
JB		 4362019-07-01 Jan Beulich <jbeulich@suse.com>
437
438 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
439 register operands.
440 * i386-tbl.h: Re-generate.
441
cd546e7b
JB		 4422019-07-01 Jan Beulich <jbeulich@suse.com>
443
444 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
445 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
446 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
447 * i386-tbl.h: Re-generate.
448
e3bba3fc
JB		 4492019-07-01 Jan Beulich <jbeulich@suse.com>
450
451 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
452 Disp8MemShift from register only templates.
453 * i386-tbl.h: Re-generate.
454
36cc073e
JB		 4552019-07-01 Jan Beulich <jbeulich@suse.com>
456
457 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
458 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
459 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
460 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
461 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
462 EVEX_W_0F11_P_3_M_1): Delete.
463 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
464 EVEX_W_0F11_P_3): New.
465 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
466 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
467 MOD_EVEX_0F11_PREFIX_3 table entries.
468 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
469 PREFIX_EVEX_0F11 table entries.
470 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
471 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
472 EVEX_W_0F11_P_3_M_{0,1} table entries.
473
219920a7
JB		 4742019-07-01 Jan Beulich <jbeulich@suse.com>
475
476 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
477 Delete.
478
e395f487
L		 4792019-06-27 H.J. Lu <hongjiu.lu@intel.com>
480
481 PR binutils/24719
482 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
483 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
484 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
485 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
486 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
487 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
488 EVEX_LEN_0F38C7_R_6_P_2_W_1.
489 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
490 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
491 PREFIX_EVEX_0F38C6_REG_6 entries.
492 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
493 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
494 EVEX_W_0F38C7_R_6_P_2 entries.
495 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
496 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
497 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
498 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
499 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
500 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
501 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
502
2b7bcc87
JB		 5032019-06-27 Jan Beulich <jbeulich@suse.com>
504
505 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
506 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
507 VEX_LEN_0F2D_P_3): Delete.
508 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
509 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
510 (prefix_table): ... here.
511
c1dc7af5
JB		 5122019-06-27 Jan Beulich <jbeulich@suse.com>
513
514 * i386-dis.c (Iq): Delete.
515 (Id): New.
516 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
517 TBM insns.
518 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
519 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
520 (OP_E_memory): Also honor needindex when deciding whether an
521 address size prefix needs printing.
522 (OP_I): Remove handling of q_mode. Add handling of d_mode.
523
d7560e2d
JW		 5242019-06-26 Jim Wilson <jimw@sifive.com>
525
526 PR binutils/24739
527 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
528 Set info->display_endian to info->endian_code.
529
2c703856
JB		 5302019-06-25 Jan Beulich <jbeulich@suse.com>
531
532 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
533 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
534 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
535 OPERAND_TYPE_ACC64 entries.
536 * i386-init.h: Re-generate.
537
54fbadc0
JB		 5382019-06-25 Jan Beulich <jbeulich@suse.com>
539
540 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
541 Delete.
542 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
543 of dqa_mode.
544 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
545 entries here.
546 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
547 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
548
a280ab8e
JB		 5492019-06-25 Jan Beulich <jbeulich@suse.com>
550
551 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
552 variables.
553
e1a1babd
JB		 5542019-06-25 Jan Beulich <jbeulich@suse.com>
555
556 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
557 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
558 movnti.
d7560e2d 559 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 560 * i386-tbl.h: Re-generate.
561
b8364fa7
JB		 5622019-06-25 Jan Beulich <jbeulich@suse.com>
563
564 * i386-opc.tbl (and): Mark Imm8S form for optimization.
565 * i386-tbl.h: Re-generate.
566
ad692897
L		 5672019-06-21 H.J. Lu <hongjiu.lu@intel.com>
568
569 * i386-dis-evex.h: Break into ...
570 * i386-dis-evex-len.h: New file.
571 * i386-dis-evex-mod.h: Likewise.
572 * i386-dis-evex-prefix.h: Likewise.
573 * i386-dis-evex-reg.h: Likewise.
574 * i386-dis-evex-w.h: Likewise.
575 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
576 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
577 i386-dis-evex-mod.h.
578
f0a6222e
L		 5792019-06-19 H.J. Lu <hongjiu.lu@intel.com>
580
581 PR binutils/24700
582 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
583 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
584 EVEX_W_0F385B_P_2.
585 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
586 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
587 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
588 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
589 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
590 EVEX_LEN_0F385B_P_2_W_1.
591 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
592 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
593 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
594 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
595 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
596 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
597 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
598 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
599 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
600 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
601
6e1c90b7
L		 6022019-06-17 H.J. Lu <hongjiu.lu@intel.com>
603
604 PR binutils/24691
605 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
606 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
607 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
608 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
609 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
610 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
611 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
612 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
613 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
614 EVEX_LEN_0F3A43_P_2_W_1.
615 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
616 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
617 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
618 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
619 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
620 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
621 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
622 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
623 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
624 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
625 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
626 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
627
bcc5a6eb
NC		 6282019-06-14 Nick Clifton <nickc@redhat.com>
629
630 * po/fr.po; Updated French translation.
631
e4c4ac46
SH		 6322019-06-13 Stafford Horne <shorne@gmail.com>
633
634 * or1k-asm.c: Regenerated.
635 * or1k-desc.c: Regenerated.
636 * or1k-desc.h: Regenerated.
637 * or1k-dis.c: Regenerated.
638 * or1k-ibld.c: Regenerated.
639 * or1k-opc.c: Regenerated.
640 * or1k-opc.h: Regenerated.
641 * or1k-opinst.c: Regenerated.
642
a0e44ef5
PB		 6432019-06-12 Peter Bergner <bergner@linux.ibm.com>
644
645 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
646
12efd68d
L		 6472019-06-05 H.J. Lu <hongjiu.lu@intel.com>
648
649 PR binutils/24633
650 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
651 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
652 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
653 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
654 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
655 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
656 EVEX_LEN_0F3A1B_P_2_W_1.
657 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
658 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
659 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
660 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
661 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
662 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
663 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
664 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
665
63c6fc6c
L		 6662019-06-04 H.J. Lu <hongjiu.lu@intel.com>
667
668 PR binutils/24626
669 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
670 EVEX.vvvv when disassembling VEX and EVEX instructions.
671 (OP_VEX): Set vex.register_specifier to 0 after readding
672 vex.register_specifier.
673 (OP_Vex_2src_1): Likewise.
674 (OP_Vex_2src_2): Likewise.
675 (OP_LWP_E): Likewise.
676 (OP_EX_Vex): Don't check vex.register_specifier.
677 (OP_XMM_Vex): Likewise.
678
9186c494
L		 6792019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
680 Lili Cui <lili.cui@intel.com>
681
682 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
683 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
684 instructions.
685 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
686 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
687 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
688 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
689 (i386_cpu_flags): Add cpuavx512_vp2intersect.
690 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
691 * i386-init.h: Regenerated.
692 * i386-tbl.h: Likewise.
693
5d79adc4
L		 6942019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
695 Lili Cui <lili.cui@intel.com>
696
697 * doc/c-i386.texi: Document enqcmd.
698 * testsuite/gas/i386/enqcmd-intel.d: New file.
699 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
700 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
701 * testsuite/gas/i386/enqcmd.d: Likewise.
702 * testsuite/gas/i386/enqcmd.s: Likewise.
703 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
704 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
705 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
706 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
707 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
708 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
709 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
710 and x86-64-enqcmd.
711
a9d96ab9
AH		 7122019-06-04 Alan Hayward <alan.hayward@arm.com>
713
714 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
715
4f6d070a
AM		 7162019-06-03 Alan Modra <amodra@gmail.com>
717
718 * ppc-dis.c (prefix_opcd_indices): Correct size.
719
a2f4b66c
L		 7202019-05-28 H.J. Lu <hongjiu.lu@intel.com>
721
722 PR gas/24625
723 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
724 Disp8ShiftVL.
725 * i386-tbl.h: Regenerated.
726
405b5bd8
AM		 7272019-05-24 Alan Modra <amodra@gmail.com>
728
729 * po/POTFILES.in: Regenerate.
730
8acf1435
PB		 7312019-05-24 Peter Bergner <bergner@linux.ibm.com>
732 Alan Modra <amodra@gmail.com>
733
734 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
735 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
736 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
737 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
738 XTOP>): Define and add entries.
739 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
740 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
741 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
742 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
743
dd7efa79
PB		 7442019-05-24 Peter Bergner <bergner@linux.ibm.com>
745 Alan Modra <amodra@gmail.com>
746
747 * ppc-dis.c (ppc_opts): Add "future" entry.
748 (PREFIX_OPCD_SEGS): Define.
749 (prefix_opcd_indices): New array.
750 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
751 (lookup_prefix): New function.
752 (print_insn_powerpc): Handle 64-bit prefix instructions.
753 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
754 (PMRR, POWERXX): Define.
755 (prefix_opcodes): New instruction table.
756 (prefix_num_opcodes): New constant.
757
79472b45
JM		 7582019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
759
760 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
761 * configure: Regenerated.
762 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
763 and cpu/bpf.opc.
764 (HFILES): Add bpf-desc.h and bpf-opc.h.
765 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
766 bpf-ibld.c and bpf-opc.c.
767 (BPF_DEPS): Define.
768 * Makefile.in: Regenerated.
769 * disassemble.c (ARCH_bpf): Define.
770 (disassembler): Add case for bfd_arch_bpf.
771 (disassemble_init_for_target): Likewise.
772 (enum epbf_isa_attr): Define.
773 * disassemble.h: extern print_insn_bpf.
774 * bpf-asm.c: Generated.
775 * bpf-opc.h: Likewise.
776 * bpf-opc.c: Likewise.
777 * bpf-ibld.c: Likewise.
778 * bpf-dis.c: Likewise.
779 * bpf-desc.h: Likewise.
780 * bpf-desc.c: Likewise.
781
ba6cd17f
SD		 7822019-05-21 Sudakshina Das <sudi.das@arm.com>
783
784 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
785 and VMSR with the new operands.
786
e39c1607
SD		 7872019-05-21 Sudakshina Das <sudi.das@arm.com>
788
789 * arm-dis.c (enum mve_instructions): New enum
790 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
791 and cneg.
792 (mve_opcodes): New instructions as above.
793 (is_mve_encoding_conflict): Add cases for csinc, csinv,
794 csneg and csel.
795 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
796
23d00a41
SD		 7972019-05-21 Sudakshina Das <sudi.das@arm.com>
798
799 * arm-dis.c (emun mve_instructions): Updated for new instructions.
800 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
801 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
802 uqshl, urshrl and urshr.
803 (is_mve_okay_in_it): Add new instructions to TRUE list.
804 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
805 (print_insn_mve): Updated to accept new %j,
806 %<bitfield>m and %<bitfield>n patterns.
807
cd4797ee
FS		 8082019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
809
810 * mips-opc.c (mips_builtin_opcodes): Change source register
811 constraint for DAUI.
812
999b073b
NC		 8132019-05-20 Nick Clifton <nickc@redhat.com>
814
815 * po/fr.po: Updated French translation.
816
14b456f2
AV		 8172019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
818 Michael Collison <michael.collison@arm.com>
819
820 * arm-dis.c (thumb32_opcodes): Add new instructions.
821 (enum mve_instructions): Likewise.
822 (enum mve_undefined): Add new reasons.
823 (is_mve_encoding_conflict): Handle new instructions.
824 (is_mve_undefined): Likewise.
825 (is_mve_unpredictable): Likewise.
826 (print_mve_undefined): Likewise.
827 (print_mve_size): Likewise.
828
f49bb598
AV		 8292019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
830 Michael Collison <michael.collison@arm.com>
831
832 * arm-dis.c (thumb32_opcodes): Add new instructions.
833 (enum mve_instructions): Likewise.
834 (is_mve_encoding_conflict): Handle new instructions.
835 (is_mve_undefined): Likewise.
836 (is_mve_unpredictable): Likewise.
837 (print_mve_size): Likewise.
838
56858bea
AV		 8392019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
840 Michael Collison <michael.collison@arm.com>
841
842 * arm-dis.c (thumb32_opcodes): Add new instructions.
843 (enum mve_instructions): Likewise.
844 (is_mve_encoding_conflict): Likewise.
845 (is_mve_unpredictable): Likewise.
846 (print_mve_size): Likewise.
847
e523f101
AV		 8482019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
849 Michael Collison <michael.collison@arm.com>
850
851 * arm-dis.c (thumb32_opcodes): Add new instructions.
852 (enum mve_instructions): Likewise.
853 (is_mve_encoding_conflict): Handle new instructions.
854 (is_mve_undefined): Likewise.
855 (is_mve_unpredictable): Likewise.
856 (print_mve_size): Likewise.
857
66dcaa5d
AV		 8582019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
859 Michael Collison <michael.collison@arm.com>
860
861 * arm-dis.c (thumb32_opcodes): Add new instructions.
862 (enum mve_instructions): Likewise.
863 (is_mve_encoding_conflict): Handle new instructions.
864 (is_mve_undefined): Likewise.
865 (is_mve_unpredictable): Likewise.
866 (print_mve_size): Likewise.
867 (print_insn_mve): Likewise.
868
d052b9b7
AV		 8692019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
870 Michael Collison <michael.collison@arm.com>
871
872 * arm-dis.c (thumb32_opcodes): Add new instructions.
873 (print_insn_thumb32): Handle new instructions.
874
ed63aa17
AV		 8752019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
876 Michael Collison <michael.collison@arm.com>
877
878 * arm-dis.c (enum mve_instructions): Add new instructions.
879 (enum mve_undefined): Add new reasons.
880 (is_mve_encoding_conflict): Handle new instructions.
881 (is_mve_undefined): Likewise.
882 (is_mve_unpredictable): Likewise.
883 (print_mve_undefined): Likewise.
884 (print_mve_size): Likewise.
885 (print_mve_shift_n): Likewise.
886 (print_insn_mve): Likewise.
887
897b9bbc
AV		 8882019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
889 Michael Collison <michael.collison@arm.com>
890
891 * arm-dis.c (enum mve_instructions): Add new instructions.
892 (is_mve_encoding_conflict): Handle new instructions.
893 (is_mve_unpredictable): Likewise.
894 (print_mve_rotate): Likewise.
895 (print_mve_size): Likewise.
896 (print_insn_mve): Likewise.
897
1c8f2df8
AV		 8982019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
899 Michael Collison <michael.collison@arm.com>
900
901 * arm-dis.c (enum mve_instructions): Add new instructions.
902 (is_mve_encoding_conflict): Handle new instructions.
903 (is_mve_unpredictable): Likewise.
904 (print_mve_size): Likewise.
905 (print_insn_mve): Likewise.
906
d3b63143
AV		 9072019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
908 Michael Collison <michael.collison@arm.com>
909
910 * arm-dis.c (enum mve_instructions): Add new instructions.
911 (enum mve_undefined): Add new reasons.
912 (is_mve_encoding_conflict): Handle new instructions.
913 (is_mve_undefined): Likewise.
914 (is_mve_unpredictable): Likewise.
915 (print_mve_undefined): Likewise.
916 (print_mve_size): Likewise.
917 (print_insn_mve): Likewise.
918
14925797
AV		 9192019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
920 Michael Collison <michael.collison@arm.com>
921
922 * arm-dis.c (enum mve_instructions): Add new instructions.
923 (is_mve_encoding_conflict): Handle new instructions.
924 (is_mve_undefined): Likewise.
925 (is_mve_unpredictable): Likewise.
926 (print_mve_size): Likewise.
927 (print_insn_mve): Likewise.
928
c507f10b
AV		 9292019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
930 Michael Collison <michael.collison@arm.com>
931
932 * arm-dis.c (enum mve_instructions): Add new instructions.
933 (enum mve_unpredictable): Add new reasons.
934 (enum mve_undefined): Likewise.
935 (is_mve_okay_in_it): Handle new isntructions.
936 (is_mve_encoding_conflict): Likewise.
937 (is_mve_undefined): Likewise.
938 (is_mve_unpredictable): Likewise.
939 (print_mve_vmov_index): Likewise.
940 (print_simd_imm8): Likewise.
941 (print_mve_undefined): Likewise.
942 (print_mve_unpredictable): Likewise.
943 (print_mve_size): Likewise.
944 (print_insn_mve): Likewise.
945
bf0b396d
AV		 9462019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
947 Michael Collison <michael.collison@arm.com>
948
949 * arm-dis.c (enum mve_instructions): Add new instructions.
950 (enum mve_unpredictable): Add new reasons.
951 (enum mve_undefined): Likewise.
952 (is_mve_encoding_conflict): Handle new instructions.
953 (is_mve_undefined): Likewise.
954 (is_mve_unpredictable): Likewise.
955 (print_mve_undefined): Likewise.
956 (print_mve_unpredictable): Likewise.
957 (print_mve_rounding_mode): Likewise.
958 (print_mve_vcvt_size): Likewise.
959 (print_mve_size): Likewise.
960 (print_insn_mve): Likewise.
961
ef1576a1
AV		 9622019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
963 Michael Collison <michael.collison@arm.com>
964
965 * arm-dis.c (enum mve_instructions): Add new instructions.
966 (enum mve_unpredictable): Add new reasons.
967 (enum mve_undefined): Likewise.
968 (is_mve_undefined): Handle new instructions.
969 (is_mve_unpredictable): Likewise.
970 (print_mve_undefined): Likewise.
971 (print_mve_unpredictable): Likewise.
972 (print_mve_size): Likewise.
973 (print_insn_mve): Likewise.
974
aef6d006
AV		 9752019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
976 Michael Collison <michael.collison@arm.com>
977
978 * arm-dis.c (enum mve_instructions): Add new instructions.
979 (enum mve_undefined): Add new reasons.
980 (insns): Add new instructions.
981 (is_mve_encoding_conflict):
982 (print_mve_vld_str_addr): New print function.
983 (is_mve_undefined): Handle new instructions.
984 (is_mve_unpredictable): Likewise.
985 (print_mve_undefined): Likewise.
986 (print_mve_size): Likewise.
987 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
988 (print_insn_mve): Handle new operands.
989
04d54ace
AV		 9902019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
991 Michael Collison <michael.collison@arm.com>
992
993 * arm-dis.c (enum mve_instructions): Add new instructions.
994 (enum mve_unpredictable): Add new reasons.
995 (is_mve_encoding_conflict): Handle new instructions.
996 (is_mve_unpredictable): Likewise.
997 (mve_opcodes): Add new instructions.
998 (print_mve_unpredictable): Handle new reasons.
999 (print_mve_register_blocks): New print function.
1000 (print_mve_size): Handle new instructions.
1001 (print_insn_mve): Likewise.
1002
9743db03
AV		 10032019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1004 Michael Collison <michael.collison@arm.com>
1005
1006 * arm-dis.c (enum mve_instructions): Add new instructions.
1007 (enum mve_unpredictable): Add new reasons.
1008 (enum mve_undefined): Likewise.
1009 (is_mve_encoding_conflict): Handle new instructions.
1010 (is_mve_undefined): Likewise.
1011 (is_mve_unpredictable): Likewise.
1012 (coprocessor_opcodes): Move NEON VDUP from here...
1013 (neon_opcodes): ... to here.
1014 (mve_opcodes): Add new instructions.
1015 (print_mve_undefined): Handle new reasons.
1016 (print_mve_unpredictable): Likewise.
1017 (print_mve_size): Handle new instructions.
1018 (print_insn_neon): Handle vdup.
1019 (print_insn_mve): Handle new operands.
1020
143275ea
AV		 10212019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1022 Michael Collison <michael.collison@arm.com>
1023
1024 * arm-dis.c (enum mve_instructions): Add new instructions.
1025 (enum mve_unpredictable): Add new values.
1026 (mve_opcodes): Add new instructions.
1027 (vec_condnames): New array with vector conditions.
1028 (mve_predicatenames): New array with predicate suffixes.
1029 (mve_vec_sizename): New array with vector sizes.
1030 (enum vpt_pred_state): New enum with vector predication states.
1031 (struct vpt_block): New struct type for vpt blocks.
1032 (vpt_block_state): Global struct to keep track of state.
1033 (mve_extract_pred_mask): New helper function.
1034 (num_instructions_vpt_block): Likewise.
1035 (mark_outside_vpt_block): Likewise.
1036 (mark_inside_vpt_block): Likewise.
1037 (invert_next_predicate_state): Likewise.
1038 (update_next_predicate_state): Likewise.
1039 (update_vpt_block_state): Likewise.
1040 (is_vpt_instruction): Likewise.
1041 (is_mve_encoding_conflict): Add entries for new instructions.
1042 (is_mve_unpredictable): Likewise.
1043 (print_mve_unpredictable): Handle new cases.
1044 (print_instruction_predicate): Likewise.
1045 (print_mve_size): New function.
1046 (print_vec_condition): New function.
1047 (print_insn_mve): Handle vpt blocks and new print operands.
1048
f08d8ce3
AV		 10492019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1050
1051 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1052 8, 14 and 15 for Armv8.1-M Mainline.
1053
73cd51e5
AV		 10542019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1055 Michael Collison <michael.collison@arm.com>
1056
1057 * arm-dis.c (enum mve_instructions): New enum.
1058 (enum mve_unpredictable): Likewise.
1059 (enum mve_undefined): Likewise.
1060 (struct mopcode32): New struct.
1061 (is_mve_okay_in_it): New function.
1062 (is_mve_architecture): Likewise.
1063 (arm_decode_field): Likewise.
1064 (arm_decode_field_multiple): Likewise.
1065 (is_mve_encoding_conflict): Likewise.
1066 (is_mve_undefined): Likewise.
1067 (is_mve_unpredictable): Likewise.
1068 (print_mve_undefined): Likewise.
1069 (print_mve_unpredictable): Likewise.
1070 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1071 (print_insn_mve): New function.
1072 (print_insn_thumb32): Handle MVE architecture.
1073 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1074
3076e594
NC		 10752019-05-10 Nick Clifton <nickc@redhat.com>
1076
1077 PR 24538
1078 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1079 end of the table prematurely.
1080
387e7624
FS		 10812019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1082
1083 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1084 macros for R6.
1085
0067be51
AM		 10862019-05-11 Alan Modra <amodra@gmail.com>
1087
1088 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1089 when -Mraw is in effect.
1090
42e6288f
MM		 10912019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1092
1093 * aarch64-dis-2.c: Regenerate.
1094 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1095 (OP_SVE_BBB): New variant set.
1096 (OP_SVE_DDDD): New variant set.
1097 (OP_SVE_HHH): New variant set.
1098 (OP_SVE_HHHU): New variant set.
1099 (OP_SVE_SSS): New variant set.
1100 (OP_SVE_SSSU): New variant set.
1101 (OP_SVE_SHH): New variant set.
1102 (OP_SVE_SBBU): New variant set.
1103 (OP_SVE_DSS): New variant set.
1104 (OP_SVE_DHHU): New variant set.
1105 (OP_SVE_VMV_HSD_BHS): New variant set.
1106 (OP_SVE_VVU_HSD_BHS): New variant set.
1107 (OP_SVE_VVVU_SD_BH): New variant set.
1108 (OP_SVE_VVVU_BHSD): New variant set.
1109 (OP_SVE_VVV_QHD_DBS): New variant set.
1110 (OP_SVE_VVV_HSD_BHS): New variant set.
1111 (OP_SVE_VVV_HSD_BHS2): New variant set.
1112 (OP_SVE_VVV_BHS_HSD): New variant set.
1113 (OP_SVE_VV_BHS_HSD): New variant set.
1114 (OP_SVE_VVV_SD): New variant set.
1115 (OP_SVE_VVU_BHS_HSD): New variant set.
1116 (OP_SVE_VZVV_SD): New variant set.
1117 (OP_SVE_VZVV_BH): New variant set.
1118 (OP_SVE_VZV_SD): New variant set.
1119 (aarch64_opcode_table): Add sve2 instructions.
1120
28ed815a
MM		 11212019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1122
1123 * aarch64-asm-2.c: Regenerated.
1124 * aarch64-dis-2.c: Regenerated.
1125 * aarch64-opc-2.c: Regenerated.
1126 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1127 for SVE_SHLIMM_UNPRED_22.
1128 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1129 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1130 operand.
1131
fd1dc4a0
MM		 11322019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1133
1134 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1135 sve_size_tsz_bhs iclass encode.
1136 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1137 sve_size_tsz_bhs iclass decode.
1138
31e36ab3
MM		 11392019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1140
1141 * aarch64-asm-2.c: Regenerated.
1142 * aarch64-dis-2.c: Regenerated.
1143 * aarch64-opc-2.c: Regenerated.
1144 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1145 for SVE_Zm4_11_INDEX.
1146 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1147 (fields): Handle SVE_i2h field.
1148 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1149 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1150
1be5f94f
MM		 11512019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1152
1153 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1154 sve_shift_tsz_bhsd iclass encode.
1155 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1156 sve_shift_tsz_bhsd iclass decode.
1157
3c17238b
MM		 11582019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1159
1160 * aarch64-asm-2.c: Regenerated.
1161 * aarch64-dis-2.c: Regenerated.
1162 * aarch64-opc-2.c: Regenerated.
1163 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1164 (aarch64_encode_variant_using_iclass): Handle
1165 sve_shift_tsz_hsd iclass encode.
1166 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1167 sve_shift_tsz_hsd iclass decode.
1168 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1169 for SVE_SHRIMM_UNPRED_22.
1170 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1171 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1172 operand.
1173
cd50a87a
MM		 11742019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1175
1176 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1177 sve_size_013 iclass encode.
1178 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1179 sve_size_013 iclass decode.
1180
3c705960
MM		 11812019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1182
1183 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1184 sve_size_bh iclass encode.
1185 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1186 sve_size_bh iclass decode.
1187
0a57e14f
MM		 11882019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1189
1190 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1191 sve_size_sd2 iclass encode.
1192 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1193 sve_size_sd2 iclass decode.
1194 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1195 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1196
c469c864
MM		 11972019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1198
1199 * aarch64-asm-2.c: Regenerated.
1200 * aarch64-dis-2.c: Regenerated.
1201 * aarch64-opc-2.c: Regenerated.
1202 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1203 for SVE_ADDR_ZX.
1204 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1205 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1206
116adc27
MM		 12072019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1208
1209 * aarch64-asm-2.c: Regenerated.
1210 * aarch64-dis-2.c: Regenerated.
1211 * aarch64-opc-2.c: Regenerated.
1212 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1213 for SVE_Zm3_11_INDEX.
1214 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1215 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1216 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1217 fields.
1218 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1219
3bd82c86
MM		 12202019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1221
1222 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1223 sve_size_hsd2 iclass encode.
1224 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1225 sve_size_hsd2 iclass decode.
1226 * aarch64-opc.c (fields): Handle SVE_size field.
1227 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1228
adccc507
MM		 12292019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1230
1231 * aarch64-asm-2.c: Regenerated.
1232 * aarch64-dis-2.c: Regenerated.
1233 * aarch64-opc-2.c: Regenerated.
1234 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1235 for SVE_IMM_ROT3.
1236 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1237 (fields): Handle SVE_rot3 field.
1238 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1239 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1240
5cd99750
MM		 12412019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1242
1243 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1244 instructions.
1245
7ce2460a
MM		 12462019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1247
1248 * aarch64-tbl.h
1249 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1250 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1251 aarch64_feature_sve2bitperm): New feature sets.
1252 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1253 for feature set addresses.
1254 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1255 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1256
41cee089
FS		 12572019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1258 Faraz Shahbazker <fshahbazker@wavecomp.com>
1259
1260 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1261 argument and set ASE_EVA_R6 appropriately.
1262 (set_default_mips_dis_options): Pass ISA to above.
1263 (parse_mips_dis_option): Likewise.
1264 * mips-opc.c (EVAR6): New macro.
1265 (mips_builtin_opcodes): Add llwpe, scwpe.
1266
b83b4b13
SD		 12672019-05-01 Sudakshina Das <sudi.das@arm.com>
1268
1269 * aarch64-asm-2.c: Regenerated.
1270 * aarch64-dis-2.c: Regenerated.
1271 * aarch64-opc-2.c: Regenerated.
1272 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1273 AARCH64_OPND_TME_UIMM16.
1274 (aarch64_print_operand): Likewise.
1275 * aarch64-tbl.h (QL_IMM_NIL): New.
1276 (TME): New.
1277 (_TME_INSN): New.
1278 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1279
4a90ce95
JD		 12802019-04-29 John Darrington <john@darrington.wattle.id.au>
1281
1282 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1283
a45328b9
AB		 12842019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1285 Faraz Shahbazker <fshahbazker@wavecomp.com>
1286
1287 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1288
d10be0cb
JD		 12892019-04-24 John Darrington <john@darrington.wattle.id.au>
1290
1291 * s12z-opc.h: Add extern "C" bracketing to help
1292 users who wish to use this interface in c++ code.
1293
a679f24e
JD		 12942019-04-24 John Darrington <john@darrington.wattle.id.au>
1295
1296 * s12z-opc.c (bm_decode): Handle bit map operations with the
1297 "reserved0" mode.
1298
32c36c3c
AV		 12992019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1300
1301 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1302 specifier. Add entries for VLDR and VSTR of system registers.
1303 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1304 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1305 of %J and %K format specifier.
1306
efd6b359
AV		 13072019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1308
1309 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1310 Add new entries for VSCCLRM instruction.
1311 (print_insn_coprocessor): Handle new %C format control code.
1312
6b0dd094
AV		 13132019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1314
1315 * arm-dis.c (enum isa): New enum.
1316 (struct sopcode32): New structure.
1317 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1318 set isa field of all current entries to ANY.
1319 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1320 Only match an entry if its isa field allows the current mode.
1321
4b5a202f
AV		 13222019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1323
1324 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1325 CLRM.
1326 (print_insn_thumb32): Add logic to print %n CLRM register list.
1327
60f993ce
AV		 13282019-04-15 Sudakshina Das <sudi.das@arm.com>
1329
1330 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1331 and %Q patterns.
1332
f6b2b12d
AV		 13332019-04-15 Sudakshina Das <sudi.das@arm.com>
1334
1335 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1336 (print_insn_thumb32): Edit the switch case for %Z.
1337
1889da70
AV		 13382019-04-15 Sudakshina Das <sudi.das@arm.com>
1339
1340 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1341
65d1bc05
AV		 13422019-04-15 Sudakshina Das <sudi.das@arm.com>
1343
1344 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1345
1caf72a5
AV		 13462019-04-15 Sudakshina Das <sudi.das@arm.com>
1347
1348 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1349
f1c7f421
AV		 13502019-04-15 Sudakshina Das <sudi.das@arm.com>
1351
1352 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1353 Arm register with r13 and r15 unpredictable.
1354 (thumb32_opcodes): New instructions for bfx and bflx.
1355
4389b29a
AV		 13562019-04-15 Sudakshina Das <sudi.das@arm.com>
1357
1358 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1359
e5d6e09e
AV		 13602019-04-15 Sudakshina Das <sudi.das@arm.com>
1361
1362 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1363
e12437dc
AV		 13642019-04-15 Sudakshina Das <sudi.das@arm.com>
1365
1366 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1367
031254f2
AV		 13682019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1369
1370 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1371
e5a557ac
JD		 13722019-04-12 John Darrington <john@darrington.wattle.id.au>
1373
1374 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1375 "optr". ("operator" is a reserved word in c++).
1376
bd7ceb8d
SD		 13772019-04-11 Sudakshina Das <sudi.das@arm.com>
1378
1379 * aarch64-opc.c (aarch64_print_operand): Add case for
1380 AARCH64_OPND_Rt_SP.
1381 (verify_constraints): Likewise.
1382 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1383 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1384 to accept Rt|SP as first operand.
1385 (AARCH64_OPERANDS): Add new Rt_SP.
1386 * aarch64-asm-2.c: Regenerated.
1387 * aarch64-dis-2.c: Regenerated.
1388 * aarch64-opc-2.c: Regenerated.
1389
e54010f1
SD		 13902019-04-11 Sudakshina Das <sudi.das@arm.com>
1391
1392 * aarch64-asm-2.c: Regenerated.
1393 * aarch64-dis-2.c: Likewise.
1394 * aarch64-opc-2.c: Likewise.
1395 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1396
7e96e219
RS		 13972019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1398
1399 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1400
6f2791d5
L		 14012019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1402
1403 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1404 * i386-init.h: Regenerated.
1405
e392bad3
AM		 14062019-04-07 Alan Modra <amodra@gmail.com>
1407
1408 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1409 op_separator to control printing of spaces, comma and parens
1410 rather than need_comma, need_paren and spaces vars.
1411
dffaa15c
AM		 14122019-04-07 Alan Modra <amodra@gmail.com>
1413
1414 PR 24421
1415 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1416 (print_insn_neon, print_insn_arm): Likewise.
1417
d6aab7a1
XG		 14182019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1419
1420 * i386-dis-evex.h (evex_table): Updated to support BF16
1421 instructions.
1422 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1423 and EVEX_W_0F3872_P_3.
1424 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1425 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1426 * i386-opc.h (enum): Add CpuAVX512_BF16.
1427 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1428 * i386-opc.tbl: Add AVX512 BF16 instructions.
1429 * i386-init.h: Regenerated.
1430 * i386-tbl.h: Likewise.
1431
66e85460
AM		 14322019-04-05 Alan Modra <amodra@gmail.com>
1433
1434 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1435 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1436 to favour printing of "-" branch hint when using the "y" bit.
1437 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1438
c2b1c275
AM		 14392019-04-05 Alan Modra <amodra@gmail.com>
1440
1441 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1442 opcode until first operand is output.
1443
aae9718e
PB		 14442019-04-04 Peter Bergner <bergner@linux.ibm.com>
1445
1446 PR gas/24349
1447 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1448 (valid_bo_post_v2): Add support for 'at' branch hints.
1449 (insert_bo): Only error on branch on ctr.
1450 (get_bo_hint_mask): New function.
1451 (insert_boe): Add new 'branch_taken' formal argument. Add support
1452 for inserting 'at' branch hints.
1453 (extract_boe): Add new 'branch_taken' formal argument. Add support
1454 for extracting 'at' branch hints.
1455 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1456 (BOE): Delete operand.
1457 (BOM, BOP): New operands.
1458 (RM): Update value.
1459 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1460 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1461 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1462 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1463 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1464 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1465 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1466 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1467 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1468 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1469 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1470 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1471 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1472 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1473 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1474 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1475 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1476 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1477 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1478 bttarl+>: New extended mnemonics.
1479
96a86c01
AM		 14802019-03-28 Alan Modra <amodra@gmail.com>
1481
1482 PR 24390
1483 * ppc-opc.c (BTF): Define.
1484 (powerpc_opcodes): Use for mtfsb*.
1485 * ppc-dis.c (print_insn_powerpc): Print fields with both
1486 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1487
796d6298
TC		 14882019-03-25 Tamar Christina <tamar.christina@arm.com>
1489
1490 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1491 (mapping_symbol_for_insn): Implement new algorithm.
1492 (print_insn): Remove duplicate code.
1493
60df3720
TC		 14942019-03-25 Tamar Christina <tamar.christina@arm.com>
1495
1496 * aarch64-dis.c (print_insn_aarch64):
1497 Implement override.
1498
51457761
TC		 14992019-03-25 Tamar Christina <tamar.christina@arm.com>
1500
1501 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1502 order.
1503
53b2f36b
TC		 15042019-03-25 Tamar Christina <tamar.christina@arm.com>
1505
1506 * aarch64-dis.c (last_stop_offset): New.
1507 (print_insn_aarch64): Use stop_offset.
1508
89199bb5
L		 15092019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1510
1511 PR gas/24359
1512 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1513 CPU_ANY_AVX2_FLAGS.
1514 * i386-init.h: Regenerated.
1515
97ed31ae
L		 15162019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1517
1518 PR gas/24348
1519 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1520 vmovdqu16, vmovdqu32 and vmovdqu64.
1521 * i386-tbl.h: Regenerated.
1522
0919bfe9
AK		 15232019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1524
1525 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1526 from vstrszb, vstrszh, and vstrszf.
1527
15282019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1529
1530 * s390-opc.txt: Add instruction descriptions.
1531
21820ebe
JW		 15322019-02-08 Jim Wilson <jimw@sifive.com>
1533
1534 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1535 <bne>: Likewise.
1536
f7dd2fb2
TC		 15372019-02-07 Tamar Christina <tamar.christina@arm.com>
1538
1539 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1540
6456d318
TC		 15412019-02-07 Tamar Christina <tamar.christina@arm.com>
1542
1543 PR binutils/23212
1544 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1545 * aarch64-opc.c (verify_elem_sd): New.
1546 (fields): Add FLD_sz entr.
1547 * aarch64-tbl.h (_SIMD_INSN): New.
1548 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1549 fmulx scalar and vector by element isns.
1550
4a83b610
NC		 15512019-02-07 Nick Clifton <nickc@redhat.com>
1552
1553 * po/sv.po: Updated Swedish translation.
1554
fc60b8c8
AK		 15552019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1556
1557 * s390-mkopc.c (main): Accept arch13 as cpu string.
1558 * s390-opc.c: Add new instruction formats and instruction opcode
1559 masks.
1560 * s390-opc.txt: Add new arch13 instructions.
1561
e10620d3
TC		 15622019-01-25 Sudakshina Das <sudi.das@arm.com>
1563
1564 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1565 (aarch64_opcode): Change encoding for stg, stzg
1566 st2g and st2zg.
1567 * aarch64-asm-2.c: Regenerated.
1568 * aarch64-dis-2.c: Regenerated.
1569 * aarch64-opc-2.c: Regenerated.
1570
20a4ca55
SD		 15712019-01-25 Sudakshina Das <sudi.das@arm.com>
1572
1573 * aarch64-asm-2.c: Regenerated.
1574 * aarch64-dis-2.c: Likewise.
1575 * aarch64-opc-2.c: Likewise.
1576 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1577
550fd7bf
SD		 15782019-01-25 Sudakshina Das <sudi.das@arm.com>
1579 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1580
1581 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1582 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1583 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1584 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1585 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1586 case for ldstgv_indexed.
1587 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1588 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1589 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1590 * aarch64-asm-2.c: Regenerated.
1591 * aarch64-dis-2.c: Regenerated.
1592 * aarch64-opc-2.c: Regenerated.
1593
d9938630
NC		 15942019-01-23 Nick Clifton <nickc@redhat.com>
1595
1596 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1597
375cd423
NC		 15982019-01-21 Nick Clifton <nickc@redhat.com>
1599
1600 * po/de.po: Updated German translation.
1601 * po/uk.po: Updated Ukranian translation.
1602
57299f48
CX		 16032019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1604 * mips-dis.c (mips_arch_choices): Fix typo in
1605 gs464, gs464e and gs264e descriptors.
1606
f48dfe41
NC		 16072019-01-19 Nick Clifton <nickc@redhat.com>
1608
1609 * configure: Regenerate.
1610 * po/opcodes.pot: Regenerate.
1611
f974f26c
NC		 16122018-06-24 Nick Clifton <nickc@redhat.com>
1613
1614 2.32 branch created.
1615
39f286cd
JD		 16162019-01-09 John Darrington <john@darrington.wattle.id.au>
1617
448b8ca8
JD		 1618 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1619 if it is null.
1620 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1621 zero.
1622
3107326d
AP		 16232019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1624
1625 * configure: Regenerate.
1626
7e9ca91e
AM		 16272019-01-07 Alan Modra <amodra@gmail.com>
1628
1629 * configure: Regenerate.
1630 * po/POTFILES.in: Regenerate.
1631
ef1ad42b
JD		 16322019-01-03 John Darrington <john@darrington.wattle.id.au>
1633
1634 * s12z-opc.c: New file.
1635 * s12z-opc.h: New file.
1636 * s12z-dis.c: Removed all code not directly related to display
1637 of instructions. Used the interface provided by the new files
1638 instead.
1639 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1640 * Makefile.in: Regenerate.
ef1ad42b 1641 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1642 * configure: Regenerate.
ef1ad42b 1643
82704155
AM		 16442019-01-01 Alan Modra <amodra@gmail.com>
1645
1646 Update year range in copyright notice of all files.
1647
d5c04e1b 1648For older changes see ChangeLog-2018
3499769a 1649\f
d5c04e1b 1650Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1651
1652Copying and distribution of this file, with or without modification,
1653are permitted in any medium without royalty provided the copyright
1654notice and this notice are preserved.
1655
1656Local Variables:
1657mode: change-log
1658left-margin: 8
1659fill-column: 74
1660version-control: never
1661End:
GDB Binutils - Deliverables
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