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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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f2ae14a1
RS		 12013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
2
3 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
4 and SD A(B) macros up.
5 * micromips-opc.c (micromips_opcodes): Likewise.
6
04c9d415
RS		 72013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
8
9 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
10 instructions.
11
5c324c16
RS		 122013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
13
14 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
15 MDMX-like instructions.
16 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
17 printing "Q" operands for INSN_5400 instructions.
18
23e69e47
RS		 192013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
20
21 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
22 "+S" for "cins".
23 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
24 Combine cases.
25
27c5c572
RS		 262013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
27
28 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
29 "jalx".
30 * mips16-opc.c (mips16_opcodes): Likewise.
31 * micromips-opc.c (micromips_opcodes): Likewise.
32 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
33 (print_insn_mips16): Handle "+i".
34 (print_insn_micromips): Likewise. Conditionally preserve the
35 ISA bit for "a" but not for "+i".
36
e76ff5ab
RS		 372013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
38
39 * micromips-opc.c (WR_mhi): Rename to..
40 (WR_mh): ...this.
41 (micromips_opcodes): Update "movep" entry accordingly. Replace
42 "mh,mi" with "mh".
43 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
44 (micromips_to_32_reg_h_map1): ...this.
45 (micromips_to_32_reg_i_map): Rename to...
46 (micromips_to_32_reg_h_map2): ...this.
47 (print_micromips_insn): Remove "mi" case. Print both registers
48 in the pair for "mh".
49
fa7616a4
RS		 502013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
51
52 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
53 * micromips-opc.c (micromips_opcodes): Likewise.
54 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
55 and "+T" handling. Check for a "0" suffix when deciding whether to
56 use coprocessor 0 names. In that case, also check for ",H" selectors.
57
fb798c50
AK		 582013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
59
60 * s390-opc.c (J12_12, J24_24): New macros.
61 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
62 (MASK_MII_UPI): Rename to MASK_MII_UPP.
63 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
64
58ae08f2
AM		 652013-07-04 Alan Modra <amodra@gmail.com>
66
67 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
68
b5e04c2b
NC		 692013-06-26 Nick Clifton <nickc@redhat.com>
70
71 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
72 field when checking for type 2 nop.
73 * rx-decode.c: Regenerate.
74
833794fc
MR		 752013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
76
77 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
78 and "movep" macros.
79
1bbce132
MR		 802013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
81
82 * mips-dis.c (is_mips16_plt_tail): New function.
83 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
84 word.
85 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
86
34c911a4
NC		 872013-06-21 DJ Delorie <dj@redhat.com>
88
89 * msp430-decode.opc: New.
90 * msp430-decode.c: New/generated.
91 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
92 (MAINTAINER_CLEANFILES): Likewise.
93 Add rule to build msp430-decode.c frommsp430decode.opc
94 using the opc2c program.
95 * Makefile.in: Regenerate.
96 * configure.in: Add msp430-decode.lo to msp430 architecture files.
97 * configure: Regenerate.
98
b9eead84
YZ		 992013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
100
101 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
102 (SYMTAB_AVAILABLE): Removed.
103 (#include "elf/aarch64.h): Ditto.
104
7f3c4072
CM		 1052013-06-17 Catherine Moore <clm@codesourcery.com>
106 Maciej W. Rozycki <macro@codesourcery.com>
107 Chao-Ying Fu <fu@mips.com>
108
109 * micromips-opc.c (EVA): Define.
110 (TLBINV): Define.
111 (micromips_opcodes): Add EVA opcodes.
112 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
113 (print_insn_args): Handle EVA offsets.
114 (print_insn_micromips): Likewise.
115 * mips-opc.c (EVA): Define.
116 (TLBINV): Define.
117 (mips_builtin_opcodes): Add EVA opcodes.
118
de40ceb6
AM		 1192013-06-17 Alan Modra <amodra@gmail.com>
120
121 * Makefile.am (mips-opc.lo): Add rules to create automatic
122 dependency files. Pass archdefs.
123 (micromips-opc.lo, mips16-opc.lo): Likewise.
124 * Makefile.in: Regenerate.
125
3531d549
DD		 1262013-06-14 DJ Delorie <dj@redhat.com>
127
128 * rx-decode.opc (rx_decode_opcode): Bit operations on
129 registers are 32-bit operations, not 8-bit operations.
130 * rx-decode.c: Regenerate.
131
ba92f7fb
CF		 1322013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
133
134 * micromips-opc.c (IVIRT): New define.
135 (IVIRT64): New define.
136 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
137 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
138
139 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
140 dmtgc0 to print cp0 names.
141
9daf7bab
SL		 1422013-06-09 Sandra Loosemore <sandra@codesourcery.com>
143
144 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
145 argument.
146
d301a56b
RS		 1472013-06-08 Catherine Moore <clm@codesourcery.com>
148 Richard Sandiford <rdsandiford@googlemail.com>
149
150 * micromips-opc.c (D32, D33, MC): Update definitions.
151 (micromips_opcodes): Initialize ase field.
152 * mips-dis.c (mips_arch_choice): Add ase field.
153 (mips_arch_choices): Initialize ase field.
154 (set_default_mips_dis_options): Declare and setup mips_ase.
155 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
156 MT32, MC): Update definitions.
157 (mips_builtin_opcodes): Initialize ase field.
158
a3dcb6c5
RS		 1592013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
160
161 * s390-opc.txt (flogr): Require a register pair destination.
162
6cf1d90c
AK		 1632013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
164
165 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
166 instruction format.
167
c77c0862
RS		 1682013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
169
170 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
171
c0637f3a
PB		 1722013-05-20 Peter Bergner <bergner@vnet.ibm.com>
173
174 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
175 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
176 XLS_MASK, PPCVSX2): New defines.
177 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
178 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
179 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
180 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
181 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
182 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
183 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
184 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
185 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
186 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
187 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
188 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
189 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
190 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
191 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
192 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
193 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
194 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
195 <lxvx, stxvx>: New extended mnemonics.
196
4934fdaf
AM		 1972013-05-17 Alan Modra <amodra@gmail.com>
198
199 * ia64-raw.tbl: Replace non-ASCII char.
200 * ia64-waw.tbl: Likewise.
201 * ia64-asmtab.c: Regenerate.
202
6091d651
SE		 2032013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
204
205 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
206 * i386-init.h: Regenerated.
207
d2865ed3
YZ		 2082013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
209
210 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
211 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
212 check from [0, 255] to [-128, 255].
213
b015e599
AP		 2142013-05-09 Andrew Pinski <apinski@cavium.com>
215
216 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
217 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
218 (parse_mips_dis_option): Handle the virt option.
219 (print_insn_args): Handle "+J".
220 (print_mips_disassembler_options): Print out message about virt64.
221 * mips-opc.c (IVIRT): New define.
222 (IVIRT64): New define.
223 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
224 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
225 Move rfe to the bottom as it conflicts with tlbgp.
226
9f0682fe
AM		 2272013-05-09 Alan Modra <amodra@gmail.com>
228
229 * ppc-opc.c (extract_vlesi): Properly sign extend.
230 (extract_vlensi): Likewise. Comment reason for setting invalid.
231
13761a11
NC		 2322013-05-02 Nick Clifton <nickc@redhat.com>
233
234 * msp430-dis.c: Add support for MSP430X instructions.
235
e3031850
SL		 2362013-04-24 Sandra Loosemore <sandra@codesourcery.com>
237
238 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
239 to "eccinj".
240
17310e56
NC		 2412013-04-17 Wei-chen Wang <cole945@gmail.com>
242
243 PR binutils/15369
244 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
245 of CGEN_CPU_ENDIAN.
246 (hash_insns_list): Likewise.
247
731df338
JK		 2482013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
249
250 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
251 warning workaround.
252
5f77db52
JB		 2532013-04-08 Jan Beulich <jbeulich@suse.com>
254
255 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
256 * i386-tbl.h: Re-generate.
257
0afd1215
DM		 2582013-04-06 David S. Miller <davem@davemloft.net>
259
260 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
261 of an opcode, prefer the one with F_PREFERRED set.
262 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
263 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
264 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
265 mark existing mnenomics as aliases. Add "cc" suffix to edge
266 instructions generating condition codes, mark existing mnenomics
267 as aliases. Add "fp" prefix to VIS compare instructions, mark
268 existing mnenomics as aliases.
269
41702d50
NC		 2702013-04-03 Nick Clifton <nickc@redhat.com>
271
272 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
273 destination address by subtracting the operand from the current
274 address.
275 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
276 a positive value in the insn.
277 (extract_u16_loop): Do not negate the returned value.
278 (D16_LOOP): Add V850_INVERSE_PCREL flag.
279
280 (ceilf.sw): Remove duplicate entry.
281 (cvtf.hs): New entry.
282 (cvtf.sh): Likewise.
283 (fmaf.s): Likewise.
284 (fmsf.s): Likewise.
285 (fnmaf.s): Likewise.
286 (fnmsf.s): Likewise.
287 (maddf.s): Restrict to E3V5 architectures.
288 (msubf.s): Likewise.
289 (nmaddf.s): Likewise.
290 (nmsubf.s): Likewise.
291
55cf16e1
L		 2922013-03-27 H.J. Lu <hongjiu.lu@intel.com>
293
294 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
295 check address mode.
296 (print_insn): Pass sizeflag to get_sib.
297
51dcdd4d
NC		 2982013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
299
300 PR binutils/15068
301 * tic6x-dis.c: Add support for displaying 16-bit insns.
302
795b8e6b
NC		 3032013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
304
305 PR gas/15095
306 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
307 individual msb and lsb halves in src1 & src2 fields. Discard the
308 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
309 follow what Ti SDK does in that case as any value in the src1
310 field yields the same output with SDK disassembler.
311
314d60dd
ME		 3122013-03-12 Michael Eager <eager@eagercon.com>
313
795b8e6b 314 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 315
dad60f8e
SL		 3162013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
317
318 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
319
f5cb796a
SL		 3202013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
321
322 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
323
21fde85c
SL		 3242013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
325
326 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
327
dd5181d5
KT		 3282013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
329
330 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
331 (thumb32_opcodes): Likewise.
332 (print_insn_thumb32): Handle 'S' control char.
333
87a8d6cb
NC		 3342013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
335
336 * lm32-desc.c: Regenerate.
337
99dce992
L		 3382013-03-01 H.J. Lu <hongjiu.lu@intel.com>
339
340 * i386-reg.tbl (riz): Add RegRex64.
341 * i386-tbl.h: Regenerated.
342
e60bb1dd
YZ		 3432013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
344
345 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
346 (aarch64_feature_crc): New static.
347 (CRC): New macro.
348 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
349 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
350 * aarch64-asm-2.c: Re-generate.
351 * aarch64-dis-2.c: Ditto.
352 * aarch64-opc-2.c: Ditto.
353
c7570fcd
AM		 3542013-02-27 Alan Modra <amodra@gmail.com>
355
356 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
357 * rl78-decode.c: Regenerate.
358
151fa98f
NC		 3592013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
360
361 * rl78-decode.opc: Fix encoding of DIVWU insn.
362 * rl78-decode.c: Regenerate.
363
5c111e37
L		 3642013-02-19 H.J. Lu <hongjiu.lu@intel.com>
365
366 PR gas/15159
367 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
368
369 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
370 (cpu_flags): Add CpuSMAP.
371
372 * i386-opc.h (CpuSMAP): New.
373 (i386_cpu_flags): Add cpusmap.
374
375 * i386-opc.tbl: Add clac and stac.
376
377 * i386-init.h: Regenerated.
378 * i386-tbl.h: Likewise.
379
9d1df426
NC		 3802013-02-15 Markos Chandras <markos.chandras@imgtec.com>
381
382 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
383 which also makes the disassembler output be in little
384 endian like it should be.
385
a1ccaec9
YZ		 3862013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
387
388 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
389 fields to NULL.
390 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
391
ef068ef4 3922013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 393
394 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
395 section disassembled.
396
6fe6ded9
RE		 3972013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
398
399 * arm-dis.c: Update strht pattern.
400
0aa27725
RS		 4012013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
402
403 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
404 single-float. Disable ll, lld, sc and scd for EE. Disable the
405 trunc.w.s macro for EE.
406
36591ba1
SL		 4072013-02-06 Sandra Loosemore <sandra@codesourcery.com>
408 Andrew Jenner <andrew@codesourcery.com>
409
410 Based on patches from Altera Corporation.
411
412 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
413 nios2-opc.c.
414 * Makefile.in: Regenerated.
415 * configure.in: Add case for bfd_nios2_arch.
416 * configure: Regenerated.
417 * disassemble.c (ARCH_nios2): Define.
418 (disassembler): Add case for bfd_arch_nios2.
419 * nios2-dis.c: New file.
420 * nios2-opc.c: New file.
421
545093a4
AM		 4222013-02-04 Alan Modra <amodra@gmail.com>
423
424 * po/POTFILES.in: Regenerate.
425 * rl78-decode.c: Regenerate.
426 * rx-decode.c: Regenerate.
427
e30181a5
YZ		 4282013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
429
430 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
431 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
432 * aarch64-asm.c (convert_xtl_to_shll): New function.
433 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
434 calling convert_xtl_to_shll.
435 * aarch64-dis.c (convert_shll_to_xtl): New function.
436 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
437 calling convert_shll_to_xtl.
438 * aarch64-gen.c: Update copyright year.
439 * aarch64-asm-2.c: Re-generate.
440 * aarch64-dis-2.c: Re-generate.
441 * aarch64-opc-2.c: Re-generate.
442
78c8d46c
NC		 4432013-01-24 Nick Clifton <nickc@redhat.com>
444
445 * v850-dis.c: Add support for e3v5 architecture.
446 * v850-opc.c: Likewise.
447
f5555712
YZ		 4482013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
449
450 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
451 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
452 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 453 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 454 alignment check; change to call set_sft_amount_out_of_range_error
455 instead of set_imm_out_of_range_error.
456 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
457 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
458 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
459 SIMD_IMM_SFT.
460
2f81ff92
L		 4612013-01-16 H.J. Lu <hongjiu.lu@intel.com>
462
463 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
464
465 * i386-init.h: Regenerated.
466 * i386-tbl.h: Likewise.
467
dd42f060
NC		 4682013-01-15 Nick Clifton <nickc@redhat.com>
469
470 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
471 values.
472 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
473
a4533ed8
NC		 4742013-01-14 Will Newton <will.newton@imgtec.com>
475
476 * metag-dis.c (REG_WIDTH): Increase to 64.
477
5817ffd1
PB		 4782013-01-10 Peter Bergner <bergner@vnet.ibm.com>
479
480 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
481 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
482 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
483 (SH6): Update.
484 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
485 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
486 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
487 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
488
a3c62988
NC		 4892013-01-10 Will Newton <will.newton@imgtec.com>
490
491 * Makefile.am: Add Meta.
492 * configure.in: Add Meta.
493 * disassemble.c: Add Meta support.
494 * metag-dis.c: New file.
495 * Makefile.in: Regenerate.
496 * configure: Regenerate.
497
73335eae
NC		 4982013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
499
500 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
501 (match_opcode): Rename to cr16_match_opcode.
502
e407c74b
NC		 5032013-01-04 Juergen Urban <JuergenUrban@gmx.de>
504
505 * mips-dis.c: Add names for CP0 registers of r5900.
506 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
507 instructions sq and lq.
508 Add support for MIPS r5900 CPU.
509 Add support for 128 bit MMI (Multimedia Instructions).
510 Add support for EE instructions (Emotion Engine).
511 Disable unsupported floating point instructions (64 bit and
512 undefined compare operations).
513 Enable instructions of MIPS ISA IV which are supported by r5900.
514 Disable 64 bit co processor instructions.
515 Disable 64 bit multiplication and division instructions.
516 Disable instructions for co-processor 2 and 3, because these are
517 not supported (preparation for later VU0 support (Vector Unit)).
518 Disable cvt.w.s because this behaves like trunc.w.s and the
519 correct execution can't be ensured on r5900.
520 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
521 will confuse less developers and compilers.
522
a32c3ff8
NC		 5232013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
524
fb098a1e
YZ		 525 * aarch64-opc.c (aarch64_print_operand): Change to print
526 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
527 in comment.
528 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
529 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
530 OP_MOV_IMM_WIDE.
531
5322013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
533
534 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
535 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 536
62658407
L		 5372013-01-02 H.J. Lu <hongjiu.lu@intel.com>
538
539 * i386-gen.c (process_copyright): Update copyright year to 2013.
540
bab4becb 5412013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 542
bab4becb
NC		 543 * cr16-dis.c (match_opcode,make_instruction): Remove static
544 declaration.
545 (dwordU,wordU): Moved typedefs to opcode/cr16.h
546 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 547
bab4becb 548For older changes see ChangeLog-2012
252b5132 549\f
bab4becb 550Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 551
552Copying and distribution of this file, with or without modification,
553are permitted in any medium without royalty provided the copyright
554notice and this notice are preserved.
555
252b5132 556Local Variables:
2f6d2f85
NC		 557mode: change-log
558left-margin: 8
559fill-column: 74
252b5132
RH		 560version-control: never
561End:
GDB Binutils - Deliverables
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