projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| f5555712 YZ |
1 | 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> |
| 2 | ||
| 3 | * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI. | |
| 4 | * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise. | |
| 5 | * aarch64-opc.c (operand_general_constraint_met_p): For | |
| 6 | AARCH64_MOD_LSL, move the range check on the shift amount before the | |
| 7 | alignment check; change to call set_sft_amount_out_of_range_error | |
| 8 | instead of set_imm_out_of_range_error. | |
| 9 | * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL. | |
| 10 | (aarch64_opcode_table): Remove the OP enumerator from the asimdimm | |
| 11 | 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to | |
| 12 | SIMD_IMM_SFT. | |
| 13 | ||
| 2f81ff92 L |
14 | 2013-01-16 H.J. Lu <hongjiu.lu@intel.com> |
| 15 | ||
| 16 | * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64. | |
| 17 | ||
| 18 | * i386-init.h: Regenerated. | |
| 19 | * i386-tbl.h: Likewise. | |
| 20 | ||
| dd42f060 NC |
21 | 2013-01-15 Nick Clifton <nickc@redhat.com> |
| 22 | ||
| 23 | * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE | |
| 24 | values. | |
| 25 | * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute. | |
| 26 | ||
| a4533ed8 NC |
27 | 2013-01-14 Will Newton <will.newton@imgtec.com> |
| 28 | ||
| 29 | * metag-dis.c (REG_WIDTH): Increase to 64. | |
| 30 | ||
| 5817ffd1 PB |
31 | 2013-01-10 Peter Bergner <bergner@vnet.ibm.com> |
| 32 | ||
| 33 | * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries. | |
| 34 | * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK, | |
| 35 | XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines. | |
| 36 | (SH6): Update. | |
| 37 | <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.", | |
| 38 | "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.", | |
| 39 | "treclaim.", "tsr.">: Add POWER8 HTM opcodes. | |
| 40 | <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes. | |
| 41 | ||
| a3c62988 NC |
42 | 2013-01-10 Will Newton <will.newton@imgtec.com> |
| 43 | ||
| 44 | * Makefile.am: Add Meta. | |
| 45 | * configure.in: Add Meta. | |
| 46 | * disassemble.c: Add Meta support. | |
| 47 | * metag-dis.c: New file. | |
| 48 | * Makefile.in: Regenerate. | |
| 49 | * configure: Regenerate. | |
| 50 | ||
| 73335eae NC |
51 | 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com> |
| 52 | ||
| 53 | * cr16-dis.c (make_instruction): Rename to cr16_make_instruction. | |
| 54 | (match_opcode): Rename to cr16_match_opcode. | |
| 55 | ||
| e407c74b NC |
56 | 2013-01-04 Juergen Urban <JuergenUrban@gmx.de> |
| 57 | ||
| 58 | * mips-dis.c: Add names for CP0 registers of r5900. | |
| 59 | * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for | |
| 60 | instructions sq and lq. | |
| 61 | Add support for MIPS r5900 CPU. | |
| 62 | Add support for 128 bit MMI (Multimedia Instructions). | |
| 63 | Add support for EE instructions (Emotion Engine). | |
| 64 | Disable unsupported floating point instructions (64 bit and | |
| 65 | undefined compare operations). | |
| 66 | Enable instructions of MIPS ISA IV which are supported by r5900. | |
| 67 | Disable 64 bit co processor instructions. | |
| 68 | Disable 64 bit multiplication and division instructions. | |
| 69 | Disable instructions for co-processor 2 and 3, because these are | |
| 70 | not supported (preparation for later VU0 support (Vector Unit)). | |
| 71 | Disable cvt.w.s because this behaves like trunc.w.s and the | |
| 72 | correct execution can't be ensured on r5900. | |
| 73 | Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This | |
| 74 | will confuse less developers and compilers. | |
| 75 | ||
| a32c3ff8 NC |
76 | 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com> |
| 77 | ||
| fb098a1e YZ |
78 | * aarch64-opc.c (aarch64_print_operand): Change to print |
| 79 | AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal | |
| 80 | in comment. | |
| 81 | * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag | |
| 82 | from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and | |
| 83 | OP_MOV_IMM_WIDE. | |
| 84 | ||
| 85 | 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com> | |
| 86 | ||
| 87 | * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP, | |
| 88 | PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM. | |
| a32c3ff8 | 89 | |
| 62658407 L |
90 | 2013-01-02 H.J. Lu <hongjiu.lu@intel.com> |
| 91 | ||
| 92 | * i386-gen.c (process_copyright): Update copyright year to 2013. | |
| 93 | ||
| bab4becb | 94 | 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com> |
| 5bf135a7 | 95 | |
| bab4becb NC |
96 | * cr16-dis.c (match_opcode,make_instruction): Remove static |
| 97 | declaration. | |
| 98 | (dwordU,wordU): Moved typedefs to opcode/cr16.h | |
| 99 | (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'. | |
| 5bf135a7 | 100 | |
| bab4becb | 101 | For older changes see ChangeLog-2012 |
| 252b5132 | 102 | \f |
| bab4becb | 103 | Copyright (C) 2013 Free Software Foundation, Inc. |
| 752937aa NC |
104 | |
| 105 | Copying and distribution of this file, with or without modification, | |
| 106 | are permitted in any medium without royalty provided the copyright | |
| 107 | notice and this notice are preserved. | |
| 108 | ||
| 252b5132 | 109 | Local Variables: |
| 2f6d2f85 NC |
110 | mode: change-log |
| 111 | left-margin: 8 | |
| 112 | fill-column: 74 | |
| 252b5132 RH |
113 | version-control: never |
| 114 | End: |