Commit | Line | Data |
---|---|---|
a18cd0ca AM |
1 | 2020-03-25 Alan Modra <amodra@gmail.com> |
2 | ||
3 | * z80-dis.c (suffix): Init mybuf. | |
4 | ||
57cb32b3 AM |
5 | 2020-03-22 Alan Modra <amodra@gmail.com> |
6 | ||
7 | * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that | |
8 | successflly read from section. | |
9 | ||
beea5cc1 AM |
10 | 2020-03-22 Alan Modra <amodra@gmail.com> |
11 | ||
12 | * arc-dis.c (find_format): Use ISO C string concatenation rather | |
13 | than line continuation within a string. Don't access needs_limm | |
14 | before testing opcode != NULL. | |
15 | ||
03704c77 AM |
16 | 2020-03-22 Alan Modra <amodra@gmail.com> |
17 | ||
18 | * ns32k-dis.c (print_insn_arg): Update comment. | |
19 | (print_insn_ns32k): Reduce size of index_offset array, and | |
20 | initialize, passing -1 to print_insn_arg for args that are not | |
21 | an index. Don't exit arg loop early. Abort on bad arg number. | |
22 | ||
d1023b5d AM |
23 | 2020-03-22 Alan Modra <amodra@gmail.com> |
24 | ||
25 | * s12z-dis.c (abstract_read_memory): Don't print error on EOI. | |
26 | * s12z-opc.c: Formatting. | |
27 | (operands_f): Return an int. | |
28 | (opr_n_bytes_p1): Return -1 on reaching buffer memory limit. | |
29 | (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes), | |
30 | (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes), | |
31 | (exg_sex_discrim): Likewise. | |
32 | (create_immediate_operand, create_bitfield_operand), | |
33 | (create_register_operand_with_size, create_register_all_operand), | |
34 | (create_register_all16_operand, create_simple_memory_operand), | |
35 | (create_memory_operand, create_memory_auto_operand): Don't | |
36 | segfault on malloc failure. | |
37 | (z_ext24_decode): Return an int status, negative on fail, zero | |
38 | on success. | |
39 | (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2), | |
40 | (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base), | |
41 | (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7), | |
42 | (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x), | |
43 | (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode), | |
44 | (mov_imm_opr, ld_18bit_decode, exg_sex_decode), | |
45 | (loop_primitive_decode, shift_decode, psh_pul_decode), | |
46 | (bit_field_decode): Similarly. | |
47 | (z_decode_signed_value, decode_signed_value): Similarly. Add arg | |
48 | to return value, update callers. | |
49 | (x_opr_decode_with_size): Check all reads, returning NULL on fail. | |
50 | Don't segfault on NULL operand. | |
51 | (decode_operation): Return OP_INVALID on first fail. | |
52 | (decode_s12z): Check all reads, returning -1 on fail. | |
53 | ||
340f3ac8 AM |
54 | 2020-03-20 Alan Modra <amodra@gmail.com> |
55 | ||
56 | * metag-dis.c (print_insn_metag): Don't ignore status from | |
57 | read_memory_func. | |
58 | ||
fe90ae8a AM |
59 | 2020-03-20 Alan Modra <amodra@gmail.com> |
60 | ||
61 | * nds32-dis.c (print_insn_nds32): Remove unnecessary casts. | |
62 | Initialize parts of buffer not written when handling a possible | |
63 | 2-byte insn at end of section. Don't attempt decoding of such | |
64 | an insn by the 4-byte machinery. | |
65 | ||
833d919c AM |
66 | 2020-03-20 Alan Modra <amodra@gmail.com> |
67 | ||
68 | * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of | |
69 | partially filled buffer. Prevent lookup of 4-byte insns when | |
70 | only VLE 2-byte insns are possible due to section size. Print | |
71 | ".word" rather than ".long" for 2-byte leftovers. | |
72 | ||
327ef784 NC |
73 | 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com> |
74 | ||
75 | PR 25641 | |
76 | * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes. | |
77 | ||
1673df32 JB |
78 | 2020-03-13 Jan Beulich <jbeulich@suse.com> |
79 | ||
80 | * i386-dis.c (X86_64_0D): Rename to ... | |
81 | (X86_64_0E): ... this. | |
82 | ||
384f3689 L |
83 | 2020-03-09 H.J. Lu <hongjiu.lu@intel.com> |
84 | ||
85 | * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP). | |
86 | * Makefile.in: Regenerated. | |
87 | ||
865e2027 JB |
88 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
89 | ||
90 | * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp* | |
91 | 3-operand pseudos. | |
92 | * i386-tbl.h: Re-generate. | |
93 | ||
2f13234b JB |
94 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
95 | ||
96 | * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*, | |
97 | vprot*, vpsha*, and vpshl*. | |
98 | * i386-tbl.h: Re-generate. | |
99 | ||
3fabc179 JB |
100 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
101 | ||
102 | * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps, | |
103 | vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops. | |
104 | * i386-tbl.h: Re-generate. | |
105 | ||
3677e4c1 JB |
106 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
107 | ||
108 | * i386-gen.c (set_bitfield): Ignore zero-length field names. | |
109 | * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps, | |
110 | cmpss, cmppd, and cmpsd 2-operand pseudo-ops. | |
111 | * i386-tbl.h: Re-generate. | |
112 | ||
4c4898e8 JB |
113 | 2020-03-09 Jan Beulich <jbeulich@suse.com> |
114 | ||
115 | * i386-gen.c (struct template_arg, struct template_instance, | |
116 | struct template_param, struct template, templates, | |
117 | parse_template, expand_templates): New. | |
118 | (process_i386_opcodes): Various local variables moved to | |
119 | expand_templates. Call parse_template and expand_templates. | |
120 | * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc. | |
121 | * i386-tbl.h: Re-generate. | |
122 | ||
bc49bfd8 JB |
123 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
124 | ||
125 | * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph, | |
126 | vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate | |
127 | register and memory source templates. Replace VexW= by VexW* | |
128 | where applicable. | |
129 | * i386-tbl.h: Re-generate. | |
130 | ||
4873e243 JB |
131 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
132 | ||
133 | * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace | |
134 | VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable. | |
135 | * i386-tbl.h: Re-generate. | |
136 | ||
672a349b JB |
137 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
138 | ||
139 | * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax. | |
140 | * i386-tbl.h: Re-generate. | |
141 | ||
4ed21b58 JB |
142 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
143 | ||
144 | * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants. | |
145 | (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps, | |
146 | pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use | |
147 | VexW0 on SSE2AVX variants. | |
148 | (vmovq): Drop NoRex64 from XMM/XMM variants. | |
149 | (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb, | |
150 | vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where | |
151 | applicable use VexW0. | |
152 | * i386-tbl.h: Re-generate. | |
153 | ||
643bb870 JB |
154 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
155 | ||
156 | * i386-gen.c (opcode_modifiers): Remove Rex64 field. | |
157 | * i386-opc.h (Rex64): Delete. | |
158 | (struct i386_opcode_modifier): Remove rex64 field. | |
159 | * i386-opc.tbl (crc32): Drop Rex64. | |
160 | Replace Rex64 with Size64 everywhere else. | |
161 | * i386-tbl.h: Re-generate. | |
162 | ||
a23b33b3 JB |
163 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
164 | ||
165 | * i386-dis.c (OP_E_memory): Exclude recording of used address | |
166 | prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit | |
167 | addressed memory operands for MPX insns. | |
168 | ||
a0497384 JB |
169 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
170 | ||
171 | * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept, | |
172 | invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx, | |
173 | adox, mwaitx, rdpid, movdiri): Add IgnoreSize. | |
174 | (ptwrite): Split into non-64-bit and 64-bit forms. | |
175 | * i386-tbl.h: Re-generate. | |
176 | ||
b630c145 JB |
177 | 2020-03-06 Jan Beulich <jbeulich@suse.com> |
178 | ||
179 | * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand | |
180 | template. | |
181 | * i386-tbl.h: Re-generate. | |
182 | ||
a847e322 JB |
183 | 2020-03-04 Jan Beulich <jbeulich@suse.com> |
184 | ||
185 | * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New. | |
186 | (prefix_table): Move vmmcall here. Add vmgexit. | |
187 | (rm_table): Replace vmmcall entry by prefix_table[] escape. | |
188 | * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry. | |
189 | (cpu_flags): Add CpuSEV_ES entry. | |
190 | * i386-opc.h (CpuSEV_ES): New. | |
191 | (union i386_cpu_flags): Add cpusev_es field. | |
192 | * i386-opc.tbl (vmgexit): New. | |
193 | * i386-init.h, i386-tbl.h: Re-generate. | |
194 | ||
3cd7f3e3 L |
195 | 2020-03-03 H.J. Lu <hongjiu.lu@intel.com> |
196 | ||
197 | * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize | |
198 | with MnemonicSize. | |
199 | * i386-opc.h (IGNORESIZE): New. | |
200 | (DEFAULTSIZE): Likewise. | |
201 | (IgnoreSize): Removed. | |
202 | (DefaultSize): Likewise. | |
203 | (MnemonicSize): New. | |
204 | (i386_opcode_modifier): Replace ignoresize/defaultsize with | |
205 | mnemonicsize. | |
206 | * i386-opc.tbl (IgnoreSize): New. | |
207 | (DefaultSize): Likewise. | |
208 | * i386-tbl.h: Regenerated. | |
209 | ||
b8ba1385 SB |
210 | 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com> |
211 | ||
212 | PR 25627 | |
213 | * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX | |
214 | instructions. | |
215 | ||
10d97a0f L |
216 | 2020-03-03 H.J. Lu <hongjiu.lu@intel.com> |
217 | ||
218 | PR gas/25622 | |
219 | * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd, | |
220 | vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax. | |
221 | * i386-tbl.h: Regenerated. | |
222 | ||
dc1e8a47 AM |
223 | 2020-02-26 Alan Modra <amodra@gmail.com> |
224 | ||
225 | * aarch64-asm.c: Indent labels correctly. | |
226 | * aarch64-dis.c: Likewise. | |
227 | * aarch64-gen.c: Likewise. | |
228 | * aarch64-opc.c: Likewise. | |
229 | * alpha-dis.c: Likewise. | |
230 | * i386-dis.c: Likewise. | |
231 | * nds32-asm.c: Likewise. | |
232 | * nfp-dis.c: Likewise. | |
233 | * visium-dis.c: Likewise. | |
234 | ||
265b4673 CZ |
235 | 2020-02-25 Claudiu Zissulescu <claziss@gmail.com> |
236 | ||
237 | * arc-regs.h (int_vector_base): Make it available for all ARC | |
238 | CPUs. | |
239 | ||
bd0cf5a6 NC |
240 | 2020-02-20 Nelson Chu <nelson.chu@sifive.com> |
241 | ||
242 | * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is | |
243 | changed. | |
244 | ||
fa164239 JW |
245 | 2020-02-19 Nelson Chu <nelson.chu@sifive.com> |
246 | ||
247 | * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed | |
248 | c.mv/c.li if rs1 is zero. | |
249 | ||
272a84b1 L |
250 | 2020-02-17 H.J. Lu <hongjiu.lu@intel.com> |
251 | ||
252 | * i386-gen.c (cpu_flag_init): Replace CpuABM with | |
253 | CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add | |
254 | CPU_POPCNT_FLAGS. | |
255 | (cpu_flags): Remove CpuABM. Add CpuPOPCNT. | |
256 | * i386-opc.h (CpuABM): Removed. | |
257 | (CpuPOPCNT): New. | |
258 | (i386_cpu_flags): Remove cpuabm. Add cpupopcnt. | |
259 | * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on | |
260 | popcnt. Remove CpuABM from lzcnt. | |
261 | * i386-init.h: Regenerated. | |
262 | * i386-tbl.h: Likewise. | |
263 | ||
1f730c46 JB |
264 | 2020-02-17 Jan Beulich <jbeulich@suse.com> |
265 | ||
266 | * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss): | |
267 | Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/ | |
268 | VexW1 instead of open-coding them. | |
269 | * i386-tbl.h: Re-generate. | |
270 | ||
c8f8eebc JB |
271 | 2020-02-17 Jan Beulich <jbeulich@suse.com> |
272 | ||
273 | * i386-opc.tbl (AddrPrefixOpReg): Define. | |
274 | (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx, | |
275 | umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64 | |
276 | templates. Drop NoRex64. | |
277 | * i386-tbl.h: Re-generate. | |
278 | ||
b9915cbc JB |
279 | 2020-02-17 Jan Beulich <jbeulich@suse.com> |
280 | ||
281 | PR gas/6518 | |
282 | * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq, | |
283 | vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms | |
284 | into Intel syntax instance (with Unpsecified) and AT&T one | |
285 | (without). | |
286 | (vcvtneps2bf16): Likewise, along with folding the two so far | |
287 | separate ones. | |
288 | * i386-tbl.h: Re-generate. | |
289 | ||
ce504911 L |
290 | 2020-02-16 H.J. Lu <hongjiu.lu@intel.com> |
291 | ||
292 | * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from | |
293 | CPU_ANY_SSE4A_FLAGS. | |
294 | ||
dabec65d AM |
295 | 2020-02-17 Alan Modra <amodra@gmail.com> |
296 | ||
297 | * i386-gen.c (cpu_flag_init): Correct last change. | |
298 | ||
af5c13b0 L |
299 | 2020-02-16 H.J. Lu <hongjiu.lu@intel.com> |
300 | ||
301 | * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove | |
302 | CPU_ANY_SSE4_FLAGS. | |
303 | ||
6867aac0 L |
304 | 2020-02-14 H.J. Lu <hongjiu.lu@intel.com> |
305 | ||
306 | * i386-opc.tbl (movsx): Remove Intel syntax comments. | |
307 | (movzx): Likewise. | |
308 | ||
65fca059 JB |
309 | 2020-02-14 Jan Beulich <jbeulich@suse.com> |
310 | ||
311 | PR gas/25438 | |
312 | * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as | |
313 | destination for Cpu64-only variant. | |
314 | (movzx): Fold patterns. | |
315 | * i386-tbl.h: Re-generate. | |
316 | ||
7deea9aa JB |
317 | 2020-02-13 Jan Beulich <jbeulich@suse.com> |
318 | ||
319 | * i386-gen.c (cpu_flag_init): Move CpuSSE4a from | |
320 | CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add | |
321 | CPU_ANY_SSE4_FLAGS entry. | |
322 | * i386-init.h: Re-generate. | |
323 | ||
6c0946d0 JB |
324 | 2020-02-12 Jan Beulich <jbeulich@suse.com> |
325 | ||
326 | * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form | |
327 | with Unspecified, making the present one AT&T syntax only. | |
328 | * i386-tbl.h: Re-generate. | |
329 | ||
ddb56fe6 JB |
330 | 2020-02-12 Jan Beulich <jbeulich@suse.com> |
331 | ||
332 | * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants. | |
333 | * i386-tbl.h: Re-generate. | |
334 | ||
5990e377 JB |
335 | 2020-02-12 Jan Beulich <jbeulich@suse.com> |
336 | ||
337 | PR gas/24546 | |
338 | * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode. | |
339 | * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into | |
340 | Amd64 and Intel64 templates. | |
341 | (call, jmp): Likewise for far indirect variants. Dro | |
342 | Unspecified. | |
343 | * i386-tbl.h: Re-generate. | |
344 | ||
50128d0c JB |
345 | 2020-02-11 Jan Beulich <jbeulich@suse.com> |
346 | ||
347 | * i386-gen.c (opcode_modifiers): Remove ShortForm entry. | |
348 | * i386-opc.h (ShortForm): Delete. | |
349 | (struct i386_opcode_modifier): Remove shortform field. | |
350 | * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld, | |
351 | fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub, | |
352 | fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp, | |
353 | ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq): | |
354 | Drop ShortForm. | |
355 | * i386-tbl.h: Re-generate. | |
356 | ||
1e05b5c4 JB |
357 | 2020-02-11 Jan Beulich <jbeulich@suse.com> |
358 | ||
359 | * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip, | |
360 | fucompi): Drop ShortForm from operand-less templates. | |
361 | * i386-tbl.h: Re-generate. | |
362 | ||
2f5dd314 AM |
363 | 2020-02-11 Alan Modra <amodra@gmail.com> |
364 | ||
365 | * cgen-ibld.in (extract_normal): Set *valuep on all return paths. | |
366 | * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c, | |
367 | * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, | |
368 | * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c, | |
369 | * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate. | |
370 | ||
5aae9ae9 MM |
371 | 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> |
372 | ||
373 | * arm-dis.c (print_insn_cde): Define 'V' parse character. | |
374 | (cde_opcodes): Add VCX* instructions. | |
375 | ||
4934a27c MM |
376 | 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> |
377 | Matthew Malcomson <matthew.malcomson@arm.com> | |
378 | ||
379 | * arm-dis.c (struct cdeopcode32): New. | |
380 | (CDE_OPCODE): New macro. | |
381 | (cde_opcodes): New disassembly table. | |
382 | (regnames): New option to table. | |
383 | (cde_coprocs): New global variable. | |
384 | (print_insn_cde): New | |
385 | (print_insn_thumb32): Use print_insn_cde. | |
386 | (parse_arm_disassembler_options): Parse coprocN args. | |
387 | ||
4b5aaf5f L |
388 | 2020-02-10 H.J. Lu <hongjiu.lu@intel.com> |
389 | ||
390 | PR gas/25516 | |
391 | * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64 | |
392 | with ISA64. | |
393 | * i386-opc.h (AMD64): Removed. | |
394 | (Intel64): Likewose. | |
395 | (AMD64): New. | |
396 | (INTEL64): Likewise. | |
397 | (INTEL64ONLY): Likewise. | |
398 | (i386_opcode_modifier): Replace amd64 and intel64 with isa64. | |
399 | * i386-opc.tbl (Amd64): New. | |
400 | (Intel64): Likewise. | |
401 | (Intel64Only): Likewise. | |
402 | Replace AMD64 with Amd64. Update sysenter/sysenter with | |
403 | Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter. | |
404 | * i386-tbl.h: Regenerated. | |
405 | ||
9fc0b501 SB |
406 | 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com> |
407 | ||
408 | PR 25469 | |
409 | * z80-dis.c: Add support for GBZ80 opcodes. | |
410 | ||
c5d7be0c AM |
411 | 2020-02-04 Alan Modra <amodra@gmail.com> |
412 | ||
413 | * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned. | |
414 | ||
44e4546f AM |
415 | 2020-02-03 Alan Modra <amodra@gmail.com> |
416 | ||
417 | * m32c-ibld.c: Regenerate. | |
418 | ||
b2b1453a AM |
419 | 2020-02-01 Alan Modra <amodra@gmail.com> |
420 | ||
421 | * frv-ibld.c: Regenerate. | |
422 | ||
4102be5c JB |
423 | 2020-01-31 Jan Beulich <jbeulich@suse.com> |
424 | ||
425 | * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete. | |
426 | (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label. | |
427 | (OP_E_memory): Replace xmm_mdq_mode case label by | |
428 | vex_scalar_w_dq_mode one. | |
429 | * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar. | |
430 | ||
825bd36c JB |
431 | 2020-01-31 Jan Beulich <jbeulich@suse.com> |
432 | ||
433 | * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete. | |
434 | (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode, | |
435 | vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments. | |
436 | (intel_operand_size): Drop vex_w_dq_mode case label. | |
437 | ||
c3036ed0 RS |
438 | 2020-01-31 Richard Sandiford <richard.sandiford@arm.com> |
439 | ||
440 | * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt. | |
441 | Remove C_SCAN_MOVPRFX for SVE bfcvtnt. | |
442 | ||
0c115f84 AM |
443 | 2020-01-30 Alan Modra <amodra@gmail.com> |
444 | ||
445 | * m32c-ibld.c: Regenerate. | |
446 | ||
bd434cc4 JM |
447 | 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> |
448 | ||
449 | * bpf-opc.c: Regenerate. | |
450 | ||
aeab2b26 JB |
451 | 2020-01-30 Jan Beulich <jbeulich@suse.com> |
452 | ||
453 | * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators. | |
454 | (dis386): Use them to replace C2/C3 table entries. | |
455 | (x86_64_table): Add X86_64_C2 and X86_64_C3 entries. | |
456 | * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64 | |
457 | ones. Use Size64 instead of DefaultSize on Intel64 ones. | |
458 | * i386-tbl.h: Re-generate. | |
459 | ||
62b3f548 JB |
460 | 2020-01-30 Jan Beulich <jbeulich@suse.com> |
461 | ||
462 | * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword | |
463 | forms. | |
464 | (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop | |
465 | DefaultSize. | |
466 | * i386-tbl.h: Re-generate. | |
467 | ||
1bd8ae10 AM |
468 | 2020-01-30 Alan Modra <amodra@gmail.com> |
469 | ||
470 | * tic4x-dis.c (tic4x_dp): Make unsigned. | |
471 | ||
bc31405e L |
472 | 2020-01-27 H.J. Lu <hongjiu.lu@intel.com> |
473 | Jan Beulich <jbeulich@suse.com> | |
474 | ||
475 | PR binutils/25445 | |
476 | * i386-dis.c (MOVSXD_Fixup): New function. | |
477 | (movsxd_mode): New enum. | |
478 | (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd. | |
479 | (intel_operand_size): Handle movsxd_mode. | |
480 | (OP_E_register): Likewise. | |
481 | (OP_G): Likewise. | |
482 | * i386-opc.tbl: Remove Rex64 and allow 32-bit destination | |
483 | register on movsxd. Add movsxd with 16-bit destination register | |
484 | for AMD64 and Intel64 ISAs. | |
485 | * i386-tbl.h: Regenerated. | |
486 | ||
7568c93b TC |
487 | 2020-01-27 Tamar Christina <tamar.christina@arm.com> |
488 | ||
489 | PR 25403 | |
490 | * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv. | |
491 | * aarch64-asm-2.c: Regenerate | |
492 | * aarch64-dis-2.c: Likewise. | |
493 | * aarch64-opc-2.c: Likewise. | |
494 | ||
c006a730 JB |
495 | 2020-01-21 Jan Beulich <jbeulich@suse.com> |
496 | ||
497 | * i386-opc.tbl (sysret): Drop DefaultSize. | |
498 | * i386-tbl.h: Re-generate. | |
499 | ||
c906a69a JB |
500 | 2020-01-21 Jan Beulich <jbeulich@suse.com> |
501 | ||
502 | * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and | |
503 | Dword. | |
504 | (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword. | |
505 | * i386-tbl.h: Re-generate. | |
506 | ||
26916852 NC |
507 | 2020-01-20 Nick Clifton <nickc@redhat.com> |
508 | ||
509 | * po/de.po: Updated German translation. | |
510 | * po/pt_BR.po: Updated Brazilian Portuguese translation. | |
511 | * po/uk.po: Updated Ukranian translation. | |
512 | ||
4d6cbb64 AM |
513 | 2020-01-20 Alan Modra <amodra@gmail.com> |
514 | ||
515 | * hppa-dis.c (fput_const): Remove useless cast. | |
516 | ||
2bddb71a AM |
517 | 2020-01-20 Alan Modra <amodra@gmail.com> |
518 | ||
519 | * arm-dis.c (print_insn_arm): Wrap 'T' value. | |
520 | ||
1b1bb2c6 NC |
521 | 2020-01-18 Nick Clifton <nickc@redhat.com> |
522 | ||
523 | * configure: Regenerate. | |
524 | * po/opcodes.pot: Regenerate. | |
525 | ||
ae774686 NC |
526 | 2020-01-18 Nick Clifton <nickc@redhat.com> |
527 | ||
528 | Binutils 2.34 branch created. | |
529 | ||
07f1f3aa CB |
530 | 2020-01-17 Christian Biesinger <cbiesinger@google.com> |
531 | ||
532 | * opintl.h: Fix spelling error (seperate). | |
533 | ||
42e04b36 L |
534 | 2020-01-17 H.J. Lu <hongjiu.lu@intel.com> |
535 | ||
536 | * i386-opc.tbl: Add {vex} pseudo prefix. | |
537 | * i386-tbl.h: Regenerated. | |
538 | ||
2da2eaf4 AV |
539 | 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
540 | ||
541 | PR 25376 | |
542 | * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. | |
543 | (neon_opcodes): Likewise. | |
544 | (select_arm_features): Make sure we enable MVE bits when selecting | |
545 | armv8.1-m.main. Make sure we do not enable MVE bits when not selecting | |
546 | any architecture. | |
547 | ||
d0849eed JB |
548 | 2020-01-16 Jan Beulich <jbeulich@suse.com> |
549 | ||
550 | * i386-opc.tbl: Drop stale comment from XOP section. | |
551 | ||
9cf70a44 JB |
552 | 2020-01-16 Jan Beulich <jbeulich@suse.com> |
553 | ||
554 | * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms. | |
555 | (extractps): Add VexWIG to SSE2AVX forms. | |
556 | * i386-tbl.h: Re-generate. | |
557 | ||
4814632e JB |
558 | 2020-01-16 Jan Beulich <jbeulich@suse.com> |
559 | ||
560 | * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop | |
561 | Size64 from and use VexW1 on SSE2AVX forms. | |
562 | (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from | |
563 | VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1. | |
564 | * i386-tbl.h: Re-generate. | |
565 | ||
aad09917 AM |
566 | 2020-01-15 Alan Modra <amodra@gmail.com> |
567 | ||
568 | * tic4x-dis.c (tic4x_version): Make unsigned long. | |
569 | (optab, optab_special, registernames): New file scope vars. | |
570 | (tic4x_print_register): Set up registernames rather than | |
571 | malloc'd registertable. | |
572 | (tic4x_disassemble): Delete optable and optable_special. Use | |
573 | optab and optab_special instead. Throw away old optab, | |
574 | optab_special and registernames when info->mach changes. | |
575 | ||
7a6bf3be SB |
576 | 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com> |
577 | ||
578 | PR 25377 | |
579 | * z80-dis.c (suffix): Use .db instruction to generate double | |
580 | prefix. | |
581 | ||
ca1eaac0 AM |
582 | 2020-01-14 Alan Modra <amodra@gmail.com> |
583 | ||
584 | * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short | |
585 | values to unsigned before shifting. | |
586 | ||
1d67fe3b TT |
587 | 2020-01-13 Thomas Troeger <tstroege@gmx.de> |
588 | ||
589 | * arm-dis.c (print_insn_arm): Fill in insn info fields for control | |
590 | flow instructions. | |
591 | (print_insn_thumb16, print_insn_thumb32): Likewise. | |
592 | (print_insn): Initialize the insn info. | |
593 | * i386-dis.c (print_insn): Initialize the insn info fields, and | |
594 | detect jumps. | |
595 | ||
5e4f7e05 CZ |
596 | 2012-01-13 Claudiu Zissulescu <claziss@gmail.com> |
597 | ||
598 | * arc-opc.c (C_NE): Make it required. | |
599 | ||
b9fe6b8a CZ |
600 | 2012-01-13 Claudiu Zissulescu <claziss@gmail.com> |
601 | ||
602 | * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo | |
603 | reserved register name. | |
604 | ||
90dee485 AM |
605 | 2020-01-13 Alan Modra <amodra@gmail.com> |
606 | ||
607 | * ns32k-dis.c (Is_gen): Use strchr, add 'f'. | |
608 | (print_insn_ns32k): Adjust ioffset for 'f' index_offset. | |
609 | ||
febda64f AM |
610 | 2020-01-13 Alan Modra <amodra@gmail.com> |
611 | ||
612 | * wasm32-dis.c (print_insn_wasm32): Localise variables. Store | |
613 | result of wasm_read_leb128 in a uint64_t and check that bits | |
614 | are not lost when copying to other locals. Use uint32_t for | |
615 | most locals. Use PRId64 when printing int64_t. | |
616 | ||
df08b588 AM |
617 | 2020-01-13 Alan Modra <amodra@gmail.com> |
618 | ||
619 | * score-dis.c: Formatting. | |
620 | * score7-dis.c: Formatting. | |
621 | ||
b2c759ce AM |
622 | 2020-01-13 Alan Modra <amodra@gmail.com> |
623 | ||
624 | * score-dis.c (print_insn_score48): Use unsigned variables for | |
625 | unsigned values. Don't left shift negative values. | |
626 | (print_insn_score32): Likewise. | |
627 | * score7-dis.c (print_insn_score32, print_insn_score16): Likewise. | |
628 | ||
5496abe1 AM |
629 | 2020-01-13 Alan Modra <amodra@gmail.com> |
630 | ||
631 | * tic4x-dis.c (tic4x_print_register): Remove dead code. | |
632 | ||
202e762b AM |
633 | 2020-01-13 Alan Modra <amodra@gmail.com> |
634 | ||
635 | * fr30-ibld.c: Regenerate. | |
636 | ||
7ef412cf AM |
637 | 2020-01-13 Alan Modra <amodra@gmail.com> |
638 | ||
639 | * xgate-dis.c (print_insn): Don't left shift signed value. | |
640 | (ripBits): Formatting, use 1u. | |
641 | ||
7f578b95 AM |
642 | 2020-01-10 Alan Modra <amodra@gmail.com> |
643 | ||
644 | * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned. | |
645 | * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval. | |
646 | ||
441af85b AM |
647 | 2020-01-10 Alan Modra <amodra@gmail.com> |
648 | ||
649 | * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG, | |
650 | and XRREG value earlier to avoid a shift with negative exponent. | |
651 | * m10200-dis.c (disassemble): Similarly. | |
652 | ||
bce58db4 NC |
653 | 2020-01-09 Nick Clifton <nickc@redhat.com> |
654 | ||
655 | PR 25224 | |
656 | * z80-dis.c (ld_ii_ii): Use correct cast. | |
657 | ||
40c75bc8 SB |
658 | 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com> |
659 | ||
660 | PR 25224 | |
661 | * z80-dis.c (ld_ii_ii): Use character constant when checking | |
662 | opcode byte value. | |
663 | ||
d835a58b JB |
664 | 2020-01-09 Jan Beulich <jbeulich@suse.com> |
665 | ||
666 | * i386-dis.c (SEP_Fixup): New. | |
667 | (SEP): Define. | |
668 | (dis386_twobyte): Use it for sysenter/sysexit. | |
669 | (enum x86_64_isa): Change amd64 enumerator to value 1. | |
670 | (OP_J): Compare isa64 against intel64 instead of amd64. | |
671 | * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64 | |
672 | forms. | |
673 | * i386-tbl.h: Re-generate. | |
674 | ||
030a2e78 AM |
675 | 2020-01-08 Alan Modra <amodra@gmail.com> |
676 | ||
677 | * z8k-dis.c: Include libiberty.h | |
678 | (instr_data_s): Make max_fetched unsigned. | |
679 | (z8k_lookup_instr): Make nibl_index and tabl_index unsigned. | |
680 | Don't exceed byte_info bounds. | |
681 | (output_instr): Make num_bytes unsigned. | |
682 | (unpack_instr): Likewise for nibl_count and loop. | |
683 | * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and | |
684 | idx unsigned. | |
685 | * z8k-opc.h: Regenerate. | |
686 | ||
bb82aefe SV |
687 | 2020-01-07 Shahab Vahedi <shahab@synopsys.com> |
688 | ||
689 | * arc-tbl.h (llock): Use 'LLOCK' as class. | |
690 | (llockd): Likewise. | |
691 | (scond): Use 'SCOND' as class. | |
692 | (scondd): Likewise. | |
693 | (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit. | |
694 | (scondd): Likewise. | |
695 | ||
cc6aa1a6 AM |
696 | 2020-01-06 Alan Modra <amodra@gmail.com> |
697 | ||
698 | * m32c-ibld.c: Regenerate. | |
699 | ||
660e62b1 AM |
700 | 2020-01-06 Alan Modra <amodra@gmail.com> |
701 | ||
702 | PR 25344 | |
703 | * z80-dis.c (suffix): Don't use a local struct buffer copy. | |
704 | Peek at next byte to prevent recursion on repeated prefix bytes. | |
705 | Ensure uninitialised "mybuf" is not accessed. | |
706 | (print_insn_z80): Don't zero n_fetch and n_used here,.. | |
707 | (print_insn_z80_buf): ..do it here instead. | |
708 | ||
c9ae58fe AM |
709 | 2020-01-04 Alan Modra <amodra@gmail.com> |
710 | ||
711 | * m32r-ibld.c: Regenerate. | |
712 | ||
5f57d4ec AM |
713 | 2020-01-04 Alan Modra <amodra@gmail.com> |
714 | ||
715 | * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value. | |
716 | ||
2c5c1196 AM |
717 | 2020-01-04 Alan Modra <amodra@gmail.com> |
718 | ||
719 | * crx-dis.c (match_opcode): Avoid shift left of signed value. | |
720 | ||
2e98c6c5 AM |
721 | 2020-01-04 Alan Modra <amodra@gmail.com> |
722 | ||
723 | * d30v-dis.c (print_insn): Avoid signed overflow in left shift. | |
724 | ||
567dfba2 JB |
725 | 2020-01-03 Jan Beulich <jbeulich@suse.com> |
726 | ||
5437a02a JB |
727 | * aarch64-tbl.h (aarch64_opcode_table): Use |
728 | SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}. | |
729 | ||
730 | 2020-01-03 Jan Beulich <jbeulich@suse.com> | |
731 | ||
732 | * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD | |
567dfba2 JB |
733 | forms of SUDOT and USDOT. |
734 | ||
8c45011a JB |
735 | 2020-01-03 Jan Beulich <jbeulich@suse.com> |
736 | ||
5437a02a | 737 | * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from |
8c45011a JB |
738 | uzip{1,2}. |
739 | * opcodes/aarch64-dis-2.c: Re-generate. | |
740 | ||
f4950f76 JB |
741 | 2020-01-03 Jan Beulich <jbeulich@suse.com> |
742 | ||
5437a02a | 743 | * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit |
f4950f76 JB |
744 | FMMLA encoding. |
745 | * opcodes/aarch64-dis-2.c: Re-generate. | |
746 | ||
6655dba2 SB |
747 | 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com> |
748 | ||
749 | * z80-dis.c: Add support for eZ80 and Z80 instructions. | |
750 | ||
b14ce8bf AM |
751 | 2020-01-01 Alan Modra <amodra@gmail.com> |
752 | ||
753 | Update year range in copyright notice of all files. | |
754 | ||
0b114740 | 755 | For older changes see ChangeLog-2019 |
3499769a | 756 | \f |
0b114740 | 757 | Copyright (C) 2020 Free Software Foundation, Inc. |
3499769a AM |
758 | |
759 | Copying and distribution of this file, with or without modification, | |
760 | are permitted in any medium without royalty provided the copyright | |
761 | notice and this notice are preserved. | |
762 | ||
763 | Local Variables: | |
764 | mode: change-log | |
765 | left-margin: 8 | |
766 | fill-column: 74 | |
767 | version-control: never | |
768 | End: |