[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2017-04-05  Pedro Alves  <palves@redhat.com>

	* arc-dis.c (parse_option, parse_disassembler_options): Constify.
	* arm-dis.c (parse_arm_disassembler_options): Constify.
	* ppc-dis.c (powerpc_init_dialect): Constify local.
	* vax-dis.c (parse_disassembler_options): Constify.

2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>

	* riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
	RISCV_GP_SYMBOL.

2017-03-30  Pip Cet  <pipcet@gmail.com>

	* configure.ac: Add (empty) bfd_wasm32_arch target.
	* configure: Regenerate
	* po/opcodes.pot: Regenerate.

2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>

	Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
	OSA2015.
	* opcodes/sparc-opc.c (asi_table): New ASIs.

2017-03-29  Alan Modra  <amodra@gmail.com>

	* ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
	"raw" option.
	(lookup_powerpc): Don't special case -1 dialect.  Handle
	PPC_OPCODE_RAW.
	(print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
	lookup_powerpc call, pass it on second.

2017-03-27  Alan Modra  <amodra@gmail.com>

	PR 21303
	* ppc-dis.c (struct ppc_mopt): Comment.
	(ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.

2017-03-27  Rinat Zelig  <rinat@mellanox.com>

	* arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
	* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
	F_NPS_M, F_NPS_CORE, F_NPS_ALL.
	(insert_nps_misc_imm_offset): New function.
	(extract_nps_misc imm_offset): New function.
	(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
	(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.

2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-mkopc.c (main): Remove vx2 check.
	* s390-opc.txt: Remove vx2 instruction flags.

2017-03-21  Rinat Zelig  <rinat@mellanox.com>

	* arc-nps400-tbl.h: Add cp32/cp16 instructions format.
	* arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
	(insert_nps_imm_offset): New function.
	(extract_nps_imm_offset): New function.
	(insert_nps_imm_entry): New function.
	(extract_nps_imm_entry): New function.

2017-03-17  Alan Modra  <amodra@gmail.com>

	PR 21248
	* ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
	mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
	those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.

2017-03-14  Kito Cheng  <kito.cheng@gmail.com>

	* riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
	<c.andi>: Likewise.
	<c.addiw> Likewise.

2017-03-14  Kito Cheng  <kito.cheng@gmail.com>

	* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.

2017-03-13  Andrew Waterman  <andrew@sifive.com>

	* riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
	<srl> Likewise.
	<srai> Likewise.
	<sra> Likewise.

2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Replace S with Load.
	* i386-opc.h (S): Removed.
	(Load): New.
	(i386_opcode_modifier): Replace s with load.
	* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
	and {evex}.  Replace S with Load.
	* i386-tbl.h: Regenerated.

2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Use CpuCET on rdsspq.
	* i386-tbl.h: Regenerated.

2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
	<vsx>: Do not use PPC_OPCODE_VSX3;

2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.

2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (REG_0F1E_MOD_3): New enum.
	(MOD_0F1E_PREFIX_1): Likewise.
	(MOD_0F38F5_PREFIX_2): Likewise.
	(MOD_0F38F6_PREFIX_0): Likewise.
	(RM_0F1E_MOD_3_REG_7): Likewise.
	(PREFIX_MOD_0_0F01_REG_5): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
	(PREFIX_0F1E): Likewise.
	(PREFIX_MOD_0_0FAE_REG_5): Likewise.
	(PREFIX_0F38F5): Likewise.
	(dis386_twobyte): Use PREFIX_0F1E.
	(reg_table): Add REG_0F1E_MOD_3.
	(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
	PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
	PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
	PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
	(three_byte_table): Use PREFIX_0F38F5.
	(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
	Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
	(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
	RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
	PREFIX_MOD_3_0F01_REG_5_RM_2.
	* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
	(cpu_flags): Add CpuCET.
	* i386-opc.h (CpuCET): New enum.
	(CpuUnused): Commented out.
	(i386_cpu_flags): Add cpucet.
	* i386-opc.tbl: Add Intel CET instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2017-03-06  Alan Modra  <amodra@gmail.com>

	PR 21124
	* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
	(extract_raq, extract_ras, extract_rbx): New functions.
	(powerpc_operands): Use opposite corresponding insert function.
	(Q_MASK): Define.
	(powerpc_opcodes): Apply Q_MASK to all quad insns with even
	register restriction.

2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>

	* disassemble.c Include "safe-ctype.h".
	(disassemble_init_for_target): Handle s390 init.
	(remove_whitespace_and_extra_commas): New function.
	(disassembler_options_cmp): Likewise.
	* arm-dis.c: Include "libiberty.h".
	(NUM_ELEM): Delete.
	(regnames): Use long disassembler style names.
	Add force-thumb and no-force-thumb options.
	(NUM_ARM_REGNAMES): Rename from this...
	(NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
	(get_arm_regname_num_options): Delete.
	(set_arm_regname_option): Likewise.
	(get_arm_regnames): Likewise.
	(parse_disassembler_options): Likewise.
	(parse_arm_disassembler_option): Rename from this...
	(parse_arm_disassembler_options): ...to this.  Make static.
	Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
	(print_insn): Use parse_arm_disassembler_options.
	(disassembler_options_arm): New function.
	(print_arm_disassembler_options): Handle updated regnames.
	* ppc-dis.c: Include "libiberty.h".
	(ppc_opts): Add "32" and "64" entries.
	(ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
	(powerpc_init_dialect): Add break to switch statement.
	Use new FOR_EACH_DISASSEMBLER_OPTION macro.
	(disassembler_options_powerpc): New function.
	(print_ppc_disassembler_options): Use ARRAY_SIZE.
	Remove printing of "32" and "64".
	* s390-dis.c: Include "libiberty.h".
	(init_flag): Remove unneeded variable.
	(struct s390_options_t): New structure type.
	(options): New structure.
	(init_disasm): Rename from this...
	(disassemble_init_s390): ...to this.  Add initializations for
	current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
	(print_insn_s390): Delete call to init_disasm.
	(disassembler_options_s390): New function.
	(print_s390_disassembler_options): Print using information from
	struct 'options'.
	* po/opcodes.pot: Regenerate.

2017-02-28  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (PCMPESTR_Fixup): New.
	(VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
	(prefix_table): Use PCMPESTR_Fixup.
	(vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
	PCMPESTR_Fixup.
	(vex_w_table): Delete VPCMPESTR{I,M} entries.
	* i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
	Split 64-bit and non-64-bit variants.
	* opcodes/i386-tbl.h: Re-generate.

2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>

	* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
	(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
	(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
	(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
	(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
	(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
	(OP_SVE_V_HSD): New macros.
	(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
	(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
	(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
	(aarch64_opcode_table): Add new SVE instructions.
	(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
	for rotation operands.  Add new SVE operands.
	* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
	(ins_sve_quad_index): Likewise.
	(ins_imm_rotate): Split into...
	(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
	* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
	(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
	functions.
	(aarch64_ins_sve_addr_ri_s4): New function.
	(aarch64_ins_sve_quad_index): Likewise.
	(do_misc_encoding): Handle "MOV Zn.Q, Qm".
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
	(ext_sve_quad_index): Likewise.
	(ext_imm_rotate): Split into...
	(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
	* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
	(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
	functions.
	(aarch64_ext_sve_addr_ri_s4): New function.
	(aarch64_ext_sve_quad_index): Likewise.
	(aarch64_ext_sve_index): Allow quad indices.
	(do_misc_decoding): Likewise.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
	aarch64_field_kinds.
	(OPD_F_OD_MASK): Widen by one bit.
	(OPD_F_NO_ZR): Bump accordingly.
	(get_operand_field_width): New function.
	* aarch64-opc.c (fields): Add new SVE fields.
	(operand_general_constraint_met_p): Handle new SVE operands.
	(aarch64_print_operand): Likewise.
	* aarch64-opc-2.c: Regenerate.

2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>

	* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
	(aarch64_feature_compnum): ...this.
	(SIMD_V8_3): Replace with...
	(COMPNUM): ...this.
	(CNUM_INSN): New macro.
	(aarch64_opcode_table): Use it for the complex number instructions.

2017-02-24  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.

2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>

	Add support for associating SPARC ASIs with an architecture level.
	* include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
	* opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
	decoding of SPARC ASIs.

2017-02-23  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (get_valid_dis386): Don't special case VEX opcode
	82. For 3-byte VEX only special case opcode 77 in VEX_0F space.

2017-02-21  Jan Beulich  <jbeulich@suse.com>

	* aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
	1 (instead of to itself). Correct typo.

2017-02-14  Andrew Waterman  <andrew@sifive.com>

	* riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
	pseudoinstructions.

2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
	(aarch64_sys_reg_supported_p): Handle them.

2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (UIMM6_20R): Define.
	(SIMM12_20): Use above.
	(SIMM12_20R): Define.
	(SIMM3_5_S): Use above.
	(UIMM7_A32_11R_S): Define.
	(UIMM7_9_S): Use above.
	(UIMM3_13R_S): Define.
	(SIMM11_A32_7_S): Use above.
	(SIMM9_8R): Define.
	(UIMM10_A32_8_S): Use above.
	(UIMM8_8R_S): Define.
	(W6): Use above.
	(arc_relax_opcodes): Use all above defines.

2017-02-15  Vineet Gupta <vgupta@synopsys.com>

	* arc-regs.h: Distinguish some of the registers different on
	ARC700 and HS38 cpus.

2017-02-14  Alan Modra  <amodra@gmail.com>

	PR 21118
	* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
	with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.

2017-02-11  Stafford Horne  <shorne@gmail.com>
	    Alan Modra  <amodra@gmail.com>

	* cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
	Use insn_bytes_value and insn_int_value directly instead.  Don't
	free allocated memory until function exit.

2017-02-10  Nicholas Piggin  <npiggin@gmail.com>

	* ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.

2017-02-03  Nick Clifton  <nickc@redhat.com>

	PR 21096
	* aarch64-opc.c (print_register_list): Ensure that the register
	list index will fir into the tb buffer.
	(print_register_offset_address): Likewise.
	* tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.

2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>

	PR 21056
	* tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
	instructions when the previous fetch packet ends with a 32-bit
	instruction.

2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>

        * pru-opc.c: Remove vague reference to a future GDB port.

2017-01-20  Nick Clifton  <nickc@redhat.com>

	* po/ga.po: Updated Irish translation.

2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.

2017-01-13  Yao Qi  <yao.qi@linaro.org>

	* m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
	if FETCH_DATA returns 0.
	(m68k_scan_mask): Likewise.
	(print_insn_m68k): Update code to handle -1 return value.

2017-01-13  Yao Qi  <yao.qi@linaro.org>

	* m68k-dis.c (enum print_insn_arg_error): New.
	(NEXTBYTE): Replace -3 with
	PRINT_INSN_ARG_MEMORY_ERROR.
	(NEXTULONG): Likewise.
	(NEXTSINGLE): Likewise.
	(NEXTDOUBLE): Likewise.
	(NEXTDOUBLE): Likewise.
	(NEXTPACKED): Likewise.
	(FETCH_ARG): Likewise.
	(FETCH_DATA): Update comments.
	(print_insn_arg): Update comments. Replace magic numbers with
	enum.
	(match_insn_m68k): Likewise.

2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
	CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
	* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
	(i386_cpu_flags): Add cpuavx512_vpopcntdq.
	* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.

2017-01-12  Yao Qi  <yao.qi@linaro.org>

	* msp430-dis.c (msp430_singleoperand): Return -1 if
	msp430dis_opcode_signed returns false.
	(msp430_doubleoperand): Likewise.
	(msp430_branchinstr): Return -1 if
	msp430dis_opcode_unsigned returns false.
	(msp430x_calla_instr): Likewise.
	(print_insn_msp430): Likewise.

2017-01-05  Nick Clifton  <nickc@redhat.com>

	PR 20946
	* frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
	could not be matched.
	(frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
	NULL.

2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
	(aarch64_opcode_table): Use RCPC_INSN.

2017-01-03  Kito Cheng  <kito.cheng@gmail.com>

	* riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
	extension.
	* riscv-opcodes/all-opcodes: Likewise.

2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>

	* riscv-dis.c (print_insn_args): Add fall through comment.

2017-01-03  Nick Clifton  <nickc@redhat.com>

	* po/sr.po: New Serbian translation.
	* configure.ac (ALL_LINGUAS): Add sr.
	* configure: Regenerate.

2017-01-02  Alan Modra  <amodra@gmail.com>

	* epiphany-desc.h: Regenerate.
	* epiphany-opc.h: Regenerate.
	* fr30-desc.h: Regenerate.
	* fr30-opc.h: Regenerate.
	* frv-desc.h: Regenerate.
	* frv-opc.h: Regenerate.
	* ip2k-desc.h: Regenerate.
	* ip2k-opc.h: Regenerate.
	* iq2000-desc.h: Regenerate.
	* iq2000-opc.h: Regenerate.
	* lm32-desc.h: Regenerate.
	* lm32-opc.h: Regenerate.
	* m32c-desc.h: Regenerate.
	* m32c-opc.h: Regenerate.
	* m32r-desc.h: Regenerate.
	* m32r-opc.h: Regenerate.
	* mep-desc.h: Regenerate.
	* mep-opc.h: Regenerate.
	* mt-desc.h: Regenerate.
	* mt-opc.h: Regenerate.
	* or1k-desc.h: Regenerate.
	* or1k-opc.h: Regenerate.
	* xc16x-desc.h: Regenerate.
	* xc16x-opc.h: Regenerate.
	* xstormy16-desc.h: Regenerate.
	* xstormy16-opc.h: Regenerate.

2017-01-02  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2016
\f
Copyright (C) 2017 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
f995bbe8 PA	1	2017-04-05 Pedro Alves <palves@redhat.com>
	2
	3	* arc-dis.c (parse_option, parse_disassembler_options): Constify.
	4	* arm-dis.c (parse_arm_disassembler_options): Constify.
	5	* ppc-dis.c (powerpc_init_dialect): Constify local.
	6	* vax-dis.c (parse_disassembler_options): Constify.
	7
b5292032 PD	8	2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
	9
	10	* riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
	11	RISCV_GP_SYMBOL.
	12
f96bd6c2 PC	13	2017-03-30 Pip Cet <pipcet@gmail.com>
	14
	15	* configure.ac: Add (empty) bfd_wasm32_arch target.
	16	* configure: Regenerate
	17	* po/opcodes.pot: Regenerate.
	18
f7c514a3 JM	19	2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
	20
	21	Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
	22	OSA2015.
	23	* opcodes/sparc-opc.c (asi_table): New ASIs.
	24
52be03fd AM	25	2017-03-29 Alan Modra <amodra@gmail.com>
	26
	27	* ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
	28	"raw" option.
	29	(lookup_powerpc): Don't special case -1 dialect. Handle
	30	PPC_OPCODE_RAW.
	31	(print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
	32	lookup_powerpc call, pass it on second.
	33
9b753937 AM	34	2017-03-27 Alan Modra <amodra@gmail.com>
	35
	36	PR 21303
	37	* ppc-dis.c (struct ppc_mopt): Comment.
	38	(ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
	39
c0c31e91 RZ	40	2017-03-27 Rinat Zelig <rinat@mellanox.com>
	41
	42	* arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
	43	* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
	44	F_NPS_M, F_NPS_CORE, F_NPS_ALL.
	45	(insert_nps_misc_imm_offset): New function.
	46	(extract_nps_misc imm_offset): New function.
	47	(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
	48	(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
	49
2253c8f0 AK	50	2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	51
	52	* s390-mkopc.c (main): Remove vx2 check.
	53	* s390-opc.txt: Remove vx2 instruction flags.
	54
645d3342 RZ	55	2017-03-21 Rinat Zelig <rinat@mellanox.com>
	56
	57	* arc-nps400-tbl.h: Add cp32/cp16 instructions format.
	58	* arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
	59	(insert_nps_imm_offset): New function.
	60	(extract_nps_imm_offset): New function.
	61	(insert_nps_imm_entry): New function.
	62	(extract_nps_imm_entry): New function.
	63
4b94dd2d AM	64	2017-03-17 Alan Modra <amodra@gmail.com>
	65
	66	PR 21248
	67	* ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
	68	mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
	69	those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
	70
b416fe87 KC	71	2017-03-14 Kito Cheng <kito.cheng@gmail.com>
	72
	73	* riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
	74	<c.andi>: Likewise.
	75	<c.addiw> Likewise.
	76
03b039a5 KC	77	2017-03-14 Kito Cheng <kito.cheng@gmail.com>
	78
	79	* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
	80
2c232b83 AW	81	2017-03-13 Andrew Waterman <andrew@sifive.com>
	82
	83	* riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
	84	<srl> Likewise.
	85	<srai> Likewise.
	86	<sra> Likewise.
	87
86fa6981 L	88	2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
	89
	90	* i386-gen.c (opcode_modifiers): Replace S with Load.
	91	* i386-opc.h (S): Removed.
	92	(Load): New.
	93	(i386_opcode_modifier): Replace s with load.
	94	* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
	95	and {evex}. Replace S with Load.
	96	* i386-tbl.h: Regenerated.
	97
c1fe188b L	98	2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
	99
	100	* i386-opc.tbl: Use CpuCET on rdsspq.
	101	* i386-tbl.h: Regenerated.
	102
4b8b687e PB	103	2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
	104
	105	* ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
	106	<vsx>: Do not use PPC_OPCODE_VSX3;
	107
1437d063 PB	108	2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
	109
	110	* ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
	111
603555e5 L	112	2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
	113
	114	* i386-dis.c (REG_0F1E_MOD_3): New enum.
	115	(MOD_0F1E_PREFIX_1): Likewise.
	116	(MOD_0F38F5_PREFIX_2): Likewise.
	117	(MOD_0F38F6_PREFIX_0): Likewise.
	118	(RM_0F1E_MOD_3_REG_7): Likewise.
	119	(PREFIX_MOD_0_0F01_REG_5): Likewise.
	120	(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
	121	(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
	122	(PREFIX_0F1E): Likewise.
	123	(PREFIX_MOD_0_0FAE_REG_5): Likewise.
	124	(PREFIX_0F38F5): Likewise.
	125	(dis386_twobyte): Use PREFIX_0F1E.
	126	(reg_table): Add REG_0F1E_MOD_3.
	127	(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
	128	PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
	129	PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
	130	PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
	131	(three_byte_table): Use PREFIX_0F38F5.
	132	(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
	133	Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
	134	(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
	135	RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
	136	PREFIX_MOD_3_0F01_REG_5_RM_2.
	137	* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
	138	(cpu_flags): Add CpuCET.
	139	* i386-opc.h (CpuCET): New enum.
	140	(CpuUnused): Commented out.
	141	(i386_cpu_flags): Add cpucet.
	142	* i386-opc.tbl: Add Intel CET instructions.
	143	* i386-init.h: Regenerated.
	144	* i386-tbl.h: Likewise.
	145
73f07bff AM	146	2017-03-06 Alan Modra <amodra@gmail.com>
	147
	148	PR 21124
	149	* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
	150	(extract_raq, extract_ras, extract_rbx): New functions.
	151	(powerpc_operands): Use opposite corresponding insert function.
	152	(Q_MASK): Define.
	153	(powerpc_opcodes): Apply Q_MASK to all quad insns with even
	154	register restriction.
	155
65b48a81 PB	156	2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
	157
	158	* disassemble.c Include "safe-ctype.h".
	159	(disassemble_init_for_target): Handle s390 init.
	160	(remove_whitespace_and_extra_commas): New function.
	161	(disassembler_options_cmp): Likewise.
	162	* arm-dis.c: Include "libiberty.h".
	163	(NUM_ELEM): Delete.
	164	(regnames): Use long disassembler style names.
	165	Add force-thumb and no-force-thumb options.
	166	(NUM_ARM_REGNAMES): Rename from this...
	167	(NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
	168	(get_arm_regname_num_options): Delete.
	169	(set_arm_regname_option): Likewise.
	170	(get_arm_regnames): Likewise.
	171	(parse_disassembler_options): Likewise.
	172	(parse_arm_disassembler_option): Rename from this...
	173	(parse_arm_disassembler_options): ...to this. Make static.
	174	Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
	175	(print_insn): Use parse_arm_disassembler_options.
	176	(disassembler_options_arm): New function.
	177	(print_arm_disassembler_options): Handle updated regnames.
	178	* ppc-dis.c: Include "libiberty.h".
	179	(ppc_opts): Add "32" and "64" entries.
	180	(ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
	181	(powerpc_init_dialect): Add break to switch statement.
	182	Use new FOR_EACH_DISASSEMBLER_OPTION macro.
	183	(disassembler_options_powerpc): New function.
	184	(print_ppc_disassembler_options): Use ARRAY_SIZE.
	185	Remove printing of "32" and "64".
	186	* s390-dis.c: Include "libiberty.h".
	187	(init_flag): Remove unneeded variable.
	188	(struct s390_options_t): New structure type.
	189	(options): New structure.
	190	(init_disasm): Rename from this...
	191	(disassemble_init_s390): ...to this. Add initializations for
	192	current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
	193	(print_insn_s390): Delete call to init_disasm.
	194	(disassembler_options_s390): New function.
	195	(print_s390_disassembler_options): Print using information from
	196	struct 'options'.
	197	* po/opcodes.pot: Regenerate.
	198
15c7c1d8 JB	199	2017-02-28 Jan Beulich <jbeulich@suse.com>
	200
	201	* i386-dis.c (PCMPESTR_Fixup): New.
	202	(VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
	203	(prefix_table): Use PCMPESTR_Fixup.
	204	(vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
	205	PCMPESTR_Fixup.
	206	(vex_w_table): Delete VPCMPESTR{I,M} entries.
	207	* i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
	208	Split 64-bit and non-64-bit variants.
	209	* opcodes/i386-tbl.h: Re-generate.
	210
582e12bf RS	211	2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
	212
	213	* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
	214	(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
	215	(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
	216	(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
	217	(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
	218	(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
	219	(OP_SVE_V_HSD): New macros.
	220	(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
	221	(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
	222	(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
	223	(aarch64_opcode_table): Add new SVE instructions.
	224	(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
	225	for rotation operands. Add new SVE operands.
	226	* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
	227	(ins_sve_quad_index): Likewise.
	228	(ins_imm_rotate): Split into...
	229	(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
	230	* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
	231	(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
	232	functions.
	233	(aarch64_ins_sve_addr_ri_s4): New function.
	234	(aarch64_ins_sve_quad_index): Likewise.
	235	(do_misc_encoding): Handle "MOV Zn.Q, Qm".
	236	* aarch64-asm-2.c: Regenerate.
	237	* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
	238	(ext_sve_quad_index): Likewise.
	239	(ext_imm_rotate): Split into...
	240	(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
	241	* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
	242	(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
	243	functions.
	244	(aarch64_ext_sve_addr_ri_s4): New function.
	245	(aarch64_ext_sve_quad_index): Likewise.
	246	(aarch64_ext_sve_index): Allow quad indices.
	247	(do_misc_decoding): Likewise.
	248	* aarch64-dis-2.c: Regenerate.
	249	* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
	250	aarch64_field_kinds.
	251	(OPD_F_OD_MASK): Widen by one bit.
	252	(OPD_F_NO_ZR): Bump accordingly.
	253	(get_operand_field_width): New function.
	254	* aarch64-opc.c (fields): Add new SVE fields.
	255	(operand_general_constraint_met_p): Handle new SVE operands.
	256	(aarch64_print_operand): Likewise.
	257	* aarch64-opc-2.c: Regenerate.
	258
f482d304 RS	259	2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
	260
	261	* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
	262	(aarch64_feature_compnum): ...this.
	263	(SIMD_V8_3): Replace with...
	264	(COMPNUM): ...this.
	265	(CNUM_INSN): New macro.
	266	(aarch64_opcode_table): Use it for the complex number instructions.
	267
7db2c588 JB	268	2017-02-24 Jan Beulich <jbeulich@suse.com>
	269
	270	* i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
	271
1e9d41d4 SL	272	2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
	273
	274	Add support for associating SPARC ASIs with an architecture level.
	275	* include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
	276	* opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
	277	decoding of SPARC ASIs.
	278
53c4d625 JB	279	2017-02-23 Jan Beulich <jbeulich@suse.com>
	280
	281	* i386-dis.c (get_valid_dis386): Don't special case VEX opcode
	282	82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
	283
11648de5 JB	284	2017-02-21 Jan Beulich <jbeulich@suse.com>
	285
	286	* aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
	287	1 (instead of to itself). Correct typo.
	288
f98d33be AW	289	2017-02-14 Andrew Waterman <andrew@sifive.com>
	290
	291	* riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
	292	pseudoinstructions.
	293
773fb663 RS	294	2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
	295
	296	* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
	297	(aarch64_sys_reg_supported_p): Handle them.
	298
cc07cda6 CZ	299	2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
	300
	301	* arc-opc.c (UIMM6_20R): Define.
	302	(SIMM12_20): Use above.
	303	(SIMM12_20R): Define.
	304	(SIMM3_5_S): Use above.
	305	(UIMM7_A32_11R_S): Define.
	306	(UIMM7_9_S): Use above.
	307	(UIMM3_13R_S): Define.
	308	(SIMM11_A32_7_S): Use above.
	309	(SIMM9_8R): Define.
	310	(UIMM10_A32_8_S): Use above.
	311	(UIMM8_8R_S): Define.
	312	(W6): Use above.
	313	(arc_relax_opcodes): Use all above defines.
	314
66a5a740 VG	315	2017-02-15 Vineet Gupta <vgupta@synopsys.com>
	316
	317	* arc-regs.h: Distinguish some of the registers different on
	318	ARC700 and HS38 cpus.
	319
7e0de605 AM	320	2017-02-14 Alan Modra <amodra@gmail.com>
	321
	322	PR 21118
	323	* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
	324	with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
	325
54064fdb AM	326	2017-02-11 Stafford Horne <shorne@gmail.com>
	327	Alan Modra <amodra@gmail.com>
	328
	329	* cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
	330	Use insn_bytes_value and insn_int_value directly instead. Don't
	331	free allocated memory until function exit.
	332
dce75bf9 NP	333	2017-02-10 Nicholas Piggin <npiggin@gmail.com>
	334
	335	* ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
	336
1b7e3d2f NC	337	2017-02-03 Nick Clifton <nickc@redhat.com>
	338
	339	PR 21096
	340	* aarch64-opc.c (print_register_list): Ensure that the register
	341	list index will fir into the tb buffer.
	342	(print_register_offset_address): Likewise.
	343	* tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
	344
8ec5cf65 AD	345	2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
	346
	347	PR 21056
	348	* tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
	349	instructions when the previous fetch packet ends with a 32-bit
	350	instruction.
	351
a1aa5e81 DD	352	2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
	353
	354	* pru-opc.c: Remove vague reference to a future GDB port.
	355
add3afb2 NC	356	2017-01-20 Nick Clifton <nickc@redhat.com>
	357
	358	* po/ga.po: Updated Irish translation.
	359
c13a63b0 SN	360	2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
	361
	362	* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
	363
9608051a YQ	364	2017-01-13 Yao Qi <yao.qi@linaro.org>
	365
	366	* m68k-dis.c (match_insn_m68k): Extend comments. Return -1
	367	if FETCH_DATA returns 0.
	368	(m68k_scan_mask): Likewise.
	369	(print_insn_m68k): Update code to handle -1 return value.
	370
f622ea96 YQ	371	2017-01-13 Yao Qi <yao.qi@linaro.org>
	372
	373	* m68k-dis.c (enum print_insn_arg_error): New.
	374	(NEXTBYTE): Replace -3 with
	375	PRINT_INSN_ARG_MEMORY_ERROR.
	376	(NEXTULONG): Likewise.
	377	(NEXTSINGLE): Likewise.
	378	(NEXTDOUBLE): Likewise.
	379	(NEXTDOUBLE): Likewise.
	380	(NEXTPACKED): Likewise.
	381	(FETCH_ARG): Likewise.
	382	(FETCH_DATA): Update comments.
	383	(print_insn_arg): Update comments. Replace magic numbers with
	384	enum.
	385	(match_insn_m68k): Likewise.
	386
620214f7 IT	387	2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
	388
	389	* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
	390	* i386-dis-evex.h (evex_table): Updated.
	391	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
	392	CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	393	(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
	394	* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
	395	(i386_cpu_flags): Add cpuavx512_vpopcntdq.
	396	* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
	397	* i386-init.h: Regenerate.
	398	* i386-tbl.h: Ditto.
	399
d95014a2 YQ	400	2017-01-12 Yao Qi <yao.qi@linaro.org>
	401
	402	* msp430-dis.c (msp430_singleoperand): Return -1 if
	403	msp430dis_opcode_signed returns false.
	404	(msp430_doubleoperand): Likewise.
	405	(msp430_branchinstr): Return -1 if
	406	msp430dis_opcode_unsigned returns false.
	407	(msp430x_calla_instr): Likewise.
	408	(print_insn_msp430): Likewise.
	409
0ae60c3e NC	410	2017-01-05 Nick Clifton <nickc@redhat.com>
	411
	412	PR 20946
	413	* frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
	414	could not be matched.
	415	(frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
	416	NULL.
	417
d74d4880 SN	418	2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
	419
	420	* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
	421	(aarch64_opcode_table): Use RCPC_INSN.
	422
cc917fd9 KC	423	2017-01-03 Kito Cheng <kito.cheng@gmail.com>
	424
	425	* riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
	426	extension.
	427	* riscv-opcodes/all-opcodes: Likewise.
	428
b52d3cfc DP	429	2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
	430
	431	* riscv-dis.c (print_insn_args): Add fall through comment.
	432
f90c58d5 NC	433	2017-01-03 Nick Clifton <nickc@redhat.com>
	434
	435	* po/sr.po: New Serbian translation.
	436	* configure.ac (ALL_LINGUAS): Add sr.
	437	* configure: Regenerate.
	438
f47b0d4a AM	439	2017-01-02 Alan Modra <amodra@gmail.com>
	440
	441	* epiphany-desc.h: Regenerate.
	442	* epiphany-opc.h: Regenerate.
	443	* fr30-desc.h: Regenerate.
	444	* fr30-opc.h: Regenerate.
	445	* frv-desc.h: Regenerate.
	446	* frv-opc.h: Regenerate.
	447	* ip2k-desc.h: Regenerate.
	448	* ip2k-opc.h: Regenerate.
	449	* iq2000-desc.h: Regenerate.
	450	* iq2000-opc.h: Regenerate.
	451	* lm32-desc.h: Regenerate.
	452	* lm32-opc.h: Regenerate.
	453	* m32c-desc.h: Regenerate.
	454	* m32c-opc.h: Regenerate.
	455	* m32r-desc.h: Regenerate.
	456	* m32r-opc.h: Regenerate.
	457	* mep-desc.h: Regenerate.
	458	* mep-opc.h: Regenerate.
	459	* mt-desc.h: Regenerate.
	460	* mt-opc.h: Regenerate.
	461	* or1k-desc.h: Regenerate.
	462	* or1k-opc.h: Regenerate.
	463	* xc16x-desc.h: Regenerate.
	464	* xc16x-opc.h: Regenerate.
	465	* xstormy16-desc.h: Regenerate.
	466	* xstormy16-opc.h: Regenerate.
	467
2571583a AM	468	2017-01-02 Alan Modra <amodra@gmail.com>
	469
	470	Update year range in copyright notice of all files.
	471
5c1ad6b5	472	For older changes see ChangeLog-2016
3499769a	473	\f
5c1ad6b5	474	Copyright (C) 2017 Free Software Foundation, Inc.
3499769a AM	475
	476	Copying and distribution of this file, with or without modification,
	477	are permitted in any medium without royalty provided the copyright
	478	notice and this notice are preserved.
	479
	480	Local Variables:
	481	mode: change-log
	482	left-margin: 8
	483	fill-column: 74
	484	version-control: never
	485	End: