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2010-05-26 Tristan Gingold <gingold@adacore.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
51b5d4a8
AM		 12010-05-19 Alan Modra <amodra@gmail.com>
2
3 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
4 divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
5
85d4ac0b
AM		 62010-05-13 Alan Modra <amodra@gmail.com>
7
8 * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
9
4547cb56
NC		 102010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
11
12 * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
13 format.
14 (print_insn_thumb16): Add support for new %W format.
15
6540b386
TG		 162010-05-07 Tristan Gingold <gingold@adacore.com>
17
18 * Makefile.in: Regenerate with automake 1.11.1.
19 * aclocal.m4: Ditto.
20
3e01a7fd
NC		 212010-05-05 Nick Clifton <nickc@redhat.com>
22
23 * po/es.po: Updated Spanish translation.
24
9c9c98a5
NC		 252010-04-22 Nick Clifton <nickc@redhat.com>
26
27 * po/opcodes.pot: Updated by the Translation project.
28 * po/vi.po: Updated Vietnamese translation.
29
f07af43e
L		 302010-04-16 H.J. Lu <hongjiu.lu@intel.com>
31
32 * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
33 bits in opcode.
34
3d540e93
NC		 352010-04-09 Nick Clifton <nickc@redhat.com>
36
37 * i386-dis.c (print_insn): Remove unused variable op.
38 (OP_sI): Remove unused variable mask.
39
397841b5
AM		 402010-04-07 Alan Modra <amodra@gmail.com>
41
42 * configure: Regenerate.
43
cee62821
PB		 442010-04-06 Peter Bergner <bergner@vnet.ibm.com>
45
46 * ppc-opc.c (RBOPT): New define.
47 ("dccci"): Enable for PPCA2. Make operands optional.
48 ("iccci"): Likewise. Do not deprecate for PPC476.
49
accf4463
NC		 502010-04-02 Masaki Muranaka <monaka@monami-software.com>
51
52 * cr16-opc.c (cr16_instruction): Fix typo in comment.
53
40b36596
JM		 542010-03-25 Joseph Myers <joseph@codesourcery.com>
55
56 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
57 * Makefile.in: Regenerate.
58 * configure.in (bfd_tic6x_arch): New.
59 * configure: Regenerate.
60 * disassemble.c (ARCH_tic6x): Define if ARCH_all.
61 (disassembler): Handle TI C6X.
62 * tic6x-dis.c: New.
63
1985c81c
MF		 642010-03-24 Mike Frysinger <vapier@gentoo.org>
65
66 * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
67
f66187fd
JM		 682010-03-23 Joseph Myers <joseph@codesourcery.com>
69
70 * dis-buf.c (buffer_read_memory): Give error for reading just
71 before the start of memory.
72
ce7d077e
SP		 732010-03-22 Sebastian Pop <sebastian.pop@amd.com>
74 Quentin Neill <quentin.neill@amd.com>
75
76 * i386-dis.c (OP_LWP_I): Removed.
77 (reg_table): Do not use OP_LWP_I, use Iq.
78 (OP_LWPCB_E): Remove use of names16.
79 (OP_LWP_E): Same.
80 * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
81 should not set the Vex.length bit.
82 * i386-tbl.h: Regenerated.
83
63d0fa4e
AM		 842010-02-25 Edmar Wienskoski <edmar@freescale.com>
85
86 * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
87
c060226a
NC		 882010-02-24 Nick Clifton <nickc@redhat.com>
89
90 PR binutils/6773
91 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
92 <prefix>asx. Replace <prefix>subaddx with <prefix>sax.
93 (thumb32_opcodes): Likewise.
94
ab7875de
NC		 952010-02-15 Nick Clifton <nickc@redhat.com>
96
97 * po/vi.po: Updated Vietnamese translation.
98
fee1d3e8
DE		 992010-02-12 Doug Evans <dje@sebabeach.org>
100
101 * lm32-opinst.c: Regenerate.
102
37ec9240
DE		 1032010-02-11 Doug Evans <dje@sebabeach.org>
104
9468ae89
DE		 105 * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
106 (print_address): Delete CGEN_PRINT_ADDRESS.
107 * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
108 * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
109 * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
110 * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
111
37ec9240
DE		 112 * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
113 * frv-desc.c, * frv-desc.h, * frv-opc.c,
114 * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
115 * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
116 * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
117 * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
118 * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
119 * mep-desc.c, * mep-desc.h, * mep-opc.c,
120 * mt-desc.c, * mt-desc.h, * mt-opc.c,
121 * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
122 * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
123 * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
124
c75ef631
L		 1252010-02-11 H.J. Lu <hongjiu.lu@intel.com>
126
127 * i386-dis.c: Update copyright.
128 * i386-gen.c: Likewise.
129 * i386-opc.h: Likewise.
130 * i386-opc.tbl: Likewise.
131
a683cc34
SP		 1322010-02-10 Quentin Neill <quentin.neill@amd.com>
133 Sebastian Pop <sebastian.pop@amd.com>
134
135 * i386-dis.c (OP_EX_VexImmW): Reintroduced
136 function to handle 5th imm8 operand.
137 (PREFIX_VEX_3A48): Added.
138 (PREFIX_VEX_3A49): Added.
139 (VEX_W_3A48_P_2): Added.
140 (VEX_W_3A49_P_2): Added.
141 (prefix table): Added entries for PREFIX_VEX_3A48
142 and PREFIX_VEX_3A49.
143 (vex table): Added entries for VEX_W_3A48_P_2 and
144 and VEX_W_3A49_P_2.
145 * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
146 for Vec_Imm4 operands.
147 * i386-opc.h (enum): Added Vec_Imm4.
148 (i386_operand_type): Added vec_imm4.
149 * i386-opc.tbl: Add entries for vpermilp[ds].
150 * i386-init.h: Regenerated.
151 * i386-tbl.h: Regenerated.
152
cdc51b07
RS		 1532010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
154
155 * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
156 and "pwr7". Move "a2" into alphabetical order.
157
ce3d2015
AM		 1582010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
159
160 * ppc-dis.c (ppc_opts): Add titan entry.
161 * ppc-opc.c (TITAN, MULHW): Define.
162 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
163
68339fdf
SP		 1642010-02-03 Quentin Neill <quentin.neill@amd.com>
165
166 * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
167 to CPU_BDVER1_FLAGS
168 * i386-init.h: Regenerated.
169
f3d55a94
AG		 1702010-02-03 Anthony Green <green@moxielogic.com>
171
172 * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
173 0x0f, and make 0x00 an illegal instruction.
174
b0e28b39
DJ		 1752010-01-29 Daniel Jacobowitz <dan@codesourcery.com>
176
177 * opcodes/arm-dis.c (struct arm_private_data): New.
178 (print_insn_coprocessor, print_insn_arm): Update to use struct
179 arm_private_data.
180 (is_mapping_symbol, get_map_sym_type): New functions.
181 (get_sym_code_type): Check the symbol's section. Do not check
182 mapping symbols.
183 (print_insn): Default to disassembling ARM mode code. Check
184 for mapping symbols separately from other symbols. Use
185 struct arm_private_data.
186
1c480963
L		 1872010-01-28 H.J. Lu <hongjiu.lu@intel.com>
188
189 * i386-dis.c (EXVexWdqScalar): New.
190 (vex_scalar_w_dq_mode): Likewise.
191 (prefix_table): Update entries for PREFIX_VEX_3899,
192 PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
193 PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
194 PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
195 PREFIX_VEX_38BD and PREFIX_VEX_38BF.
196 (intel_operand_size): Handle vex_scalar_w_dq_mode.
197 (OP_EX): Likewise.
198
539f890d
L		 1992010-01-27 H.J. Lu <hongjiu.lu@intel.com>
200
201 * i386-dis.c (XMScalar): New.
202 (EXdScalar): Likewise.
203 (EXqScalar): Likewise.
204 (EXqScalarS): Likewise.
205 (VexScalar): Likewise.
206 (EXdVexScalarS): Likewise.
207 (EXqVexScalarS): Likewise.
208 (XMVexScalar): Likewise.
209 (scalar_mode): Likewise.
210 (d_scalar_mode): Likewise.
211 (d_scalar_swap_mode): Likewise.
212 (q_scalar_mode): Likewise.
213 (q_scalar_swap_mode): Likewise.
214 (vex_scalar_mode): Likewise.
215 (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
216 VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
217 VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
218 VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
219 VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
220 VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
221 VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
222 VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
223 VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
224 VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
225 (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
226 VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
227 VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
228 VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
229 VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
230 VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
231 VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
232 VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
233 VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
234 (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
235 q_scalar_mode, q_scalar_swap_mode.
236 (OP_XMM): Handle scalar_mode.
237 (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
238 and q_scalar_swap_mode.
239 (OP_VEX): Handle vex_scalar_mode.
240
208b4d78
L		 2412010-01-24 H.J. Lu <hongjiu.lu@intel.com>
242
243 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
244
448b213a
L		 2452010-01-24 H.J. Lu <hongjiu.lu@intel.com>
246
247 * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
248
47cf8fa0
L		 2492010-01-24 H.J. Lu <hongjiu.lu@intel.com>
250
251 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
252
592d1631
L		 2532010-01-24 H.J. Lu <hongjiu.lu@intel.com>
254
255 * i386-dis.c (Bad_Opcode): New.
256 (bad_opcode): Likewise.
257 (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
258 (dis386_twobyte): Likewise.
259 (reg_table): Likewise.
260 (prefix_table): Likewise.
261 (x86_64_table): Likewise.
262 (vex_len_table): Likewise.
263 (vex_w_table): Likewise.
264 (mod_table): Likewise.
265 (rm_table): Likewise.
266 (float_reg): Likewise.
267 (reg_table): Remove trailing "(bad)" entries.
268 (prefix_table): Likewise.
269 (x86_64_table): Likewise.
270 (vex_len_table): Likewise.
271 (vex_w_table): Likewise.
272 (mod_table): Likewise.
273 (rm_table): Likewise.
274 (get_valid_dis386): Handle bytemode 0.
275
712366da
L		 2762010-01-23 H.J. Lu <hongjiu.lu@intel.com>
277
278 * i386-opc.h (VEXScalar): New.
279
280 * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
281 instructions.
282 * i386-tbl.h: Regenerated.
283
706e8205 2842010-01-21 H.J. Lu <hongjiu.lu@intel.com>
73bb6729
L		 285
286 * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
287
288 * i386-opc.tbl: Add xsave64 and xrstor64.
289 * i386-tbl.h: Regenerated.
290
99ea83aa
NC		 2912010-01-20 Nick Clifton <nickc@redhat.com>
292
293 PR 11170
294 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
295 based post-indexed addressing.
296
a6461c02
SP		 2972010-01-15 Sebastian Pop <sebastian.pop@amd.com>
298
299 * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
300 * i386-tbl.h: Regenerated.
301
a2a7d12c
L		 3022010-01-14 H.J. Lu <hongjiu.lu@intel.com>
303
304 * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
305 comments.
306
b9733481
L		 3072010-01-14 H.J. Lu <hongjiu.lu@intel.com>
308
309 * i386-dis.c (names_mm): New.
310 (intel_names_mm): Likewise.
311 (att_names_mm): Likewise.
312 (names_xmm): Likewise.
313 (intel_names_xmm): Likewise.
314 (att_names_xmm): Likewise.
315 (names_ymm): Likewise.
316 (intel_names_ymm): Likewise.
317 (att_names_ymm): Likewise.
318 (print_insn): Set names_mm, names_xmm and names_ymm.
319 (OP_MMX): Use names_mm, names_xmm and names_ymm.
320 (OP_XMM): Likewise.
321 (OP_EM): Likewise.
322 (OP_EMC): Likewise.
323 (OP_MXC): Likewise.
324 (OP_EX): Likewise.
325 (XMM_Fixup): Likewise.
326 (OP_VEX): Likewise.
327 (OP_EX_VexReg): Likewise.
328 (OP_Vex_2src): Likewise.
329 (OP_Vex_2src_1): Likewise.
330 (OP_Vex_2src_2): Likewise.
331 (OP_REG_VexI4): Likewise.
332
5e6718e4
L		 3332010-01-13 H.J. Lu <hongjiu.lu@intel.com>
334
335 * i386-dis.c (print_insn): Update comments.
336
d869730d
L		 3372010-01-12 H.J. Lu <hongjiu.lu@intel.com>
338
339 * i386-dis.c (rex_original): Removed.
340 (ckprefix): Remove rex_original.
341 (print_insn): Update comments.
342
3725885a
RW		 3432010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
344
345 * Makefile.in: Regenerate.
346 * configure: Regenerate.
347
b7cd1872
DE		 3482010-01-07 Doug Evans <dje@sebabeach.org>
349
350 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
351 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
352 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
353 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
354 * xstormy16-ibld.c: Regenerate.
355
69dd9865
SP		 3562010-01-06 Quentin Neill <quentin.neill@amd.com>
357
358 * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
359 * i386-init.h: Regenerated.
360
e3e535bc
NC		 3612010-01-06 Daniel Gutson <dgutson@codesourcery.com>
362
363 * arm-dis.c (print_insn): Fixed search for next symbol and data
364 dumping condition, and the initial mapping symbol state.
365
fe8afbc4
DE		 3662010-01-05 Doug Evans <dje@sebabeach.org>
367
368 * cgen-ibld.in: #include "cgen/basic-modes.h".
369 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
370 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
371 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
372 * xstormy16-ibld.c: Regenerate.
373
2edcd244
NC		 3742010-01-04 Nick Clifton <nickc@redhat.com>
375
376 PR 11123
377 * arm-dis.c (print_insn_coprocessor): Initialise value.
378
0dc93057
AM		 3792010-01-04 Edmar Wienskoski <edmar@freescale.com>
380
381 * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
382
05994f45
DE		 3832010-01-02 Doug Evans <dje@sebabeach.org>
384
385 * cgen-asm.in: Update copyright year.
386 * cgen-dis.in: Update copyright year.
387 * cgen-ibld.in: Update copyright year.
388 * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
389 * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
390 * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
391 * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
392 * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
393 * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
394 * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
395 * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
396 * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
397 * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
398 * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
399 * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
400 * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
401 * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
402 * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
403 * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
404 * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
405 * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
406 * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
407 * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
408 * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
2426c15f 409
43ecc30f 410For older changes see ChangeLog-2009
252b5132
RH		 411\f
412Local Variables:
2f6d2f85
NC		 413mode: change-log
414left-margin: 8
415fill-column: 74
252b5132
RH		 416version-control: never
417End:
GDB Binutils - Deliverables
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