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ubsan: ns32k: left shift cannot be represented in type 'int'
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
fb4cb4e2
AM		 12019-12-11 Alan Modra <amodra@gmail.com>
2
3 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
4 (bit_extract_simple, sign_extend): Likewise.
5
96f1f604
AM		 62019-12-11 Alan Modra <amodra@gmail.com>
7
8 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
9
8c9b4171
AM		 102019-12-11 Alan Modra <amodra@gmail.com>
11
12 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
13
334175b6
AM		 142019-12-11 Alan Modra <amodra@gmail.com>
15
16 * m68k-dis.c (COERCE32): Cast value first.
17 (NEXTLONG, NEXTULONG): Avoid signed overflow.
18
f8a87c78
AM		 192019-12-11 Alan Modra <amodra@gmail.com>
20
21 * h8300-dis.c (extract_immediate): Avoid signed overflow.
22 (bfd_h8_disassemble): Likewise.
23
159653d8
AM		 242019-12-11 Alan Modra <amodra@gmail.com>
25
26 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
27 past end of operands array.
28
d93bba9e
AM		 292019-12-11 Alan Modra <amodra@gmail.com>
30
31 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
32 overflow when collecting bytes of a number.
33
c202f69e
AM		 342019-12-11 Alan Modra <amodra@gmail.com>
35
36 * cris-dis.c (print_with_operands): Avoid signed integer
37 overflow when collecting bytes of a 32-bit integer.
38
0ef562a4
AM		 392019-12-11 Alan Modra <amodra@gmail.com>
40
41 * cr16-dis.c (EXTRACT, SBM): Rewrite.
42 (cr16_match_opcode): Delete duplicate bcond test.
43
2fd2b153
AM		 442019-12-11 Alan Modra <amodra@gmail.com>
45
46 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
47 (SIGNBIT): New.
48 (MASKBITS, SIGNEXTEND): Rewrite.
49 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
50 unsigned arithmetic, instead assign result of SIGNEXTEND back
51 to x.
52 (fmtconst_val): Use 1u in shift expression.
53
a11db3e9
AM		 542019-12-11 Alan Modra <amodra@gmail.com>
55
56 * arc-dis.c (find_format_from_table): Use ull constant when
57 shifting by up to 32.
58
9d48687b
AM		 592019-12-11 Alan Modra <amodra@gmail.com>
60
61 PR 25270
62 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
63 false when field is zero for sve_size_tsz_bhs.
64
b8e61daa
AM		 652019-12-11 Alan Modra <amodra@gmail.com>
66
67 * epiphany-ibld.c: Regenerate.
68
20135676
AM		 692019-12-10 Alan Modra <amodra@gmail.com>
70
71 PR 24960
72 * disassemble.c (disassemble_free_target): New function.
73
103ebbc3
AM		 742019-12-10 Alan Modra <amodra@gmail.com>
75
76 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
77 * disassemble.c (disassemble_init_for_target): Likewise.
78 * bpf-dis.c: Regenerate.
79 * epiphany-dis.c: Regenerate.
80 * fr30-dis.c: Regenerate.
81 * frv-dis.c: Regenerate.
82 * ip2k-dis.c: Regenerate.
83 * iq2000-dis.c: Regenerate.
84 * lm32-dis.c: Regenerate.
85 * m32c-dis.c: Regenerate.
86 * m32r-dis.c: Regenerate.
87 * mep-dis.c: Regenerate.
88 * mt-dis.c: Regenerate.
89 * or1k-dis.c: Regenerate.
90 * xc16x-dis.c: Regenerate.
91 * xstormy16-dis.c: Regenerate.
92
6f0e0752
AM		 932019-12-10 Alan Modra <amodra@gmail.com>
94
95 * ppc-dis.c (private): Delete variable.
96 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
97 (powerpc_init_dialect): Don't use global private.
98
e7c22a69
AM		 992019-12-10 Alan Modra <amodra@gmail.com>
100
101 * s12z-opc.c: Formatting.
102
0a6aef6b
AM		 1032019-12-08 Alan Modra <amodra@gmail.com>
104
105 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
106 registers.
107
2dc4b12f
JB		 1082019-12-05 Jan Beulich <jbeulich@suse.com>
109
110 * aarch64-tbl.h (aarch64_feature_crypto,
111 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
112 CRYPTO_V8_2_INSN): Delete.
113
378fd436
AM		 1142019-12-05 Alan Modra <amodra@gmail.com>
115
116 PR 25249
117 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
118 (struct string_buf): New.
119 (strbuf): New function.
120 (get_field): Use strbuf rather than strdup of local temp.
121 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
122 (get_field_rfsl, get_field_imm15): Likewise.
123 (get_field_rd, get_field_r1, get_field_r2): Update macros.
124 (get_field_special): Likewise. Don't strcpy spr. Formatting.
125 (print_insn_microblaze): Formatting. Init and pass string_buf to
126 get_field functions.
127
0ba59a29
JB		 1282019-12-04 Jan Beulich <jbeulich@suse.com>
129
130 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
131 * i386-tbl.h: Re-generate.
132
77ad8092
JB		 1332019-12-04 Jan Beulich <jbeulich@suse.com>
134
135 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
136
3036c899
JB		 1372019-12-04 Jan Beulich <jbeulich@suse.com>
138
139 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
140 forms.
141 (xbegin): Drop DefaultSize.
142 * i386-tbl.h: Re-generate.
143
8b301fbb
MI		 1442019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
145
146 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
147 Change the coproc CRC conditions to use the extension
148 feature set, second word, base on ARM_EXT2_CRC.
149
6aa385b9
JB		 1502019-11-14 Jan Beulich <jbeulich@suse.com>
151
152 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
153 * i386-tbl.h: Re-generate.
154
0cfa3eb3
JB		 1552019-11-14 Jan Beulich <jbeulich@suse.com>
156
157 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
158 JumpInterSegment, and JumpAbsolute entries.
159 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
160 JUMP_ABSOLUTE): Define.
161 (struct i386_opcode_modifier): Extend jump field to 3 bits.
162 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
163 fields.
164 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
165 JumpInterSegment): Define.
166 * i386-tbl.h: Re-generate.
167
6f2f06be
JB		 1682019-11-14 Jan Beulich <jbeulich@suse.com>
169
170 * i386-gen.c (operand_type_init): Remove
171 OPERAND_TYPE_JUMPABSOLUTE entry.
172 (opcode_modifiers): Add JumpAbsolute entry.
173 (operand_types): Remove JumpAbsolute entry.
174 * i386-opc.h (JumpAbsolute): Move between enums.
175 (struct i386_opcode_modifier): Add jumpabsolute field.
176 (union i386_operand_type): Remove jumpabsolute field.
177 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
178 * i386-init.h, i386-tbl.h: Re-generate.
179
601e8564
JB		 1802019-11-14 Jan Beulich <jbeulich@suse.com>
181
182 * i386-gen.c (opcode_modifiers): Add AnySize entry.
183 (operand_types): Remove AnySize entry.
184 * i386-opc.h (AnySize): Move between enums.
185 (struct i386_opcode_modifier): Add anysize field.
186 (OTUnused): Un-comment.
187 (union i386_operand_type): Remove anysize field.
188 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
189 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
190 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
191 AnySize.
192 * i386-tbl.h: Re-generate.
193
7722d40a
JW		 1942019-11-12 Nelson Chu <nelson.chu@sifive.com>
195
196 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
197 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
198 use the floating point register (FPR).
199
ce760a76
MI		 2002019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
201
202 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
203 cmode 1101.
204 (is_mve_encoding_conflict): Update cmode conflict checks for
205 MVE_VMVN_IMM.
206
51c8edf6
JB		 2072019-11-12 Jan Beulich <jbeulich@suse.com>
208
209 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
210 entry.
211 (operand_types): Remove EsSeg entry.
212 (main): Replace stale use of OTMax.
213 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
214 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
215 (EsSeg): Delete.
216 (OTUnused): Comment out.
217 (union i386_operand_type): Remove esseg field.
218 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
219 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
220 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
221 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
222 * i386-init.h, i386-tbl.h: Re-generate.
223
474da251
JB		 2242019-11-12 Jan Beulich <jbeulich@suse.com>
225
226 * i386-gen.c (operand_instances): Add RegB entry.
227 * i386-opc.h (enum operand_instance): Add RegB.
228 * i386-opc.tbl (RegC, RegD, RegB): Define.
229 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
230 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
231 monitorx, mwaitx): Drop ImmExt and convert encodings
232 accordingly.
233 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
234 (edx, rdx): Add Instance=RegD.
235 (ebx, rbx): Add Instance=RegB.
236 * i386-tbl.h: Re-generate.
237
75e5731b
JB		 2382019-11-12 Jan Beulich <jbeulich@suse.com>
239
240 * i386-gen.c (operand_type_init): Adjust
241 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
242 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
243 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
244 (operand_instances): New.
245 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
246 (output_operand_type): New parameter "instance". Process it.
247 (process_i386_operand_type): New local variable "instance".
248 (main): Adjust static assertions.
249 * i386-opc.h (INSTANCE_WIDTH): Define.
250 (enum operand_instance): New.
251 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
252 (union i386_operand_type): Replace acc, inoutportreg, and
253 shiftcount by instance.
254 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
255 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
256 Add Instance=.
257 * i386-init.h, i386-tbl.h: Re-generate.
258
91802f3c
JB		 2592019-11-11 Jan Beulich <jbeulich@suse.com>
260
261 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
262 smaxp/sminp entries' "tied_operand" field to 2.
263
4f5fc85d
JB		 2642019-11-11 Jan Beulich <jbeulich@suse.com>
265
266 * aarch64-opc.c (operand_general_constraint_met_p): Replace
267 "index" local variable by that of the already existing "num".
268
dc2be329
L		 2692019-11-08 H.J. Lu <hongjiu.lu@intel.com>
270
271 PR gas/25167
272 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
273 * i386-tbl.h: Regenerated.
274
f74a6307
JB		 2752019-11-08 Jan Beulich <jbeulich@suse.com>
276
277 * i386-gen.c (operand_type_init): Add Class= to
278 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
279 OPERAND_TYPE_REGBND entry.
280 (operand_classes): Add RegMask and RegBND entries.
281 (operand_types): Drop RegMask and RegBND entry.
282 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
283 (RegMask, RegBND): Delete.
284 (union i386_operand_type): Remove regmask and regbnd fields.
285 * i386-opc.tbl (RegMask, RegBND): Define.
286 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
287 Class=RegBND.
288 * i386-init.h, i386-tbl.h: Re-generate.
289
3528c362
JB		 2902019-11-08 Jan Beulich <jbeulich@suse.com>
291
292 * i386-gen.c (operand_type_init): Add Class= to
293 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
294 OPERAND_TYPE_REGZMM entries.
295 (operand_classes): Add RegMMX and RegSIMD entries.
296 (operand_types): Drop RegMMX and RegSIMD entries.
297 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
298 (RegMMX, RegSIMD): Delete.
299 (union i386_operand_type): Remove regmmx and regsimd fields.
300 * i386-opc.tbl (RegMMX): Define.
301 (RegXMM, RegYMM, RegZMM): Add Class=.
302 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
303 Class=RegSIMD.
304 * i386-init.h, i386-tbl.h: Re-generate.
305
4a5c67ed
JB		 3062019-11-08 Jan Beulich <jbeulich@suse.com>
307
308 * i386-gen.c (operand_type_init): Add Class= to
309 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
310 entries.
311 (operand_classes): Add RegCR, RegDR, and RegTR entries.
312 (operand_types): Drop Control, Debug, and Test entries.
313 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
314 (Control, Debug, Test): Delete.
315 (union i386_operand_type): Remove control, debug, and test
316 fields.
317 * i386-opc.tbl (Control, Debug, Test): Define.
318 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
319 Class=RegDR, and Test by Class=RegTR.
320 * i386-init.h, i386-tbl.h: Re-generate.
321
00cee14f
JB		 3222019-11-08 Jan Beulich <jbeulich@suse.com>
323
324 * i386-gen.c (operand_type_init): Add Class= to
325 OPERAND_TYPE_SREG entry.
326 (operand_classes): Add SReg entry.
327 (operand_types): Drop SReg entry.
328 * i386-opc.h (enum operand_class): Add SReg.
329 (SReg): Delete.
330 (union i386_operand_type): Remove sreg field.
331 * i386-opc.tbl (SReg): Define.
332 * i386-reg.tbl: Replace SReg by Class=SReg.
333 * i386-init.h, i386-tbl.h: Re-generate.
334
bab6aec1
JB		 3352019-11-08 Jan Beulich <jbeulich@suse.com>
336
337 * i386-gen.c (operand_type_init): Add Class=. New
338 OPERAND_TYPE_ANYIMM entry.
339 (operand_classes): New.
340 (operand_types): Drop Reg entry.
341 (output_operand_type): New parameter "class". Process it.
342 (process_i386_operand_type): New local variable "class".
343 (main): Adjust static assertions.
344 * i386-opc.h (CLASS_WIDTH): Define.
345 (enum operand_class): New.
346 (Reg): Replace by Class. Adjust comment.
347 (union i386_operand_type): Replace reg by class.
348 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
349 Class=.
350 * i386-reg.tbl: Replace Reg by Class=Reg.
351 * i386-init.h: Re-generate.
352
1f4cd317
MM		 3532019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
354
355 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
356 (aarch64_opcode_table): Add data gathering hint mnemonic.
357 * opcodes/aarch64-dis-2.c: Account for new instruction.
358
616ce08e
MM		 3592019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
360
361 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
362
363
8382113f
MM		 3642019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
365
366 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
367 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
368 aarch64_feature_f64mm): New feature sets.
369 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
370 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
371 instructions.
372 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
373 macros.
374 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
375 (OP_SVE_QQQ): New qualifier.
376 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
377 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
378 the movprfx constraint.
379 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
380 (aarch64_opcode_table): Define new instructions smmla,
381 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
382 uzip{1/2}, trn{1/2}.
383 * aarch64-opc.c (operand_general_constraint_met_p): Handle
384 AARCH64_OPND_SVE_ADDR_RI_S4x32.
385 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
386 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
387 Account for new instructions.
388 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
389 S4x32 operand.
390 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
391
aab2c27d
MM		 3922019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3932019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
394
395 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
396 Armv8.6-A.
397 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
398 (neon_opcodes): Add bfloat SIMD instructions.
399 (print_insn_coprocessor): Add new control character %b to print
400 condition code without checking cp_num.
401 (print_insn_neon): Account for BFloat16 instructions that have no
402 special top-byte handling.
403
33593eaf
MM		 4042019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4052019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
406
407 * arm-dis.c (print_insn_coprocessor,
408 print_insn_generic_coprocessor): Create wrapper functions around
409 the implementation of the print_insn_coprocessor control codes.
410 (print_insn_coprocessor_1): Original print_insn_coprocessor
411 function that now takes which array to look at as an argument.
412 (print_insn_arm): Use both print_insn_coprocessor and
413 print_insn_generic_coprocessor.
414 (print_insn_thumb32): As above.
415
df678013
MM		 4162019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4172019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
418
419 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
420 in reglane special case.
421 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
422 aarch64_find_next_opcode): Account for new instructions.
423 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
424 in reglane special case.
425 * aarch64-opc.c (struct operand_qualifier_data): Add data for
426 new AARCH64_OPND_QLF_S_2H qualifier.
427 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
428 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
429 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
430 sets.
431 (BFLOAT_SVE, BFLOAT): New feature set macros.
432 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
433 instructions.
434 (aarch64_opcode_table): Define new instructions bfdot,
435 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
436 bfcvtn2, bfcvt.
437
8ae2d3d9
MM		 4382019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4392019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
440
441 * aarch64-tbl.h (ARMV8_6): New macro.
442
142861df
JB		 4432019-11-07 Jan Beulich <jbeulich@suse.com>
444
445 * i386-dis.c (prefix_table): Add mcommit.
446 (rm_table): Add rdpru.
447 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
448 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
449 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
450 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
451 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
452 * i386-opc.tbl (mcommit, rdpru): New.
453 * i386-init.h, i386-tbl.h: Re-generate.
454
081e283f
JB		 4552019-11-07 Jan Beulich <jbeulich@suse.com>
456
457 * i386-dis.c (OP_Mwait): Drop local variable "names", use
458 "names32" instead.
459 (OP_Monitor): Drop local variable "op1_names", re-purpose
460 "names" for it instead, and replace former "names" uses by
461 "names32" ones.
462
c050c89a
JB		 4632019-11-07 Jan Beulich <jbeulich@suse.com>
464
465 PR/gas 25167
466 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
467 operand-less forms.
468 * opcodes/i386-tbl.h: Re-generate.
469
7abb8d81
JB		 4702019-11-05 Jan Beulich <jbeulich@suse.com>
471
472 * i386-dis.c (OP_Mwaitx): Delete.
473 (prefix_table): Use OP_Mwait for mwaitx entry.
474 (OP_Mwait): Also handle mwaitx.
475
267b8516
JB		 4762019-11-05 Jan Beulich <jbeulich@suse.com>
477
478 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
479 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
480 (prefix_table): Add respective entries.
481 (rm_table): Link to those entries.
482
f8687e93
JB		 4832019-11-05 Jan Beulich <jbeulich@suse.com>
484
485 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
486 (REG_0F1C_P_0_MOD_0): ... this.
487 (REG_0F1E_MOD_3): Rename to ...
488 (REG_0F1E_P_1_MOD_3): ... this.
489 (RM_0F01_REG_5): Rename to ...
490 (RM_0F01_REG_5_MOD_3): ... this.
491 (RM_0F01_REG_7): Rename to ...
492 (RM_0F01_REG_7_MOD_3): ... this.
493 (RM_0F1E_MOD_3_REG_7): Rename to ...
494 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
495 (RM_0FAE_REG_6): Rename to ...
496 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
497 (RM_0FAE_REG_7): Rename to ...
498 (RM_0FAE_REG_7_MOD_3): ... this.
499 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
500 (PREFIX_0F01_REG_5_MOD_0): ... this.
501 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
502 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
503 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
504 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
505 (PREFIX_0FAE_REG_0): Rename to ...
506 (PREFIX_0FAE_REG_0_MOD_3): ... this.
507 (PREFIX_0FAE_REG_1): Rename to ...
508 (PREFIX_0FAE_REG_1_MOD_3): ... this.
509 (PREFIX_0FAE_REG_2): Rename to ...
510 (PREFIX_0FAE_REG_2_MOD_3): ... this.
511 (PREFIX_0FAE_REG_3): Rename to ...
512 (PREFIX_0FAE_REG_3_MOD_3): ... this.
513 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
514 (PREFIX_0FAE_REG_4_MOD_0): ... this.
515 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
516 (PREFIX_0FAE_REG_4_MOD_3): ... this.
517 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
518 (PREFIX_0FAE_REG_5_MOD_0): ... this.
519 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
520 (PREFIX_0FAE_REG_5_MOD_3): ... this.
521 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
522 (PREFIX_0FAE_REG_6_MOD_0): ... this.
523 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
524 (PREFIX_0FAE_REG_6_MOD_3): ... this.
525 (PREFIX_0FAE_REG_7): Rename to ...
526 (PREFIX_0FAE_REG_7_MOD_0): ... this.
527 (PREFIX_MOD_0_0FC3): Rename to ...
528 (PREFIX_0FC3_MOD_0): ... this.
529 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
530 (PREFIX_0FC7_REG_6_MOD_0): ... this.
531 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
532 (PREFIX_0FC7_REG_6_MOD_3): ... this.
533 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
534 (PREFIX_0FC7_REG_7_MOD_3): ... this.
535 (reg_table, prefix_table, mod_table, rm_table): Adjust
536 accordingly.
537
5103274f
NC		 5382019-11-04 Nick Clifton <nickc@redhat.com>
539
540 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
541 of a v850 system register. Move the v850_sreg_names array into
542 this function.
543 (get_v850_reg_name): Likewise for ordinary register names.
544 (get_v850_vreg_name): Likewise for vector register names.
545 (get_v850_cc_name): Likewise for condition codes.
546 * get_v850_float_cc_name): Likewise for floating point condition
547 codes.
548 (get_v850_cacheop_name): Likewise for cache-ops.
549 (get_v850_prefop_name): Likewise for pref-ops.
550 (disassemble): Use the new accessor functions.
551
1820262b
DB		 5522019-10-30 Delia Burduv <delia.burduv@arm.com>
553
554 * aarch64-opc.c (print_immediate_offset_address): Don't print the
555 immediate for the writeback form of ldraa/ldrab if it is 0.
556 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
557 * aarch64-opc-2.c: Regenerated.
558
3cc17af5
JB		 5592019-10-30 Jan Beulich <jbeulich@suse.com>
560
561 * i386-gen.c (operand_type_shorthands): Delete.
562 (operand_type_init): Expand previous shorthands.
563 (set_bitfield_from_shorthand): Rename back to ...
564 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
565 of operand_type_init[].
566 (set_bitfield): Adjust call to the above function.
567 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
568 RegXMM, RegYMM, RegZMM): Define.
569 * i386-reg.tbl: Expand prior shorthands.
570
a2cebd03
JB		 5712019-10-30 Jan Beulich <jbeulich@suse.com>
572
573 * i386-gen.c (output_i386_opcode): Change order of fields
574 emitted to output.
575 * i386-opc.h (struct insn_template): Move operands field.
576 Convert extension_opcode field to unsigned short.
577 * i386-tbl.h: Re-generate.
578
507916b8
JB		 5792019-10-30 Jan Beulich <jbeulich@suse.com>
580
581 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
582 of W.
583 * i386-opc.h (W): Extend comment.
584 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
585 general purpose variants not allowing for byte operands.
586 * i386-tbl.h: Re-generate.
587
efea62b4
NC		 5882019-10-29 Nick Clifton <nickc@redhat.com>
589
590 * tic30-dis.c (print_branch): Correct size of operand array.
591
9adb2591
NC		 5922019-10-29 Nick Clifton <nickc@redhat.com>
593
594 * d30v-dis.c (print_insn): Check that operand index is valid
595 before attempting to access the operands array.
596
993a00a9
NC		 5972019-10-29 Nick Clifton <nickc@redhat.com>
598
599 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
600 locating the bit to be tested.
601
66a66a17
NC		 6022019-10-29 Nick Clifton <nickc@redhat.com>
603
604 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
605 values.
606 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
607 (print_insn_s12z): Check for illegal size values.
608
1ee3542c
NC		 6092019-10-28 Nick Clifton <nickc@redhat.com>
610
611 * csky-dis.c (csky_chars_to_number): Check for a negative
612 count. Use an unsigned integer to construct the return value.
613
bbf9a0b5
NC		 6142019-10-28 Nick Clifton <nickc@redhat.com>
615
616 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
617 operand buffer. Set value to 15 not 13.
618 (get_register_operand): Use OPERAND_BUFFER_LEN.
619 (get_indirect_operand): Likewise.
620 (print_two_operand): Likewise.
621 (print_three_operand): Likewise.
622 (print_oar_insn): Likewise.
623
d1e304bc
NC		 6242019-10-28 Nick Clifton <nickc@redhat.com>
625
626 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
627 (bit_extract_simple): Likewise.
628 (bit_copy): Likewise.
629 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
630 index_offset array are not accessed.
631
dee33451
NC		 6322019-10-28 Nick Clifton <nickc@redhat.com>
633
634 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
635 operand.
636
27cee81d
NC		 6372019-10-25 Nick Clifton <nickc@redhat.com>
638
639 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
640 access to opcodes.op array element.
641
de6d8dc2
NC		 6422019-10-23 Nick Clifton <nickc@redhat.com>
643
644 * rx-dis.c (get_register_name): Fix spelling typo in error
645 message.
646 (get_condition_name, get_flag_name, get_double_register_name)
647 (get_double_register_high_name, get_double_register_low_name)
648 (get_double_control_register_name, get_double_condition_name)
649 (get_opsize_name, get_size_name): Likewise.
650
6207ed28
NC		 6512019-10-22 Nick Clifton <nickc@redhat.com>
652
653 * rx-dis.c (get_size_name): New function. Provides safe
654 access to name array.
655 (get_opsize_name): Likewise.
656 (print_insn_rx): Use the accessor functions.
657
12234dfd
NC		 6582019-10-16 Nick Clifton <nickc@redhat.com>
659
660 * rx-dis.c (get_register_name): New function. Provides safe
661 access to name array.
662 (get_condition_name, get_flag_name, get_double_register_name)
663 (get_double_register_high_name, get_double_register_low_name)
664 (get_double_control_register_name, get_double_condition_name):
665 Likewise.
666 (print_insn_rx): Use the accessor functions.
667
1d378749
NC		 6682019-10-09 Nick Clifton <nickc@redhat.com>
669
670 PR 25041
671 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
672 instructions.
673
d241b910
JB		 6742019-10-07 Jan Beulich <jbeulich@suse.com>
675
676 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
677 (cmpsd): Likewise. Move EsSeg to other operand.
678 * opcodes/i386-tbl.h: Re-generate.
679
f5c5b7c1
AM		 6802019-09-23 Alan Modra <amodra@gmail.com>
681
682 * m68k-dis.c: Include cpu-m68k.h
683
7beeaeb8
AM		 6842019-09-23 Alan Modra <amodra@gmail.com>
685
686 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
687 "elf/mips.h" earlier.
688
3f9aad11
JB		 6892018-09-20 Jan Beulich <jbeulich@suse.com>
690
691 PR gas/25012
692 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
693 with SReg operand.
694 * i386-tbl.h: Re-generate.
695
fd361982
AM		 6962019-09-18 Alan Modra <amodra@gmail.com>
697
698 * arc-ext.c: Update throughout for bfd section macro changes.
699
e0b2a78c
SM		 7002019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
701
702 * Makefile.in: Re-generate.
703 * configure: Re-generate.
704
7e9ad3a3
JW		 7052019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
706
707 * riscv-opc.c (riscv_opcodes): Change subset field
708 to insn_class field for all instructions.
709 (riscv_insn_types): Likewise.
710
bb695960
PB		 7112019-09-16 Phil Blundell <pb@pbcl.net>
712
713 * configure: Regenerated.
714
8063ab7e
MV		 7152019-09-10 Miod Vallat <miod@online.fr>
716
717 PR 24982
718 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
719
60391a25
PB		 7202019-09-09 Phil Blundell <pb@pbcl.net>
721
722 binutils 2.33 branch created.
723
f44b758d
NC		 7242019-09-03 Nick Clifton <nickc@redhat.com>
725
726 PR 24961
727 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
728 greater than zero before indexing via (bufcnt -1).
729
1e4b5e7d
NC		 7302019-09-03 Nick Clifton <nickc@redhat.com>
731
732 PR 24958
733 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
734 (MAX_SPEC_REG_NAME_LEN): Define.
735 (struct mmix_dis_info): Use defined constants for array lengths.
736 (get_reg_name): New function.
737 (get_sprec_reg_name): New function.
738 (print_insn_mmix): Use new functions.
739
c4a23bf8
SP		 7402019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
741
742 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
743 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
744 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
745
a051e2f3
KT		 7462019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
747
748 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
749 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
750 (aarch64_sys_reg_supported_p): Update checks for the above.
751
08132bdd
SP		 7522019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
753
754 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
755 cases MVE_SQRSHRL and MVE_UQRSHLL.
756 (print_insn_mve): Add case for specifier 'k' to check
757 specific bit of the instruction.
758
d88bdcb4
PA		 7592019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
760
761 PR 24854
762 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
763 encountering an unknown machine type.
764 (print_insn_arc): Handle arc_insn_length returning 0. In error
765 cases return -1 rather than calling abort.
766
bc750500
JB		 7672019-08-07 Jan Beulich <jbeulich@suse.com>
768
769 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
770 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
771 IgnoreSize.
772 * i386-tbl.h: Re-generate.
773
23d188c7
BW		 7742019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
775
776 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
777 instructions.
778
c0d6f62f
JW		 7792019-07-30 Mel Chen <mel.chen@sifive.com>
780
781 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
782 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
783
784 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
785 fscsr.
786
0f3f7167
CZ		 7872019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
788
789 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
790 and MPY class instructions.
791 (parse_option): Add nps400 option.
792 (print_arc_disassembler_options): Add nps400 info.
793
7e126ba3
CZ		 7942019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
795
796 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
797 (bspop): Likewise.
798 (modapp): Likewise.
799 * arc-opc.c (RAD_CHK): Add.
800 * arc-tbl.h: Regenerate.
801
a028026d
KT		 8022019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
803
804 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
805 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
806
ac79ff9e
NC		 8072019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
808
809 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
810 instructions as UNPREDICTABLE.
811
231097b0
JM		 8122019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
813
814 * bpf-desc.c: Regenerated.
815
1d942ae9
JB		 8162019-07-17 Jan Beulich <jbeulich@suse.com>
817
818 * i386-gen.c (static_assert): Define.
819 (main): Use it.
820 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
821 (Opcode_Modifier_Num): ... this.
822 (Mem): Delete.
823
dfd69174
JB		 8242019-07-16 Jan Beulich <jbeulich@suse.com>
825
826 * i386-gen.c (operand_types): Move RegMem ...
827 (opcode_modifiers): ... here.
828 * i386-opc.h (RegMem): Move to opcode modifer enum.
829 (union i386_operand_type): Move regmem field ...
830 (struct i386_opcode_modifier): ... here.
831 * i386-opc.tbl (RegMem): Define.
832 (mov, movq): Move RegMem on segment, control, debug, and test
833 register flavors.
834 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
835 to non-SSE2AVX flavor.
836 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
837 Move RegMem on register only flavors. Drop IgnoreSize from
838 legacy encoding flavors.
839 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
840 flavors.
841 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
842 register only flavors.
843 (vmovd): Move RegMem and drop IgnoreSize on register only
844 flavor. Change opcode and operand order to store form.
845 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
846
21df382b
JB		 8472019-07-16 Jan Beulich <jbeulich@suse.com>
848
849 * i386-gen.c (operand_type_init, operand_types): Replace SReg
850 entries.
851 * i386-opc.h (SReg2, SReg3): Replace by ...
852 (SReg): ... this.
853 (union i386_operand_type): Replace sreg fields.
854 * i386-opc.tbl (mov, ): Use SReg.
855 (push, pop): Likewies. Drop i386 and x86-64 specific segment
856 register flavors.
857 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
858 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
859
3719fd55
JM		 8602019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
861
862 * bpf-desc.c: Regenerate.
863 * bpf-opc.c: Likewise.
864 * bpf-opc.h: Likewise.
865
92434a14
JM		 8662019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
867
868 * bpf-desc.c: Regenerate.
869 * bpf-opc.c: Likewise.
870
43dd7626
HPN		 8712019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
872
873 * arm-dis.c (print_insn_coprocessor): Rename index to
874 index_operand.
875
98602811
JW		 8762019-07-05 Kito Cheng <kito.cheng@sifive.com>
877
878 * riscv-opc.c (riscv_insn_types): Add r4 type.
879
880 * riscv-opc.c (riscv_insn_types): Add b and j type.
881
882 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
883 format for sb type and correct s type.
884
01c1ee4a
RS		 8852019-07-02 Richard Sandiford <richard.sandiford@arm.com>
886
887 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
888 SVE FMOV alias of FCPY.
889
83adff69
RS		 8902019-07-02 Richard Sandiford <richard.sandiford@arm.com>
891
892 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
893 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
894
89418844
RS		 8952019-07-02 Richard Sandiford <richard.sandiford@arm.com>
896
897 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
898 registers in an instruction prefixed by MOVPRFX.
899
41be57ca
MM		 9002019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
901
902 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
903 sve_size_13 icode to account for variant behaviour of
904 pmull{t,b}.
905 * aarch64-dis-2.c: Regenerate.
906 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
907 sve_size_13 icode to account for variant behaviour of
908 pmull{t,b}.
909 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
910 (OP_SVE_VVV_Q_D): Add new qualifier.
911 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
912 (struct aarch64_opcode): Split pmull{t,b} into those requiring
913 AES and those not.
914
9d3bf266
JB		 9152019-07-01 Jan Beulich <jbeulich@suse.com>
916
917 * opcodes/i386-gen.c (operand_type_init): Remove
918 OPERAND_TYPE_VEC_IMM4 entry.
919 (operand_types): Remove Vec_Imm4.
920 * opcodes/i386-opc.h (Vec_Imm4): Delete.
921 (union i386_operand_type): Remove vec_imm4.
922 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
923 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
924
c3949f43
JB		 9252019-07-01 Jan Beulich <jbeulich@suse.com>
926
927 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
928 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
929 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
930 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
931 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
932 monitorx, mwaitx): Drop ImmExt from operand-less forms.
933 * i386-tbl.h: Re-generate.
934
5641ec01
JB		 9352019-07-01 Jan Beulich <jbeulich@suse.com>
936
937 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
938 register operands.
939 * i386-tbl.h: Re-generate.
940
79dec6b7
JB		 9412019-07-01 Jan Beulich <jbeulich@suse.com>
942
943 * i386-opc.tbl (C): New.
944 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
945 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
946 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
947 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
948 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
949 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
950 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
951 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
952 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
953 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
954 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
955 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
956 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
957 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
958 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
959 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
960 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
961 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
962 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
963 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
964 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
965 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
966 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
967 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
968 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
969 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
970 flavors.
971 * i386-tbl.h: Re-generate.
972
a0a1771e
JB		 9732019-07-01 Jan Beulich <jbeulich@suse.com>
974
975 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
976 register operands.
977 * i386-tbl.h: Re-generate.
978
cd546e7b
JB		 9792019-07-01 Jan Beulich <jbeulich@suse.com>
980
981 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
982 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
983 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
984 * i386-tbl.h: Re-generate.
985
e3bba3fc
JB		 9862019-07-01 Jan Beulich <jbeulich@suse.com>
987
988 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
989 Disp8MemShift from register only templates.
990 * i386-tbl.h: Re-generate.
991
36cc073e
JB		 9922019-07-01 Jan Beulich <jbeulich@suse.com>
993
994 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
995 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
996 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
997 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
998 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
999 EVEX_W_0F11_P_3_M_1): Delete.
1000 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1001 EVEX_W_0F11_P_3): New.
1002 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1003 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1004 MOD_EVEX_0F11_PREFIX_3 table entries.
1005 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1006 PREFIX_EVEX_0F11 table entries.
1007 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1008 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1009 EVEX_W_0F11_P_3_M_{0,1} table entries.
1010
219920a7
JB		 10112019-07-01 Jan Beulich <jbeulich@suse.com>
1012
1013 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1014 Delete.
1015
e395f487
L		 10162019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1017
1018 PR binutils/24719
1019 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1020 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1021 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1022 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1023 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1024 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1025 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1026 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1027 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1028 PREFIX_EVEX_0F38C6_REG_6 entries.
1029 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1030 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1031 EVEX_W_0F38C7_R_6_P_2 entries.
1032 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1033 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1034 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1035 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1036 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1037 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1038 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1039
2b7bcc87
JB		 10402019-06-27 Jan Beulich <jbeulich@suse.com>
1041
1042 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1043 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1044 VEX_LEN_0F2D_P_3): Delete.
1045 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1046 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1047 (prefix_table): ... here.
1048
c1dc7af5
JB		 10492019-06-27 Jan Beulich <jbeulich@suse.com>
1050
1051 * i386-dis.c (Iq): Delete.
1052 (Id): New.
1053 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1054 TBM insns.
1055 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1056 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1057 (OP_E_memory): Also honor needindex when deciding whether an
1058 address size prefix needs printing.
1059 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1060
d7560e2d
JW		 10612019-06-26 Jim Wilson <jimw@sifive.com>
1062
1063 PR binutils/24739
1064 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1065 Set info->display_endian to info->endian_code.
1066
2c703856
JB		 10672019-06-25 Jan Beulich <jbeulich@suse.com>
1068
1069 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1070 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1071 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1072 OPERAND_TYPE_ACC64 entries.
1073 * i386-init.h: Re-generate.
1074
54fbadc0
JB		 10752019-06-25 Jan Beulich <jbeulich@suse.com>
1076
1077 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1078 Delete.
1079 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1080 of dqa_mode.
1081 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1082 entries here.
1083 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1084 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1085
a280ab8e
JB		 10862019-06-25 Jan Beulich <jbeulich@suse.com>
1087
1088 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1089 variables.
1090
e1a1babd
JB		 10912019-06-25 Jan Beulich <jbeulich@suse.com>
1092
1093 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1094 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1095 movnti.
d7560e2d 1096 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1097 * i386-tbl.h: Re-generate.
1098
b8364fa7
JB		 10992019-06-25 Jan Beulich <jbeulich@suse.com>
1100
1101 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1102 * i386-tbl.h: Re-generate.
1103
ad692897
L		 11042019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1105
1106 * i386-dis-evex.h: Break into ...
1107 * i386-dis-evex-len.h: New file.
1108 * i386-dis-evex-mod.h: Likewise.
1109 * i386-dis-evex-prefix.h: Likewise.
1110 * i386-dis-evex-reg.h: Likewise.
1111 * i386-dis-evex-w.h: Likewise.
1112 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1113 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1114 i386-dis-evex-mod.h.
1115
f0a6222e
L		 11162019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1117
1118 PR binutils/24700
1119 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1120 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1121 EVEX_W_0F385B_P_2.
1122 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1123 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1124 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1125 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1126 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1127 EVEX_LEN_0F385B_P_2_W_1.
1128 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1129 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1130 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1131 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1132 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1133 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1134 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1135 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1136 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1137 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1138
6e1c90b7
L		 11392019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1140
1141 PR binutils/24691
1142 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1143 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1144 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1145 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1146 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1147 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1148 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1149 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1150 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1151 EVEX_LEN_0F3A43_P_2_W_1.
1152 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1153 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1154 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1155 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1156 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1157 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1158 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1159 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1160 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1161 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1162 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1163 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1164
bcc5a6eb
NC		 11652019-06-14 Nick Clifton <nickc@redhat.com>
1166
1167 * po/fr.po; Updated French translation.
1168
e4c4ac46
SH		 11692019-06-13 Stafford Horne <shorne@gmail.com>
1170
1171 * or1k-asm.c: Regenerated.
1172 * or1k-desc.c: Regenerated.
1173 * or1k-desc.h: Regenerated.
1174 * or1k-dis.c: Regenerated.
1175 * or1k-ibld.c: Regenerated.
1176 * or1k-opc.c: Regenerated.
1177 * or1k-opc.h: Regenerated.
1178 * or1k-opinst.c: Regenerated.
1179
a0e44ef5
PB		 11802019-06-12 Peter Bergner <bergner@linux.ibm.com>
1181
1182 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1183
12efd68d
L		 11842019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1185
1186 PR binutils/24633
1187 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1188 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1189 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1190 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1191 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1192 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1193 EVEX_LEN_0F3A1B_P_2_W_1.
1194 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1195 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1196 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1197 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1198 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1199 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1200 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1201 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1202
63c6fc6c
L		 12032019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1204
1205 PR binutils/24626
1206 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1207 EVEX.vvvv when disassembling VEX and EVEX instructions.
1208 (OP_VEX): Set vex.register_specifier to 0 after readding
1209 vex.register_specifier.
1210 (OP_Vex_2src_1): Likewise.
1211 (OP_Vex_2src_2): Likewise.
1212 (OP_LWP_E): Likewise.
1213 (OP_EX_Vex): Don't check vex.register_specifier.
1214 (OP_XMM_Vex): Likewise.
1215
9186c494
L		 12162019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1217 Lili Cui <lili.cui@intel.com>
1218
1219 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1220 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1221 instructions.
1222 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1223 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1224 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1225 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1226 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1227 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1228 * i386-init.h: Regenerated.
1229 * i386-tbl.h: Likewise.
1230
5d79adc4
L		 12312019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1232 Lili Cui <lili.cui@intel.com>
1233
1234 * doc/c-i386.texi: Document enqcmd.
1235 * testsuite/gas/i386/enqcmd-intel.d: New file.
1236 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1237 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1238 * testsuite/gas/i386/enqcmd.d: Likewise.
1239 * testsuite/gas/i386/enqcmd.s: Likewise.
1240 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1241 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1242 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1243 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1244 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1245 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1246 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1247 and x86-64-enqcmd.
1248
a9d96ab9
AH		 12492019-06-04 Alan Hayward <alan.hayward@arm.com>
1250
1251 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1252
4f6d070a
AM		 12532019-06-03 Alan Modra <amodra@gmail.com>
1254
1255 * ppc-dis.c (prefix_opcd_indices): Correct size.
1256
a2f4b66c
L		 12572019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1258
1259 PR gas/24625
1260 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1261 Disp8ShiftVL.
1262 * i386-tbl.h: Regenerated.
1263
405b5bd8
AM		 12642019-05-24 Alan Modra <amodra@gmail.com>
1265
1266 * po/POTFILES.in: Regenerate.
1267
8acf1435
PB		 12682019-05-24 Peter Bergner <bergner@linux.ibm.com>
1269 Alan Modra <amodra@gmail.com>
1270
1271 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1272 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1273 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1274 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1275 XTOP>): Define and add entries.
1276 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1277 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1278 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1279 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1280
dd7efa79
PB		 12812019-05-24 Peter Bergner <bergner@linux.ibm.com>
1282 Alan Modra <amodra@gmail.com>
1283
1284 * ppc-dis.c (ppc_opts): Add "future" entry.
1285 (PREFIX_OPCD_SEGS): Define.
1286 (prefix_opcd_indices): New array.
1287 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1288 (lookup_prefix): New function.
1289 (print_insn_powerpc): Handle 64-bit prefix instructions.
1290 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1291 (PMRR, POWERXX): Define.
1292 (prefix_opcodes): New instruction table.
1293 (prefix_num_opcodes): New constant.
1294
79472b45
JM		 12952019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1296
1297 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1298 * configure: Regenerated.
1299 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1300 and cpu/bpf.opc.
1301 (HFILES): Add bpf-desc.h and bpf-opc.h.
1302 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1303 bpf-ibld.c and bpf-opc.c.
1304 (BPF_DEPS): Define.
1305 * Makefile.in: Regenerated.
1306 * disassemble.c (ARCH_bpf): Define.
1307 (disassembler): Add case for bfd_arch_bpf.
1308 (disassemble_init_for_target): Likewise.
1309 (enum epbf_isa_attr): Define.
1310 * disassemble.h: extern print_insn_bpf.
1311 * bpf-asm.c: Generated.
1312 * bpf-opc.h: Likewise.
1313 * bpf-opc.c: Likewise.
1314 * bpf-ibld.c: Likewise.
1315 * bpf-dis.c: Likewise.
1316 * bpf-desc.h: Likewise.
1317 * bpf-desc.c: Likewise.
1318
ba6cd17f
SD		 13192019-05-21 Sudakshina Das <sudi.das@arm.com>
1320
1321 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1322 and VMSR with the new operands.
1323
e39c1607
SD		 13242019-05-21 Sudakshina Das <sudi.das@arm.com>
1325
1326 * arm-dis.c (enum mve_instructions): New enum
1327 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1328 and cneg.
1329 (mve_opcodes): New instructions as above.
1330 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1331 csneg and csel.
1332 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1333
23d00a41
SD		 13342019-05-21 Sudakshina Das <sudi.das@arm.com>
1335
1336 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1337 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1338 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1339 uqshl, urshrl and urshr.
1340 (is_mve_okay_in_it): Add new instructions to TRUE list.
1341 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1342 (print_insn_mve): Updated to accept new %j,
1343 %<bitfield>m and %<bitfield>n patterns.
1344
cd4797ee
FS		 13452019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1346
1347 * mips-opc.c (mips_builtin_opcodes): Change source register
1348 constraint for DAUI.
1349
999b073b
NC		 13502019-05-20 Nick Clifton <nickc@redhat.com>
1351
1352 * po/fr.po: Updated French translation.
1353
14b456f2
AV		 13542019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1355 Michael Collison <michael.collison@arm.com>
1356
1357 * arm-dis.c (thumb32_opcodes): Add new instructions.
1358 (enum mve_instructions): Likewise.
1359 (enum mve_undefined): Add new reasons.
1360 (is_mve_encoding_conflict): Handle new instructions.
1361 (is_mve_undefined): Likewise.
1362 (is_mve_unpredictable): Likewise.
1363 (print_mve_undefined): Likewise.
1364 (print_mve_size): Likewise.
1365
f49bb598
AV		 13662019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1367 Michael Collison <michael.collison@arm.com>
1368
1369 * arm-dis.c (thumb32_opcodes): Add new instructions.
1370 (enum mve_instructions): Likewise.
1371 (is_mve_encoding_conflict): Handle new instructions.
1372 (is_mve_undefined): Likewise.
1373 (is_mve_unpredictable): Likewise.
1374 (print_mve_size): Likewise.
1375
56858bea
AV		 13762019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1377 Michael Collison <michael.collison@arm.com>
1378
1379 * arm-dis.c (thumb32_opcodes): Add new instructions.
1380 (enum mve_instructions): Likewise.
1381 (is_mve_encoding_conflict): Likewise.
1382 (is_mve_unpredictable): Likewise.
1383 (print_mve_size): Likewise.
1384
e523f101
AV		 13852019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1386 Michael Collison <michael.collison@arm.com>
1387
1388 * arm-dis.c (thumb32_opcodes): Add new instructions.
1389 (enum mve_instructions): Likewise.
1390 (is_mve_encoding_conflict): Handle new instructions.
1391 (is_mve_undefined): Likewise.
1392 (is_mve_unpredictable): Likewise.
1393 (print_mve_size): Likewise.
1394
66dcaa5d
AV		 13952019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1396 Michael Collison <michael.collison@arm.com>
1397
1398 * arm-dis.c (thumb32_opcodes): Add new instructions.
1399 (enum mve_instructions): Likewise.
1400 (is_mve_encoding_conflict): Handle new instructions.
1401 (is_mve_undefined): Likewise.
1402 (is_mve_unpredictable): Likewise.
1403 (print_mve_size): Likewise.
1404 (print_insn_mve): Likewise.
1405
d052b9b7
AV		 14062019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1407 Michael Collison <michael.collison@arm.com>
1408
1409 * arm-dis.c (thumb32_opcodes): Add new instructions.
1410 (print_insn_thumb32): Handle new instructions.
1411
ed63aa17
AV		 14122019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1413 Michael Collison <michael.collison@arm.com>
1414
1415 * arm-dis.c (enum mve_instructions): Add new instructions.
1416 (enum mve_undefined): Add new reasons.
1417 (is_mve_encoding_conflict): Handle new instructions.
1418 (is_mve_undefined): Likewise.
1419 (is_mve_unpredictable): Likewise.
1420 (print_mve_undefined): Likewise.
1421 (print_mve_size): Likewise.
1422 (print_mve_shift_n): Likewise.
1423 (print_insn_mve): Likewise.
1424
897b9bbc
AV		 14252019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1426 Michael Collison <michael.collison@arm.com>
1427
1428 * arm-dis.c (enum mve_instructions): Add new instructions.
1429 (is_mve_encoding_conflict): Handle new instructions.
1430 (is_mve_unpredictable): Likewise.
1431 (print_mve_rotate): Likewise.
1432 (print_mve_size): Likewise.
1433 (print_insn_mve): Likewise.
1434
1c8f2df8
AV		 14352019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1436 Michael Collison <michael.collison@arm.com>
1437
1438 * arm-dis.c (enum mve_instructions): Add new instructions.
1439 (is_mve_encoding_conflict): Handle new instructions.
1440 (is_mve_unpredictable): Likewise.
1441 (print_mve_size): Likewise.
1442 (print_insn_mve): Likewise.
1443
d3b63143
AV		 14442019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1445 Michael Collison <michael.collison@arm.com>
1446
1447 * arm-dis.c (enum mve_instructions): Add new instructions.
1448 (enum mve_undefined): Add new reasons.
1449 (is_mve_encoding_conflict): Handle new instructions.
1450 (is_mve_undefined): Likewise.
1451 (is_mve_unpredictable): Likewise.
1452 (print_mve_undefined): Likewise.
1453 (print_mve_size): Likewise.
1454 (print_insn_mve): Likewise.
1455
14925797
AV		 14562019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1457 Michael Collison <michael.collison@arm.com>
1458
1459 * arm-dis.c (enum mve_instructions): Add new instructions.
1460 (is_mve_encoding_conflict): Handle new instructions.
1461 (is_mve_undefined): Likewise.
1462 (is_mve_unpredictable): Likewise.
1463 (print_mve_size): Likewise.
1464 (print_insn_mve): Likewise.
1465
c507f10b
AV		 14662019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1467 Michael Collison <michael.collison@arm.com>
1468
1469 * arm-dis.c (enum mve_instructions): Add new instructions.
1470 (enum mve_unpredictable): Add new reasons.
1471 (enum mve_undefined): Likewise.
1472 (is_mve_okay_in_it): Handle new isntructions.
1473 (is_mve_encoding_conflict): Likewise.
1474 (is_mve_undefined): Likewise.
1475 (is_mve_unpredictable): Likewise.
1476 (print_mve_vmov_index): Likewise.
1477 (print_simd_imm8): Likewise.
1478 (print_mve_undefined): Likewise.
1479 (print_mve_unpredictable): Likewise.
1480 (print_mve_size): Likewise.
1481 (print_insn_mve): Likewise.
1482
bf0b396d
AV		 14832019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1484 Michael Collison <michael.collison@arm.com>
1485
1486 * arm-dis.c (enum mve_instructions): Add new instructions.
1487 (enum mve_unpredictable): Add new reasons.
1488 (enum mve_undefined): Likewise.
1489 (is_mve_encoding_conflict): Handle new instructions.
1490 (is_mve_undefined): Likewise.
1491 (is_mve_unpredictable): Likewise.
1492 (print_mve_undefined): Likewise.
1493 (print_mve_unpredictable): Likewise.
1494 (print_mve_rounding_mode): Likewise.
1495 (print_mve_vcvt_size): Likewise.
1496 (print_mve_size): Likewise.
1497 (print_insn_mve): Likewise.
1498
ef1576a1
AV		 14992019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1500 Michael Collison <michael.collison@arm.com>
1501
1502 * arm-dis.c (enum mve_instructions): Add new instructions.
1503 (enum mve_unpredictable): Add new reasons.
1504 (enum mve_undefined): Likewise.
1505 (is_mve_undefined): Handle new instructions.
1506 (is_mve_unpredictable): Likewise.
1507 (print_mve_undefined): Likewise.
1508 (print_mve_unpredictable): Likewise.
1509 (print_mve_size): Likewise.
1510 (print_insn_mve): Likewise.
1511
aef6d006
AV		 15122019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1513 Michael Collison <michael.collison@arm.com>
1514
1515 * arm-dis.c (enum mve_instructions): Add new instructions.
1516 (enum mve_undefined): Add new reasons.
1517 (insns): Add new instructions.
1518 (is_mve_encoding_conflict):
1519 (print_mve_vld_str_addr): New print function.
1520 (is_mve_undefined): Handle new instructions.
1521 (is_mve_unpredictable): Likewise.
1522 (print_mve_undefined): Likewise.
1523 (print_mve_size): Likewise.
1524 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1525 (print_insn_mve): Handle new operands.
1526
04d54ace
AV		 15272019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1528 Michael Collison <michael.collison@arm.com>
1529
1530 * arm-dis.c (enum mve_instructions): Add new instructions.
1531 (enum mve_unpredictable): Add new reasons.
1532 (is_mve_encoding_conflict): Handle new instructions.
1533 (is_mve_unpredictable): Likewise.
1534 (mve_opcodes): Add new instructions.
1535 (print_mve_unpredictable): Handle new reasons.
1536 (print_mve_register_blocks): New print function.
1537 (print_mve_size): Handle new instructions.
1538 (print_insn_mve): Likewise.
1539
9743db03
AV		 15402019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1541 Michael Collison <michael.collison@arm.com>
1542
1543 * arm-dis.c (enum mve_instructions): Add new instructions.
1544 (enum mve_unpredictable): Add new reasons.
1545 (enum mve_undefined): Likewise.
1546 (is_mve_encoding_conflict): Handle new instructions.
1547 (is_mve_undefined): Likewise.
1548 (is_mve_unpredictable): Likewise.
1549 (coprocessor_opcodes): Move NEON VDUP from here...
1550 (neon_opcodes): ... to here.
1551 (mve_opcodes): Add new instructions.
1552 (print_mve_undefined): Handle new reasons.
1553 (print_mve_unpredictable): Likewise.
1554 (print_mve_size): Handle new instructions.
1555 (print_insn_neon): Handle vdup.
1556 (print_insn_mve): Handle new operands.
1557
143275ea
AV		 15582019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1559 Michael Collison <michael.collison@arm.com>
1560
1561 * arm-dis.c (enum mve_instructions): Add new instructions.
1562 (enum mve_unpredictable): Add new values.
1563 (mve_opcodes): Add new instructions.
1564 (vec_condnames): New array with vector conditions.
1565 (mve_predicatenames): New array with predicate suffixes.
1566 (mve_vec_sizename): New array with vector sizes.
1567 (enum vpt_pred_state): New enum with vector predication states.
1568 (struct vpt_block): New struct type for vpt blocks.
1569 (vpt_block_state): Global struct to keep track of state.
1570 (mve_extract_pred_mask): New helper function.
1571 (num_instructions_vpt_block): Likewise.
1572 (mark_outside_vpt_block): Likewise.
1573 (mark_inside_vpt_block): Likewise.
1574 (invert_next_predicate_state): Likewise.
1575 (update_next_predicate_state): Likewise.
1576 (update_vpt_block_state): Likewise.
1577 (is_vpt_instruction): Likewise.
1578 (is_mve_encoding_conflict): Add entries for new instructions.
1579 (is_mve_unpredictable): Likewise.
1580 (print_mve_unpredictable): Handle new cases.
1581 (print_instruction_predicate): Likewise.
1582 (print_mve_size): New function.
1583 (print_vec_condition): New function.
1584 (print_insn_mve): Handle vpt blocks and new print operands.
1585
f08d8ce3
AV		 15862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1587
1588 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1589 8, 14 and 15 for Armv8.1-M Mainline.
1590
73cd51e5
AV		 15912019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1592 Michael Collison <michael.collison@arm.com>
1593
1594 * arm-dis.c (enum mve_instructions): New enum.
1595 (enum mve_unpredictable): Likewise.
1596 (enum mve_undefined): Likewise.
1597 (struct mopcode32): New struct.
1598 (is_mve_okay_in_it): New function.
1599 (is_mve_architecture): Likewise.
1600 (arm_decode_field): Likewise.
1601 (arm_decode_field_multiple): Likewise.
1602 (is_mve_encoding_conflict): Likewise.
1603 (is_mve_undefined): Likewise.
1604 (is_mve_unpredictable): Likewise.
1605 (print_mve_undefined): Likewise.
1606 (print_mve_unpredictable): Likewise.
1607 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1608 (print_insn_mve): New function.
1609 (print_insn_thumb32): Handle MVE architecture.
1610 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1611
3076e594
NC		 16122019-05-10 Nick Clifton <nickc@redhat.com>
1613
1614 PR 24538
1615 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1616 end of the table prematurely.
1617
387e7624
FS		 16182019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1619
1620 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1621 macros for R6.
1622
0067be51
AM		 16232019-05-11 Alan Modra <amodra@gmail.com>
1624
1625 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1626 when -Mraw is in effect.
1627
42e6288f
MM		 16282019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1629
1630 * aarch64-dis-2.c: Regenerate.
1631 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1632 (OP_SVE_BBB): New variant set.
1633 (OP_SVE_DDDD): New variant set.
1634 (OP_SVE_HHH): New variant set.
1635 (OP_SVE_HHHU): New variant set.
1636 (OP_SVE_SSS): New variant set.
1637 (OP_SVE_SSSU): New variant set.
1638 (OP_SVE_SHH): New variant set.
1639 (OP_SVE_SBBU): New variant set.
1640 (OP_SVE_DSS): New variant set.
1641 (OP_SVE_DHHU): New variant set.
1642 (OP_SVE_VMV_HSD_BHS): New variant set.
1643 (OP_SVE_VVU_HSD_BHS): New variant set.
1644 (OP_SVE_VVVU_SD_BH): New variant set.
1645 (OP_SVE_VVVU_BHSD): New variant set.
1646 (OP_SVE_VVV_QHD_DBS): New variant set.
1647 (OP_SVE_VVV_HSD_BHS): New variant set.
1648 (OP_SVE_VVV_HSD_BHS2): New variant set.
1649 (OP_SVE_VVV_BHS_HSD): New variant set.
1650 (OP_SVE_VV_BHS_HSD): New variant set.
1651 (OP_SVE_VVV_SD): New variant set.
1652 (OP_SVE_VVU_BHS_HSD): New variant set.
1653 (OP_SVE_VZVV_SD): New variant set.
1654 (OP_SVE_VZVV_BH): New variant set.
1655 (OP_SVE_VZV_SD): New variant set.
1656 (aarch64_opcode_table): Add sve2 instructions.
1657
28ed815a
MM		 16582019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1659
1660 * aarch64-asm-2.c: Regenerated.
1661 * aarch64-dis-2.c: Regenerated.
1662 * aarch64-opc-2.c: Regenerated.
1663 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1664 for SVE_SHLIMM_UNPRED_22.
1665 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1666 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1667 operand.
1668
fd1dc4a0
MM		 16692019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1670
1671 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1672 sve_size_tsz_bhs iclass encode.
1673 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1674 sve_size_tsz_bhs iclass decode.
1675
31e36ab3
MM		 16762019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1677
1678 * aarch64-asm-2.c: Regenerated.
1679 * aarch64-dis-2.c: Regenerated.
1680 * aarch64-opc-2.c: Regenerated.
1681 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1682 for SVE_Zm4_11_INDEX.
1683 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1684 (fields): Handle SVE_i2h field.
1685 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1686 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1687
1be5f94f
MM		 16882019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1689
1690 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1691 sve_shift_tsz_bhsd iclass encode.
1692 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1693 sve_shift_tsz_bhsd iclass decode.
1694
3c17238b
MM		 16952019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1696
1697 * aarch64-asm-2.c: Regenerated.
1698 * aarch64-dis-2.c: Regenerated.
1699 * aarch64-opc-2.c: Regenerated.
1700 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1701 (aarch64_encode_variant_using_iclass): Handle
1702 sve_shift_tsz_hsd iclass encode.
1703 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1704 sve_shift_tsz_hsd iclass decode.
1705 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1706 for SVE_SHRIMM_UNPRED_22.
1707 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1708 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1709 operand.
1710
cd50a87a
MM		 17112019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1712
1713 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1714 sve_size_013 iclass encode.
1715 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1716 sve_size_013 iclass decode.
1717
3c705960
MM		 17182019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1719
1720 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1721 sve_size_bh iclass encode.
1722 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1723 sve_size_bh iclass decode.
1724
0a57e14f
MM		 17252019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1726
1727 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1728 sve_size_sd2 iclass encode.
1729 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1730 sve_size_sd2 iclass decode.
1731 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1732 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1733
c469c864
MM		 17342019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1735
1736 * aarch64-asm-2.c: Regenerated.
1737 * aarch64-dis-2.c: Regenerated.
1738 * aarch64-opc-2.c: Regenerated.
1739 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1740 for SVE_ADDR_ZX.
1741 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1742 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1743
116adc27
MM		 17442019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1745
1746 * aarch64-asm-2.c: Regenerated.
1747 * aarch64-dis-2.c: Regenerated.
1748 * aarch64-opc-2.c: Regenerated.
1749 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1750 for SVE_Zm3_11_INDEX.
1751 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1752 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1753 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1754 fields.
1755 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1756
3bd82c86
MM		 17572019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1758
1759 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1760 sve_size_hsd2 iclass encode.
1761 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1762 sve_size_hsd2 iclass decode.
1763 * aarch64-opc.c (fields): Handle SVE_size field.
1764 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1765
adccc507
MM		 17662019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1767
1768 * aarch64-asm-2.c: Regenerated.
1769 * aarch64-dis-2.c: Regenerated.
1770 * aarch64-opc-2.c: Regenerated.
1771 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1772 for SVE_IMM_ROT3.
1773 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1774 (fields): Handle SVE_rot3 field.
1775 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1776 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1777
5cd99750
MM		 17782019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1779
1780 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1781 instructions.
1782
7ce2460a
MM		 17832019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1784
1785 * aarch64-tbl.h
1786 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1787 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1788 aarch64_feature_sve2bitperm): New feature sets.
1789 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1790 for feature set addresses.
1791 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1792 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1793
41cee089
FS		 17942019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1795 Faraz Shahbazker <fshahbazker@wavecomp.com>
1796
1797 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1798 argument and set ASE_EVA_R6 appropriately.
1799 (set_default_mips_dis_options): Pass ISA to above.
1800 (parse_mips_dis_option): Likewise.
1801 * mips-opc.c (EVAR6): New macro.
1802 (mips_builtin_opcodes): Add llwpe, scwpe.
1803
b83b4b13
SD		 18042019-05-01 Sudakshina Das <sudi.das@arm.com>
1805
1806 * aarch64-asm-2.c: Regenerated.
1807 * aarch64-dis-2.c: Regenerated.
1808 * aarch64-opc-2.c: Regenerated.
1809 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1810 AARCH64_OPND_TME_UIMM16.
1811 (aarch64_print_operand): Likewise.
1812 * aarch64-tbl.h (QL_IMM_NIL): New.
1813 (TME): New.
1814 (_TME_INSN): New.
1815 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1816
4a90ce95
JD		 18172019-04-29 John Darrington <john@darrington.wattle.id.au>
1818
1819 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1820
a45328b9
AB		 18212019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1822 Faraz Shahbazker <fshahbazker@wavecomp.com>
1823
1824 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1825
d10be0cb
JD		 18262019-04-24 John Darrington <john@darrington.wattle.id.au>
1827
1828 * s12z-opc.h: Add extern "C" bracketing to help
1829 users who wish to use this interface in c++ code.
1830
a679f24e
JD		 18312019-04-24 John Darrington <john@darrington.wattle.id.au>
1832
1833 * s12z-opc.c (bm_decode): Handle bit map operations with the
1834 "reserved0" mode.
1835
32c36c3c
AV		 18362019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1837
1838 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1839 specifier. Add entries for VLDR and VSTR of system registers.
1840 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1841 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1842 of %J and %K format specifier.
1843
efd6b359
AV		 18442019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1845
1846 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1847 Add new entries for VSCCLRM instruction.
1848 (print_insn_coprocessor): Handle new %C format control code.
1849
6b0dd094
AV		 18502019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1851
1852 * arm-dis.c (enum isa): New enum.
1853 (struct sopcode32): New structure.
1854 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1855 set isa field of all current entries to ANY.
1856 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1857 Only match an entry if its isa field allows the current mode.
1858
4b5a202f
AV		 18592019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1860
1861 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1862 CLRM.
1863 (print_insn_thumb32): Add logic to print %n CLRM register list.
1864
60f993ce
AV		 18652019-04-15 Sudakshina Das <sudi.das@arm.com>
1866
1867 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1868 and %Q patterns.
1869
f6b2b12d
AV		 18702019-04-15 Sudakshina Das <sudi.das@arm.com>
1871
1872 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1873 (print_insn_thumb32): Edit the switch case for %Z.
1874
1889da70
AV		 18752019-04-15 Sudakshina Das <sudi.das@arm.com>
1876
1877 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1878
65d1bc05
AV		 18792019-04-15 Sudakshina Das <sudi.das@arm.com>
1880
1881 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1882
1caf72a5
AV		 18832019-04-15 Sudakshina Das <sudi.das@arm.com>
1884
1885 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1886
f1c7f421
AV		 18872019-04-15 Sudakshina Das <sudi.das@arm.com>
1888
1889 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1890 Arm register with r13 and r15 unpredictable.
1891 (thumb32_opcodes): New instructions for bfx and bflx.
1892
4389b29a
AV		 18932019-04-15 Sudakshina Das <sudi.das@arm.com>
1894
1895 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1896
e5d6e09e
AV		 18972019-04-15 Sudakshina Das <sudi.das@arm.com>
1898
1899 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1900
e12437dc
AV		 19012019-04-15 Sudakshina Das <sudi.das@arm.com>
1902
1903 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1904
031254f2
AV		 19052019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1906
1907 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1908
e5a557ac
JD		 19092019-04-12 John Darrington <john@darrington.wattle.id.au>
1910
1911 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1912 "optr". ("operator" is a reserved word in c++).
1913
bd7ceb8d
SD		 19142019-04-11 Sudakshina Das <sudi.das@arm.com>
1915
1916 * aarch64-opc.c (aarch64_print_operand): Add case for
1917 AARCH64_OPND_Rt_SP.
1918 (verify_constraints): Likewise.
1919 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1920 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1921 to accept Rt|SP as first operand.
1922 (AARCH64_OPERANDS): Add new Rt_SP.
1923 * aarch64-asm-2.c: Regenerated.
1924 * aarch64-dis-2.c: Regenerated.
1925 * aarch64-opc-2.c: Regenerated.
1926
e54010f1
SD		 19272019-04-11 Sudakshina Das <sudi.das@arm.com>
1928
1929 * aarch64-asm-2.c: Regenerated.
1930 * aarch64-dis-2.c: Likewise.
1931 * aarch64-opc-2.c: Likewise.
1932 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1933
7e96e219
RS		 19342019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1935
1936 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1937
6f2791d5
L		 19382019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1939
1940 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1941 * i386-init.h: Regenerated.
1942
e392bad3
AM		 19432019-04-07 Alan Modra <amodra@gmail.com>
1944
1945 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1946 op_separator to control printing of spaces, comma and parens
1947 rather than need_comma, need_paren and spaces vars.
1948
dffaa15c
AM		 19492019-04-07 Alan Modra <amodra@gmail.com>
1950
1951 PR 24421
1952 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1953 (print_insn_neon, print_insn_arm): Likewise.
1954
d6aab7a1
XG		 19552019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1956
1957 * i386-dis-evex.h (evex_table): Updated to support BF16
1958 instructions.
1959 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1960 and EVEX_W_0F3872_P_3.
1961 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1962 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1963 * i386-opc.h (enum): Add CpuAVX512_BF16.
1964 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1965 * i386-opc.tbl: Add AVX512 BF16 instructions.
1966 * i386-init.h: Regenerated.
1967 * i386-tbl.h: Likewise.
1968
66e85460
AM		 19692019-04-05 Alan Modra <amodra@gmail.com>
1970
1971 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1972 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1973 to favour printing of "-" branch hint when using the "y" bit.
1974 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1975
c2b1c275
AM		 19762019-04-05 Alan Modra <amodra@gmail.com>
1977
1978 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1979 opcode until first operand is output.
1980
aae9718e
PB		 19812019-04-04 Peter Bergner <bergner@linux.ibm.com>
1982
1983 PR gas/24349
1984 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1985 (valid_bo_post_v2): Add support for 'at' branch hints.
1986 (insert_bo): Only error on branch on ctr.
1987 (get_bo_hint_mask): New function.
1988 (insert_boe): Add new 'branch_taken' formal argument. Add support
1989 for inserting 'at' branch hints.
1990 (extract_boe): Add new 'branch_taken' formal argument. Add support
1991 for extracting 'at' branch hints.
1992 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1993 (BOE): Delete operand.
1994 (BOM, BOP): New operands.
1995 (RM): Update value.
1996 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1997 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1998 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1999 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2000 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2001 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2002 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2003 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2004 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2005 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2006 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2007 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2008 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2009 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2010 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2011 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2012 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2013 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2014 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2015 bttarl+>: New extended mnemonics.
2016
96a86c01
AM		 20172019-03-28 Alan Modra <amodra@gmail.com>
2018
2019 PR 24390
2020 * ppc-opc.c (BTF): Define.
2021 (powerpc_opcodes): Use for mtfsb*.
2022 * ppc-dis.c (print_insn_powerpc): Print fields with both
2023 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2024
796d6298
TC		 20252019-03-25 Tamar Christina <tamar.christina@arm.com>
2026
2027 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2028 (mapping_symbol_for_insn): Implement new algorithm.
2029 (print_insn): Remove duplicate code.
2030
60df3720
TC		 20312019-03-25 Tamar Christina <tamar.christina@arm.com>
2032
2033 * aarch64-dis.c (print_insn_aarch64):
2034 Implement override.
2035
51457761
TC		 20362019-03-25 Tamar Christina <tamar.christina@arm.com>
2037
2038 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2039 order.
2040
53b2f36b
TC		 20412019-03-25 Tamar Christina <tamar.christina@arm.com>
2042
2043 * aarch64-dis.c (last_stop_offset): New.
2044 (print_insn_aarch64): Use stop_offset.
2045
89199bb5
L		 20462019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2047
2048 PR gas/24359
2049 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2050 CPU_ANY_AVX2_FLAGS.
2051 * i386-init.h: Regenerated.
2052
97ed31ae
L		 20532019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2054
2055 PR gas/24348
2056 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2057 vmovdqu16, vmovdqu32 and vmovdqu64.
2058 * i386-tbl.h: Regenerated.
2059
0919bfe9
AK		 20602019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2061
2062 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2063 from vstrszb, vstrszh, and vstrszf.
2064
20652019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2066
2067 * s390-opc.txt: Add instruction descriptions.
2068
21820ebe
JW		 20692019-02-08 Jim Wilson <jimw@sifive.com>
2070
2071 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2072 <bne>: Likewise.
2073
f7dd2fb2
TC		 20742019-02-07 Tamar Christina <tamar.christina@arm.com>
2075
2076 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2077
6456d318
TC		 20782019-02-07 Tamar Christina <tamar.christina@arm.com>
2079
2080 PR binutils/23212
2081 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2082 * aarch64-opc.c (verify_elem_sd): New.
2083 (fields): Add FLD_sz entr.
2084 * aarch64-tbl.h (_SIMD_INSN): New.
2085 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2086 fmulx scalar and vector by element isns.
2087
4a83b610
NC		 20882019-02-07 Nick Clifton <nickc@redhat.com>
2089
2090 * po/sv.po: Updated Swedish translation.
2091
fc60b8c8
AK		 20922019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2093
2094 * s390-mkopc.c (main): Accept arch13 as cpu string.
2095 * s390-opc.c: Add new instruction formats and instruction opcode
2096 masks.
2097 * s390-opc.txt: Add new arch13 instructions.
2098
e10620d3
TC		 20992019-01-25 Sudakshina Das <sudi.das@arm.com>
2100
2101 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2102 (aarch64_opcode): Change encoding for stg, stzg
2103 st2g and st2zg.
2104 * aarch64-asm-2.c: Regenerated.
2105 * aarch64-dis-2.c: Regenerated.
2106 * aarch64-opc-2.c: Regenerated.
2107
20a4ca55
SD		 21082019-01-25 Sudakshina Das <sudi.das@arm.com>
2109
2110 * aarch64-asm-2.c: Regenerated.
2111 * aarch64-dis-2.c: Likewise.
2112 * aarch64-opc-2.c: Likewise.
2113 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2114
550fd7bf
SD		 21152019-01-25 Sudakshina Das <sudi.das@arm.com>
2116 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2117
2118 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2119 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2120 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2121 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2122 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2123 case for ldstgv_indexed.
2124 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2125 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2126 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2127 * aarch64-asm-2.c: Regenerated.
2128 * aarch64-dis-2.c: Regenerated.
2129 * aarch64-opc-2.c: Regenerated.
2130
d9938630
NC		 21312019-01-23 Nick Clifton <nickc@redhat.com>
2132
2133 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2134
375cd423
NC		 21352019-01-21 Nick Clifton <nickc@redhat.com>
2136
2137 * po/de.po: Updated German translation.
2138 * po/uk.po: Updated Ukranian translation.
2139
57299f48
CX		 21402019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2141 * mips-dis.c (mips_arch_choices): Fix typo in
2142 gs464, gs464e and gs264e descriptors.
2143
f48dfe41
NC		 21442019-01-19 Nick Clifton <nickc@redhat.com>
2145
2146 * configure: Regenerate.
2147 * po/opcodes.pot: Regenerate.
2148
f974f26c
NC		 21492018-06-24 Nick Clifton <nickc@redhat.com>
2150
2151 2.32 branch created.
2152
39f286cd
JD		 21532019-01-09 John Darrington <john@darrington.wattle.id.au>
2154
448b8ca8
JD		 2155 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2156 if it is null.
2157 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2158 zero.
2159
3107326d
AP		 21602019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2161
2162 * configure: Regenerate.
2163
7e9ca91e
AM		 21642019-01-07 Alan Modra <amodra@gmail.com>
2165
2166 * configure: Regenerate.
2167 * po/POTFILES.in: Regenerate.
2168
ef1ad42b
JD		 21692019-01-03 John Darrington <john@darrington.wattle.id.au>
2170
2171 * s12z-opc.c: New file.
2172 * s12z-opc.h: New file.
2173 * s12z-dis.c: Removed all code not directly related to display
2174 of instructions. Used the interface provided by the new files
2175 instead.
2176 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2177 * Makefile.in: Regenerate.
ef1ad42b 2178 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2179 * configure: Regenerate.
ef1ad42b 2180
82704155
AM		 21812019-01-01 Alan Modra <amodra@gmail.com>
2182
2183 Update year range in copyright notice of all files.
2184
d5c04e1b 2185For older changes see ChangeLog-2018
3499769a 2186\f
d5c04e1b 2187Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2188
2189Copying and distribution of this file, with or without modification,
2190are permitted in any medium without royalty provided the copyright
2191notice and this notice are preserved.
2192
2193Local Variables:
2194mode: change-log
2195left-margin: 8
2196fill-column: 74
2197version-control: never
2198End:
GDB Binutils - Deliverables
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