projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
daily update
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
d6787ef9
EB		 12013-08-05 Eric Botcazou <ebotcazou@adacore.com>
2 Konrad Eisele <konrad@gaisler.com>
3
4 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
5 bfd_mach_sparc.
6 * sparc-opc.c (MASK_LEON): Define.
7 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
8 (letandleon): New macro.
9 (v9andleon): Likewise.
10 (sparc_opc): Add leon.
11 (umac): Enable for letandleon.
12 (smac): Likewise.
13 (casa): Enable for v9andleon.
14 (cas): Likewise.
15 (casl): Likewise.
16
14daeee3
RS		 172013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
18 Richard Sandiford <rdsandiford@googlemail.com>
19
20 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
21 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
22 (print_vu0_channel): New function.
23 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
24 (print_insn_args): Handle '#'.
25 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
26 * mips-opc.c (mips_vu0_channel_mask): New constant.
27 (decode_mips_operand): Handle new VU0 operand types.
28 (VU0, VU0CH): New macros.
29 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
30 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
31 Use "+6" rather than "G" for QMFC2 and QMTC2.
32
3ccad066
RS		 332013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
34
35 * mips-formats.h (PCREL): Reorder parameters and update the definition
36 to match new mips_pcrel_operand layout.
37 (JUMP, JALX, BRANCH): Update accordingly.
38 * mips16-opc.c (decode_mips16_operand): Likewise.
39
df34fbcc
RS		 402013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
41
42 * micromips-opc.c (WR_s): Delete.
43
fc76e730
RS		 442013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
45
46 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
47 New macros.
48 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
49 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
50 (mips_builtin_opcodes): Use the new position-based read-write flags
51 instead of field-based ones. Use UDI for "udi..." instructions.
52 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
53 New macros.
54 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
55 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
56 (WR_SP, RD_16): New macros.
57 (RD_SP): Redefine as an INSN2_* flag.
58 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
59 (mips16_opcodes): Use the new position-based read-write flags
60 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
61 pinfo2 field.
62 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
63 New macros.
64 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
65 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
66 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
67 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
68 (micromips_opcodes): Use the new position-based read-write flags
69 instead of field-based ones.
70 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
71 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
72 of field-based flags.
73
26545944
RS		 742013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
75
76 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
77 (WR_SP): Replace with...
78 (MOD_SP): ...this.
79 (mips16_opcodes): Update accordingly.
80 * mips-dis.c (print_insn_mips16): Likewise.
81
a8d92fc6
RS		 822013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
83
84 * mips16-opc.c (mips16_opcodes): Reformat.
85
6a819047
RS		 862013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
87
88 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
89 for operands that are hard-coded to $0.
90 * micromips-opc.c (micromips_opcodes): Likewise.
91
344c74a6
RS		 922013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
93
94 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
95 for the single-operand forms of JALR and JALR.HB.
96 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
97 and JALRS.HB.
98
41989114
RS		 992013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
100
101 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
102 instructions. Fix them to use WR_MACC instead of WR_CC and
103 add missing RD_MACCs.
104
6d075bce
RS		 1052013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
106
107 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
108
4f6ffcd3
PB		 1092013-07-29 Peter Bergner <bergner@vnet.ibm.com>
110
111 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
112
43234a1e
L		 1132013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
114 Alexander Ivchenko <alexander.ivchenko@intel.com>
115 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
116 Sergey Lega <sergey.s.lega@intel.com>
117 Anna Tikhonova <anna.tikhonova@intel.com>
118 Ilya Tocar <ilya.tocar@intel.com>
119 Andrey Turetskiy <andrey.turetskiy@intel.com>
120 Ilya Verbin <ilya.verbin@intel.com>
121 Kirill Yukhin <kirill.yukhin@intel.com>
122 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
123
124 * i386-dis-evex.h: New.
125 * i386-dis.c (OP_Rounding): New.
126 (VPCMP_Fixup): New.
127 (OP_Mask): New.
128 (Rdq): New.
129 (XMxmmq): New.
130 (EXdScalarS): New.
131 (EXymm): New.
132 (EXEvexHalfBcstXmmq): New.
133 (EXxmm_mdq): New.
134 (EXEvexXGscat): New.
135 (EXEvexXNoBcst): New.
136 (VPCMP): New.
137 (EXxEVexR): New.
138 (EXxEVexS): New.
139 (XMask): New.
140 (MaskG): New.
141 (MaskE): New.
142 (MaskR): New.
143 (MaskVex): New.
144 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
145 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
146 evex_rounding_mode, evex_sae_mode, mask_mode.
147 (USE_EVEX_TABLE): New.
148 (EVEX_TABLE): New.
149 (EVEX enum): New.
150 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
151 REG_EVEX_0F38C7.
152 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
153 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
154 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
155 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
156 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
157 MOD_EVEX_0F38C7_REG_6.
158 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
159 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
160 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
161 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
162 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
163 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
164 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
165 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
166 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
167 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
168 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
169 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
170 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
171 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
172 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
173 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
174 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
175 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
176 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
177 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
178 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
179 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
180 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
181 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
182 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
183 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
184 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
185 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
186 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
187 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
188 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
189 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
190 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
191 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
192 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
193 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
194 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
195 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
196 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
197 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
198 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
199 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
200 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
201 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
202 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
203 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
204 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
205 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
206 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
207 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
208 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
209 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
210 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
211 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
212 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
213 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
214 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
215 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
216 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
217 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
218 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
219 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
220 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
221 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
222 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
223 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
224 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
225 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
226 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
227 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
228 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
229 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
230 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
231 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
232 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
233 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
234 PREFIX_EVEX_0F3A55.
235 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
236 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
237 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
238 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
239 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
240 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
241 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
242 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
243 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
244 VEX_W_0F3A32_P_2_LEN_0.
245 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
246 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
247 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
248 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
249 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
250 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
251 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
252 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
253 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
254 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
255 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
256 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
257 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
258 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
259 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
260 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
261 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
262 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
263 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
264 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
265 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
266 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
267 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
268 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
269 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
270 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
271 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
272 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
273 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
274 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
275 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
276 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
277 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
278 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
279 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
280 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
281 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
282 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
283 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
284 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
285 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
286 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
287 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
288 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
289 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
290 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
291 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
292 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
293 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
294 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
295 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
296 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
297 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
298 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
299 (struct vex): Add fields evex, r, v, mask_register_specifier,
300 zeroing, ll, b.
301 (intel_names_xmm): Add upper 16 registers.
302 (att_names_xmm): Ditto.
303 (intel_names_ymm): Ditto.
304 (att_names_ymm): Ditto.
305 (names_zmm): New.
306 (intel_names_zmm): Ditto.
307 (att_names_zmm): Ditto.
308 (names_mask): Ditto.
309 (intel_names_mask): Ditto.
310 (att_names_mask): Ditto.
311 (names_rounding): Ditto.
312 (names_broadcast): Ditto.
313 (x86_64_table): Add escape to evex-table.
314 (reg_table): Include reg_table evex-entries from
315 i386-dis-evex.h. Fix prefetchwt1 instruction.
316 (prefix_table): Add entries for new instructions.
317 (vex_table): Ditto.
318 (vex_len_table): Ditto.
319 (vex_w_table): Ditto.
320 (mod_table): Ditto.
321 (get_valid_dis386): Properly handle new instructions.
322 (print_insn): Handle zmm and mask registers, print mask operand.
323 (intel_operand_size): Support EVEX, new modes and sizes.
324 (OP_E_register): Handle new modes.
325 (OP_E_memory): Ditto.
326 (OP_G): Ditto.
327 (OP_XMM): Ditto.
328 (OP_EX): Ditto.
329 (OP_VEX): Ditto.
330 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
331 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
332 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
333 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
334 CpuAVX512PF and CpuVREX.
335 (operand_type_init): Add OPERAND_TYPE_REGZMM,
336 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
337 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
338 StaticRounding, SAE, Disp8MemShift, NoDefMask.
339 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
340 * i386-init.h: Regenerate.
341 * i386-opc.h (CpuAVX512F): New.
342 (CpuAVX512CD): New.
343 (CpuAVX512ER): New.
344 (CpuAVX512PF): New.
345 (CpuVREX): New.
346 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
347 cpuavx512pf and cpuvrex fields.
348 (VecSIB): Add VecSIB512.
349 (EVex): New.
350 (Masking): New.
351 (VecESize): New.
352 (Broadcast): New.
353 (StaticRounding): New.
354 (SAE): New.
355 (Disp8MemShift): New.
356 (NoDefMask): New.
357 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
358 staticrounding, sae, disp8memshift and nodefmask.
359 (RegZMM): New.
360 (Zmmword): Ditto.
361 (Vec_Disp8): Ditto.
362 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
363 fields.
364 (RegVRex): New.
365 * i386-opc.tbl: Add AVX512 instructions.
366 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
367 registers, mask registers.
368 * i386-tbl.h: Regenerate.
369
1d2db237
RS		 3702013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
371
372 PR gas/15220
373 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
374 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
375
a0046408
L		 3762013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
377
378 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
379 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
380 PREFIX_0F3ACC.
381 (prefix_table): Updated.
382 (three_byte_table): Likewise.
383 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
384 (cpu_flags): Add CpuSHA.
385 (i386_cpu_flags): Add cpusha.
386 * i386-init.h: Regenerate.
387 * i386-opc.h (CpuSHA): New.
388 (CpuUnused): Restored.
389 (i386_cpu_flags): Add cpusha.
390 * i386-opc.tbl: Add SHA instructions.
391 * i386-tbl.h: Regenerate.
392
7e8b059b
L		 3932013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
394 Kirill Yukhin <kirill.yukhin@intel.com>
395 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
396
397 * i386-dis.c (BND_Fixup): New.
398 (Ebnd): New.
399 (Ev_bnd): New.
400 (Gbnd): New.
401 (BND): New.
402 (v_bnd_mode): New.
403 (bnd_mode): New.
c623f86c
L		 404 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
405 MOD_0F1B_PREFIX_1.
406 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 407 (dis tables): Replace XX with BND for near branch and call
408 instructions.
409 (prefix_table): Add new entries.
410 (mod_table): Likewise.
411 (names_bnd): New.
412 (intel_names_bnd): New.
413 (att_names_bnd): New.
414 (BND_PREFIX): New.
415 (prefix_name): Handle BND_PREFIX.
416 (print_insn): Initialize names_bnd.
417 (intel_operand_size): Handle new modes.
418 (OP_E_register): Likewise.
419 (OP_E_memory): Likewise.
420 (OP_G): Likewise.
421 * i386-gen.c (cpu_flag_init): Add CpuMPX.
422 (cpu_flags): Add CpuMPX.
423 (operand_type_init): Add RegBND.
424 (opcode_modifiers): Add BNDPrefixOk.
425 (operand_types): Add RegBND.
426 * i386-init.h: Regenerate.
427 * i386-opc.h (CpuMPX): New.
428 (CpuUnused): Comment out.
429 (i386_cpu_flags): Add cpumpx.
430 (BNDPrefixOk): New.
431 (i386_opcode_modifier): Add bndprefixok.
432 (RegBND): New.
433 (i386_operand_type): Add regbnd.
434 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
435 Add MPX instructions and bnd prefix.
436 * i386-reg.tbl: Add bnd0-bnd3 registers.
437 * i386-tbl.h: Regenerate.
438
b56e23fb
RS		 4392013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
440
441 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
442 ATTRIBUTE_UNUSED.
443
e7ae278d
RS		 4442013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
445
446 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
447 special rules.
448 * Makefile.in: Regenerate.
449 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
450 all fields. Reformat.
451
c3c07478
RS		 4522013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
453
454 * mips16-opc.c: Include mips-formats.h.
455 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
456 static arrays.
457 (decode_mips16_operand): New function.
458 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
459 (print_insn_arg): Handle OP_ENTRY_EXIT list.
460 Abort for OP_SAVE_RESTORE_LIST.
461 (print_mips16_insn_arg): Change interface. Use mips_operand
462 structures. Delete GET_OP_S. Move GET_OP definition to...
463 (print_insn_mips16): ...here. Call init_print_arg_state.
464 Update the call to print_mips16_insn_arg.
465
ab902481
RS		 4662013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
467
468 * mips-formats.h: New file.
469 * mips-opc.c: Include mips-formats.h.
470 (reg_0_map): New static array.
471 (decode_mips_operand): New function.
472 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
473 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
474 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
475 (int_c_map): New static arrays.
476 (decode_micromips_operand): New function.
477 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
478 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
479 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
480 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
481 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
482 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
483 (micromips_imm_b_map, micromips_imm_c_map): Delete.
484 (print_reg): New function.
485 (mips_print_arg_state): New structure.
486 (init_print_arg_state, print_insn_arg): New functions.
487 (print_insn_args): Change interface and use mips_operand structures.
488 Delete GET_OP_S. Move GET_OP definition to...
489 (print_insn_mips): ...here. Update the call to print_insn_args.
490 (print_insn_micromips): Use print_insn_args.
491
cc537e56
RS		 4922013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
493
494 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
495 in macros.
496
7a5f87ce
RS		 4972013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
498
499 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
500 ADDA.S, MULA.S and SUBA.S.
501
41741fa4
L		 5022013-07-08 H.J. Lu <hongjiu.lu@intel.com>
503
504 PR gas/13572
505 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
506 * i386-tbl.h: Regenerated.
507
f2ae14a1
RS		 5082013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
509
510 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
511 and SD A(B) macros up.
512 * micromips-opc.c (micromips_opcodes): Likewise.
513
04c9d415
RS		 5142013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
515
516 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
517 instructions.
518
5c324c16
RS		 5192013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
520
521 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
522 MDMX-like instructions.
523 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
524 printing "Q" operands for INSN_5400 instructions.
525
23e69e47
RS		 5262013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
527
528 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
529 "+S" for "cins".
530 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
531 Combine cases.
532
27c5c572
RS		 5332013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
534
535 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
536 "jalx".
537 * mips16-opc.c (mips16_opcodes): Likewise.
538 * micromips-opc.c (micromips_opcodes): Likewise.
539 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
540 (print_insn_mips16): Handle "+i".
541 (print_insn_micromips): Likewise. Conditionally preserve the
542 ISA bit for "a" but not for "+i".
543
e76ff5ab
RS		 5442013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
545
546 * micromips-opc.c (WR_mhi): Rename to..
547 (WR_mh): ...this.
548 (micromips_opcodes): Update "movep" entry accordingly. Replace
549 "mh,mi" with "mh".
550 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
551 (micromips_to_32_reg_h_map1): ...this.
552 (micromips_to_32_reg_i_map): Rename to...
553 (micromips_to_32_reg_h_map2): ...this.
554 (print_micromips_insn): Remove "mi" case. Print both registers
555 in the pair for "mh".
556
fa7616a4
RS		 5572013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
558
559 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
560 * micromips-opc.c (micromips_opcodes): Likewise.
561 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
562 and "+T" handling. Check for a "0" suffix when deciding whether to
563 use coprocessor 0 names. In that case, also check for ",H" selectors.
564
fb798c50
AK		 5652013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
566
567 * s390-opc.c (J12_12, J24_24): New macros.
568 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
569 (MASK_MII_UPI): Rename to MASK_MII_UPP.
570 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
571
58ae08f2
AM		 5722013-07-04 Alan Modra <amodra@gmail.com>
573
574 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
575
b5e04c2b
NC		 5762013-06-26 Nick Clifton <nickc@redhat.com>
577
578 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
579 field when checking for type 2 nop.
580 * rx-decode.c: Regenerate.
581
833794fc
MR		 5822013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
583
584 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
585 and "movep" macros.
586
1bbce132
MR		 5872013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
588
589 * mips-dis.c (is_mips16_plt_tail): New function.
590 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
591 word.
592 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
593
34c911a4
NC		 5942013-06-21 DJ Delorie <dj@redhat.com>
595
596 * msp430-decode.opc: New.
597 * msp430-decode.c: New/generated.
598 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
599 (MAINTAINER_CLEANFILES): Likewise.
600 Add rule to build msp430-decode.c frommsp430decode.opc
601 using the opc2c program.
602 * Makefile.in: Regenerate.
603 * configure.in: Add msp430-decode.lo to msp430 architecture files.
604 * configure: Regenerate.
605
b9eead84
YZ		 6062013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
607
608 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
609 (SYMTAB_AVAILABLE): Removed.
610 (#include "elf/aarch64.h): Ditto.
611
7f3c4072
CM		 6122013-06-17 Catherine Moore <clm@codesourcery.com>
613 Maciej W. Rozycki <macro@codesourcery.com>
614 Chao-Ying Fu <fu@mips.com>
615
616 * micromips-opc.c (EVA): Define.
617 (TLBINV): Define.
618 (micromips_opcodes): Add EVA opcodes.
619 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
620 (print_insn_args): Handle EVA offsets.
621 (print_insn_micromips): Likewise.
622 * mips-opc.c (EVA): Define.
623 (TLBINV): Define.
624 (mips_builtin_opcodes): Add EVA opcodes.
625
de40ceb6
AM		 6262013-06-17 Alan Modra <amodra@gmail.com>
627
628 * Makefile.am (mips-opc.lo): Add rules to create automatic
629 dependency files. Pass archdefs.
630 (micromips-opc.lo, mips16-opc.lo): Likewise.
631 * Makefile.in: Regenerate.
632
3531d549
DD		 6332013-06-14 DJ Delorie <dj@redhat.com>
634
635 * rx-decode.opc (rx_decode_opcode): Bit operations on
636 registers are 32-bit operations, not 8-bit operations.
637 * rx-decode.c: Regenerate.
638
ba92f7fb
CF		 6392013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
640
641 * micromips-opc.c (IVIRT): New define.
642 (IVIRT64): New define.
643 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
644 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
645
646 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
647 dmtgc0 to print cp0 names.
648
9daf7bab
SL		 6492013-06-09 Sandra Loosemore <sandra@codesourcery.com>
650
651 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
652 argument.
653
d301a56b
RS		 6542013-06-08 Catherine Moore <clm@codesourcery.com>
655 Richard Sandiford <rdsandiford@googlemail.com>
656
657 * micromips-opc.c (D32, D33, MC): Update definitions.
658 (micromips_opcodes): Initialize ase field.
659 * mips-dis.c (mips_arch_choice): Add ase field.
660 (mips_arch_choices): Initialize ase field.
661 (set_default_mips_dis_options): Declare and setup mips_ase.
662 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
663 MT32, MC): Update definitions.
664 (mips_builtin_opcodes): Initialize ase field.
665
a3dcb6c5
RS		 6662013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
667
668 * s390-opc.txt (flogr): Require a register pair destination.
669
6cf1d90c
AK		 6702013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
671
672 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
673 instruction format.
674
c77c0862
RS		 6752013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
676
677 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
678
c0637f3a
PB		 6792013-05-20 Peter Bergner <bergner@vnet.ibm.com>
680
681 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
682 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
683 XLS_MASK, PPCVSX2): New defines.
684 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
685 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
686 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
687 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
688 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
689 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
690 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
691 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
692 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
693 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
694 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
695 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
696 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
697 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
698 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
699 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
700 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
701 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
702 <lxvx, stxvx>: New extended mnemonics.
703
4934fdaf
AM		 7042013-05-17 Alan Modra <amodra@gmail.com>
705
706 * ia64-raw.tbl: Replace non-ASCII char.
707 * ia64-waw.tbl: Likewise.
708 * ia64-asmtab.c: Regenerate.
709
6091d651
SE		 7102013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
711
712 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
713 * i386-init.h: Regenerated.
714
d2865ed3
YZ		 7152013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
716
717 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
718 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
719 check from [0, 255] to [-128, 255].
720
b015e599
AP		 7212013-05-09 Andrew Pinski <apinski@cavium.com>
722
723 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
724 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
725 (parse_mips_dis_option): Handle the virt option.
726 (print_insn_args): Handle "+J".
727 (print_mips_disassembler_options): Print out message about virt64.
728 * mips-opc.c (IVIRT): New define.
729 (IVIRT64): New define.
730 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
731 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
732 Move rfe to the bottom as it conflicts with tlbgp.
733
9f0682fe
AM		 7342013-05-09 Alan Modra <amodra@gmail.com>
735
736 * ppc-opc.c (extract_vlesi): Properly sign extend.
737 (extract_vlensi): Likewise. Comment reason for setting invalid.
738
13761a11
NC		 7392013-05-02 Nick Clifton <nickc@redhat.com>
740
741 * msp430-dis.c: Add support for MSP430X instructions.
742
e3031850
SL		 7432013-04-24 Sandra Loosemore <sandra@codesourcery.com>
744
745 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
746 to "eccinj".
747
17310e56
NC		 7482013-04-17 Wei-chen Wang <cole945@gmail.com>
749
750 PR binutils/15369
751 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
752 of CGEN_CPU_ENDIAN.
753 (hash_insns_list): Likewise.
754
731df338
JK		 7552013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
756
757 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
758 warning workaround.
759
5f77db52
JB		 7602013-04-08 Jan Beulich <jbeulich@suse.com>
761
762 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
763 * i386-tbl.h: Re-generate.
764
0afd1215
DM		 7652013-04-06 David S. Miller <davem@davemloft.net>
766
767 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
768 of an opcode, prefer the one with F_PREFERRED set.
769 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
770 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
771 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
772 mark existing mnenomics as aliases. Add "cc" suffix to edge
773 instructions generating condition codes, mark existing mnenomics
774 as aliases. Add "fp" prefix to VIS compare instructions, mark
775 existing mnenomics as aliases.
776
41702d50
NC		 7772013-04-03 Nick Clifton <nickc@redhat.com>
778
779 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
780 destination address by subtracting the operand from the current
781 address.
782 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
783 a positive value in the insn.
784 (extract_u16_loop): Do not negate the returned value.
785 (D16_LOOP): Add V850_INVERSE_PCREL flag.
786
787 (ceilf.sw): Remove duplicate entry.
788 (cvtf.hs): New entry.
789 (cvtf.sh): Likewise.
790 (fmaf.s): Likewise.
791 (fmsf.s): Likewise.
792 (fnmaf.s): Likewise.
793 (fnmsf.s): Likewise.
794 (maddf.s): Restrict to E3V5 architectures.
795 (msubf.s): Likewise.
796 (nmaddf.s): Likewise.
797 (nmsubf.s): Likewise.
798
55cf16e1
L		 7992013-03-27 H.J. Lu <hongjiu.lu@intel.com>
800
801 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
802 check address mode.
803 (print_insn): Pass sizeflag to get_sib.
804
51dcdd4d
NC		 8052013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
806
807 PR binutils/15068
808 * tic6x-dis.c: Add support for displaying 16-bit insns.
809
795b8e6b
NC		 8102013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
811
812 PR gas/15095
813 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
814 individual msb and lsb halves in src1 & src2 fields. Discard the
815 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
816 follow what Ti SDK does in that case as any value in the src1
817 field yields the same output with SDK disassembler.
818
314d60dd
ME		 8192013-03-12 Michael Eager <eager@eagercon.com>
820
795b8e6b 821 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 822
dad60f8e
SL		 8232013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
824
825 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
826
f5cb796a
SL		 8272013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
828
829 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
830
21fde85c
SL		 8312013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
832
833 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
834
dd5181d5
KT		 8352013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
836
837 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
838 (thumb32_opcodes): Likewise.
839 (print_insn_thumb32): Handle 'S' control char.
840
87a8d6cb
NC		 8412013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
842
843 * lm32-desc.c: Regenerate.
844
99dce992
L		 8452013-03-01 H.J. Lu <hongjiu.lu@intel.com>
846
847 * i386-reg.tbl (riz): Add RegRex64.
848 * i386-tbl.h: Regenerated.
849
e60bb1dd
YZ		 8502013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
851
852 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
853 (aarch64_feature_crc): New static.
854 (CRC): New macro.
855 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
856 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
857 * aarch64-asm-2.c: Re-generate.
858 * aarch64-dis-2.c: Ditto.
859 * aarch64-opc-2.c: Ditto.
860
c7570fcd
AM		 8612013-02-27 Alan Modra <amodra@gmail.com>
862
863 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
864 * rl78-decode.c: Regenerate.
865
151fa98f
NC		 8662013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
867
868 * rl78-decode.opc: Fix encoding of DIVWU insn.
869 * rl78-decode.c: Regenerate.
870
5c111e37
L		 8712013-02-19 H.J. Lu <hongjiu.lu@intel.com>
872
873 PR gas/15159
874 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
875
876 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
877 (cpu_flags): Add CpuSMAP.
878
879 * i386-opc.h (CpuSMAP): New.
880 (i386_cpu_flags): Add cpusmap.
881
882 * i386-opc.tbl: Add clac and stac.
883
884 * i386-init.h: Regenerated.
885 * i386-tbl.h: Likewise.
886
9d1df426
NC		 8872013-02-15 Markos Chandras <markos.chandras@imgtec.com>
888
889 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
890 which also makes the disassembler output be in little
891 endian like it should be.
892
a1ccaec9
YZ		 8932013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
894
895 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
896 fields to NULL.
897 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
898
ef068ef4 8992013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 900
901 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
902 section disassembled.
903
6fe6ded9
RE		 9042013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
905
906 * arm-dis.c: Update strht pattern.
907
0aa27725
RS		 9082013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
909
910 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
911 single-float. Disable ll, lld, sc and scd for EE. Disable the
912 trunc.w.s macro for EE.
913
36591ba1
SL		 9142013-02-06 Sandra Loosemore <sandra@codesourcery.com>
915 Andrew Jenner <andrew@codesourcery.com>
916
917 Based on patches from Altera Corporation.
918
919 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
920 nios2-opc.c.
921 * Makefile.in: Regenerated.
922 * configure.in: Add case for bfd_nios2_arch.
923 * configure: Regenerated.
924 * disassemble.c (ARCH_nios2): Define.
925 (disassembler): Add case for bfd_arch_nios2.
926 * nios2-dis.c: New file.
927 * nios2-opc.c: New file.
928
545093a4
AM		 9292013-02-04 Alan Modra <amodra@gmail.com>
930
931 * po/POTFILES.in: Regenerate.
932 * rl78-decode.c: Regenerate.
933 * rx-decode.c: Regenerate.
934
e30181a5
YZ		 9352013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
936
937 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
938 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
939 * aarch64-asm.c (convert_xtl_to_shll): New function.
940 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
941 calling convert_xtl_to_shll.
942 * aarch64-dis.c (convert_shll_to_xtl): New function.
943 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
944 calling convert_shll_to_xtl.
945 * aarch64-gen.c: Update copyright year.
946 * aarch64-asm-2.c: Re-generate.
947 * aarch64-dis-2.c: Re-generate.
948 * aarch64-opc-2.c: Re-generate.
949
78c8d46c
NC		 9502013-01-24 Nick Clifton <nickc@redhat.com>
951
952 * v850-dis.c: Add support for e3v5 architecture.
953 * v850-opc.c: Likewise.
954
f5555712
YZ		 9552013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
956
957 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
958 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
959 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 960 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 961 alignment check; change to call set_sft_amount_out_of_range_error
962 instead of set_imm_out_of_range_error.
963 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
964 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
965 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
966 SIMD_IMM_SFT.
967
2f81ff92
L		 9682013-01-16 H.J. Lu <hongjiu.lu@intel.com>
969
970 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
971
972 * i386-init.h: Regenerated.
973 * i386-tbl.h: Likewise.
974
dd42f060
NC		 9752013-01-15 Nick Clifton <nickc@redhat.com>
976
977 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
978 values.
979 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
980
a4533ed8
NC		 9812013-01-14 Will Newton <will.newton@imgtec.com>
982
983 * metag-dis.c (REG_WIDTH): Increase to 64.
984
5817ffd1
PB		 9852013-01-10 Peter Bergner <bergner@vnet.ibm.com>
986
987 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
988 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
989 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
990 (SH6): Update.
991 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
992 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
993 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
994 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
995
a3c62988
NC		 9962013-01-10 Will Newton <will.newton@imgtec.com>
997
998 * Makefile.am: Add Meta.
999 * configure.in: Add Meta.
1000 * disassemble.c: Add Meta support.
1001 * metag-dis.c: New file.
1002 * Makefile.in: Regenerate.
1003 * configure: Regenerate.
1004
73335eae
NC		 10052013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1006
1007 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1008 (match_opcode): Rename to cr16_match_opcode.
1009
e407c74b
NC		 10102013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1011
1012 * mips-dis.c: Add names for CP0 registers of r5900.
1013 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1014 instructions sq and lq.
1015 Add support for MIPS r5900 CPU.
1016 Add support for 128 bit MMI (Multimedia Instructions).
1017 Add support for EE instructions (Emotion Engine).
1018 Disable unsupported floating point instructions (64 bit and
1019 undefined compare operations).
1020 Enable instructions of MIPS ISA IV which are supported by r5900.
1021 Disable 64 bit co processor instructions.
1022 Disable 64 bit multiplication and division instructions.
1023 Disable instructions for co-processor 2 and 3, because these are
1024 not supported (preparation for later VU0 support (Vector Unit)).
1025 Disable cvt.w.s because this behaves like trunc.w.s and the
1026 correct execution can't be ensured on r5900.
1027 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1028 will confuse less developers and compilers.
1029
a32c3ff8
NC		 10302013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1031
fb098a1e
YZ		 1032 * aarch64-opc.c (aarch64_print_operand): Change to print
1033 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1034 in comment.
1035 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1036 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1037 OP_MOV_IMM_WIDE.
1038
10392013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1040
1041 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1042 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 1043
62658407
L		 10442013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1045
1046 * i386-gen.c (process_copyright): Update copyright year to 2013.
1047
bab4becb 10482013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 1049
bab4becb
NC		 1050 * cr16-dis.c (match_opcode,make_instruction): Remove static
1051 declaration.
1052 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1053 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 1054
bab4becb 1055For older changes see ChangeLog-2012
252b5132 1056\f
bab4becb 1057Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1058
1059Copying and distribution of this file, with or without modification,
1060are permitted in any medium without royalty provided the copyright
1061notice and this notice are preserved.
1062
252b5132 1063Local Variables:
2f6d2f85
NC		 1064mode: change-log
1065left-margin: 8
1066fill-column: 74
252b5132
RH		 1067version-control: never
1068End:
GDB Binutils - Deliverables
This page took 0.640231 seconds and 4 git commands to generate.