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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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e3f9e852
RS		 12013-09-17 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
2
3 * s390-opc.txt (clih): Make the immediate unsigned.
4
74db7efb
NC		 52013-09-04 Roland McGrath <mcgrathr@google.com>
6
7 PR gas/15914
8 * arm-dis.c (arm_opcodes): Add udf.
9 (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
10 (thumb32_opcodes): Add udf.w.
11 (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
12
c8094e01
AK		 132013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
14
15 * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
16 For the load fp integer instructions only the suppression flag was
17 new with z196 version.
18
7e105031
NC		 192013-08-28 Nick Clifton <nickc@redhat.com>
20
21 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
22 immediate is not suitable for the 32-bit ABI.
23
fb6f3895
MR		 242013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
25
26 * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
27 replacing NODS.
28
9aff4b7a
NC		 292013-08-23 Yuri Chornoivan <yurchor@ukr.net>
30
31 PR binutils/15834
32 * aarch64-asm.c: Fix typos.
33 * aarch64-dis.c: Likewise.
34 * msp430-dis.c: Likewise.
35
5e0dc5ba
RS		 362013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
37
38 * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
39 macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
40 Use +H rather than +C for the real "dext".
41 * mips-opc.c (mips_builtin_opcodes): Likewise.
42
0f35dbc4
RS		 432013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
44
45 * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
46 * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
47 and OPTIONAL_MAPPED_REG.
48 * mips-opc.c (decode_mips_operand): Likewise.
49 * mips16-opc.c (decode_mips16_operand): Likewise.
50 * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
51
79ceb7cb
L		 522013-08-19 H.J. Lu <hongjiu.lu@intel.com>
53
54 * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
55 (PREFIX_EVEX_0F3A3F): Likewise.
56 * i386-dis-evex.h (evex_table): Updated.
57
ee5734f0
RS		 582013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
59
60 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
61 VCLIPW.
62
d6787ef9
EB		 632013-08-05 Eric Botcazou <ebotcazou@adacore.com>
64 Konrad Eisele <konrad@gaisler.com>
65
66 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
67 bfd_mach_sparc.
68 * sparc-opc.c (MASK_LEON): Define.
69 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
70 (letandleon): New macro.
71 (v9andleon): Likewise.
72 (sparc_opc): Add leon.
73 (umac): Enable for letandleon.
74 (smac): Likewise.
75 (casa): Enable for v9andleon.
76 (cas): Likewise.
77 (casl): Likewise.
78
14daeee3
RS		 792013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
80 Richard Sandiford <rdsandiford@googlemail.com>
81
82 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
83 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
84 (print_vu0_channel): New function.
85 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
86 (print_insn_args): Handle '#'.
87 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
88 * mips-opc.c (mips_vu0_channel_mask): New constant.
89 (decode_mips_operand): Handle new VU0 operand types.
90 (VU0, VU0CH): New macros.
91 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
92 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
93 Use "+6" rather than "G" for QMFC2 and QMTC2.
94
3ccad066
RS		 952013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
96
97 * mips-formats.h (PCREL): Reorder parameters and update the definition
98 to match new mips_pcrel_operand layout.
99 (JUMP, JALX, BRANCH): Update accordingly.
100 * mips16-opc.c (decode_mips16_operand): Likewise.
101
df34fbcc
RS		 1022013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
103
104 * micromips-opc.c (WR_s): Delete.
105
fc76e730
RS		 1062013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
107
108 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
109 New macros.
110 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
111 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
112 (mips_builtin_opcodes): Use the new position-based read-write flags
113 instead of field-based ones. Use UDI for "udi..." instructions.
114 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
115 New macros.
116 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
117 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
118 (WR_SP, RD_16): New macros.
119 (RD_SP): Redefine as an INSN2_* flag.
120 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
121 (mips16_opcodes): Use the new position-based read-write flags
122 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
123 pinfo2 field.
124 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
125 New macros.
126 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
127 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
128 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
129 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
130 (micromips_opcodes): Use the new position-based read-write flags
131 instead of field-based ones.
132 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
133 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
134 of field-based flags.
135
26545944
RS		 1362013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
137
138 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
139 (WR_SP): Replace with...
140 (MOD_SP): ...this.
141 (mips16_opcodes): Update accordingly.
142 * mips-dis.c (print_insn_mips16): Likewise.
143
a8d92fc6
RS		 1442013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
145
146 * mips16-opc.c (mips16_opcodes): Reformat.
147
6a819047
RS		 1482013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
149
150 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
151 for operands that are hard-coded to $0.
152 * micromips-opc.c (micromips_opcodes): Likewise.
153
344c74a6
RS		 1542013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
155
156 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
157 for the single-operand forms of JALR and JALR.HB.
158 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
159 and JALRS.HB.
160
41989114
RS		 1612013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
162
163 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
164 instructions. Fix them to use WR_MACC instead of WR_CC and
165 add missing RD_MACCs.
166
6d075bce
RS		 1672013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
168
169 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
170
4f6ffcd3
PB		 1712013-07-29 Peter Bergner <bergner@vnet.ibm.com>
172
173 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
174
43234a1e
L		 1752013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
176 Alexander Ivchenko <alexander.ivchenko@intel.com>
177 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
178 Sergey Lega <sergey.s.lega@intel.com>
179 Anna Tikhonova <anna.tikhonova@intel.com>
180 Ilya Tocar <ilya.tocar@intel.com>
181 Andrey Turetskiy <andrey.turetskiy@intel.com>
182 Ilya Verbin <ilya.verbin@intel.com>
183 Kirill Yukhin <kirill.yukhin@intel.com>
184 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
185
186 * i386-dis-evex.h: New.
187 * i386-dis.c (OP_Rounding): New.
188 (VPCMP_Fixup): New.
189 (OP_Mask): New.
190 (Rdq): New.
191 (XMxmmq): New.
192 (EXdScalarS): New.
193 (EXymm): New.
194 (EXEvexHalfBcstXmmq): New.
195 (EXxmm_mdq): New.
196 (EXEvexXGscat): New.
197 (EXEvexXNoBcst): New.
198 (VPCMP): New.
199 (EXxEVexR): New.
200 (EXxEVexS): New.
201 (XMask): New.
202 (MaskG): New.
203 (MaskE): New.
204 (MaskR): New.
205 (MaskVex): New.
206 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
207 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
208 evex_rounding_mode, evex_sae_mode, mask_mode.
209 (USE_EVEX_TABLE): New.
210 (EVEX_TABLE): New.
211 (EVEX enum): New.
212 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
213 REG_EVEX_0F38C7.
214 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
215 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
216 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
217 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
218 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
219 MOD_EVEX_0F38C7_REG_6.
220 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
221 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
222 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
223 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
224 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
225 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
226 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
227 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
228 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
229 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
230 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
231 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
232 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
233 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
234 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
235 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
236 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
237 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
238 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
239 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
240 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
241 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
242 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
243 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
244 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
245 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
246 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
247 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
248 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
249 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
250 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
251 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
252 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
253 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
254 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
255 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
256 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
257 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
258 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
259 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
260 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
261 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
262 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
263 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
264 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
265 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
266 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
267 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
268 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
269 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
270 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
271 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
272 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
273 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
274 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
275 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
276 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
277 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
278 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
279 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
280 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
281 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
282 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
283 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
284 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
285 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
286 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
287 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
288 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
289 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
290 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
291 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
292 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
293 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
294 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
295 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
296 PREFIX_EVEX_0F3A55.
297 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
298 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
299 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
300 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
301 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
302 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
303 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
304 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
305 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
306 VEX_W_0F3A32_P_2_LEN_0.
307 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
308 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
309 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
310 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
311 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
312 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
313 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
314 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
315 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
316 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
317 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
318 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
319 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
320 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
321 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
322 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
323 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
324 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
325 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
326 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
327 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
328 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
329 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
330 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
331 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
332 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
333 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
334 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
335 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
336 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
337 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
338 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
339 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
340 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
341 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
342 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
343 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
344 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
345 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
346 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
347 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
348 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
349 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
350 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
351 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
352 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
353 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
354 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
355 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
356 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
357 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
358 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
359 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
360 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
361 (struct vex): Add fields evex, r, v, mask_register_specifier,
362 zeroing, ll, b.
363 (intel_names_xmm): Add upper 16 registers.
364 (att_names_xmm): Ditto.
365 (intel_names_ymm): Ditto.
366 (att_names_ymm): Ditto.
367 (names_zmm): New.
368 (intel_names_zmm): Ditto.
369 (att_names_zmm): Ditto.
370 (names_mask): Ditto.
371 (intel_names_mask): Ditto.
372 (att_names_mask): Ditto.
373 (names_rounding): Ditto.
374 (names_broadcast): Ditto.
375 (x86_64_table): Add escape to evex-table.
376 (reg_table): Include reg_table evex-entries from
377 i386-dis-evex.h. Fix prefetchwt1 instruction.
378 (prefix_table): Add entries for new instructions.
379 (vex_table): Ditto.
380 (vex_len_table): Ditto.
381 (vex_w_table): Ditto.
382 (mod_table): Ditto.
383 (get_valid_dis386): Properly handle new instructions.
384 (print_insn): Handle zmm and mask registers, print mask operand.
385 (intel_operand_size): Support EVEX, new modes and sizes.
386 (OP_E_register): Handle new modes.
387 (OP_E_memory): Ditto.
388 (OP_G): Ditto.
389 (OP_XMM): Ditto.
390 (OP_EX): Ditto.
391 (OP_VEX): Ditto.
392 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
393 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
394 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
395 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
396 CpuAVX512PF and CpuVREX.
397 (operand_type_init): Add OPERAND_TYPE_REGZMM,
398 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
399 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
400 StaticRounding, SAE, Disp8MemShift, NoDefMask.
401 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
402 * i386-init.h: Regenerate.
403 * i386-opc.h (CpuAVX512F): New.
404 (CpuAVX512CD): New.
405 (CpuAVX512ER): New.
406 (CpuAVX512PF): New.
407 (CpuVREX): New.
408 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
409 cpuavx512pf and cpuvrex fields.
410 (VecSIB): Add VecSIB512.
411 (EVex): New.
412 (Masking): New.
413 (VecESize): New.
414 (Broadcast): New.
415 (StaticRounding): New.
416 (SAE): New.
417 (Disp8MemShift): New.
418 (NoDefMask): New.
419 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
420 staticrounding, sae, disp8memshift and nodefmask.
421 (RegZMM): New.
422 (Zmmword): Ditto.
423 (Vec_Disp8): Ditto.
424 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
425 fields.
426 (RegVRex): New.
427 * i386-opc.tbl: Add AVX512 instructions.
428 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
429 registers, mask registers.
430 * i386-tbl.h: Regenerate.
431
1d2db237
RS		 4322013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
433
434 PR gas/15220
435 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
436 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
437
a0046408
L		 4382013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
439
440 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
441 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
442 PREFIX_0F3ACC.
443 (prefix_table): Updated.
444 (three_byte_table): Likewise.
445 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
446 (cpu_flags): Add CpuSHA.
447 (i386_cpu_flags): Add cpusha.
448 * i386-init.h: Regenerate.
449 * i386-opc.h (CpuSHA): New.
450 (CpuUnused): Restored.
451 (i386_cpu_flags): Add cpusha.
452 * i386-opc.tbl: Add SHA instructions.
453 * i386-tbl.h: Regenerate.
454
7e8b059b
L		 4552013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
456 Kirill Yukhin <kirill.yukhin@intel.com>
457 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
458
459 * i386-dis.c (BND_Fixup): New.
460 (Ebnd): New.
461 (Ev_bnd): New.
462 (Gbnd): New.
463 (BND): New.
464 (v_bnd_mode): New.
465 (bnd_mode): New.
c623f86c
L		 466 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
467 MOD_0F1B_PREFIX_1.
468 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 469 (dis tables): Replace XX with BND for near branch and call
470 instructions.
471 (prefix_table): Add new entries.
472 (mod_table): Likewise.
473 (names_bnd): New.
474 (intel_names_bnd): New.
475 (att_names_bnd): New.
476 (BND_PREFIX): New.
477 (prefix_name): Handle BND_PREFIX.
478 (print_insn): Initialize names_bnd.
479 (intel_operand_size): Handle new modes.
480 (OP_E_register): Likewise.
481 (OP_E_memory): Likewise.
482 (OP_G): Likewise.
483 * i386-gen.c (cpu_flag_init): Add CpuMPX.
484 (cpu_flags): Add CpuMPX.
485 (operand_type_init): Add RegBND.
486 (opcode_modifiers): Add BNDPrefixOk.
487 (operand_types): Add RegBND.
488 * i386-init.h: Regenerate.
489 * i386-opc.h (CpuMPX): New.
490 (CpuUnused): Comment out.
491 (i386_cpu_flags): Add cpumpx.
492 (BNDPrefixOk): New.
493 (i386_opcode_modifier): Add bndprefixok.
494 (RegBND): New.
495 (i386_operand_type): Add regbnd.
496 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
497 Add MPX instructions and bnd prefix.
498 * i386-reg.tbl: Add bnd0-bnd3 registers.
499 * i386-tbl.h: Regenerate.
500
b56e23fb
RS		 5012013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
502
503 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
504 ATTRIBUTE_UNUSED.
505
e7ae278d
RS		 5062013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
507
508 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
509 special rules.
510 * Makefile.in: Regenerate.
511 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
512 all fields. Reformat.
513
c3c07478
RS		 5142013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
515
516 * mips16-opc.c: Include mips-formats.h.
517 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
518 static arrays.
519 (decode_mips16_operand): New function.
520 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
521 (print_insn_arg): Handle OP_ENTRY_EXIT list.
522 Abort for OP_SAVE_RESTORE_LIST.
523 (print_mips16_insn_arg): Change interface. Use mips_operand
524 structures. Delete GET_OP_S. Move GET_OP definition to...
525 (print_insn_mips16): ...here. Call init_print_arg_state.
526 Update the call to print_mips16_insn_arg.
527
ab902481
RS		 5282013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
529
530 * mips-formats.h: New file.
531 * mips-opc.c: Include mips-formats.h.
532 (reg_0_map): New static array.
533 (decode_mips_operand): New function.
534 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
535 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
536 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
537 (int_c_map): New static arrays.
538 (decode_micromips_operand): New function.
539 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
540 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
541 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
542 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
543 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
544 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
545 (micromips_imm_b_map, micromips_imm_c_map): Delete.
546 (print_reg): New function.
547 (mips_print_arg_state): New structure.
548 (init_print_arg_state, print_insn_arg): New functions.
549 (print_insn_args): Change interface and use mips_operand structures.
550 Delete GET_OP_S. Move GET_OP definition to...
551 (print_insn_mips): ...here. Update the call to print_insn_args.
552 (print_insn_micromips): Use print_insn_args.
553
cc537e56
RS		 5542013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
555
556 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
557 in macros.
558
7a5f87ce
RS		 5592013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
560
561 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
562 ADDA.S, MULA.S and SUBA.S.
563
41741fa4
L		 5642013-07-08 H.J. Lu <hongjiu.lu@intel.com>
565
566 PR gas/13572
567 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
568 * i386-tbl.h: Regenerated.
569
f2ae14a1
RS		 5702013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
571
572 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
573 and SD A(B) macros up.
574 * micromips-opc.c (micromips_opcodes): Likewise.
575
04c9d415
RS		 5762013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
577
578 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
579 instructions.
580
5c324c16
RS		 5812013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
582
583 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
584 MDMX-like instructions.
585 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
586 printing "Q" operands for INSN_5400 instructions.
587
23e69e47
RS		 5882013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
589
590 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
591 "+S" for "cins".
592 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
593 Combine cases.
594
27c5c572
RS		 5952013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
596
597 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
598 "jalx".
599 * mips16-opc.c (mips16_opcodes): Likewise.
600 * micromips-opc.c (micromips_opcodes): Likewise.
601 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
602 (print_insn_mips16): Handle "+i".
603 (print_insn_micromips): Likewise. Conditionally preserve the
604 ISA bit for "a" but not for "+i".
605
e76ff5ab
RS		 6062013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
607
608 * micromips-opc.c (WR_mhi): Rename to..
609 (WR_mh): ...this.
610 (micromips_opcodes): Update "movep" entry accordingly. Replace
611 "mh,mi" with "mh".
612 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
613 (micromips_to_32_reg_h_map1): ...this.
614 (micromips_to_32_reg_i_map): Rename to...
615 (micromips_to_32_reg_h_map2): ...this.
616 (print_micromips_insn): Remove "mi" case. Print both registers
617 in the pair for "mh".
618
fa7616a4
RS		 6192013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
620
621 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
622 * micromips-opc.c (micromips_opcodes): Likewise.
623 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
624 and "+T" handling. Check for a "0" suffix when deciding whether to
625 use coprocessor 0 names. In that case, also check for ",H" selectors.
626
fb798c50
AK		 6272013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
628
629 * s390-opc.c (J12_12, J24_24): New macros.
630 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
631 (MASK_MII_UPI): Rename to MASK_MII_UPP.
632 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
633
58ae08f2
AM		 6342013-07-04 Alan Modra <amodra@gmail.com>
635
636 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
637
b5e04c2b
NC		 6382013-06-26 Nick Clifton <nickc@redhat.com>
639
640 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
641 field when checking for type 2 nop.
642 * rx-decode.c: Regenerate.
643
833794fc
MR		 6442013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
645
646 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
647 and "movep" macros.
648
1bbce132
MR		 6492013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
650
651 * mips-dis.c (is_mips16_plt_tail): New function.
652 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
653 word.
654 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
655
34c911a4
NC		 6562013-06-21 DJ Delorie <dj@redhat.com>
657
658 * msp430-decode.opc: New.
659 * msp430-decode.c: New/generated.
660 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
661 (MAINTAINER_CLEANFILES): Likewise.
662 Add rule to build msp430-decode.c frommsp430decode.opc
663 using the opc2c program.
664 * Makefile.in: Regenerate.
665 * configure.in: Add msp430-decode.lo to msp430 architecture files.
666 * configure: Regenerate.
667
b9eead84
YZ		 6682013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
669
670 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
671 (SYMTAB_AVAILABLE): Removed.
672 (#include "elf/aarch64.h): Ditto.
673
7f3c4072
CM		 6742013-06-17 Catherine Moore <clm@codesourcery.com>
675 Maciej W. Rozycki <macro@codesourcery.com>
676 Chao-Ying Fu <fu@mips.com>
677
678 * micromips-opc.c (EVA): Define.
679 (TLBINV): Define.
680 (micromips_opcodes): Add EVA opcodes.
681 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
682 (print_insn_args): Handle EVA offsets.
683 (print_insn_micromips): Likewise.
684 * mips-opc.c (EVA): Define.
685 (TLBINV): Define.
686 (mips_builtin_opcodes): Add EVA opcodes.
687
de40ceb6
AM		 6882013-06-17 Alan Modra <amodra@gmail.com>
689
690 * Makefile.am (mips-opc.lo): Add rules to create automatic
691 dependency files. Pass archdefs.
692 (micromips-opc.lo, mips16-opc.lo): Likewise.
693 * Makefile.in: Regenerate.
694
3531d549
DD		 6952013-06-14 DJ Delorie <dj@redhat.com>
696
697 * rx-decode.opc (rx_decode_opcode): Bit operations on
698 registers are 32-bit operations, not 8-bit operations.
699 * rx-decode.c: Regenerate.
700
ba92f7fb
CF		 7012013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
702
703 * micromips-opc.c (IVIRT): New define.
704 (IVIRT64): New define.
705 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
706 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
707
708 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
709 dmtgc0 to print cp0 names.
710
9daf7bab
SL		 7112013-06-09 Sandra Loosemore <sandra@codesourcery.com>
712
713 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
714 argument.
715
d301a56b
RS		 7162013-06-08 Catherine Moore <clm@codesourcery.com>
717 Richard Sandiford <rdsandiford@googlemail.com>
718
719 * micromips-opc.c (D32, D33, MC): Update definitions.
720 (micromips_opcodes): Initialize ase field.
721 * mips-dis.c (mips_arch_choice): Add ase field.
722 (mips_arch_choices): Initialize ase field.
723 (set_default_mips_dis_options): Declare and setup mips_ase.
724 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
725 MT32, MC): Update definitions.
726 (mips_builtin_opcodes): Initialize ase field.
727
a3dcb6c5
RS		 7282013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
729
730 * s390-opc.txt (flogr): Require a register pair destination.
731
6cf1d90c
AK		 7322013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
733
734 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
735 instruction format.
736
c77c0862
RS		 7372013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
738
739 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
740
c0637f3a
PB		 7412013-05-20 Peter Bergner <bergner@vnet.ibm.com>
742
743 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
744 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
745 XLS_MASK, PPCVSX2): New defines.
746 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
747 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
748 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
749 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
750 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
751 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
752 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
753 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
754 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
755 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
756 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
757 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
758 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
759 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
760 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
761 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
762 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
763 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
764 <lxvx, stxvx>: New extended mnemonics.
765
4934fdaf
AM		 7662013-05-17 Alan Modra <amodra@gmail.com>
767
768 * ia64-raw.tbl: Replace non-ASCII char.
769 * ia64-waw.tbl: Likewise.
770 * ia64-asmtab.c: Regenerate.
771
6091d651
SE		 7722013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
773
774 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
775 * i386-init.h: Regenerated.
776
d2865ed3
YZ		 7772013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
778
779 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
780 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
781 check from [0, 255] to [-128, 255].
782
b015e599
AP		 7832013-05-09 Andrew Pinski <apinski@cavium.com>
784
785 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
786 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
787 (parse_mips_dis_option): Handle the virt option.
788 (print_insn_args): Handle "+J".
789 (print_mips_disassembler_options): Print out message about virt64.
790 * mips-opc.c (IVIRT): New define.
791 (IVIRT64): New define.
792 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
793 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
794 Move rfe to the bottom as it conflicts with tlbgp.
795
9f0682fe
AM		 7962013-05-09 Alan Modra <amodra@gmail.com>
797
798 * ppc-opc.c (extract_vlesi): Properly sign extend.
799 (extract_vlensi): Likewise. Comment reason for setting invalid.
800
13761a11
NC		 8012013-05-02 Nick Clifton <nickc@redhat.com>
802
803 * msp430-dis.c: Add support for MSP430X instructions.
804
e3031850
SL		 8052013-04-24 Sandra Loosemore <sandra@codesourcery.com>
806
807 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
808 to "eccinj".
809
17310e56
NC		 8102013-04-17 Wei-chen Wang <cole945@gmail.com>
811
812 PR binutils/15369
813 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
814 of CGEN_CPU_ENDIAN.
815 (hash_insns_list): Likewise.
816
731df338
JK		 8172013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
818
819 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
820 warning workaround.
821
5f77db52
JB		 8222013-04-08 Jan Beulich <jbeulich@suse.com>
823
824 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
825 * i386-tbl.h: Re-generate.
826
0afd1215
DM		 8272013-04-06 David S. Miller <davem@davemloft.net>
828
829 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
830 of an opcode, prefer the one with F_PREFERRED set.
831 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
832 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
833 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
834 mark existing mnenomics as aliases. Add "cc" suffix to edge
835 instructions generating condition codes, mark existing mnenomics
836 as aliases. Add "fp" prefix to VIS compare instructions, mark
837 existing mnenomics as aliases.
838
41702d50
NC		 8392013-04-03 Nick Clifton <nickc@redhat.com>
840
841 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
842 destination address by subtracting the operand from the current
843 address.
844 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
845 a positive value in the insn.
846 (extract_u16_loop): Do not negate the returned value.
847 (D16_LOOP): Add V850_INVERSE_PCREL flag.
848
849 (ceilf.sw): Remove duplicate entry.
850 (cvtf.hs): New entry.
851 (cvtf.sh): Likewise.
852 (fmaf.s): Likewise.
853 (fmsf.s): Likewise.
854 (fnmaf.s): Likewise.
855 (fnmsf.s): Likewise.
856 (maddf.s): Restrict to E3V5 architectures.
857 (msubf.s): Likewise.
858 (nmaddf.s): Likewise.
859 (nmsubf.s): Likewise.
860
55cf16e1
L		 8612013-03-27 H.J. Lu <hongjiu.lu@intel.com>
862
863 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
864 check address mode.
865 (print_insn): Pass sizeflag to get_sib.
866
51dcdd4d
NC		 8672013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
868
869 PR binutils/15068
870 * tic6x-dis.c: Add support for displaying 16-bit insns.
871
795b8e6b
NC		 8722013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
873
874 PR gas/15095
875 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
876 individual msb and lsb halves in src1 & src2 fields. Discard the
877 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
878 follow what Ti SDK does in that case as any value in the src1
879 field yields the same output with SDK disassembler.
880
314d60dd
ME		 8812013-03-12 Michael Eager <eager@eagercon.com>
882
795b8e6b 883 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 884
dad60f8e
SL		 8852013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
886
887 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
888
f5cb796a
SL		 8892013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
890
891 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
892
21fde85c
SL		 8932013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
894
895 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
896
dd5181d5
KT		 8972013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
898
899 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
900 (thumb32_opcodes): Likewise.
901 (print_insn_thumb32): Handle 'S' control char.
902
87a8d6cb
NC		 9032013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
904
905 * lm32-desc.c: Regenerate.
906
99dce992
L		 9072013-03-01 H.J. Lu <hongjiu.lu@intel.com>
908
909 * i386-reg.tbl (riz): Add RegRex64.
910 * i386-tbl.h: Regenerated.
911
e60bb1dd
YZ		 9122013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
913
914 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
915 (aarch64_feature_crc): New static.
916 (CRC): New macro.
917 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
918 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
919 * aarch64-asm-2.c: Re-generate.
920 * aarch64-dis-2.c: Ditto.
921 * aarch64-opc-2.c: Ditto.
922
c7570fcd
AM		 9232013-02-27 Alan Modra <amodra@gmail.com>
924
925 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
926 * rl78-decode.c: Regenerate.
927
151fa98f
NC		 9282013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
929
930 * rl78-decode.opc: Fix encoding of DIVWU insn.
931 * rl78-decode.c: Regenerate.
932
5c111e37
L		 9332013-02-19 H.J. Lu <hongjiu.lu@intel.com>
934
935 PR gas/15159
936 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
937
938 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
939 (cpu_flags): Add CpuSMAP.
940
941 * i386-opc.h (CpuSMAP): New.
942 (i386_cpu_flags): Add cpusmap.
943
944 * i386-opc.tbl: Add clac and stac.
945
946 * i386-init.h: Regenerated.
947 * i386-tbl.h: Likewise.
948
9d1df426
NC		 9492013-02-15 Markos Chandras <markos.chandras@imgtec.com>
950
951 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
952 which also makes the disassembler output be in little
953 endian like it should be.
954
a1ccaec9
YZ		 9552013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
956
957 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
958 fields to NULL.
959 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
960
ef068ef4 9612013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 962
963 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
964 section disassembled.
965
6fe6ded9
RE		 9662013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
967
968 * arm-dis.c: Update strht pattern.
969
0aa27725
RS		 9702013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
971
972 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
973 single-float. Disable ll, lld, sc and scd for EE. Disable the
974 trunc.w.s macro for EE.
975
36591ba1
SL		 9762013-02-06 Sandra Loosemore <sandra@codesourcery.com>
977 Andrew Jenner <andrew@codesourcery.com>
978
979 Based on patches from Altera Corporation.
980
981 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
982 nios2-opc.c.
983 * Makefile.in: Regenerated.
984 * configure.in: Add case for bfd_nios2_arch.
985 * configure: Regenerated.
986 * disassemble.c (ARCH_nios2): Define.
987 (disassembler): Add case for bfd_arch_nios2.
988 * nios2-dis.c: New file.
989 * nios2-opc.c: New file.
990
545093a4
AM		 9912013-02-04 Alan Modra <amodra@gmail.com>
992
993 * po/POTFILES.in: Regenerate.
994 * rl78-decode.c: Regenerate.
995 * rx-decode.c: Regenerate.
996
e30181a5
YZ		 9972013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
998
999 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1000 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
1001 * aarch64-asm.c (convert_xtl_to_shll): New function.
1002 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1003 calling convert_xtl_to_shll.
1004 * aarch64-dis.c (convert_shll_to_xtl): New function.
1005 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1006 calling convert_shll_to_xtl.
1007 * aarch64-gen.c: Update copyright year.
1008 * aarch64-asm-2.c: Re-generate.
1009 * aarch64-dis-2.c: Re-generate.
1010 * aarch64-opc-2.c: Re-generate.
1011
78c8d46c
NC		 10122013-01-24 Nick Clifton <nickc@redhat.com>
1013
1014 * v850-dis.c: Add support for e3v5 architecture.
1015 * v850-opc.c: Likewise.
1016
f5555712
YZ		 10172013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1018
1019 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1020 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1021 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 1022 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 1023 alignment check; change to call set_sft_amount_out_of_range_error
1024 instead of set_imm_out_of_range_error.
1025 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1026 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1027 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1028 SIMD_IMM_SFT.
1029
2f81ff92
L		 10302013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1031
1032 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1033
1034 * i386-init.h: Regenerated.
1035 * i386-tbl.h: Likewise.
1036
dd42f060
NC		 10372013-01-15 Nick Clifton <nickc@redhat.com>
1038
1039 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1040 values.
1041 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1042
a4533ed8
NC		 10432013-01-14 Will Newton <will.newton@imgtec.com>
1044
1045 * metag-dis.c (REG_WIDTH): Increase to 64.
1046
5817ffd1
PB		 10472013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1048
1049 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1050 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1051 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1052 (SH6): Update.
1053 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1054 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1055 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1056 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1057
a3c62988
NC		 10582013-01-10 Will Newton <will.newton@imgtec.com>
1059
1060 * Makefile.am: Add Meta.
1061 * configure.in: Add Meta.
1062 * disassemble.c: Add Meta support.
1063 * metag-dis.c: New file.
1064 * Makefile.in: Regenerate.
1065 * configure: Regenerate.
1066
73335eae
NC		 10672013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1068
1069 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1070 (match_opcode): Rename to cr16_match_opcode.
1071
e407c74b
NC		 10722013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1073
1074 * mips-dis.c: Add names for CP0 registers of r5900.
1075 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1076 instructions sq and lq.
1077 Add support for MIPS r5900 CPU.
1078 Add support for 128 bit MMI (Multimedia Instructions).
1079 Add support for EE instructions (Emotion Engine).
1080 Disable unsupported floating point instructions (64 bit and
1081 undefined compare operations).
1082 Enable instructions of MIPS ISA IV which are supported by r5900.
1083 Disable 64 bit co processor instructions.
1084 Disable 64 bit multiplication and division instructions.
1085 Disable instructions for co-processor 2 and 3, because these are
1086 not supported (preparation for later VU0 support (Vector Unit)).
1087 Disable cvt.w.s because this behaves like trunc.w.s and the
1088 correct execution can't be ensured on r5900.
1089 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1090 will confuse less developers and compilers.
1091
a32c3ff8
NC		 10922013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1093
fb098a1e
YZ		 1094 * aarch64-opc.c (aarch64_print_operand): Change to print
1095 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1096 in comment.
1097 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1098 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1099 OP_MOV_IMM_WIDE.
1100
11012013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1102
1103 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1104 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 1105
62658407
L		 11062013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1107
1108 * i386-gen.c (process_copyright): Update copyright year to 2013.
1109
bab4becb 11102013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 1111
bab4becb
NC		 1112 * cr16-dis.c (match_opcode,make_instruction): Remove static
1113 declaration.
1114 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1115 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 1116
bab4becb 1117For older changes see ChangeLog-2012
252b5132 1118\f
bab4becb 1119Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1120
1121Copying and distribution of this file, with or without modification,
1122are permitted in any medium without royalty provided the copyright
1123notice and this notice are preserved.
1124
252b5132 1125Local Variables:
2f6d2f85
NC		 1126mode: change-log
1127left-margin: 8
1128fill-column: 74
252b5132
RH		 1129version-control: never
1130End:
GDB Binutils - Deliverables
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