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Simplify calls to init_psymbol_list
[deliverable/binutils-gdb.git] / opcodes / ChangeLog-2014
CommitLineData
b90efa5b
AM		 12014-12-27 Anthony Green <green@moxielofic.com
2
3 * moxie-opc.c (moxie_form1_opc_info): sto/ldo are now encoded with
4 16-bit immediat values instead of 32.
5 * moxie-dis.c (print_insn_moxie): Ditto.
6
72014-12-24 Anthony Green <green@moxielogic.com>
8
9 * moxie-opc: Define mul.x and umul.x instructions. Remove
10 trailing .l from add, sub, mul, div and udiv instructions.
11
122014-12-16 Matthew Fortune <matthew.fortune@imgtec.com>
13
14 * mips-opc.c (mips_builtin_opcodes): Add JALRC alias for
15 JIALC. Remove the operand from NAL.
16
172014-12-12 Anthony Green <green@moxielogic.com>
18
19 * moxie-opc.c: Define zex instructions.
20
212014-12-06 Eric Botcazou <ebotcazou@adacore.com>
22
23 * configure.ac: Add Visium support.
24 * configure: Regenerate.
25 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add visium-dis.c and
26 visium-opc.c.
27 * Makefile.in: Regenerate.
28 * disassemble.c (ARCH_visium): Define if ARCH_all.
29 (disassembler): Deal with bfd_arch_visium if ARCH_visium.
30 * visium-dis.c: New file.
31 * visium-opc.c: Likewise.
32 * po/POTFILES.in: Regenerate.
33
342014-11-30 Alan Modra <amodra@gmail.com>
35
36 * ppc-opc.c (powerpc_opcodes): Make mftb* generate mfspr for
37 power4 and later.
38
392014-11-28 Sandra Loosemore <sandra@codesourcery.com>
40
41 * nios2-opc.c (nios2_r1_opcodes): Remove deleted attributes
42 from descriptors.
43
442014-11-28 Alan Modra <amodra@gmail.com>
45
46 * ppc-opc.c (powerpc_opcodes <mftb>): Don't deprecate for power7.
47 (TB): Delete.
48 (insert_tbr, extract_tbr): Validate tbr number.
49
502014-11-24 H.J. Lu <hongjiu.lu@intel.com>
51
52 * configure: Regenerated.
53
542014-11-17 Ilya Tocar <ilya.tocar@intel.com>
55
56 * i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb,
57 vpmultishiftqb.
58 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2.
59 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS.
60 (cpu_flags): Add CpuAVX512VBMI.
61 * i386-opc.h (enum): Add CpuAVX512VBMI.
62 (i386_cpu_flags): Add cpuavx512vbmi.
63 * i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b,
64 vpermt2b.
65 * i386-init.h: Regenerated.
66 * i386-tbl.h: Likewise.
67
682014-11-17 Ilya Tocar <ilya.tocar@intel.com>
69
70 * i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
71 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4,
72 PREFIX_EVEX_0F38B5.
73 * i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS.
74 (cpu_flags): Add CpuAVX512IFMA.
75 * i386-opc.h (enum): Add CpuAVX512IFMA.
76 (i386_cpu_flags): Add cpuavx512ifma.
77 * i386-opc.tbl: Add vpmadd52huq, vpmadd52luq.
78 * i386-init.h: Regenerated.
79 * i386-tbl.h: Likewise.
80
812014-11-17 Ilya Tocar <ilya.tocar@intel.com>
82
83 * i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7.
84 (prefix_table): Add pcommit.
85 * i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS.
86 (cpu_flags): Add CpuPCOMMIT.
87 * i386-opc.h (enum): Add CpuPCOMMIT.
88 (i386_cpu_flags): Add cpupcommit.
89 * i386-opc.tbl: Add pcommit.
90 * i386-init.h: Regenerated.
91 * i386-tbl.h: Likewise.
92
932014-11-17 Ilya Tocar <ilya.tocar@intel.com>
94
95 * i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
96 (prefix_table): Add clwb.
97 * i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
98 (cpu_flags): Add CpuCLWB.
99 * i386-opc.h (enum): Add CpuCLWB.
100 (i386_cpu_flags): Add cpuclwb.
101 * i386-opc.tbl: Add clwb.
102 * i386-init.h: Regenerated.
103 * i386-tbl.h: Likewise.
104
1052014-11-06 Sandra Loosemore <sandra@codesourcery.com>
106
107 * nios2-dis.c (nios2_find_opcode_hash): Add mach parameter.
108 (nios2_disassemble): Adjust call to nios2_find_opcode_hash.
109
1102014-11-03 Nick Clifton <nickc@redhat.com>
111
112 * po/fi.po: Updated Finnish translation.
113
1142014-10-31 Andrew Pinski <apinski@cavium.com>
115 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
116
117 * mips-dis.c (mips_arch_choices): Add octeon3.
118 * mips-opc.c (IOCT): Include INSN_OCTEON3.
119 (IOCT2): Likewise.
120 (IOCT3): New define.
121 (IVIRT): New define.
122 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
123 tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
124 IVIRT instructions.
125 Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
126 operand for IOCT3.
127
1282014-10-29 Nick Clifton <nickc@redhat.com>
129
130 * po/de.po: Updated German translation.
131
1322014-10-23 Sandra Loosemore <sandra@codesourcery.com>
133
134 * nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
135 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes. Use new
136 MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers. Add
137 size and format initializers. Merge 'b' arguments into 'j'.
138 (NIOS2_NUM_OPCODES): Adjust definition.
139 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
140 (nios2_opcodes): Adjust.
141 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
142 * nios2-dis.c (INSNLEN): Update comment.
143 (nios2_hash_init, nios2_hash): Delete.
144 (OPCODE_HASH_SIZE): New.
145 (nios2_r1_extract_opcode): New.
146 (nios2_disassembler_state): New.
147 (nios2_r1_disassembler_state): New.
148 (nios2_init_opcode_hash): Add state parameter. Adjust to use it.
149 (nios2_find_opcode_hash): Use state object.
150 (bad_opcode): New.
151 (nios2_print_insn_arg): Add op parameter. Use it to access
152 format. Remove 'b' case.
153 (nios2_disassemble): Remove special case for nop. Remove
154 hard-coded instruction size.
155
1562014-10-21 Jan Beulich <jbeulich@suse.com>
157
158 * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
159
1602014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
161
162 * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
163 entries.
164 Annotate several instructions with the HWCAP2_VIS3B hwcap.
165
1662014-10-15 Tristan Gingold <gingold@adacore.com>
167
168 * configure: Regenerate.
169
1702014-10-09 Jose E. Marchesi &lt;jose.marchesi@oracle.com&gt;
171
172 * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
173 `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
174 Annotate table with HWCAP2 bits.
175 Add instructions xmontmul, xmontsqr, xmpmul.
176 (sparc-opcodes): Add the `mwait', `wr r,r,%mwait', `wr
177 r,i,%mwait' and `rd %mwait,r' instructions.
178 Add rd/wr instructions for accessing the %mcdper ancillary state
179 register.
180 (sparc-opcodes): Add sparc5/vis4.0 instructions:
181 subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
182 fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
183 fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
184 fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
185 fpsubus16, and faligndatai.
186 * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
187 ancillary state register to the table.
188 (print_insn_sparc): Handle the %mcdper ancillary state register.
189 (print_insn_sparc): Handle new operand type '}'.
190
1912014-09-22 H.J. Lu <hongjiu.lu@intel.com>
192
193 * i386-dis.c (MOD_0F20): Removed.
194 (MOD_0F21): Likewise.
195 (MOD_0F22): Likewise.
196 (MOD_0F23): Likewise.
197 (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
198 MOD_0F23 with "movZ".
199 (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
200 (OP_R): Check mod/rm byte and call OP_E_register.
201
2022014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
203
204 * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
205 keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
206 keyword_aridxi): Add audio ISA extension.
207 (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
208 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
209 keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
210 for nds32-dis.c using.
211 (build_opcode_syntax): Remove dead code.
212 (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
213 parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
214 parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
215 operand parser.
216 * nds32-asm.h: Declare.
217 * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
218 decoding by switch.
219
2202014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
221 Matthew Fortune <matthew.fortune@imgtec.com>
222
223 * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
224 mips64r6.
225 (parse_mips_dis_option): Allow MSA and virtualization support for
226 mips64r6.
227 (mips_print_arg_state): Add fields dest_regno and seen_dest.
228 (mips_seen_register): New function.
229 (print_insn_arg): Refactored code to use mips_seen_register
230 function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
231 OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
232 the register rather than aborting.
233 (print_insn_args): Add length argument. Add code to correctly
234 calculate the instruction address for pc relative instructions.
235 (validate_insn_args): New static function.
236 (print_insn_mips): Prevent jalx disassembling for r6. Use
237 validate_insn_args.
238 (print_insn_micromips): Use validate_insn_args.
239 all the arguments are valid.
240 * mips-formats.h (PREV_CHECK): New define.
241 * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
242 -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
243 (RD_pc): New define.
244 (FS): New define.
245 (I37): New define.
246 (I69): New define.
247 (mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
248 MIPS R6 instructions from MIPS R2 instructions.
249
2502014-09-10 H.J. Lu <hongjiu.lu@intel.com>
251
252 * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
253 (putop): Handle "%LP".
254
2552014-09-03 Jiong Wang <jiong.wang@arm.com>
256
257 * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
258 * aarch64-dis-2.c: Update auto-generated file.
259
2602014-09-03 Jiong Wang <jiong.wang@arm.com>
261
262 * aarch64-tbl.h (QL_R4NIL): New qualifiers.
263 (aarch64_feature_lse): New feature added.
264 (LSE): New Added.
265 (aarch64_opcode_table): New LSE instructions added. Improve
266 descriptions for ldarb/ldarh/ldar.
267 (aarch64_opcode_table): Describe PAIRREG.
268 * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
269 * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
270 (aarch64_print_operand): Recognize PAIRREG.
271 (operand_general_constraint_met_p): Check reg pair constraints for CASP
272 instructions.
273 * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
274 (do_special_decoding): Recognize F_LSE_SZ.
275 * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
276
2772014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
278
279 * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
280 (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
281 "sdbbp", "syscall" and "wait".
282
2832014-08-21 Nathan Sidwell <nathan@codesourcery.com>
284 Maciej W. Rozycki <macro@codesourcery.com>
285
286 * arm-dis.c (print_arm_address): Negate the GPR-relative offset
287 returned if the U bit is set.
288
2892014-08-21 Maciej W. Rozycki <macro@codesourcery.com>
290
291 * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
292 48-bit "li" encoding.
293
2942014-08-19 Andreas Arnez <arnez@linux.vnet.ibm.com>
295
296 * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
297 (s390_print_insn_with_opcode, opcode_mask_more_specific): New
298 static functions, code was moved from...
299 (print_insn_s390): ...here.
300 (s390_extract_operand): Adjust comment. Change type of first
301 parameter from 'unsigned char *' to 'const bfd_byte *'.
302 (union operand_value): New.
303 (s390_extract_operand): Change return type to union operand_value.
304 Also avoid integer overflow in sign-extension.
305 (s390_print_insn_with_opcode): Adjust to changed return value from
306 s390_extract_operand(). Change "%i" printf format to "%u" for
307 unsigned values.
308 (init_disasm): Simplify initialization of opc_index[]. This also
309 fixes an access after the last element of s390_opcodes[].
310 (print_insn_s390): Simplify the opcode search loop.
311 Check architecture mask against all searched opcodes, not just the
312 first matching one.
313 (s390_print_insn_with_opcode): Drop function pointer dereferences
314 without effect.
315 (print_insn_s390): Likewise.
316 (s390_insn_length): Simplify formula for return value.
317 (s390_print_insn_with_opcode): Avoid special handling for the
318 separator before the first operand. Use new local variable
319 'flags' in place of 'operand->flags'.
320
3212014-08-14 Mike Frysinger <vapier@gentoo.org>
322
323 * bfin-dis.c (struct private): Change int's to bfd_boolean's.
324 (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
325 decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
326 Change assignment of 1 to priv->comment to TRUE.
327 (print_insn_bfin): Change legal to a bfd_boolean. Change
328 assignment of 0/1 with priv comment and parallel and legal
329 to FALSE/TRUE.
330
3312014-08-14 Mike Frysinger <vapier@gentoo.org>
332
333 * bfin-dis.c (OUT): Define.
334 (decode_CC2stat_0): Declare new op_names array.
335 Replace multiple if statements with a single one.
336
3372014-08-14 Mike Frysinger <vapier@gentoo.org>
338
339 * bfin-dis.c (struct private): Add iw0.
340 (_print_insn_bfin): Assign iw0 to priv.iw0.
341 (print_insn_bfin): Drop ifetch and use priv.iw0.
342
3432014-08-13 Mike Frysinger <vapier@gentoo.org>
344
345 * bfin-dis.c (comment, parallel): Move from global scope ...
346 (struct private): ... to this new struct.
347 (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
348 decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
349 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
350 decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
351 decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
352 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
353 decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
354 print_insn_bfin): Declare private struct. Use priv's comment and
355 parallel members.
356
3572014-08-13 Mike Frysinger <vapier@gentoo.org>
358
359 * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
360 (_print_insn_bfin): Add check for unaligned pc.
361
3622014-08-13 Mike Frysinger <vapier@gentoo.org>
363
364 * bfin-dis.c (ifetch): New function.
365 (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
366 -1 when it errors.
367
3682014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
369
370 * micromips-opc.c (COD): Rename throughout to...
371 (CM): New define, update to use INSN_COPROC_MOVE.
372 (LCD): Rename throughout to...
373 (LC): New define, update to use INSN_LOAD_COPROC.
374 * mips-opc.c: Likewise.
375
3762014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
377
378 * micromips-opc.c (COD, LCD) New macros.
379 (cfc1, ctc1): Remove FP_S attribute.
380 (dmfc1, mfc1, mfhc1): Add LCD attribute.
381 (dmtc1, mtc1, mthc1): Add COD attribute.
382 * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
383
3842014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
385 Alexander Ivchenko <alexander.ivchenko@intel.com>
386 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
387 Sergey Lega <sergey.s.lega@intel.com>
388 Anna Tikhonova <anna.tikhonova@intel.com>
389 Ilya Tocar <ilya.tocar@intel.com>
390 Andrey Turetskiy <andrey.turetskiy@intel.com>
391 Ilya Verbin <ilya.verbin@intel.com>
392 Kirill Yukhin <kirill.yukhin@intel.com>
393 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
394
395 * i386-dis-evex.h: Updated.
396 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
397 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
398 PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
399 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
400 PREFIX_EVEX_0F3A67.
401 (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
402 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
403 (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
404 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
405 EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
406 EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
407 EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
408 EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
409 EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
410 (prefix_table): Add entries for new instructions.
411 (vex_len_table): Ditto.
412 (vex_w_table): Ditto.
413 (OP_E_memory): Update xmmq_mode handling.
414 * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
415 (cpu_flags): Add CpuAVX512DQ.
416 * i386-init.h: Regenerared.
417 * i386-opc.h (CpuAVX512DQ): New.
418 (i386_cpu_flags): Add cpuavx512dq.
419 * i386-opc.tbl: Add AVX512DQ instructions.
420 * i386-tbl.h: Regenerate.
421
4222014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
423 Alexander Ivchenko <alexander.ivchenko@intel.com>
424 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
425 Sergey Lega <sergey.s.lega@intel.com>
426 Anna Tikhonova <anna.tikhonova@intel.com>
427 Ilya Tocar <ilya.tocar@intel.com>
428 Andrey Turetskiy <andrey.turetskiy@intel.com>
429 Ilya Verbin <ilya.verbin@intel.com>
430 Kirill Yukhin <kirill.yukhin@intel.com>
431 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
432
433 * i386-dis-evex.h: Add new instructions (prefixes bellow).
434 * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
435 (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
436 (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
437 PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
438 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
439 PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
440 PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
441 PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
442 PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
443 PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
444 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
445 PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
446 PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
447 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
448 PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
449 PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
450 PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
451 PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
452 PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
453 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
454 PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
455 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
456 (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
457 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
458 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
459 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
460 VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
461 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
462 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
463 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
464 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
465 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
466 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
467 (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
468 EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
469 EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
470 EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
471 EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
472 EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
473 EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
474 (prefix_table): Add entries for new instructions.
475 (vex_table) : Ditto.
476 (vex_len_table): Ditto.
477 (vex_w_table): Ditto.
478 (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
479 mask_bd_mode handling.
480 (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
481 handling.
482 (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
483 handling.
484 (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
485 (OP_EX): Add dqw_swap_mode handling.
486 (OP_VEX): Add mask_bd_mode handling.
487 (OP_Mask): Add mask_bd_mode handling.
488 * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
489 (cpu_flags): Add CpuAVX512BW.
490 * i386-init.h: Regenerated.
491 * i386-opc.h (CpuAVX512BW): New.
492 (i386_cpu_flags): Add cpuavx512bw.
493 * i386-opc.tbl: Add AVX512BW instructions.
494 * i386-tbl.h: Regenerate.
495
4962014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
497 Alexander Ivchenko <alexander.ivchenko@intel.com>
498 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
499 Sergey Lega <sergey.s.lega@intel.com>
500 Anna Tikhonova <anna.tikhonova@intel.com>
501 Ilya Tocar <ilya.tocar@intel.com>
502 Andrey Turetskiy <andrey.turetskiy@intel.com>
503 Ilya Verbin <ilya.verbin@intel.com>
504 Kirill Yukhin <kirill.yukhin@intel.com>
505 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
506
507 * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
508 * i386-tbl.h: Regenerate.
509
5102014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
511 Alexander Ivchenko <alexander.ivchenko@intel.com>
512 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
513 Sergey Lega <sergey.s.lega@intel.com>
514 Anna Tikhonova <anna.tikhonova@intel.com>
515 Ilya Tocar <ilya.tocar@intel.com>
516 Andrey Turetskiy <andrey.turetskiy@intel.com>
517 Ilya Verbin <ilya.verbin@intel.com>
518 Kirill Yukhin <kirill.yukhin@intel.com>
519 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
520
521 * i386-dis.c (intel_operand_size): Support 128/256 length in
522 vex_vsib_q_w_dq_mode.
523 (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
524 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
525 (cpu_flags): Add CpuAVX512VL.
526 * i386-init.h: Regenerated.
527 * i386-opc.h (CpuAVX512VL): New.
528 (i386_cpu_flags): Add cpuavx512vl.
529 (BROADCAST_1TO4, BROADCAST_1TO2): Define.
530 * i386-opc.tbl: Add AVX512VL instructions.
531 * i386-tbl.h: Regenerate.
532
5332014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
534
535 * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
536 * or1k-opinst.c: Regenerate.
537
5382014-07-08 Ilya Tocar <ilya.tocar@intel.com>
539
540 * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
541 (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
542
5432014-07-04 Alan Modra <amodra@gmail.com>
544
545 * configure.ac: Rename from configure.in.
546 * Makefile.in: Regenerate.
547 * config.in: Regenerate.
548
5492014-07-04 Alan Modra <amodra@gmail.com>
550
551 * configure.in: Include bfd/version.m4.
552 (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
553 (BFD_VERSION): Delete.
554 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
555 * configure: Regenerate.
556 * Makefile.in: Regenerate.
557
5582014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
559 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
560 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
561 Soundararajan <Sounderarajan.D@atmel.com>
562
563 * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
564 (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
565 machine is not avrtiny.
566
5672014-06-26 Philippe De Muyter <phdm@macqel.be>
568
569 * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
570 constants.
571
5722014-06-12 Alan Modra <amodra@gmail.com>
573
574 * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
575 * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
576
5772014-06-10 H.J. Lu <hongjiu.lu@intel.com>
578
579 * i386-dis.c (fwait_prefix): New.
580 (ckprefix): Set fwait_prefix.
581 (print_insn): Properly print prefixes before fwait.
582
5832014-06-07 Alan Modra <amodra@gmail.com>
584
585 * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
586
5872014-06-05 Joel Brobecker <brobecker@adacore.com>
588
589 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
590 bfd's development.sh.
591 * Makefile.in, configure: Regenerate.
592
5932014-06-03 Nick Clifton <nickc@redhat.com>
594
595 * msp430-dis.c (msp430_doubleoperand): Use extension_word to
596 decide when extended addressing is being used.
597
5982014-06-02 Eric Botcazou <ebotcazou@adacore.com>
599
600 * sparc-opc.c (cas): Disable for LEON.
601 (casl): Likewise.
602
6032014-05-20 Alan Modra <amodra@gmail.com>
604
605 * m68k-dis.c: Don't include setjmp.h.
606
6072014-05-09 H.J. Lu <hongjiu.lu@intel.com>
608
609 * i386-dis.c (ADDR16_PREFIX): Removed.
610 (ADDR32_PREFIX): Likewise.
611 (DATA16_PREFIX): Likewise.
612 (DATA32_PREFIX): Likewise.
613 (prefix_name): Updated.
614 (print_insn): Simplify data and address size prefixes processing.
615
6162014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
617
618 * or1k-desc.c: Regenerated.
619 * or1k-desc.h: Likewise.
620 * or1k-opc.c: Likewise.
621 * or1k-opc.h: Likewise.
622 * or1k-opinst.c: Likewise.
623
6242014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
625
626 * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
627 (I34): New define.
628 (I36): New define.
629 (I66): New define.
630 (I68): New define.
631 * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
632 mips64r5.
633 (parse_mips_dis_option): Update MSA and virtualization support to
634 allow mips64r3 and mips64r5.
635
6362014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
637
638 * mips-opc.c (G3): Remove I4.
639
6402014-05-05 H.J. Lu <hongjiu.lu@intel.com>
641
642 PR binutils/16893
643 * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
644 (end_codep): Likewise.
645 (mandatory_prefix): Likewise.
646 (active_seg_prefix): Likewise.
647 (ckprefix): Set active_seg_prefix to the active segment register
648 prefix.
649 (seg_prefix): Removed.
650 (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
651 for prefix index. Ignore the index if it is invalid and the
652 mandatory prefix isn't required.
653 (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
654 mandatory. Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
655 in used_prefixes here. Don't print unused prefixes. Check
656 active_seg_prefix for the active segment register prefix.
657 Restore the DFLAG bit in sizeflag if the data size prefix is
658 unused. Check the unused mandatory PREFIX_XXX prefixes
659 (append_seg): Only print the segment register which gets used.
660 (OP_E_memory): Check active_seg_prefix for the segment register
661 prefix.
662 (OP_OFF): Likewise.
663 (OP_OFF64): Likewise.
664 (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
665
6662014-05-02 H.J. Lu <hongjiu.lu@intel.com>
667
668 PR binutils/16886
669 * config.in: Regenerated.
670 * configure: Likewise.
671 * configure.in: Check if sigsetjmp is available.
672 * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
673 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
674 (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
675 * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
676 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
677 (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
678 * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
679 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
680 (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
681 * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
682 (OPCODES_SIGSETJMP): Likewise.
683 (OPCODES_SIGLONGJMP): Likewise.
684 * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
685 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
686 (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
687 * xtensa-dis.c (dis_private): Replace jmp_buf with
688 OPCODES_SIGJMP_BUF.
689 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
690 (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
691 * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
692 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
693 (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
694
6952014-05-01 H.J. Lu <hongjiu.lu@intel.com>
696
697 PR binutils/16891
698 * i386-dis.c (print_insn): Handle prefixes before fwait.
699
7002014-04-26 Alan Modra <amodra@gmail.com>
701
702 * po/POTFILES.in: Regenerate.
703
7042014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
705
706 * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
707 to allow the MIPS XPA ASE.
708 (parse_mips_dis_option): Process the -Mxpa option.
709 * mips-opc.c (XPA): New define.
710 (mips_builtin_opcodes): Add MIPS XPA instructions and move the
711 locations of the ctc0 and cfc0 instructions.
712
7132014-04-22 Christian Svensson <blue@cmd.nu>
714
715 * Makefile.am: Remove openrisc and or32 support. Add support for or1k.
716 * configure.in: Likewise.
717 * disassemble.c: Likewise.
718 * or1k-asm.c: New file.
719 * or1k-desc.c: New file.
720 * or1k-desc.h: New file.
721 * or1k-dis.c: New file.
722 * or1k-ibld.c: New file.
723 * or1k-opc.c: New file.
724 * or1k-opc.h: New file.
725 * or1k-opinst.c: New file.
726 * Makefile.in: Regenerate.
727 * configure: Regenerate.
728 * openrisc-asm.c: Delete.
729 * openrisc-desc.c: Delete.
730 * openrisc-desc.h: Delete.
731 * openrisc-dis.c: Delete.
732 * openrisc-ibld.c: Delete.
733 * openrisc-opc.c: Delete.
734 * openrisc-opc.h: Delete.
735 * or32-dis.c: Delete.
736 * or32-opc.c: Delete.
737
7382014-04-04 Ilya Tocar <ilya.tocar@intel.com>
739
740 * i386-dis.c (rm_table): Add encls, enclu.
741 * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
742 (cpu_flags): Add CpuSE1.
743 * i386-opc.h (enum): Add CpuSE1.
744 (i386_cpu_flags): Add cpuse1.
745 * i386-opc.tbl: Add encls, enclu.
746 * i386-init.h: Regenerated.
747 * i386-tbl.h: Likewise.
748
7492014-04-02 Anthony Green <green@moxielogic.com>
750
751 * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
752 instructions, sex.b and sex.s.
753
7542014-03-26 Jiong Wang <jiong.wang@arm.com>
755
756 * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
757 instructions.
758
7592014-03-20 Ilya Tocar <ilya.tocar@intel.com>
760
761 * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
762 vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
763 vscatterqps.
764 * i386-tbl.h: Regenerate.
765
7662014-03-19 Jose E. Marchesi <jose.marchesi@oracle.com>
767
768 * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
769 %hstick_enable added.
770
7712014-03-19 Nick Clifton <nickc@redhat.com>
772
773 * rx-decode.opc (bwl): Allow for bogus instructions with a size
774 field of 3.
775 (sbwl, ubwl, SCALE): Likewise.
776 * rx-decode.c: Regenerate.
777
7782014-03-12 Alan Modra <amodra@gmail.com>
779
780 * Makefile.in: Regenerate.
781
7822014-03-05 Alan Modra <amodra@gmail.com>
783
784 Update copyright years.
785
7862014-03-04 Heiher <r@hev.cc>
787
788 * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
789
7902014-03-04 Richard Sandiford <rdsandiford@googlemail.com>
791
792 * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
793 so that they come after the Loongson extensions.
794
7952014-03-03 Alan Modra <amodra@gmail.com>
796
797 * i386-gen.c (process_copyright): Emit copyright notice on one line.
798
7992014-02-28 Alan Modra <amodra@gmail.com>
800
801 * msp430-decode.c: Regenerate.
802
8032014-02-27 Jiong Wang <jiong.wang@arm.com>
804
805 * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
806 FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
807
8082014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
809
810 * aarch64-opc.c (print_register_offset_address): Call
811 get_int_reg_name to prepare the register name.
812
8132014-02-25 Ilya Tocar <ilya.tocar@intel.com>
814
815 * i386-opc.tbl: Remove wrong variant of vcvtps2ph
816 * i386-tbl.h: Regenerate.
817
8182014-02-20 Ilya Tocar <ilya.tocar@intel.com>
819
820 * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
821 (cpu_flags): Add CpuPREFETCHWT1.
822 * i386-init.h: Regenerate.
823 * i386-opc.h (CpuPREFETCHWT1): New.
824 (i386_cpu_flags): Add cpuprefetchwt1.
825 * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
826 * i386-tbl.h: Regenerate.
827
8282014-02-20 Ilya Tocar <ilya.tocar@intel.com>
829
830 * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
831 to CpuAVX512F.
832 * i386-tbl.h: Regenerate.
833
8342014-02-19 H.J. Lu <hongjiu.lu@intel.com>
835
836 * i386-gen.c (output_cpu_flags): Don't output trailing space.
837 (output_opcode_modifier): Likewise.
838 (output_operand_type): Likewise.
839 * i386-init.h: Regenerated.
840 * i386-tbl.h: Likewise.
841
8422014-02-12 Ilya Tocar <ilya.tocar@intel.com>
843
844 * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
845 MOD_0FC7_REG_5.
846 (PREFIX enum): Add PREFIX_0FAE_REG_7.
847 (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
848 (prefix_table): Add clflusopt.
849 (mod_table): Add xrstors, xsavec, xsaves.
850 * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
851 CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
852 (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
853 * i386-init.h: Regenerate.
854 * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
855 xsaves64, xsavec, xsavec64.
856 * i386-tbl.h: Regenerate.
857
8582014-02-10 Alan Modra <amodra@gmail.com>
859
860 * po/POTFILES.in: Regenerate.
861 * po/opcodes.pot: Regenerate.
862
8632014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
864 Jan Beulich <jbeulich@suse.com>
865
866 PR binutils/16490
867 * i386-dis.c (OP_E_memory): Fix shift computation for
868 vex_vsib_q_w_dq_mode.
869
8702014-01-09 Bradley Nelson <bradnelson@google.com>
871 Roland McGrath <mcgrathr@google.com>
872
873 * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
874 last_rex_prefix is -1.
875
8762014-01-08 H.J. Lu <hongjiu.lu@intel.com>
877
878 * i386-gen.c (process_copyright): Update copyright year to 2014.
879
8802014-01-03 Maciej W. Rozycki <macro@codesourcery.com>
881
882 * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
883
884For older changes see ChangeLog-2013
885\f
886Copyright (C) 2014 Free Software Foundation, Inc.
887
888Copying and distribution of this file, with or without modification,
889are permitted in any medium without royalty provided the copyright
890notice and this notice are preserved.
891
892Local Variables:
893mode: change-log
894left-margin: 8
895fill-column: 74
896version-control: never
897End:
GDB Binutils - Deliverables
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