Commit | Line | Data |
---|---|---|
a06ea964 | 1 | /* aarch64-dis.c -- AArch64 disassembler. |
b3adc24a | 2 | Copyright (C) 2009-2020 Free Software Foundation, Inc. |
a06ea964 NC |
3 | Contributed by ARM Ltd. |
4 | ||
5 | This file is part of the GNU opcodes library. | |
6 | ||
7 | This library is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11 | ||
12 | It is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; see the file COPYING3. If not, | |
19 | see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "sysdep.h" | |
22 | #include "bfd_stdint.h" | |
6394c606 | 23 | #include "disassemble.h" |
a06ea964 NC |
24 | #include "libiberty.h" |
25 | #include "opintl.h" | |
26 | #include "aarch64-dis.h" | |
a06ea964 | 27 | #include "elf-bfd.h" |
a06ea964 | 28 | |
a06ea964 NC |
29 | #define INSNLEN 4 |
30 | ||
31 | /* Cached mapping symbol state. */ | |
32 | enum map_type | |
33 | { | |
34 | MAP_INSN, | |
35 | MAP_DATA | |
36 | }; | |
37 | ||
38 | static enum map_type last_type; | |
39 | static int last_mapping_sym = -1; | |
53b2f36b | 40 | static bfd_vma last_stop_offset = 0; |
a06ea964 NC |
41 | static bfd_vma last_mapping_addr = 0; |
42 | ||
43 | /* Other options */ | |
44 | static int no_aliases = 0; /* If set disassemble as most general inst. */ | |
7d02540a TC |
45 | \fstatic int no_notes = 1; /* If set do not print disassemble notes in the |
46 | output as comments. */ | |
a06ea964 | 47 | |
7e84b55d | 48 | /* Currently active instruction sequence. */ |
bde90be2 | 49 | static aarch64_instr_sequence insn_sequence; |
7e84b55d | 50 | |
a06ea964 NC |
51 | static void |
52 | set_default_aarch64_dis_options (struct disassemble_info *info ATTRIBUTE_UNUSED) | |
53 | { | |
54 | } | |
55 | ||
56 | static void | |
57 | parse_aarch64_dis_option (const char *option, unsigned int len ATTRIBUTE_UNUSED) | |
58 | { | |
59 | /* Try to match options that are simple flags */ | |
60 | if (CONST_STRNEQ (option, "no-aliases")) | |
61 | { | |
62 | no_aliases = 1; | |
63 | return; | |
64 | } | |
65 | ||
66 | if (CONST_STRNEQ (option, "aliases")) | |
67 | { | |
68 | no_aliases = 0; | |
69 | return; | |
70 | } | |
71 | ||
7d02540a TC |
72 | if (CONST_STRNEQ (option, "no-notes")) |
73 | { | |
74 | no_notes = 1; | |
75 | return; | |
76 | } | |
77 | ||
78 | if (CONST_STRNEQ (option, "notes")) | |
79 | { | |
80 | no_notes = 0; | |
81 | return; | |
82 | } | |
83 | ||
a06ea964 NC |
84 | #ifdef DEBUG_AARCH64 |
85 | if (CONST_STRNEQ (option, "debug_dump")) | |
86 | { | |
87 | debug_dump = 1; | |
88 | return; | |
89 | } | |
90 | #endif /* DEBUG_AARCH64 */ | |
91 | ||
92 | /* Invalid option. */ | |
a6743a54 | 93 | opcodes_error_handler (_("unrecognised disassembler option: %s"), option); |
a06ea964 NC |
94 | } |
95 | ||
96 | static void | |
97 | parse_aarch64_dis_options (const char *options) | |
98 | { | |
99 | const char *option_end; | |
100 | ||
101 | if (options == NULL) | |
102 | return; | |
103 | ||
104 | while (*options != '\0') | |
105 | { | |
106 | /* Skip empty options. */ | |
107 | if (*options == ',') | |
108 | { | |
109 | options++; | |
110 | continue; | |
111 | } | |
112 | ||
113 | /* We know that *options is neither NUL or a comma. */ | |
114 | option_end = options + 1; | |
115 | while (*option_end != ',' && *option_end != '\0') | |
116 | option_end++; | |
117 | ||
118 | parse_aarch64_dis_option (options, option_end - options); | |
119 | ||
120 | /* Go on to the next one. If option_end points to a comma, it | |
121 | will be skipped above. */ | |
122 | options = option_end; | |
123 | } | |
124 | } | |
125 | \f | |
126 | /* Functions doing the instruction disassembling. */ | |
127 | ||
128 | /* The unnamed arguments consist of the number of fields and information about | |
129 | these fields where the VALUE will be extracted from CODE and returned. | |
130 | MASK can be zero or the base mask of the opcode. | |
131 | ||
132 | N.B. the fields are required to be in such an order than the most signficant | |
133 | field for VALUE comes the first, e.g. the <index> in | |
134 | SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>] | |
9aff4b7a | 135 | is encoded in H:L:M in some cases, the fields H:L:M should be passed in |
a06ea964 NC |
136 | the order of H, L, M. */ |
137 | ||
c0890d26 | 138 | aarch64_insn |
a06ea964 NC |
139 | extract_fields (aarch64_insn code, aarch64_insn mask, ...) |
140 | { | |
141 | uint32_t num; | |
142 | const aarch64_field *field; | |
143 | enum aarch64_field_kind kind; | |
144 | va_list va; | |
145 | ||
146 | va_start (va, mask); | |
147 | num = va_arg (va, uint32_t); | |
148 | assert (num <= 5); | |
149 | aarch64_insn value = 0x0; | |
150 | while (num--) | |
151 | { | |
152 | kind = va_arg (va, enum aarch64_field_kind); | |
153 | field = &fields[kind]; | |
154 | value <<= field->width; | |
155 | value |= extract_field (kind, code, mask); | |
156 | } | |
157 | return value; | |
158 | } | |
159 | ||
b5464a68 RS |
160 | /* Extract the value of all fields in SELF->fields from instruction CODE. |
161 | The least significant bit comes from the final field. */ | |
162 | ||
163 | static aarch64_insn | |
164 | extract_all_fields (const aarch64_operand *self, aarch64_insn code) | |
165 | { | |
166 | aarch64_insn value; | |
167 | unsigned int i; | |
168 | enum aarch64_field_kind kind; | |
169 | ||
170 | value = 0; | |
171 | for (i = 0; i < ARRAY_SIZE (self->fields) && self->fields[i] != FLD_NIL; ++i) | |
172 | { | |
173 | kind = self->fields[i]; | |
174 | value <<= fields[kind].width; | |
175 | value |= extract_field (kind, code, 0); | |
176 | } | |
177 | return value; | |
178 | } | |
179 | ||
a06ea964 | 180 | /* Sign-extend bit I of VALUE. */ |
f81e7e2d | 181 | static inline uint64_t |
a06ea964 NC |
182 | sign_extend (aarch64_insn value, unsigned i) |
183 | { | |
f81e7e2d | 184 | uint64_t ret, sign; |
a06ea964 NC |
185 | |
186 | assert (i < 32); | |
f81e7e2d AM |
187 | ret = value; |
188 | sign = (uint64_t) 1 << i; | |
189 | return ((ret & (sign + sign - 1)) ^ sign) - sign; | |
a06ea964 NC |
190 | } |
191 | ||
192 | /* N.B. the following inline helpfer functions create a dependency on the | |
193 | order of operand qualifier enumerators. */ | |
194 | ||
195 | /* Given VALUE, return qualifier for a general purpose register. */ | |
196 | static inline enum aarch64_opnd_qualifier | |
197 | get_greg_qualifier_from_value (aarch64_insn value) | |
198 | { | |
199 | enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_W + value; | |
200 | assert (value <= 0x1 | |
201 | && aarch64_get_qualifier_standard_value (qualifier) == value); | |
202 | return qualifier; | |
203 | } | |
204 | ||
3067d3b9 MW |
205 | /* Given VALUE, return qualifier for a vector register. This does not support |
206 | decoding instructions that accept the 2H vector type. */ | |
207 | ||
a06ea964 NC |
208 | static inline enum aarch64_opnd_qualifier |
209 | get_vreg_qualifier_from_value (aarch64_insn value) | |
210 | { | |
211 | enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_V_8B + value; | |
212 | ||
3067d3b9 MW |
213 | /* Instructions using vector type 2H should not call this function. Skip over |
214 | the 2H qualifier. */ | |
215 | if (qualifier >= AARCH64_OPND_QLF_V_2H) | |
216 | qualifier += 1; | |
217 | ||
a06ea964 NC |
218 | assert (value <= 0x8 |
219 | && aarch64_get_qualifier_standard_value (qualifier) == value); | |
220 | return qualifier; | |
221 | } | |
222 | ||
223 | /* Given VALUE, return qualifier for an FP or AdvSIMD scalar register. */ | |
224 | static inline enum aarch64_opnd_qualifier | |
225 | get_sreg_qualifier_from_value (aarch64_insn value) | |
226 | { | |
227 | enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_S_B + value; | |
228 | ||
229 | assert (value <= 0x4 | |
230 | && aarch64_get_qualifier_standard_value (qualifier) == value); | |
231 | return qualifier; | |
232 | } | |
233 | ||
234 | /* Given the instruction in *INST which is probably half way through the | |
235 | decoding and our caller wants to know the expected qualifier for operand | |
236 | I. Return such a qualifier if we can establish it; otherwise return | |
237 | AARCH64_OPND_QLF_NIL. */ | |
238 | ||
239 | static aarch64_opnd_qualifier_t | |
240 | get_expected_qualifier (const aarch64_inst *inst, int i) | |
241 | { | |
242 | aarch64_opnd_qualifier_seq_t qualifiers; | |
243 | /* Should not be called if the qualifier is known. */ | |
244 | assert (inst->operands[i].qualifier == AARCH64_OPND_QLF_NIL); | |
245 | if (aarch64_find_best_match (inst, inst->opcode->qualifiers_list, | |
246 | i, qualifiers)) | |
247 | return qualifiers[i]; | |
248 | else | |
249 | return AARCH64_OPND_QLF_NIL; | |
250 | } | |
251 | ||
252 | /* Operand extractors. */ | |
253 | ||
c2e5c986 SD |
254 | bfd_boolean |
255 | aarch64_ext_none (const aarch64_operand *self ATTRIBUTE_UNUSED, | |
256 | aarch64_opnd_info *info ATTRIBUTE_UNUSED, | |
257 | const aarch64_insn code ATTRIBUTE_UNUSED, | |
258 | const aarch64_inst *inst ATTRIBUTE_UNUSED, | |
259 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
260 | { | |
261 | return TRUE; | |
262 | } | |
263 | ||
561a72d4 | 264 | bfd_boolean |
a06ea964 NC |
265 | aarch64_ext_regno (const aarch64_operand *self, aarch64_opnd_info *info, |
266 | const aarch64_insn code, | |
561a72d4 TC |
267 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
268 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
269 | { |
270 | info->reg.regno = extract_field (self->fields[0], code, 0); | |
561a72d4 | 271 | return TRUE; |
a06ea964 NC |
272 | } |
273 | ||
561a72d4 | 274 | bfd_boolean |
ee804238 JW |
275 | aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, |
276 | const aarch64_insn code ATTRIBUTE_UNUSED, | |
561a72d4 TC |
277 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
278 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
ee804238 JW |
279 | { |
280 | assert (info->idx == 1 | |
281 | || info->idx ==3); | |
282 | info->reg.regno = inst->operands[info->idx - 1].reg.regno + 1; | |
561a72d4 | 283 | return TRUE; |
ee804238 JW |
284 | } |
285 | ||
a06ea964 | 286 | /* e.g. IC <ic_op>{, <Xt>}. */ |
561a72d4 | 287 | bfd_boolean |
a06ea964 NC |
288 | aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info, |
289 | const aarch64_insn code, | |
561a72d4 TC |
290 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
291 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
292 | { |
293 | info->reg.regno = extract_field (self->fields[0], code, 0); | |
294 | assert (info->idx == 1 | |
295 | && (aarch64_get_operand_class (inst->operands[0].type) | |
296 | == AARCH64_OPND_CLASS_SYSTEM)); | |
297 | /* This will make the constraint checking happy and more importantly will | |
298 | help the disassembler determine whether this operand is optional or | |
299 | not. */ | |
ea2deeec | 300 | info->present = aarch64_sys_ins_reg_has_xt (inst->operands[0].sysins_op); |
a06ea964 | 301 | |
561a72d4 | 302 | return TRUE; |
a06ea964 NC |
303 | } |
304 | ||
305 | /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */ | |
561a72d4 | 306 | bfd_boolean |
a06ea964 NC |
307 | aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, |
308 | const aarch64_insn code, | |
561a72d4 TC |
309 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
310 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
311 | { |
312 | /* regno */ | |
313 | info->reglane.regno = extract_field (self->fields[0], code, | |
314 | inst->opcode->mask); | |
315 | ||
316 | /* Index and/or type. */ | |
317 | if (inst->opcode->iclass == asisdone | |
318 | || inst->opcode->iclass == asimdins) | |
319 | { | |
320 | if (info->type == AARCH64_OPND_En | |
321 | && inst->opcode->operands[0] == AARCH64_OPND_Ed) | |
322 | { | |
323 | unsigned shift; | |
324 | /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */ | |
325 | assert (info->idx == 1); /* Vn */ | |
326 | aarch64_insn value = extract_field (FLD_imm4, code, 0); | |
327 | /* Depend on AARCH64_OPND_Ed to determine the qualifier. */ | |
328 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
329 | shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier)); | |
330 | info->reglane.index = value >> shift; | |
331 | } | |
332 | else | |
333 | { | |
334 | /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>]. | |
335 | imm5<3:0> <V> | |
336 | 0000 RESERVED | |
337 | xxx1 B | |
338 | xx10 H | |
339 | x100 S | |
340 | 1000 D */ | |
341 | int pos = -1; | |
342 | aarch64_insn value = extract_field (FLD_imm5, code, 0); | |
343 | while (++pos <= 3 && (value & 0x1) == 0) | |
344 | value >>= 1; | |
345 | if (pos > 3) | |
561a72d4 | 346 | return FALSE; |
a06ea964 NC |
347 | info->qualifier = get_sreg_qualifier_from_value (pos); |
348 | info->reglane.index = (unsigned) (value >> 1); | |
349 | } | |
350 | } | |
65a55fbb TC |
351 | else if (inst->opcode->iclass == dotproduct) |
352 | { | |
353 | /* Need information in other operand(s) to help decoding. */ | |
354 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
355 | switch (info->qualifier) | |
356 | { | |
00c2093f | 357 | case AARCH64_OPND_QLF_S_4B: |
df678013 | 358 | case AARCH64_OPND_QLF_S_2H: |
65a55fbb TC |
359 | /* L:H */ |
360 | info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); | |
361 | info->reglane.regno &= 0x1f; | |
362 | break; | |
363 | default: | |
561a72d4 | 364 | return FALSE; |
65a55fbb TC |
365 | } |
366 | } | |
f42f1a1d TC |
367 | else if (inst->opcode->iclass == cryptosm3) |
368 | { | |
369 | /* index for e.g. SM3TT2A <Vd>.4S, <Vn>.4S, <Vm>S[<imm2>]. */ | |
370 | info->reglane.index = extract_field (FLD_SM3_imm2, code, 0); | |
371 | } | |
a06ea964 NC |
372 | else |
373 | { | |
374 | /* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>] | |
375 | or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */ | |
376 | ||
377 | /* Need information in other operand(s) to help decoding. */ | |
378 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
379 | switch (info->qualifier) | |
380 | { | |
381 | case AARCH64_OPND_QLF_S_H: | |
369c9167 TC |
382 | if (info->type == AARCH64_OPND_Em16) |
383 | { | |
384 | /* h:l:m */ | |
385 | info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L, | |
386 | FLD_M); | |
387 | info->reglane.regno &= 0xf; | |
388 | } | |
389 | else | |
390 | { | |
391 | /* h:l */ | |
392 | info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); | |
393 | } | |
a06ea964 NC |
394 | break; |
395 | case AARCH64_OPND_QLF_S_S: | |
396 | /* h:l */ | |
397 | info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L); | |
398 | break; | |
399 | case AARCH64_OPND_QLF_S_D: | |
400 | /* H */ | |
401 | info->reglane.index = extract_field (FLD_H, code, 0); | |
402 | break; | |
403 | default: | |
561a72d4 | 404 | return FALSE; |
a06ea964 | 405 | } |
c2c4ff8d | 406 | |
369c9167 TC |
407 | if (inst->opcode->op == OP_FCMLA_ELEM |
408 | && info->qualifier != AARCH64_OPND_QLF_S_H) | |
c2c4ff8d SN |
409 | { |
410 | /* Complex operand takes two elements. */ | |
411 | if (info->reglane.index & 1) | |
561a72d4 | 412 | return FALSE; |
c2c4ff8d SN |
413 | info->reglane.index /= 2; |
414 | } | |
a06ea964 NC |
415 | } |
416 | ||
561a72d4 | 417 | return TRUE; |
a06ea964 NC |
418 | } |
419 | ||
561a72d4 | 420 | bfd_boolean |
a06ea964 NC |
421 | aarch64_ext_reglist (const aarch64_operand *self, aarch64_opnd_info *info, |
422 | const aarch64_insn code, | |
561a72d4 TC |
423 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
424 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
425 | { |
426 | /* R */ | |
427 | info->reglist.first_regno = extract_field (self->fields[0], code, 0); | |
428 | /* len */ | |
429 | info->reglist.num_regs = extract_field (FLD_len, code, 0) + 1; | |
561a72d4 | 430 | return TRUE; |
a06ea964 NC |
431 | } |
432 | ||
433 | /* Decode Rt and opcode fields of Vt in AdvSIMD load/store instructions. */ | |
561a72d4 | 434 | bfd_boolean |
a06ea964 NC |
435 | aarch64_ext_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED, |
436 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
437 | const aarch64_inst *inst, |
438 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
439 | { |
440 | aarch64_insn value; | |
441 | /* Number of elements in each structure to be loaded/stored. */ | |
442 | unsigned expected_num = get_opcode_dependent_value (inst->opcode); | |
443 | ||
444 | struct | |
445 | { | |
446 | unsigned is_reserved; | |
447 | unsigned num_regs; | |
448 | unsigned num_elements; | |
449 | } data [] = | |
450 | { {0, 4, 4}, | |
451 | {1, 4, 4}, | |
452 | {0, 4, 1}, | |
453 | {0, 4, 2}, | |
454 | {0, 3, 3}, | |
455 | {1, 3, 3}, | |
456 | {0, 3, 1}, | |
457 | {0, 1, 1}, | |
458 | {0, 2, 2}, | |
459 | {1, 2, 2}, | |
460 | {0, 2, 1}, | |
461 | }; | |
462 | ||
463 | /* Rt */ | |
464 | info->reglist.first_regno = extract_field (FLD_Rt, code, 0); | |
465 | /* opcode */ | |
466 | value = extract_field (FLD_opcode, code, 0); | |
cd3ea7c6 NC |
467 | /* PR 21595: Check for a bogus value. */ |
468 | if (value >= ARRAY_SIZE (data)) | |
561a72d4 | 469 | return FALSE; |
a06ea964 | 470 | if (expected_num != data[value].num_elements || data[value].is_reserved) |
561a72d4 | 471 | return FALSE; |
a06ea964 NC |
472 | info->reglist.num_regs = data[value].num_regs; |
473 | ||
561a72d4 | 474 | return TRUE; |
a06ea964 NC |
475 | } |
476 | ||
477 | /* Decode Rt and S fields of Vt in AdvSIMD load single structure to all | |
478 | lanes instructions. */ | |
561a72d4 | 479 | bfd_boolean |
a06ea964 NC |
480 | aarch64_ext_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED, |
481 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
482 | const aarch64_inst *inst, |
483 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
484 | { |
485 | aarch64_insn value; | |
486 | ||
487 | /* Rt */ | |
488 | info->reglist.first_regno = extract_field (FLD_Rt, code, 0); | |
489 | /* S */ | |
490 | value = extract_field (FLD_S, code, 0); | |
491 | ||
492 | /* Number of registers is equal to the number of elements in | |
493 | each structure to be loaded/stored. */ | |
494 | info->reglist.num_regs = get_opcode_dependent_value (inst->opcode); | |
495 | assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4); | |
496 | ||
497 | /* Except when it is LD1R. */ | |
498 | if (info->reglist.num_regs == 1 && value == (aarch64_insn) 1) | |
499 | info->reglist.num_regs = 2; | |
500 | ||
561a72d4 | 501 | return TRUE; |
a06ea964 NC |
502 | } |
503 | ||
504 | /* Decode Q, opcode<2:1>, S, size and Rt fields of Vt in AdvSIMD | |
505 | load/store single element instructions. */ | |
561a72d4 | 506 | bfd_boolean |
a06ea964 NC |
507 | aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, |
508 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
509 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
510 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
511 | { |
512 | aarch64_field field = {0, 0}; | |
513 | aarch64_insn QSsize; /* fields Q:S:size. */ | |
514 | aarch64_insn opcodeh2; /* opcode<2:1> */ | |
515 | ||
516 | /* Rt */ | |
517 | info->reglist.first_regno = extract_field (FLD_Rt, code, 0); | |
518 | ||
519 | /* Decode the index, opcode<2:1> and size. */ | |
520 | gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field); | |
521 | opcodeh2 = extract_field_2 (&field, code, 0); | |
522 | QSsize = extract_fields (code, 0, 3, FLD_Q, FLD_S, FLD_vldst_size); | |
523 | switch (opcodeh2) | |
524 | { | |
525 | case 0x0: | |
526 | info->qualifier = AARCH64_OPND_QLF_S_B; | |
527 | /* Index encoded in "Q:S:size". */ | |
528 | info->reglist.index = QSsize; | |
529 | break; | |
530 | case 0x1: | |
76dfed02 YZ |
531 | if (QSsize & 0x1) |
532 | /* UND. */ | |
561a72d4 | 533 | return FALSE; |
a06ea964 NC |
534 | info->qualifier = AARCH64_OPND_QLF_S_H; |
535 | /* Index encoded in "Q:S:size<1>". */ | |
536 | info->reglist.index = QSsize >> 1; | |
537 | break; | |
538 | case 0x2: | |
76dfed02 YZ |
539 | if ((QSsize >> 1) & 0x1) |
540 | /* UND. */ | |
561a72d4 | 541 | return FALSE; |
a06ea964 NC |
542 | if ((QSsize & 0x1) == 0) |
543 | { | |
544 | info->qualifier = AARCH64_OPND_QLF_S_S; | |
545 | /* Index encoded in "Q:S". */ | |
546 | info->reglist.index = QSsize >> 2; | |
547 | } | |
548 | else | |
549 | { | |
a06ea964 NC |
550 | if (extract_field (FLD_S, code, 0)) |
551 | /* UND */ | |
561a72d4 | 552 | return FALSE; |
76dfed02 YZ |
553 | info->qualifier = AARCH64_OPND_QLF_S_D; |
554 | /* Index encoded in "Q". */ | |
555 | info->reglist.index = QSsize >> 3; | |
a06ea964 NC |
556 | } |
557 | break; | |
558 | default: | |
561a72d4 | 559 | return FALSE; |
a06ea964 NC |
560 | } |
561 | ||
562 | info->reglist.has_index = 1; | |
563 | info->reglist.num_regs = 0; | |
564 | /* Number of registers is equal to the number of elements in | |
565 | each structure to be loaded/stored. */ | |
566 | info->reglist.num_regs = get_opcode_dependent_value (inst->opcode); | |
567 | assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4); | |
568 | ||
561a72d4 | 569 | return TRUE; |
a06ea964 NC |
570 | } |
571 | ||
572 | /* Decode fields immh:immb and/or Q for e.g. | |
573 | SSHR <Vd>.<T>, <Vn>.<T>, #<shift> | |
574 | or SSHR <V><d>, <V><n>, #<shift>. */ | |
575 | ||
561a72d4 | 576 | bfd_boolean |
a06ea964 NC |
577 | aarch64_ext_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED, |
578 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
579 | const aarch64_inst *inst, |
580 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
581 | { |
582 | int pos; | |
583 | aarch64_insn Q, imm, immh; | |
584 | enum aarch64_insn_class iclass = inst->opcode->iclass; | |
585 | ||
586 | immh = extract_field (FLD_immh, code, 0); | |
587 | if (immh == 0) | |
561a72d4 | 588 | return FALSE; |
a06ea964 NC |
589 | imm = extract_fields (code, 0, 2, FLD_immh, FLD_immb); |
590 | pos = 4; | |
591 | /* Get highest set bit in immh. */ | |
592 | while (--pos >= 0 && (immh & 0x8) == 0) | |
593 | immh <<= 1; | |
594 | ||
595 | assert ((iclass == asimdshf || iclass == asisdshf) | |
596 | && (info->type == AARCH64_OPND_IMM_VLSR | |
597 | || info->type == AARCH64_OPND_IMM_VLSL)); | |
598 | ||
599 | if (iclass == asimdshf) | |
600 | { | |
601 | Q = extract_field (FLD_Q, code, 0); | |
602 | /* immh Q <T> | |
603 | 0000 x SEE AdvSIMD modified immediate | |
604 | 0001 0 8B | |
605 | 0001 1 16B | |
606 | 001x 0 4H | |
607 | 001x 1 8H | |
608 | 01xx 0 2S | |
609 | 01xx 1 4S | |
610 | 1xxx 0 RESERVED | |
611 | 1xxx 1 2D */ | |
612 | info->qualifier = | |
613 | get_vreg_qualifier_from_value ((pos << 1) | (int) Q); | |
614 | } | |
615 | else | |
616 | info->qualifier = get_sreg_qualifier_from_value (pos); | |
617 | ||
618 | if (info->type == AARCH64_OPND_IMM_VLSR) | |
619 | /* immh <shift> | |
620 | 0000 SEE AdvSIMD modified immediate | |
621 | 0001 (16-UInt(immh:immb)) | |
622 | 001x (32-UInt(immh:immb)) | |
623 | 01xx (64-UInt(immh:immb)) | |
624 | 1xxx (128-UInt(immh:immb)) */ | |
625 | info->imm.value = (16 << pos) - imm; | |
626 | else | |
627 | /* immh:immb | |
628 | immh <shift> | |
629 | 0000 SEE AdvSIMD modified immediate | |
630 | 0001 (UInt(immh:immb)-8) | |
631 | 001x (UInt(immh:immb)-16) | |
632 | 01xx (UInt(immh:immb)-32) | |
633 | 1xxx (UInt(immh:immb)-64) */ | |
634 | info->imm.value = imm - (8 << pos); | |
635 | ||
561a72d4 | 636 | return TRUE; |
a06ea964 NC |
637 | } |
638 | ||
639 | /* Decode shift immediate for e.g. sshr (imm). */ | |
561a72d4 | 640 | bfd_boolean |
a06ea964 NC |
641 | aarch64_ext_shll_imm (const aarch64_operand *self ATTRIBUTE_UNUSED, |
642 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
643 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
644 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
645 | { |
646 | int64_t imm; | |
647 | aarch64_insn val; | |
648 | val = extract_field (FLD_size, code, 0); | |
649 | switch (val) | |
650 | { | |
651 | case 0: imm = 8; break; | |
652 | case 1: imm = 16; break; | |
653 | case 2: imm = 32; break; | |
561a72d4 | 654 | default: return FALSE; |
a06ea964 NC |
655 | } |
656 | info->imm.value = imm; | |
561a72d4 | 657 | return TRUE; |
a06ea964 NC |
658 | } |
659 | ||
660 | /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>. | |
661 | value in the field(s) will be extracted as unsigned immediate value. */ | |
561a72d4 | 662 | bfd_boolean |
a06ea964 NC |
663 | aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info, |
664 | const aarch64_insn code, | |
561a72d4 TC |
665 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
666 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 | 667 | { |
f81e7e2d | 668 | uint64_t imm; |
a06ea964 | 669 | |
b5464a68 | 670 | imm = extract_all_fields (self, code); |
a06ea964 | 671 | |
a06ea964 NC |
672 | if (operand_need_sign_extension (self)) |
673 | imm = sign_extend (imm, get_operand_fields_width (self) - 1); | |
674 | ||
675 | if (operand_need_shift_by_two (self)) | |
676 | imm <<= 2; | |
193614f2 SD |
677 | else if (operand_need_shift_by_four (self)) |
678 | imm <<= 4; | |
a06ea964 NC |
679 | |
680 | if (info->type == AARCH64_OPND_ADDR_ADRP) | |
681 | imm <<= 12; | |
682 | ||
683 | info->imm.value = imm; | |
561a72d4 | 684 | return TRUE; |
a06ea964 NC |
685 | } |
686 | ||
687 | /* Decode imm and its shifter for e.g. MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */ | |
561a72d4 | 688 | bfd_boolean |
a06ea964 NC |
689 | aarch64_ext_imm_half (const aarch64_operand *self, aarch64_opnd_info *info, |
690 | const aarch64_insn code, | |
561a72d4 TC |
691 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
692 | aarch64_operand_error *errors) | |
a06ea964 | 693 | { |
561a72d4 | 694 | aarch64_ext_imm (self, info, code, inst, errors); |
a06ea964 NC |
695 | info->shifter.kind = AARCH64_MOD_LSL; |
696 | info->shifter.amount = extract_field (FLD_hw, code, 0) << 4; | |
561a72d4 | 697 | return TRUE; |
a06ea964 NC |
698 | } |
699 | ||
700 | /* Decode cmode and "a:b:c:d:e:f:g:h" for e.g. | |
701 | MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */ | |
561a72d4 | 702 | bfd_boolean |
a06ea964 NC |
703 | aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, |
704 | aarch64_opnd_info *info, | |
705 | const aarch64_insn code, | |
561a72d4 TC |
706 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
707 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
708 | { |
709 | uint64_t imm; | |
710 | enum aarch64_opnd_qualifier opnd0_qualifier = inst->operands[0].qualifier; | |
711 | aarch64_field field = {0, 0}; | |
712 | ||
713 | assert (info->idx == 1); | |
714 | ||
715 | if (info->type == AARCH64_OPND_SIMD_FPIMM) | |
716 | info->imm.is_fp = 1; | |
717 | ||
718 | /* a:b:c:d:e:f:g:h */ | |
719 | imm = extract_fields (code, 0, 2, FLD_abc, FLD_defgh); | |
720 | if (!info->imm.is_fp && aarch64_get_qualifier_esize (opnd0_qualifier) == 8) | |
721 | { | |
722 | /* Either MOVI <Dd>, #<imm> | |
723 | or MOVI <Vd>.2D, #<imm>. | |
724 | <imm> is a 64-bit immediate | |
725 | 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh', | |
726 | encoded in "a:b:c:d:e:f:g:h". */ | |
727 | int i; | |
728 | unsigned abcdefgh = imm; | |
729 | for (imm = 0ull, i = 0; i < 8; i++) | |
730 | if (((abcdefgh >> i) & 0x1) != 0) | |
731 | imm |= 0xffull << (8 * i); | |
732 | } | |
733 | info->imm.value = imm; | |
734 | ||
735 | /* cmode */ | |
736 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
737 | switch (info->qualifier) | |
738 | { | |
739 | case AARCH64_OPND_QLF_NIL: | |
740 | /* no shift */ | |
741 | info->shifter.kind = AARCH64_MOD_NONE; | |
742 | return 1; | |
743 | case AARCH64_OPND_QLF_LSL: | |
744 | /* shift zeros */ | |
745 | info->shifter.kind = AARCH64_MOD_LSL; | |
746 | switch (aarch64_get_qualifier_esize (opnd0_qualifier)) | |
747 | { | |
748 | case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break; /* per word */ | |
749 | case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break; /* per half */ | |
f5555712 | 750 | case 1: gen_sub_field (FLD_cmode, 1, 0, &field); break; /* per byte */ |
561a72d4 | 751 | default: assert (0); return FALSE; |
a06ea964 NC |
752 | } |
753 | /* 00: 0; 01: 8; 10:16; 11:24. */ | |
754 | info->shifter.amount = extract_field_2 (&field, code, 0) << 3; | |
755 | break; | |
756 | case AARCH64_OPND_QLF_MSL: | |
757 | /* shift ones */ | |
758 | info->shifter.kind = AARCH64_MOD_MSL; | |
759 | gen_sub_field (FLD_cmode, 0, 1, &field); /* per word */ | |
760 | info->shifter.amount = extract_field_2 (&field, code, 0) ? 16 : 8; | |
761 | break; | |
762 | default: | |
763 | assert (0); | |
561a72d4 | 764 | return FALSE; |
a06ea964 NC |
765 | } |
766 | ||
561a72d4 | 767 | return TRUE; |
a06ea964 NC |
768 | } |
769 | ||
aa2aa4c6 | 770 | /* Decode an 8-bit floating-point immediate. */ |
561a72d4 | 771 | bfd_boolean |
aa2aa4c6 RS |
772 | aarch64_ext_fpimm (const aarch64_operand *self, aarch64_opnd_info *info, |
773 | const aarch64_insn code, | |
561a72d4 TC |
774 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
775 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
aa2aa4c6 RS |
776 | { |
777 | info->imm.value = extract_all_fields (self, code); | |
778 | info->imm.is_fp = 1; | |
561a72d4 | 779 | return TRUE; |
aa2aa4c6 RS |
780 | } |
781 | ||
582e12bf | 782 | /* Decode a 1-bit rotate immediate (#90 or #270). */ |
561a72d4 | 783 | bfd_boolean |
582e12bf RS |
784 | aarch64_ext_imm_rotate1 (const aarch64_operand *self, aarch64_opnd_info *info, |
785 | const aarch64_insn code, | |
561a72d4 TC |
786 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
787 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
c2c4ff8d SN |
788 | { |
789 | uint64_t rot = extract_field (self->fields[0], code, 0); | |
582e12bf RS |
790 | assert (rot < 2U); |
791 | info->imm.value = rot * 180 + 90; | |
561a72d4 | 792 | return TRUE; |
582e12bf | 793 | } |
c2c4ff8d | 794 | |
582e12bf | 795 | /* Decode a 2-bit rotate immediate (#0, #90, #180 or #270). */ |
561a72d4 | 796 | bfd_boolean |
582e12bf RS |
797 | aarch64_ext_imm_rotate2 (const aarch64_operand *self, aarch64_opnd_info *info, |
798 | const aarch64_insn code, | |
561a72d4 TC |
799 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
800 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
582e12bf RS |
801 | { |
802 | uint64_t rot = extract_field (self->fields[0], code, 0); | |
803 | assert (rot < 4U); | |
c2c4ff8d | 804 | info->imm.value = rot * 90; |
561a72d4 | 805 | return TRUE; |
c2c4ff8d SN |
806 | } |
807 | ||
a06ea964 | 808 | /* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */ |
561a72d4 | 809 | bfd_boolean |
a06ea964 NC |
810 | aarch64_ext_fbits (const aarch64_operand *self ATTRIBUTE_UNUSED, |
811 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
812 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
813 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
814 | { |
815 | info->imm.value = 64- extract_field (FLD_scale, code, 0); | |
561a72d4 | 816 | return TRUE; |
a06ea964 NC |
817 | } |
818 | ||
819 | /* Decode arithmetic immediate for e.g. | |
820 | SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */ | |
561a72d4 | 821 | bfd_boolean |
a06ea964 NC |
822 | aarch64_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED, |
823 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
824 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
825 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
826 | { |
827 | aarch64_insn value; | |
828 | ||
829 | info->shifter.kind = AARCH64_MOD_LSL; | |
830 | /* shift */ | |
831 | value = extract_field (FLD_shift, code, 0); | |
832 | if (value >= 2) | |
561a72d4 | 833 | return FALSE; |
a06ea964 NC |
834 | info->shifter.amount = value ? 12 : 0; |
835 | /* imm12 (unsigned) */ | |
836 | info->imm.value = extract_field (FLD_imm12, code, 0); | |
837 | ||
561a72d4 | 838 | return TRUE; |
a06ea964 NC |
839 | } |
840 | ||
e950b345 RS |
841 | /* Return true if VALUE is a valid logical immediate encoding, storing the |
842 | decoded value in *RESULT if so. ESIZE is the number of bytes in the | |
843 | decoded immediate. */ | |
561a72d4 | 844 | static bfd_boolean |
e950b345 | 845 | decode_limm (uint32_t esize, aarch64_insn value, int64_t *result) |
a06ea964 NC |
846 | { |
847 | uint64_t imm, mask; | |
a06ea964 NC |
848 | uint32_t N, R, S; |
849 | unsigned simd_size; | |
a06ea964 NC |
850 | |
851 | /* value is N:immr:imms. */ | |
852 | S = value & 0x3f; | |
853 | R = (value >> 6) & 0x3f; | |
854 | N = (value >> 12) & 0x1; | |
855 | ||
a06ea964 NC |
856 | /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R |
857 | (in other words, right rotated by R), then replicated. */ | |
858 | if (N != 0) | |
859 | { | |
860 | simd_size = 64; | |
861 | mask = 0xffffffffffffffffull; | |
862 | } | |
863 | else | |
864 | { | |
865 | switch (S) | |
866 | { | |
867 | case 0x00 ... 0x1f: /* 0xxxxx */ simd_size = 32; break; | |
868 | case 0x20 ... 0x2f: /* 10xxxx */ simd_size = 16; S &= 0xf; break; | |
869 | case 0x30 ... 0x37: /* 110xxx */ simd_size = 8; S &= 0x7; break; | |
870 | case 0x38 ... 0x3b: /* 1110xx */ simd_size = 4; S &= 0x3; break; | |
871 | case 0x3c ... 0x3d: /* 11110x */ simd_size = 2; S &= 0x1; break; | |
561a72d4 | 872 | default: return FALSE; |
a06ea964 NC |
873 | } |
874 | mask = (1ull << simd_size) - 1; | |
875 | /* Top bits are IGNORED. */ | |
876 | R &= simd_size - 1; | |
877 | } | |
e950b345 RS |
878 | |
879 | if (simd_size > esize * 8) | |
561a72d4 | 880 | return FALSE; |
e950b345 | 881 | |
a06ea964 NC |
882 | /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */ |
883 | if (S == simd_size - 1) | |
561a72d4 | 884 | return FALSE; |
a06ea964 NC |
885 | /* S+1 consecutive bits to 1. */ |
886 | /* NOTE: S can't be 63 due to detection above. */ | |
887 | imm = (1ull << (S + 1)) - 1; | |
888 | /* Rotate to the left by simd_size - R. */ | |
889 | if (R != 0) | |
890 | imm = ((imm << (simd_size - R)) & mask) | (imm >> R); | |
891 | /* Replicate the value according to SIMD size. */ | |
892 | switch (simd_size) | |
893 | { | |
894 | case 2: imm = (imm << 2) | imm; | |
1a0670f3 | 895 | /* Fall through. */ |
a06ea964 | 896 | case 4: imm = (imm << 4) | imm; |
1a0670f3 | 897 | /* Fall through. */ |
a06ea964 | 898 | case 8: imm = (imm << 8) | imm; |
1a0670f3 | 899 | /* Fall through. */ |
a06ea964 | 900 | case 16: imm = (imm << 16) | imm; |
1a0670f3 | 901 | /* Fall through. */ |
a06ea964 | 902 | case 32: imm = (imm << 32) | imm; |
1a0670f3 | 903 | /* Fall through. */ |
a06ea964 NC |
904 | case 64: break; |
905 | default: assert (0); return 0; | |
906 | } | |
907 | ||
e950b345 RS |
908 | *result = imm & ~((uint64_t) -1 << (esize * 4) << (esize * 4)); |
909 | ||
561a72d4 | 910 | return TRUE; |
e950b345 RS |
911 | } |
912 | ||
913 | /* Decode a logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>. */ | |
561a72d4 | 914 | bfd_boolean |
e950b345 RS |
915 | aarch64_ext_limm (const aarch64_operand *self, |
916 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
917 | const aarch64_inst *inst, |
918 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
e950b345 RS |
919 | { |
920 | uint32_t esize; | |
921 | aarch64_insn value; | |
922 | ||
923 | value = extract_fields (code, 0, 3, self->fields[0], self->fields[1], | |
924 | self->fields[2]); | |
925 | esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier); | |
926 | return decode_limm (esize, value, &info->imm.value); | |
927 | } | |
a06ea964 | 928 | |
e950b345 | 929 | /* Decode a logical immediate for the BIC alias of AND (etc.). */ |
561a72d4 | 930 | bfd_boolean |
e950b345 RS |
931 | aarch64_ext_inv_limm (const aarch64_operand *self, |
932 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
933 | const aarch64_inst *inst, |
934 | aarch64_operand_error *errors) | |
e950b345 | 935 | { |
561a72d4 TC |
936 | if (!aarch64_ext_limm (self, info, code, inst, errors)) |
937 | return FALSE; | |
e950b345 | 938 | info->imm.value = ~info->imm.value; |
561a72d4 | 939 | return TRUE; |
a06ea964 NC |
940 | } |
941 | ||
942 | /* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}] | |
943 | or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */ | |
561a72d4 | 944 | bfd_boolean |
a06ea964 NC |
945 | aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED, |
946 | aarch64_opnd_info *info, | |
561a72d4 TC |
947 | const aarch64_insn code, const aarch64_inst *inst, |
948 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
949 | { |
950 | aarch64_insn value; | |
951 | ||
952 | /* Rt */ | |
953 | info->reg.regno = extract_field (FLD_Rt, code, 0); | |
954 | ||
955 | /* size */ | |
956 | value = extract_field (FLD_ldst_size, code, 0); | |
957 | if (inst->opcode->iclass == ldstpair_indexed | |
958 | || inst->opcode->iclass == ldstnapair_offs | |
959 | || inst->opcode->iclass == ldstpair_off | |
960 | || inst->opcode->iclass == loadlit) | |
961 | { | |
962 | enum aarch64_opnd_qualifier qualifier; | |
963 | switch (value) | |
964 | { | |
965 | case 0: qualifier = AARCH64_OPND_QLF_S_S; break; | |
966 | case 1: qualifier = AARCH64_OPND_QLF_S_D; break; | |
967 | case 2: qualifier = AARCH64_OPND_QLF_S_Q; break; | |
561a72d4 | 968 | default: return FALSE; |
a06ea964 NC |
969 | } |
970 | info->qualifier = qualifier; | |
971 | } | |
972 | else | |
973 | { | |
974 | /* opc1:size */ | |
975 | value = extract_fields (code, 0, 2, FLD_opc1, FLD_ldst_size); | |
976 | if (value > 0x4) | |
561a72d4 | 977 | return FALSE; |
a06ea964 NC |
978 | info->qualifier = get_sreg_qualifier_from_value (value); |
979 | } | |
980 | ||
561a72d4 | 981 | return TRUE; |
a06ea964 NC |
982 | } |
983 | ||
984 | /* Decode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */ | |
561a72d4 | 985 | bfd_boolean |
a06ea964 NC |
986 | aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED, |
987 | aarch64_opnd_info *info, | |
988 | aarch64_insn code, | |
561a72d4 TC |
989 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
990 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
991 | { |
992 | /* Rn */ | |
993 | info->addr.base_regno = extract_field (FLD_Rn, code, 0); | |
561a72d4 | 994 | return TRUE; |
a06ea964 NC |
995 | } |
996 | ||
f42f1a1d TC |
997 | /* Decode the address operand for e.g. |
998 | stlur <Xt>, [<Xn|SP>{, <amount>}]. */ | |
561a72d4 | 999 | bfd_boolean |
f42f1a1d TC |
1000 | aarch64_ext_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1001 | aarch64_opnd_info *info, | |
561a72d4 TC |
1002 | aarch64_insn code, const aarch64_inst *inst, |
1003 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
f42f1a1d TC |
1004 | { |
1005 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
1006 | ||
1007 | /* Rn */ | |
1008 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1009 | ||
1010 | /* simm9 */ | |
1011 | aarch64_insn imm = extract_fields (code, 0, 1, self->fields[1]); | |
1012 | info->addr.offset.imm = sign_extend (imm, 8); | |
1013 | if (extract_field (self->fields[2], code, 0) == 1) { | |
1014 | info->addr.writeback = 1; | |
1015 | info->addr.preind = 1; | |
1016 | } | |
561a72d4 | 1017 | return TRUE; |
f42f1a1d TC |
1018 | } |
1019 | ||
a06ea964 NC |
1020 | /* Decode the address operand for e.g. |
1021 | STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
561a72d4 | 1022 | bfd_boolean |
a06ea964 NC |
1023 | aarch64_ext_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1024 | aarch64_opnd_info *info, | |
561a72d4 TC |
1025 | aarch64_insn code, const aarch64_inst *inst, |
1026 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1027 | { |
1028 | aarch64_insn S, value; | |
1029 | ||
1030 | /* Rn */ | |
1031 | info->addr.base_regno = extract_field (FLD_Rn, code, 0); | |
1032 | /* Rm */ | |
1033 | info->addr.offset.regno = extract_field (FLD_Rm, code, 0); | |
1034 | /* option */ | |
1035 | value = extract_field (FLD_option, code, 0); | |
1036 | info->shifter.kind = | |
1037 | aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */); | |
1038 | /* Fix-up the shifter kind; although the table-driven approach is | |
1039 | efficient, it is slightly inflexible, thus needing this fix-up. */ | |
1040 | if (info->shifter.kind == AARCH64_MOD_UXTX) | |
1041 | info->shifter.kind = AARCH64_MOD_LSL; | |
1042 | /* S */ | |
1043 | S = extract_field (FLD_S, code, 0); | |
1044 | if (S == 0) | |
1045 | { | |
1046 | info->shifter.amount = 0; | |
1047 | info->shifter.amount_present = 0; | |
1048 | } | |
1049 | else | |
1050 | { | |
1051 | int size; | |
1052 | /* Need information in other operand(s) to help achieve the decoding | |
1053 | from 'S' field. */ | |
1054 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
1055 | /* Get the size of the data element that is accessed, which may be | |
1056 | different from that of the source register size, e.g. in strb/ldrb. */ | |
1057 | size = aarch64_get_qualifier_esize (info->qualifier); | |
1058 | info->shifter.amount = get_logsz (size); | |
1059 | info->shifter.amount_present = 1; | |
1060 | } | |
1061 | ||
561a72d4 | 1062 | return TRUE; |
a06ea964 NC |
1063 | } |
1064 | ||
1065 | /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>], #<simm>. */ | |
561a72d4 | 1066 | bfd_boolean |
a06ea964 | 1067 | aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info, |
561a72d4 TC |
1068 | aarch64_insn code, const aarch64_inst *inst, |
1069 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1070 | { |
1071 | aarch64_insn imm; | |
1072 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
1073 | ||
1074 | /* Rn */ | |
1075 | info->addr.base_regno = extract_field (FLD_Rn, code, 0); | |
1076 | /* simm (imm9 or imm7) */ | |
1077 | imm = extract_field (self->fields[0], code, 0); | |
1078 | info->addr.offset.imm = sign_extend (imm, fields[self->fields[0]].width - 1); | |
fb3265b3 SD |
1079 | if (self->fields[0] == FLD_imm7 |
1080 | || info->qualifier == AARCH64_OPND_QLF_imm_tag) | |
a06ea964 NC |
1081 | /* scaled immediate in ld/st pair instructions. */ |
1082 | info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier); | |
1083 | /* qualifier */ | |
1084 | if (inst->opcode->iclass == ldst_unscaled | |
1085 | || inst->opcode->iclass == ldstnapair_offs | |
1086 | || inst->opcode->iclass == ldstpair_off | |
1087 | || inst->opcode->iclass == ldst_unpriv) | |
1088 | info->addr.writeback = 0; | |
1089 | else | |
1090 | { | |
1091 | /* pre/post- index */ | |
1092 | info->addr.writeback = 1; | |
1093 | if (extract_field (self->fields[1], code, 0) == 1) | |
1094 | info->addr.preind = 1; | |
1095 | else | |
1096 | info->addr.postind = 1; | |
1097 | } | |
1098 | ||
561a72d4 | 1099 | return TRUE; |
a06ea964 NC |
1100 | } |
1101 | ||
1102 | /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<simm>}]. */ | |
561a72d4 | 1103 | bfd_boolean |
a06ea964 NC |
1104 | aarch64_ext_addr_uimm12 (const aarch64_operand *self, aarch64_opnd_info *info, |
1105 | aarch64_insn code, | |
561a72d4 TC |
1106 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1107 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1108 | { |
1109 | int shift; | |
1110 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
1111 | shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier)); | |
1112 | /* Rn */ | |
1113 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1114 | /* uimm12 */ | |
1115 | info->addr.offset.imm = extract_field (self->fields[1], code, 0) << shift; | |
561a72d4 | 1116 | return TRUE; |
a06ea964 NC |
1117 | } |
1118 | ||
3f06e550 | 1119 | /* Decode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}]. */ |
561a72d4 | 1120 | bfd_boolean |
3f06e550 SN |
1121 | aarch64_ext_addr_simm10 (const aarch64_operand *self, aarch64_opnd_info *info, |
1122 | aarch64_insn code, | |
561a72d4 TC |
1123 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1124 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
3f06e550 SN |
1125 | { |
1126 | aarch64_insn imm; | |
1127 | ||
1128 | info->qualifier = get_expected_qualifier (inst, info->idx); | |
1129 | /* Rn */ | |
1130 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1131 | /* simm10 */ | |
1132 | imm = extract_fields (code, 0, 2, self->fields[1], self->fields[2]); | |
1133 | info->addr.offset.imm = sign_extend (imm, 9) << 3; | |
1134 | if (extract_field (self->fields[3], code, 0) == 1) { | |
1135 | info->addr.writeback = 1; | |
1136 | info->addr.preind = 1; | |
1137 | } | |
561a72d4 | 1138 | return TRUE; |
3f06e550 SN |
1139 | } |
1140 | ||
a06ea964 NC |
1141 | /* Decode the address operand for e.g. |
1142 | LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */ | |
561a72d4 | 1143 | bfd_boolean |
a06ea964 NC |
1144 | aarch64_ext_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1145 | aarch64_opnd_info *info, | |
561a72d4 TC |
1146 | aarch64_insn code, const aarch64_inst *inst, |
1147 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1148 | { |
1149 | /* The opcode dependent area stores the number of elements in | |
1150 | each structure to be loaded/stored. */ | |
1151 | int is_ld1r = get_opcode_dependent_value (inst->opcode) == 1; | |
1152 | ||
1153 | /* Rn */ | |
1154 | info->addr.base_regno = extract_field (FLD_Rn, code, 0); | |
1155 | /* Rm | #<amount> */ | |
1156 | info->addr.offset.regno = extract_field (FLD_Rm, code, 0); | |
1157 | if (info->addr.offset.regno == 31) | |
1158 | { | |
1159 | if (inst->opcode->operands[0] == AARCH64_OPND_LVt_AL) | |
1160 | /* Special handling of loading single structure to all lane. */ | |
1161 | info->addr.offset.imm = (is_ld1r ? 1 | |
1162 | : inst->operands[0].reglist.num_regs) | |
1163 | * aarch64_get_qualifier_esize (inst->operands[0].qualifier); | |
1164 | else | |
1165 | info->addr.offset.imm = inst->operands[0].reglist.num_regs | |
1166 | * aarch64_get_qualifier_esize (inst->operands[0].qualifier) | |
1167 | * aarch64_get_qualifier_nelem (inst->operands[0].qualifier); | |
1168 | } | |
1169 | else | |
1170 | info->addr.offset.is_reg = 1; | |
1171 | info->addr.writeback = 1; | |
1172 | ||
561a72d4 | 1173 | return TRUE; |
a06ea964 NC |
1174 | } |
1175 | ||
1176 | /* Decode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */ | |
561a72d4 | 1177 | bfd_boolean |
a06ea964 NC |
1178 | aarch64_ext_cond (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1179 | aarch64_opnd_info *info, | |
561a72d4 TC |
1180 | aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1181 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1182 | { |
1183 | aarch64_insn value; | |
1184 | /* cond */ | |
1185 | value = extract_field (FLD_cond, code, 0); | |
1186 | info->cond = get_cond_from_value (value); | |
561a72d4 | 1187 | return TRUE; |
a06ea964 NC |
1188 | } |
1189 | ||
1190 | /* Decode the system register operand for e.g. MRS <Xt>, <systemreg>. */ | |
561a72d4 | 1191 | bfd_boolean |
a06ea964 NC |
1192 | aarch64_ext_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1193 | aarch64_opnd_info *info, | |
1194 | aarch64_insn code, | |
561a72d4 TC |
1195 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1196 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1197 | { |
1198 | /* op0:op1:CRn:CRm:op2 */ | |
561a72d4 TC |
1199 | info->sysreg.value = extract_fields (code, 0, 5, FLD_op0, FLD_op1, FLD_CRn, |
1200 | FLD_CRm, FLD_op2); | |
f9830ec1 TC |
1201 | info->sysreg.flags = 0; |
1202 | ||
1203 | /* If a system instruction, check which restrictions should be on the register | |
1204 | value during decoding, these will be enforced then. */ | |
1205 | if (inst->opcode->iclass == ic_system) | |
1206 | { | |
1207 | /* Check to see if it's read-only, else check if it's write only. | |
1208 | if it's both or unspecified don't care. */ | |
1209 | if ((inst->opcode->flags & (F_SYS_READ | F_SYS_WRITE)) == F_SYS_READ) | |
1210 | info->sysreg.flags = F_REG_READ; | |
1211 | else if ((inst->opcode->flags & (F_SYS_READ | F_SYS_WRITE)) | |
1212 | == F_SYS_WRITE) | |
1213 | info->sysreg.flags = F_REG_WRITE; | |
1214 | } | |
1215 | ||
1216 | return TRUE; | |
a06ea964 NC |
1217 | } |
1218 | ||
1219 | /* Decode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */ | |
561a72d4 | 1220 | bfd_boolean |
a06ea964 NC |
1221 | aarch64_ext_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1222 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1223 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1224 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1225 | { |
1226 | int i; | |
1227 | /* op1:op2 */ | |
1228 | info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2); | |
1229 | for (i = 0; aarch64_pstatefields[i].name != NULL; ++i) | |
1230 | if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield) | |
561a72d4 | 1231 | return TRUE; |
a06ea964 | 1232 | /* Reserved value in <pstatefield>. */ |
561a72d4 | 1233 | return FALSE; |
a06ea964 NC |
1234 | } |
1235 | ||
1236 | /* Decode the system instruction op operand for e.g. AT <at_op>, <Xt>. */ | |
561a72d4 | 1237 | bfd_boolean |
a06ea964 NC |
1238 | aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1239 | aarch64_opnd_info *info, | |
1240 | aarch64_insn code, | |
561a72d4 TC |
1241 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1242 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1243 | { |
1244 | int i; | |
1245 | aarch64_insn value; | |
1246 | const aarch64_sys_ins_reg *sysins_ops; | |
1247 | /* op0:op1:CRn:CRm:op2 */ | |
1248 | value = extract_fields (code, 0, 5, | |
1249 | FLD_op0, FLD_op1, FLD_CRn, | |
1250 | FLD_CRm, FLD_op2); | |
1251 | ||
1252 | switch (info->type) | |
1253 | { | |
1254 | case AARCH64_OPND_SYSREG_AT: sysins_ops = aarch64_sys_regs_at; break; | |
1255 | case AARCH64_OPND_SYSREG_DC: sysins_ops = aarch64_sys_regs_dc; break; | |
1256 | case AARCH64_OPND_SYSREG_IC: sysins_ops = aarch64_sys_regs_ic; break; | |
1257 | case AARCH64_OPND_SYSREG_TLBI: sysins_ops = aarch64_sys_regs_tlbi; break; | |
2ac435d4 SD |
1258 | case AARCH64_OPND_SYSREG_SR: |
1259 | sysins_ops = aarch64_sys_regs_sr; | |
1260 | /* Let's remove op2 for rctx. Refer to comments in the definition of | |
1261 | aarch64_sys_regs_sr[]. */ | |
1262 | value = value & ~(0x7); | |
1263 | break; | |
561a72d4 | 1264 | default: assert (0); return FALSE; |
a06ea964 NC |
1265 | } |
1266 | ||
875880c6 | 1267 | for (i = 0; sysins_ops[i].name != NULL; ++i) |
a06ea964 NC |
1268 | if (sysins_ops[i].value == value) |
1269 | { | |
1270 | info->sysins_op = sysins_ops + i; | |
1271 | DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.", | |
875880c6 | 1272 | info->sysins_op->name, |
a06ea964 | 1273 | (unsigned)info->sysins_op->value, |
ea2deeec | 1274 | aarch64_sys_ins_reg_has_xt (info->sysins_op), i); |
561a72d4 | 1275 | return TRUE; |
a06ea964 NC |
1276 | } |
1277 | ||
561a72d4 | 1278 | return FALSE; |
a06ea964 NC |
1279 | } |
1280 | ||
1281 | /* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>. */ | |
1282 | ||
561a72d4 | 1283 | bfd_boolean |
a06ea964 NC |
1284 | aarch64_ext_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1285 | aarch64_opnd_info *info, | |
1286 | aarch64_insn code, | |
561a72d4 TC |
1287 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1288 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1289 | { |
1290 | /* CRm */ | |
1291 | info->barrier = aarch64_barrier_options + extract_field (FLD_CRm, code, 0); | |
561a72d4 | 1292 | return TRUE; |
a06ea964 NC |
1293 | } |
1294 | ||
1295 | /* Decode the prefetch operation option operand for e.g. | |
1296 | PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */ | |
1297 | ||
561a72d4 | 1298 | bfd_boolean |
a06ea964 NC |
1299 | aarch64_ext_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1300 | aarch64_opnd_info *info, | |
561a72d4 TC |
1301 | aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1302 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1303 | { |
1304 | /* prfop in Rt */ | |
1305 | info->prfop = aarch64_prfops + extract_field (FLD_Rt, code, 0); | |
561a72d4 | 1306 | return TRUE; |
a06ea964 NC |
1307 | } |
1308 | ||
9ed608f9 MW |
1309 | /* Decode the hint number for an alias taking an operand. Set info->hint_option |
1310 | to the matching name/value pair in aarch64_hint_options. */ | |
1311 | ||
561a72d4 | 1312 | bfd_boolean |
9ed608f9 MW |
1313 | aarch64_ext_hint (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1314 | aarch64_opnd_info *info, | |
1315 | aarch64_insn code, | |
561a72d4 TC |
1316 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1317 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
9ed608f9 MW |
1318 | { |
1319 | /* CRm:op2. */ | |
1320 | unsigned hint_number; | |
1321 | int i; | |
1322 | ||
1323 | hint_number = extract_fields (code, 0, 2, FLD_CRm, FLD_op2); | |
1324 | ||
1325 | for (i = 0; aarch64_hint_options[i].name != NULL; i++) | |
1326 | { | |
ff605452 | 1327 | if (hint_number == HINT_VAL (aarch64_hint_options[i].value)) |
9ed608f9 MW |
1328 | { |
1329 | info->hint_option = &(aarch64_hint_options[i]); | |
561a72d4 | 1330 | return TRUE; |
9ed608f9 MW |
1331 | } |
1332 | } | |
1333 | ||
561a72d4 | 1334 | return FALSE; |
9ed608f9 MW |
1335 | } |
1336 | ||
a06ea964 NC |
1337 | /* Decode the extended register operand for e.g. |
1338 | STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ | |
561a72d4 | 1339 | bfd_boolean |
a06ea964 NC |
1340 | aarch64_ext_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1341 | aarch64_opnd_info *info, | |
1342 | aarch64_insn code, | |
561a72d4 TC |
1343 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1344 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1345 | { |
1346 | aarch64_insn value; | |
1347 | ||
1348 | /* Rm */ | |
1349 | info->reg.regno = extract_field (FLD_Rm, code, 0); | |
1350 | /* option */ | |
1351 | value = extract_field (FLD_option, code, 0); | |
1352 | info->shifter.kind = | |
1353 | aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */); | |
1354 | /* imm3 */ | |
1355 | info->shifter.amount = extract_field (FLD_imm3, code, 0); | |
1356 | ||
1357 | /* This makes the constraint checking happy. */ | |
1358 | info->shifter.operator_present = 1; | |
1359 | ||
1360 | /* Assume inst->operands[0].qualifier has been resolved. */ | |
1361 | assert (inst->operands[0].qualifier != AARCH64_OPND_QLF_NIL); | |
1362 | info->qualifier = AARCH64_OPND_QLF_W; | |
1363 | if (inst->operands[0].qualifier == AARCH64_OPND_QLF_X | |
1364 | && (info->shifter.kind == AARCH64_MOD_UXTX | |
1365 | || info->shifter.kind == AARCH64_MOD_SXTX)) | |
1366 | info->qualifier = AARCH64_OPND_QLF_X; | |
1367 | ||
561a72d4 | 1368 | return TRUE; |
a06ea964 NC |
1369 | } |
1370 | ||
1371 | /* Decode the shifted register operand for e.g. | |
1372 | SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */ | |
561a72d4 | 1373 | bfd_boolean |
a06ea964 NC |
1374 | aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED, |
1375 | aarch64_opnd_info *info, | |
1376 | aarch64_insn code, | |
561a72d4 TC |
1377 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1378 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
1379 | { |
1380 | aarch64_insn value; | |
1381 | ||
1382 | /* Rm */ | |
1383 | info->reg.regno = extract_field (FLD_Rm, code, 0); | |
1384 | /* shift */ | |
1385 | value = extract_field (FLD_shift, code, 0); | |
1386 | info->shifter.kind = | |
1387 | aarch64_get_operand_modifier_from_value (value, FALSE /* extend_p */); | |
1388 | if (info->shifter.kind == AARCH64_MOD_ROR | |
1389 | && inst->opcode->iclass != log_shift) | |
1390 | /* ROR is not available for the shifted register operand in arithmetic | |
1391 | instructions. */ | |
561a72d4 | 1392 | return FALSE; |
a06ea964 NC |
1393 | /* imm6 */ |
1394 | info->shifter.amount = extract_field (FLD_imm6, code, 0); | |
1395 | ||
1396 | /* This makes the constraint checking happy. */ | |
1397 | info->shifter.operator_present = 1; | |
1398 | ||
561a72d4 | 1399 | return TRUE; |
a06ea964 | 1400 | } |
f11ad6bc | 1401 | |
98907a70 RS |
1402 | /* Decode an SVE address [<base>, #<offset>*<factor>, MUL VL], |
1403 | where <offset> is given by the OFFSET parameter and where <factor> is | |
1404 | 1 plus SELF's operand-dependent value. fields[0] specifies the field | |
1405 | that holds <base>. */ | |
561a72d4 | 1406 | static bfd_boolean |
98907a70 RS |
1407 | aarch64_ext_sve_addr_reg_mul_vl (const aarch64_operand *self, |
1408 | aarch64_opnd_info *info, aarch64_insn code, | |
1409 | int64_t offset) | |
1410 | { | |
1411 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1412 | info->addr.offset.imm = offset * (1 + get_operand_specific_data (self)); | |
1413 | info->addr.offset.is_reg = FALSE; | |
1414 | info->addr.writeback = FALSE; | |
1415 | info->addr.preind = TRUE; | |
1416 | if (offset != 0) | |
1417 | info->shifter.kind = AARCH64_MOD_MUL_VL; | |
1418 | info->shifter.amount = 1; | |
1419 | info->shifter.operator_present = (info->addr.offset.imm != 0); | |
1420 | info->shifter.amount_present = FALSE; | |
561a72d4 | 1421 | return TRUE; |
98907a70 RS |
1422 | } |
1423 | ||
1424 | /* Decode an SVE address [<base>, #<simm4>*<factor>, MUL VL], | |
1425 | where <simm4> is a 4-bit signed value and where <factor> is 1 plus | |
1426 | SELF's operand-dependent value. fields[0] specifies the field that | |
1427 | holds <base>. <simm4> is encoded in the SVE_imm4 field. */ | |
561a72d4 | 1428 | bfd_boolean |
98907a70 RS |
1429 | aarch64_ext_sve_addr_ri_s4xvl (const aarch64_operand *self, |
1430 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1431 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1432 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
98907a70 RS |
1433 | { |
1434 | int offset; | |
1435 | ||
1436 | offset = extract_field (FLD_SVE_imm4, code, 0); | |
1437 | offset = ((offset + 8) & 15) - 8; | |
1438 | return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset); | |
1439 | } | |
1440 | ||
1441 | /* Decode an SVE address [<base>, #<simm6>*<factor>, MUL VL], | |
1442 | where <simm6> is a 6-bit signed value and where <factor> is 1 plus | |
1443 | SELF's operand-dependent value. fields[0] specifies the field that | |
1444 | holds <base>. <simm6> is encoded in the SVE_imm6 field. */ | |
561a72d4 | 1445 | bfd_boolean |
98907a70 RS |
1446 | aarch64_ext_sve_addr_ri_s6xvl (const aarch64_operand *self, |
1447 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1448 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1449 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
98907a70 RS |
1450 | { |
1451 | int offset; | |
1452 | ||
1453 | offset = extract_field (FLD_SVE_imm6, code, 0); | |
1454 | offset = (((offset + 32) & 63) - 32); | |
1455 | return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset); | |
1456 | } | |
1457 | ||
1458 | /* Decode an SVE address [<base>, #<simm9>*<factor>, MUL VL], | |
1459 | where <simm9> is a 9-bit signed value and where <factor> is 1 plus | |
1460 | SELF's operand-dependent value. fields[0] specifies the field that | |
1461 | holds <base>. <simm9> is encoded in the concatenation of the SVE_imm6 | |
1462 | and imm3 fields, with imm3 being the less-significant part. */ | |
561a72d4 | 1463 | bfd_boolean |
98907a70 RS |
1464 | aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand *self, |
1465 | aarch64_opnd_info *info, | |
1466 | aarch64_insn code, | |
561a72d4 TC |
1467 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1468 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
98907a70 RS |
1469 | { |
1470 | int offset; | |
1471 | ||
1472 | offset = extract_fields (code, 0, 2, FLD_SVE_imm6, FLD_imm3); | |
1473 | offset = (((offset + 256) & 511) - 256); | |
1474 | return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset); | |
1475 | } | |
1476 | ||
4df068de RS |
1477 | /* Decode an SVE address [<base>, #<offset> << <shift>], where <offset> |
1478 | is given by the OFFSET parameter and where <shift> is SELF's operand- | |
1479 | dependent value. fields[0] specifies the base register field <base>. */ | |
561a72d4 | 1480 | static bfd_boolean |
4df068de RS |
1481 | aarch64_ext_sve_addr_reg_imm (const aarch64_operand *self, |
1482 | aarch64_opnd_info *info, aarch64_insn code, | |
1483 | int64_t offset) | |
1484 | { | |
1485 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1486 | info->addr.offset.imm = offset * (1 << get_operand_specific_data (self)); | |
1487 | info->addr.offset.is_reg = FALSE; | |
1488 | info->addr.writeback = FALSE; | |
1489 | info->addr.preind = TRUE; | |
1490 | info->shifter.operator_present = FALSE; | |
1491 | info->shifter.amount_present = FALSE; | |
561a72d4 | 1492 | return TRUE; |
4df068de RS |
1493 | } |
1494 | ||
582e12bf RS |
1495 | /* Decode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4> |
1496 | is a 4-bit signed number and where <shift> is SELF's operand-dependent | |
1497 | value. fields[0] specifies the base register field. */ | |
561a72d4 | 1498 | bfd_boolean |
582e12bf RS |
1499 | aarch64_ext_sve_addr_ri_s4 (const aarch64_operand *self, |
1500 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1501 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1502 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
582e12bf RS |
1503 | { |
1504 | int offset = sign_extend (extract_field (FLD_SVE_imm4, code, 0), 3); | |
1505 | return aarch64_ext_sve_addr_reg_imm (self, info, code, offset); | |
1506 | } | |
1507 | ||
4df068de RS |
1508 | /* Decode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6> |
1509 | is a 6-bit unsigned number and where <shift> is SELF's operand-dependent | |
1510 | value. fields[0] specifies the base register field. */ | |
561a72d4 | 1511 | bfd_boolean |
4df068de RS |
1512 | aarch64_ext_sve_addr_ri_u6 (const aarch64_operand *self, |
1513 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1514 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1515 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de RS |
1516 | { |
1517 | int offset = extract_field (FLD_SVE_imm6, code, 0); | |
1518 | return aarch64_ext_sve_addr_reg_imm (self, info, code, offset); | |
1519 | } | |
1520 | ||
1521 | /* Decode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift> | |
1522 | is SELF's operand-dependent value. fields[0] specifies the base | |
1523 | register field and fields[1] specifies the offset register field. */ | |
561a72d4 | 1524 | bfd_boolean |
4df068de RS |
1525 | aarch64_ext_sve_addr_rr_lsl (const aarch64_operand *self, |
1526 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1527 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1528 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de | 1529 | { |
eaf02703 | 1530 | int index_regno; |
4df068de | 1531 | |
eaf02703 MR |
1532 | index_regno = extract_field (self->fields[1], code, 0); |
1533 | if (index_regno == 31 && (self->flags & OPD_F_NO_ZR) != 0) | |
561a72d4 | 1534 | return FALSE; |
4df068de RS |
1535 | |
1536 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
eaf02703 | 1537 | info->addr.offset.regno = index_regno; |
4df068de RS |
1538 | info->addr.offset.is_reg = TRUE; |
1539 | info->addr.writeback = FALSE; | |
1540 | info->addr.preind = TRUE; | |
1541 | info->shifter.kind = AARCH64_MOD_LSL; | |
1542 | info->shifter.amount = get_operand_specific_data (self); | |
1543 | info->shifter.operator_present = (info->shifter.amount != 0); | |
1544 | info->shifter.amount_present = (info->shifter.amount != 0); | |
561a72d4 | 1545 | return TRUE; |
4df068de RS |
1546 | } |
1547 | ||
1548 | /* Decode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where | |
1549 | <shift> is SELF's operand-dependent value. fields[0] specifies the | |
1550 | base register field, fields[1] specifies the offset register field and | |
1551 | fields[2] is a single-bit field that selects SXTW over UXTW. */ | |
561a72d4 | 1552 | bfd_boolean |
4df068de RS |
1553 | aarch64_ext_sve_addr_rz_xtw (const aarch64_operand *self, |
1554 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1555 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1556 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de RS |
1557 | { |
1558 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1559 | info->addr.offset.regno = extract_field (self->fields[1], code, 0); | |
1560 | info->addr.offset.is_reg = TRUE; | |
1561 | info->addr.writeback = FALSE; | |
1562 | info->addr.preind = TRUE; | |
1563 | if (extract_field (self->fields[2], code, 0)) | |
1564 | info->shifter.kind = AARCH64_MOD_SXTW; | |
1565 | else | |
1566 | info->shifter.kind = AARCH64_MOD_UXTW; | |
1567 | info->shifter.amount = get_operand_specific_data (self); | |
1568 | info->shifter.operator_present = TRUE; | |
1569 | info->shifter.amount_present = (info->shifter.amount != 0); | |
561a72d4 | 1570 | return TRUE; |
4df068de RS |
1571 | } |
1572 | ||
1573 | /* Decode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a | |
1574 | 5-bit unsigned number and where <shift> is SELF's operand-dependent value. | |
1575 | fields[0] specifies the base register field. */ | |
561a72d4 | 1576 | bfd_boolean |
4df068de RS |
1577 | aarch64_ext_sve_addr_zi_u5 (const aarch64_operand *self, |
1578 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1579 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1580 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de RS |
1581 | { |
1582 | int offset = extract_field (FLD_imm5, code, 0); | |
1583 | return aarch64_ext_sve_addr_reg_imm (self, info, code, offset); | |
1584 | } | |
1585 | ||
1586 | /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, <modifier> {#<msz>}}], | |
1587 | where <modifier> is given by KIND and where <msz> is a 2-bit unsigned | |
1588 | number. fields[0] specifies the base register field and fields[1] | |
1589 | specifies the offset register field. */ | |
561a72d4 | 1590 | static bfd_boolean |
4df068de RS |
1591 | aarch64_ext_sve_addr_zz (const aarch64_operand *self, aarch64_opnd_info *info, |
1592 | aarch64_insn code, enum aarch64_modifier_kind kind) | |
1593 | { | |
1594 | info->addr.base_regno = extract_field (self->fields[0], code, 0); | |
1595 | info->addr.offset.regno = extract_field (self->fields[1], code, 0); | |
1596 | info->addr.offset.is_reg = TRUE; | |
1597 | info->addr.writeback = FALSE; | |
1598 | info->addr.preind = TRUE; | |
1599 | info->shifter.kind = kind; | |
1600 | info->shifter.amount = extract_field (FLD_SVE_msz, code, 0); | |
1601 | info->shifter.operator_present = (kind != AARCH64_MOD_LSL | |
1602 | || info->shifter.amount != 0); | |
1603 | info->shifter.amount_present = (info->shifter.amount != 0); | |
561a72d4 | 1604 | return TRUE; |
4df068de RS |
1605 | } |
1606 | ||
1607 | /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where | |
1608 | <msz> is a 2-bit unsigned number. fields[0] specifies the base register | |
1609 | field and fields[1] specifies the offset register field. */ | |
561a72d4 | 1610 | bfd_boolean |
4df068de RS |
1611 | aarch64_ext_sve_addr_zz_lsl (const aarch64_operand *self, |
1612 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1613 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1614 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de RS |
1615 | { |
1616 | return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_LSL); | |
1617 | } | |
1618 | ||
1619 | /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where | |
1620 | <msz> is a 2-bit unsigned number. fields[0] specifies the base register | |
1621 | field and fields[1] specifies the offset register field. */ | |
561a72d4 | 1622 | bfd_boolean |
4df068de RS |
1623 | aarch64_ext_sve_addr_zz_sxtw (const aarch64_operand *self, |
1624 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1625 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1626 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de RS |
1627 | { |
1628 | return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_SXTW); | |
1629 | } | |
1630 | ||
1631 | /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where | |
1632 | <msz> is a 2-bit unsigned number. fields[0] specifies the base register | |
1633 | field and fields[1] specifies the offset register field. */ | |
561a72d4 | 1634 | bfd_boolean |
4df068de RS |
1635 | aarch64_ext_sve_addr_zz_uxtw (const aarch64_operand *self, |
1636 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1637 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1638 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
4df068de RS |
1639 | { |
1640 | return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_UXTW); | |
1641 | } | |
1642 | ||
e950b345 RS |
1643 | /* Finish decoding an SVE arithmetic immediate, given that INFO already |
1644 | has the raw field value and that the low 8 bits decode to VALUE. */ | |
561a72d4 | 1645 | static bfd_boolean |
e950b345 RS |
1646 | decode_sve_aimm (aarch64_opnd_info *info, int64_t value) |
1647 | { | |
1648 | info->shifter.kind = AARCH64_MOD_LSL; | |
1649 | info->shifter.amount = 0; | |
1650 | if (info->imm.value & 0x100) | |
1651 | { | |
1652 | if (value == 0) | |
1653 | /* Decode 0x100 as #0, LSL #8. */ | |
1654 | info->shifter.amount = 8; | |
1655 | else | |
1656 | value *= 256; | |
1657 | } | |
1658 | info->shifter.operator_present = (info->shifter.amount != 0); | |
1659 | info->shifter.amount_present = (info->shifter.amount != 0); | |
1660 | info->imm.value = value; | |
561a72d4 | 1661 | return TRUE; |
e950b345 RS |
1662 | } |
1663 | ||
1664 | /* Decode an SVE ADD/SUB immediate. */ | |
561a72d4 | 1665 | bfd_boolean |
e950b345 RS |
1666 | aarch64_ext_sve_aimm (const aarch64_operand *self, |
1667 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
1668 | const aarch64_inst *inst, |
1669 | aarch64_operand_error *errors) | |
e950b345 | 1670 | { |
561a72d4 | 1671 | return (aarch64_ext_imm (self, info, code, inst, errors) |
e950b345 RS |
1672 | && decode_sve_aimm (info, (uint8_t) info->imm.value)); |
1673 | } | |
1674 | ||
1675 | /* Decode an SVE CPY/DUP immediate. */ | |
561a72d4 | 1676 | bfd_boolean |
e950b345 RS |
1677 | aarch64_ext_sve_asimm (const aarch64_operand *self, |
1678 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
1679 | const aarch64_inst *inst, |
1680 | aarch64_operand_error *errors) | |
e950b345 | 1681 | { |
561a72d4 | 1682 | return (aarch64_ext_imm (self, info, code, inst, errors) |
e950b345 RS |
1683 | && decode_sve_aimm (info, (int8_t) info->imm.value)); |
1684 | } | |
1685 | ||
165d4950 RS |
1686 | /* Decode a single-bit immediate that selects between #0.5 and #1.0. |
1687 | The fields array specifies which field to use. */ | |
561a72d4 | 1688 | bfd_boolean |
165d4950 RS |
1689 | aarch64_ext_sve_float_half_one (const aarch64_operand *self, |
1690 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1691 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1692 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
165d4950 RS |
1693 | { |
1694 | if (extract_field (self->fields[0], code, 0)) | |
1695 | info->imm.value = 0x3f800000; | |
1696 | else | |
1697 | info->imm.value = 0x3f000000; | |
1698 | info->imm.is_fp = TRUE; | |
561a72d4 | 1699 | return TRUE; |
165d4950 RS |
1700 | } |
1701 | ||
1702 | /* Decode a single-bit immediate that selects between #0.5 and #2.0. | |
1703 | The fields array specifies which field to use. */ | |
561a72d4 | 1704 | bfd_boolean |
165d4950 RS |
1705 | aarch64_ext_sve_float_half_two (const aarch64_operand *self, |
1706 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1707 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1708 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
165d4950 RS |
1709 | { |
1710 | if (extract_field (self->fields[0], code, 0)) | |
1711 | info->imm.value = 0x40000000; | |
1712 | else | |
1713 | info->imm.value = 0x3f000000; | |
1714 | info->imm.is_fp = TRUE; | |
561a72d4 | 1715 | return TRUE; |
165d4950 RS |
1716 | } |
1717 | ||
1718 | /* Decode a single-bit immediate that selects between #0.0 and #1.0. | |
1719 | The fields array specifies which field to use. */ | |
561a72d4 | 1720 | bfd_boolean |
165d4950 RS |
1721 | aarch64_ext_sve_float_zero_one (const aarch64_operand *self, |
1722 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1723 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1724 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
165d4950 RS |
1725 | { |
1726 | if (extract_field (self->fields[0], code, 0)) | |
1727 | info->imm.value = 0x3f800000; | |
1728 | else | |
1729 | info->imm.value = 0x0; | |
1730 | info->imm.is_fp = TRUE; | |
561a72d4 | 1731 | return TRUE; |
165d4950 RS |
1732 | } |
1733 | ||
f11ad6bc RS |
1734 | /* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields |
1735 | array specifies which field to use for Zn. MM is encoded in the | |
1736 | concatenation of imm5 and SVE_tszh, with imm5 being the less | |
1737 | significant part. */ | |
561a72d4 | 1738 | bfd_boolean |
f11ad6bc RS |
1739 | aarch64_ext_sve_index (const aarch64_operand *self, |
1740 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1741 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1742 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
f11ad6bc RS |
1743 | { |
1744 | int val; | |
1745 | ||
1746 | info->reglane.regno = extract_field (self->fields[0], code, 0); | |
1747 | val = extract_fields (code, 0, 2, FLD_SVE_tszh, FLD_imm5); | |
582e12bf | 1748 | if ((val & 31) == 0) |
f11ad6bc RS |
1749 | return 0; |
1750 | while ((val & 1) == 0) | |
1751 | val /= 2; | |
1752 | info->reglane.index = val / 2; | |
561a72d4 | 1753 | return TRUE; |
f11ad6bc RS |
1754 | } |
1755 | ||
e950b345 | 1756 | /* Decode a logical immediate for the MOV alias of SVE DUPM. */ |
561a72d4 | 1757 | bfd_boolean |
e950b345 RS |
1758 | aarch64_ext_sve_limm_mov (const aarch64_operand *self, |
1759 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 TC |
1760 | const aarch64_inst *inst, |
1761 | aarch64_operand_error *errors) | |
e950b345 RS |
1762 | { |
1763 | int esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier); | |
561a72d4 | 1764 | return (aarch64_ext_limm (self, info, code, inst, errors) |
e950b345 RS |
1765 | && aarch64_sve_dupm_mov_immediate_p (info->imm.value, esize)); |
1766 | } | |
1767 | ||
582e12bf RS |
1768 | /* Decode Zn[MM], where Zn occupies the least-significant part of the field |
1769 | and where MM occupies the most-significant part. The operand-dependent | |
1770 | value specifies the number of bits in Zn. */ | |
561a72d4 | 1771 | bfd_boolean |
582e12bf RS |
1772 | aarch64_ext_sve_quad_index (const aarch64_operand *self, |
1773 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1774 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1775 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
582e12bf RS |
1776 | { |
1777 | unsigned int reg_bits = get_operand_specific_data (self); | |
1778 | unsigned int val = extract_all_fields (self, code); | |
1779 | info->reglane.regno = val & ((1 << reg_bits) - 1); | |
1780 | info->reglane.index = val >> reg_bits; | |
561a72d4 | 1781 | return TRUE; |
582e12bf RS |
1782 | } |
1783 | ||
f11ad6bc RS |
1784 | /* Decode {Zn.<T> - Zm.<T>}. The fields array specifies which field |
1785 | to use for Zn. The opcode-dependent value specifies the number | |
1786 | of registers in the list. */ | |
561a72d4 | 1787 | bfd_boolean |
f11ad6bc RS |
1788 | aarch64_ext_sve_reglist (const aarch64_operand *self, |
1789 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 TC |
1790 | const aarch64_inst *inst ATTRIBUTE_UNUSED, |
1791 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
f11ad6bc RS |
1792 | { |
1793 | info->reglist.first_regno = extract_field (self->fields[0], code, 0); | |
1794 | info->reglist.num_regs = get_opcode_dependent_value (inst->opcode); | |
561a72d4 | 1795 | return TRUE; |
f11ad6bc | 1796 | } |
2442d846 RS |
1797 | |
1798 | /* Decode <pattern>{, MUL #<amount>}. The fields array specifies which | |
1799 | fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4 | |
1800 | field. */ | |
561a72d4 | 1801 | bfd_boolean |
2442d846 RS |
1802 | aarch64_ext_sve_scale (const aarch64_operand *self, |
1803 | aarch64_opnd_info *info, aarch64_insn code, | |
561a72d4 | 1804 | const aarch64_inst *inst, aarch64_operand_error *errors) |
2442d846 RS |
1805 | { |
1806 | int val; | |
1807 | ||
561a72d4 TC |
1808 | if (!aarch64_ext_imm (self, info, code, inst, errors)) |
1809 | return FALSE; | |
2442d846 RS |
1810 | val = extract_field (FLD_SVE_imm4, code, 0); |
1811 | info->shifter.kind = AARCH64_MOD_MUL; | |
1812 | info->shifter.amount = val + 1; | |
1813 | info->shifter.operator_present = (val != 0); | |
1814 | info->shifter.amount_present = (val != 0); | |
561a72d4 | 1815 | return TRUE; |
2442d846 | 1816 | } |
e950b345 RS |
1817 | |
1818 | /* Return the top set bit in VALUE, which is expected to be relatively | |
1819 | small. */ | |
1820 | static uint64_t | |
1821 | get_top_bit (uint64_t value) | |
1822 | { | |
1823 | while ((value & -value) != value) | |
1824 | value -= value & -value; | |
1825 | return value; | |
1826 | } | |
1827 | ||
1828 | /* Decode an SVE shift-left immediate. */ | |
561a72d4 | 1829 | bfd_boolean |
e950b345 RS |
1830 | aarch64_ext_sve_shlimm (const aarch64_operand *self, |
1831 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 | 1832 | const aarch64_inst *inst, aarch64_operand_error *errors) |
e950b345 | 1833 | { |
561a72d4 | 1834 | if (!aarch64_ext_imm (self, info, code, inst, errors) |
e950b345 | 1835 | || info->imm.value == 0) |
561a72d4 | 1836 | return FALSE; |
e950b345 RS |
1837 | |
1838 | info->imm.value -= get_top_bit (info->imm.value); | |
561a72d4 | 1839 | return TRUE; |
e950b345 RS |
1840 | } |
1841 | ||
1842 | /* Decode an SVE shift-right immediate. */ | |
561a72d4 | 1843 | bfd_boolean |
e950b345 RS |
1844 | aarch64_ext_sve_shrimm (const aarch64_operand *self, |
1845 | aarch64_opnd_info *info, const aarch64_insn code, | |
561a72d4 | 1846 | const aarch64_inst *inst, aarch64_operand_error *errors) |
e950b345 | 1847 | { |
561a72d4 | 1848 | if (!aarch64_ext_imm (self, info, code, inst, errors) |
e950b345 | 1849 | || info->imm.value == 0) |
561a72d4 | 1850 | return FALSE; |
e950b345 RS |
1851 | |
1852 | info->imm.value = get_top_bit (info->imm.value) * 2 - info->imm.value; | |
561a72d4 | 1853 | return TRUE; |
e950b345 | 1854 | } |
a06ea964 NC |
1855 | \f |
1856 | /* Bitfields that are commonly used to encode certain operands' information | |
1857 | may be partially used as part of the base opcode in some instructions. | |
1858 | For example, the bit 1 of the field 'size' in | |
1859 | FCVTXN <Vb><d>, <Va><n> | |
1860 | is actually part of the base opcode, while only size<0> is available | |
1861 | for encoding the register type. Another example is the AdvSIMD | |
1862 | instruction ORR (register), in which the field 'size' is also used for | |
1863 | the base opcode, leaving only the field 'Q' available to encode the | |
1864 | vector register arrangement specifier '8B' or '16B'. | |
1865 | ||
1866 | This function tries to deduce the qualifier from the value of partially | |
1867 | constrained field(s). Given the VALUE of such a field or fields, the | |
1868 | qualifiers CANDIDATES and the MASK (indicating which bits are valid for | |
1869 | operand encoding), the function returns the matching qualifier or | |
1870 | AARCH64_OPND_QLF_NIL if nothing matches. | |
1871 | ||
1872 | N.B. CANDIDATES is a group of possible qualifiers that are valid for | |
1873 | one operand; it has a maximum of AARCH64_MAX_QLF_SEQ_NUM qualifiers and | |
1874 | may end with AARCH64_OPND_QLF_NIL. */ | |
1875 | ||
1876 | static enum aarch64_opnd_qualifier | |
1877 | get_qualifier_from_partial_encoding (aarch64_insn value, | |
1878 | const enum aarch64_opnd_qualifier* \ | |
1879 | candidates, | |
1880 | aarch64_insn mask) | |
1881 | { | |
1882 | int i; | |
1883 | DEBUG_TRACE ("enter with value: %d, mask: %d", (int)value, (int)mask); | |
1884 | for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i) | |
1885 | { | |
1886 | aarch64_insn standard_value; | |
1887 | if (candidates[i] == AARCH64_OPND_QLF_NIL) | |
1888 | break; | |
1889 | standard_value = aarch64_get_qualifier_standard_value (candidates[i]); | |
1890 | if ((standard_value & mask) == (value & mask)) | |
1891 | return candidates[i]; | |
1892 | } | |
1893 | return AARCH64_OPND_QLF_NIL; | |
1894 | } | |
1895 | ||
1896 | /* Given a list of qualifier sequences, return all possible valid qualifiers | |
1897 | for operand IDX in QUALIFIERS. | |
1898 | Assume QUALIFIERS is an array whose length is large enough. */ | |
1899 | ||
1900 | static void | |
1901 | get_operand_possible_qualifiers (int idx, | |
1902 | const aarch64_opnd_qualifier_seq_t *list, | |
1903 | enum aarch64_opnd_qualifier *qualifiers) | |
1904 | { | |
1905 | int i; | |
1906 | for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i) | |
1907 | if ((qualifiers[i] = list[i][idx]) == AARCH64_OPND_QLF_NIL) | |
1908 | break; | |
1909 | } | |
1910 | ||
1911 | /* Decode the size Q field for e.g. SHADD. | |
1912 | We tag one operand with the qualifer according to the code; | |
1913 | whether the qualifier is valid for this opcode or not, it is the | |
1914 | duty of the semantic checking. */ | |
1915 | ||
1916 | static int | |
1917 | decode_sizeq (aarch64_inst *inst) | |
1918 | { | |
1919 | int idx; | |
1920 | enum aarch64_opnd_qualifier qualifier; | |
1921 | aarch64_insn code; | |
1922 | aarch64_insn value, mask; | |
1923 | enum aarch64_field_kind fld_sz; | |
1924 | enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM]; | |
1925 | ||
1926 | if (inst->opcode->iclass == asisdlse | |
1927 | || inst->opcode->iclass == asisdlsep | |
1928 | || inst->opcode->iclass == asisdlso | |
1929 | || inst->opcode->iclass == asisdlsop) | |
1930 | fld_sz = FLD_vldst_size; | |
1931 | else | |
1932 | fld_sz = FLD_size; | |
1933 | ||
1934 | code = inst->value; | |
1935 | value = extract_fields (code, inst->opcode->mask, 2, fld_sz, FLD_Q); | |
1936 | /* Obtain the info that which bits of fields Q and size are actually | |
1937 | available for operand encoding. Opcodes like FMAXNM and FMLA have | |
1938 | size[1] unavailable. */ | |
1939 | mask = extract_fields (~inst->opcode->mask, 0, 2, fld_sz, FLD_Q); | |
1940 | ||
1941 | /* The index of the operand we are going to tag a qualifier and the qualifer | |
1942 | itself are reasoned from the value of the size and Q fields and the | |
1943 | possible valid qualifier lists. */ | |
1944 | idx = aarch64_select_operand_for_sizeq_field_coding (inst->opcode); | |
1945 | DEBUG_TRACE ("key idx: %d", idx); | |
1946 | ||
1947 | /* For most related instruciton, size:Q are fully available for operand | |
1948 | encoding. */ | |
1949 | if (mask == 0x7) | |
1950 | { | |
1951 | inst->operands[idx].qualifier = get_vreg_qualifier_from_value (value); | |
1952 | return 1; | |
1953 | } | |
1954 | ||
1955 | get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list, | |
1956 | candidates); | |
1957 | #ifdef DEBUG_AARCH64 | |
1958 | if (debug_dump) | |
1959 | { | |
1960 | int i; | |
1961 | for (i = 0; candidates[i] != AARCH64_OPND_QLF_NIL | |
1962 | && i < AARCH64_MAX_QLF_SEQ_NUM; ++i) | |
1963 | DEBUG_TRACE ("qualifier %d: %s", i, | |
1964 | aarch64_get_qualifier_name(candidates[i])); | |
1965 | DEBUG_TRACE ("%d, %d", (int)value, (int)mask); | |
1966 | } | |
1967 | #endif /* DEBUG_AARCH64 */ | |
1968 | ||
1969 | qualifier = get_qualifier_from_partial_encoding (value, candidates, mask); | |
1970 | ||
1971 | if (qualifier == AARCH64_OPND_QLF_NIL) | |
1972 | return 0; | |
1973 | ||
1974 | inst->operands[idx].qualifier = qualifier; | |
1975 | return 1; | |
1976 | } | |
1977 | ||
1978 | /* Decode size[0]:Q, i.e. bit 22 and bit 30, for | |
1979 | e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
1980 | ||
1981 | static int | |
1982 | decode_asimd_fcvt (aarch64_inst *inst) | |
1983 | { | |
1984 | aarch64_field field = {0, 0}; | |
1985 | aarch64_insn value; | |
1986 | enum aarch64_opnd_qualifier qualifier; | |
1987 | ||
1988 | gen_sub_field (FLD_size, 0, 1, &field); | |
1989 | value = extract_field_2 (&field, inst->value, 0); | |
1990 | qualifier = value == 0 ? AARCH64_OPND_QLF_V_4S | |
1991 | : AARCH64_OPND_QLF_V_2D; | |
1992 | switch (inst->opcode->op) | |
1993 | { | |
1994 | case OP_FCVTN: | |
1995 | case OP_FCVTN2: | |
1996 | /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */ | |
1997 | inst->operands[1].qualifier = qualifier; | |
1998 | break; | |
1999 | case OP_FCVTL: | |
2000 | case OP_FCVTL2: | |
2001 | /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */ | |
2002 | inst->operands[0].qualifier = qualifier; | |
2003 | break; | |
2004 | default: | |
2005 | assert (0); | |
2006 | return 0; | |
2007 | } | |
2008 | ||
2009 | return 1; | |
2010 | } | |
2011 | ||
2012 | /* Decode size[0], i.e. bit 22, for | |
2013 | e.g. FCVTXN <Vb><d>, <Va><n>. */ | |
2014 | ||
2015 | static int | |
2016 | decode_asisd_fcvtxn (aarch64_inst *inst) | |
2017 | { | |
2018 | aarch64_field field = {0, 0}; | |
2019 | gen_sub_field (FLD_size, 0, 1, &field); | |
2020 | if (!extract_field_2 (&field, inst->value, 0)) | |
2021 | return 0; | |
2022 | inst->operands[0].qualifier = AARCH64_OPND_QLF_S_S; | |
2023 | return 1; | |
2024 | } | |
2025 | ||
2026 | /* Decode the 'opc' field for e.g. FCVT <Dd>, <Sn>. */ | |
2027 | static int | |
2028 | decode_fcvt (aarch64_inst *inst) | |
2029 | { | |
2030 | enum aarch64_opnd_qualifier qualifier; | |
2031 | aarch64_insn value; | |
2032 | const aarch64_field field = {15, 2}; | |
2033 | ||
2034 | /* opc dstsize */ | |
2035 | value = extract_field_2 (&field, inst->value, 0); | |
2036 | switch (value) | |
2037 | { | |
2038 | case 0: qualifier = AARCH64_OPND_QLF_S_S; break; | |
2039 | case 1: qualifier = AARCH64_OPND_QLF_S_D; break; | |
2040 | case 3: qualifier = AARCH64_OPND_QLF_S_H; break; | |
2041 | default: return 0; | |
2042 | } | |
2043 | inst->operands[0].qualifier = qualifier; | |
2044 | ||
2045 | return 1; | |
2046 | } | |
2047 | ||
2048 | /* Do miscellaneous decodings that are not common enough to be driven by | |
2049 | flags. */ | |
2050 | ||
2051 | static int | |
2052 | do_misc_decoding (aarch64_inst *inst) | |
2053 | { | |
c0890d26 | 2054 | unsigned int value; |
a06ea964 NC |
2055 | switch (inst->opcode->op) |
2056 | { | |
2057 | case OP_FCVT: | |
2058 | return decode_fcvt (inst); | |
c0890d26 | 2059 | |
a06ea964 NC |
2060 | case OP_FCVTN: |
2061 | case OP_FCVTN2: | |
2062 | case OP_FCVTL: | |
2063 | case OP_FCVTL2: | |
2064 | return decode_asimd_fcvt (inst); | |
c0890d26 | 2065 | |
a06ea964 NC |
2066 | case OP_FCVTXN_S: |
2067 | return decode_asisd_fcvtxn (inst); | |
c0890d26 RS |
2068 | |
2069 | case OP_MOV_P_P: | |
2070 | case OP_MOVS_P_P: | |
2071 | value = extract_field (FLD_SVE_Pn, inst->value, 0); | |
2072 | return (value == extract_field (FLD_SVE_Pm, inst->value, 0) | |
2073 | && value == extract_field (FLD_SVE_Pg4_10, inst->value, 0)); | |
2074 | ||
2075 | case OP_MOV_Z_P_Z: | |
2076 | return (extract_field (FLD_SVE_Zd, inst->value, 0) | |
2077 | == extract_field (FLD_SVE_Zm_16, inst->value, 0)); | |
2078 | ||
2079 | case OP_MOV_Z_V: | |
2080 | /* Index must be zero. */ | |
2081 | value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5); | |
582e12bf | 2082 | return value > 0 && value <= 16 && value == (value & -value); |
c0890d26 RS |
2083 | |
2084 | case OP_MOV_Z_Z: | |
2085 | return (extract_field (FLD_SVE_Zn, inst->value, 0) | |
2086 | == extract_field (FLD_SVE_Zm_16, inst->value, 0)); | |
2087 | ||
2088 | case OP_MOV_Z_Zi: | |
2089 | /* Index must be nonzero. */ | |
2090 | value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5); | |
582e12bf | 2091 | return value > 0 && value != (value & -value); |
c0890d26 RS |
2092 | |
2093 | case OP_MOVM_P_P_P: | |
2094 | return (extract_field (FLD_SVE_Pd, inst->value, 0) | |
2095 | == extract_field (FLD_SVE_Pm, inst->value, 0)); | |
2096 | ||
2097 | case OP_MOVZS_P_P_P: | |
2098 | case OP_MOVZ_P_P_P: | |
2099 | return (extract_field (FLD_SVE_Pn, inst->value, 0) | |
2100 | == extract_field (FLD_SVE_Pm, inst->value, 0)); | |
2101 | ||
2102 | case OP_NOTS_P_P_P_Z: | |
2103 | case OP_NOT_P_P_P_Z: | |
2104 | return (extract_field (FLD_SVE_Pm, inst->value, 0) | |
2105 | == extract_field (FLD_SVE_Pg4_10, inst->value, 0)); | |
2106 | ||
a06ea964 NC |
2107 | default: |
2108 | return 0; | |
2109 | } | |
2110 | } | |
2111 | ||
2112 | /* Opcodes that have fields shared by multiple operands are usually flagged | |
2113 | with flags. In this function, we detect such flags, decode the related | |
2114 | field(s) and store the information in one of the related operands. The | |
2115 | 'one' operand is not any operand but one of the operands that can | |
2116 | accommadate all the information that has been decoded. */ | |
2117 | ||
2118 | static int | |
2119 | do_special_decoding (aarch64_inst *inst) | |
2120 | { | |
2121 | int idx; | |
2122 | aarch64_insn value; | |
2123 | /* Condition for truly conditional executed instructions, e.g. b.cond. */ | |
2124 | if (inst->opcode->flags & F_COND) | |
2125 | { | |
2126 | value = extract_field (FLD_cond2, inst->value, 0); | |
2127 | inst->cond = get_cond_from_value (value); | |
2128 | } | |
2129 | /* 'sf' field. */ | |
2130 | if (inst->opcode->flags & F_SF) | |
2131 | { | |
2132 | idx = select_operand_for_sf_field_coding (inst->opcode); | |
2133 | value = extract_field (FLD_sf, inst->value, 0); | |
2134 | inst->operands[idx].qualifier = get_greg_qualifier_from_value (value); | |
2135 | if ((inst->opcode->flags & F_N) | |
2136 | && extract_field (FLD_N, inst->value, 0) != value) | |
2137 | return 0; | |
2138 | } | |
ee804238 JW |
2139 | /* 'sf' field. */ |
2140 | if (inst->opcode->flags & F_LSE_SZ) | |
2141 | { | |
2142 | idx = select_operand_for_sf_field_coding (inst->opcode); | |
2143 | value = extract_field (FLD_lse_sz, inst->value, 0); | |
2144 | inst->operands[idx].qualifier = get_greg_qualifier_from_value (value); | |
2145 | } | |
a06ea964 NC |
2146 | /* size:Q fields. */ |
2147 | if (inst->opcode->flags & F_SIZEQ) | |
2148 | return decode_sizeq (inst); | |
2149 | ||
2150 | if (inst->opcode->flags & F_FPTYPE) | |
2151 | { | |
2152 | idx = select_operand_for_fptype_field_coding (inst->opcode); | |
2153 | value = extract_field (FLD_type, inst->value, 0); | |
2154 | switch (value) | |
2155 | { | |
2156 | case 0: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_S; break; | |
2157 | case 1: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_D; break; | |
2158 | case 3: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_H; break; | |
2159 | default: return 0; | |
2160 | } | |
2161 | } | |
2162 | ||
2163 | if (inst->opcode->flags & F_SSIZE) | |
2164 | { | |
2165 | /* N.B. some opcodes like FCMGT <V><d>, <V><n>, #0 have the size[1] as part | |
2166 | of the base opcode. */ | |
2167 | aarch64_insn mask; | |
2168 | enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM]; | |
2169 | idx = select_operand_for_scalar_size_field_coding (inst->opcode); | |
2170 | value = extract_field (FLD_size, inst->value, inst->opcode->mask); | |
2171 | mask = extract_field (FLD_size, ~inst->opcode->mask, 0); | |
2172 | /* For most related instruciton, the 'size' field is fully available for | |
2173 | operand encoding. */ | |
2174 | if (mask == 0x3) | |
2175 | inst->operands[idx].qualifier = get_sreg_qualifier_from_value (value); | |
2176 | else | |
2177 | { | |
2178 | get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list, | |
2179 | candidates); | |
2180 | inst->operands[idx].qualifier | |
2181 | = get_qualifier_from_partial_encoding (value, candidates, mask); | |
2182 | } | |
2183 | } | |
2184 | ||
2185 | if (inst->opcode->flags & F_T) | |
2186 | { | |
2187 | /* Num of consecutive '0's on the right side of imm5<3:0>. */ | |
2188 | int num = 0; | |
2189 | unsigned val, Q; | |
2190 | assert (aarch64_get_operand_class (inst->opcode->operands[0]) | |
2191 | == AARCH64_OPND_CLASS_SIMD_REG); | |
2192 | /* imm5<3:0> q <t> | |
2193 | 0000 x reserved | |
2194 | xxx1 0 8b | |
2195 | xxx1 1 16b | |
2196 | xx10 0 4h | |
2197 | xx10 1 8h | |
2198 | x100 0 2s | |
2199 | x100 1 4s | |
2200 | 1000 0 reserved | |
2201 | 1000 1 2d */ | |
2202 | val = extract_field (FLD_imm5, inst->value, 0); | |
2203 | while ((val & 0x1) == 0 && ++num <= 3) | |
2204 | val >>= 1; | |
2205 | if (num > 3) | |
2206 | return 0; | |
2207 | Q = (unsigned) extract_field (FLD_Q, inst->value, inst->opcode->mask); | |
2208 | inst->operands[0].qualifier = | |
2209 | get_vreg_qualifier_from_value ((num << 1) | Q); | |
2210 | } | |
2211 | ||
2212 | if (inst->opcode->flags & F_GPRSIZE_IN_Q) | |
2213 | { | |
2214 | /* Use Rt to encode in the case of e.g. | |
2215 | STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */ | |
2216 | idx = aarch64_operand_index (inst->opcode->operands, AARCH64_OPND_Rt); | |
2217 | if (idx == -1) | |
2218 | { | |
2219 | /* Otherwise use the result operand, which has to be a integer | |
2220 | register. */ | |
2221 | assert (aarch64_get_operand_class (inst->opcode->operands[0]) | |
2222 | == AARCH64_OPND_CLASS_INT_REG); | |
2223 | idx = 0; | |
2224 | } | |
2225 | assert (idx == 0 || idx == 1); | |
2226 | value = extract_field (FLD_Q, inst->value, 0); | |
2227 | inst->operands[idx].qualifier = get_greg_qualifier_from_value (value); | |
2228 | } | |
2229 | ||
2230 | if (inst->opcode->flags & F_LDS_SIZE) | |
2231 | { | |
2232 | aarch64_field field = {0, 0}; | |
2233 | assert (aarch64_get_operand_class (inst->opcode->operands[0]) | |
2234 | == AARCH64_OPND_CLASS_INT_REG); | |
2235 | gen_sub_field (FLD_opc, 0, 1, &field); | |
2236 | value = extract_field_2 (&field, inst->value, 0); | |
2237 | inst->operands[0].qualifier | |
2238 | = value ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X; | |
2239 | } | |
2240 | ||
2241 | /* Miscellaneous decoding; done as the last step. */ | |
2242 | if (inst->opcode->flags & F_MISC) | |
2243 | return do_misc_decoding (inst); | |
2244 | ||
2245 | return 1; | |
2246 | } | |
2247 | ||
2248 | /* Converters converting a real opcode instruction to its alias form. */ | |
2249 | ||
2250 | /* ROR <Wd>, <Ws>, #<shift> | |
2251 | is equivalent to: | |
2252 | EXTR <Wd>, <Ws>, <Ws>, #<shift>. */ | |
2253 | static int | |
2254 | convert_extr_to_ror (aarch64_inst *inst) | |
2255 | { | |
2256 | if (inst->operands[1].reg.regno == inst->operands[2].reg.regno) | |
2257 | { | |
2258 | copy_operand_info (inst, 2, 3); | |
2259 | inst->operands[3].type = AARCH64_OPND_NIL; | |
2260 | return 1; | |
2261 | } | |
2262 | return 0; | |
2263 | } | |
2264 | ||
e30181a5 YZ |
2265 | /* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb> |
2266 | is equivalent to: | |
2267 | USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */ | |
2268 | static int | |
2269 | convert_shll_to_xtl (aarch64_inst *inst) | |
2270 | { | |
2271 | if (inst->operands[2].imm.value == 0) | |
2272 | { | |
2273 | inst->operands[2].type = AARCH64_OPND_NIL; | |
2274 | return 1; | |
2275 | } | |
2276 | return 0; | |
2277 | } | |
2278 | ||
a06ea964 NC |
2279 | /* Convert |
2280 | UBFM <Xd>, <Xn>, #<shift>, #63. | |
2281 | to | |
2282 | LSR <Xd>, <Xn>, #<shift>. */ | |
2283 | static int | |
2284 | convert_bfm_to_sr (aarch64_inst *inst) | |
2285 | { | |
2286 | int64_t imms, val; | |
2287 | ||
2288 | imms = inst->operands[3].imm.value; | |
2289 | val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63; | |
2290 | if (imms == val) | |
2291 | { | |
2292 | inst->operands[3].type = AARCH64_OPND_NIL; | |
2293 | return 1; | |
2294 | } | |
2295 | ||
2296 | return 0; | |
2297 | } | |
2298 | ||
2299 | /* Convert MOV to ORR. */ | |
2300 | static int | |
2301 | convert_orr_to_mov (aarch64_inst *inst) | |
2302 | { | |
2303 | /* MOV <Vd>.<T>, <Vn>.<T> | |
2304 | is equivalent to: | |
2305 | ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>. */ | |
2306 | if (inst->operands[1].reg.regno == inst->operands[2].reg.regno) | |
2307 | { | |
2308 | inst->operands[2].type = AARCH64_OPND_NIL; | |
2309 | return 1; | |
2310 | } | |
2311 | return 0; | |
2312 | } | |
2313 | ||
2314 | /* When <imms> >= <immr>, the instruction written: | |
2315 | SBFX <Xd>, <Xn>, #<lsb>, #<width> | |
2316 | is equivalent to: | |
2317 | SBFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1). */ | |
2318 | ||
2319 | static int | |
2320 | convert_bfm_to_bfx (aarch64_inst *inst) | |
2321 | { | |
2322 | int64_t immr, imms; | |
2323 | ||
2324 | immr = inst->operands[2].imm.value; | |
2325 | imms = inst->operands[3].imm.value; | |
2326 | if (imms >= immr) | |
2327 | { | |
2328 | int64_t lsb = immr; | |
2329 | inst->operands[2].imm.value = lsb; | |
2330 | inst->operands[3].imm.value = imms + 1 - lsb; | |
2331 | /* The two opcodes have different qualifiers for | |
2332 | the immediate operands; reset to help the checking. */ | |
2333 | reset_operand_qualifier (inst, 2); | |
2334 | reset_operand_qualifier (inst, 3); | |
2335 | return 1; | |
2336 | } | |
2337 | ||
2338 | return 0; | |
2339 | } | |
2340 | ||
2341 | /* When <imms> < <immr>, the instruction written: | |
2342 | SBFIZ <Xd>, <Xn>, #<lsb>, #<width> | |
2343 | is equivalent to: | |
2344 | SBFM <Xd>, <Xn>, #((64-<lsb>)&0x3f), #(<width>-1). */ | |
2345 | ||
2346 | static int | |
2347 | convert_bfm_to_bfi (aarch64_inst *inst) | |
2348 | { | |
2349 | int64_t immr, imms, val; | |
2350 | ||
2351 | immr = inst->operands[2].imm.value; | |
2352 | imms = inst->operands[3].imm.value; | |
2353 | val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64; | |
2354 | if (imms < immr) | |
2355 | { | |
2356 | inst->operands[2].imm.value = (val - immr) & (val - 1); | |
2357 | inst->operands[3].imm.value = imms + 1; | |
2358 | /* The two opcodes have different qualifiers for | |
2359 | the immediate operands; reset to help the checking. */ | |
2360 | reset_operand_qualifier (inst, 2); | |
2361 | reset_operand_qualifier (inst, 3); | |
2362 | return 1; | |
2363 | } | |
2364 | ||
2365 | return 0; | |
2366 | } | |
2367 | ||
d685192a MW |
2368 | /* The instruction written: |
2369 | BFC <Xd>, #<lsb>, #<width> | |
2370 | is equivalent to: | |
2371 | BFM <Xd>, XZR, #((64-<lsb>)&0x3f), #(<width>-1). */ | |
2372 | ||
2373 | static int | |
2374 | convert_bfm_to_bfc (aarch64_inst *inst) | |
2375 | { | |
2376 | int64_t immr, imms, val; | |
2377 | ||
2378 | /* Should have been assured by the base opcode value. */ | |
2379 | assert (inst->operands[1].reg.regno == 0x1f); | |
2380 | ||
2381 | immr = inst->operands[2].imm.value; | |
2382 | imms = inst->operands[3].imm.value; | |
2383 | val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64; | |
2384 | if (imms < immr) | |
2385 | { | |
2386 | /* Drop XZR from the second operand. */ | |
2387 | copy_operand_info (inst, 1, 2); | |
2388 | copy_operand_info (inst, 2, 3); | |
2389 | inst->operands[3].type = AARCH64_OPND_NIL; | |
2390 | ||
2391 | /* Recalculate the immediates. */ | |
2392 | inst->operands[1].imm.value = (val - immr) & (val - 1); | |
2393 | inst->operands[2].imm.value = imms + 1; | |
2394 | ||
2395 | /* The two opcodes have different qualifiers for the operands; reset to | |
2396 | help the checking. */ | |
2397 | reset_operand_qualifier (inst, 1); | |
2398 | reset_operand_qualifier (inst, 2); | |
2399 | reset_operand_qualifier (inst, 3); | |
2400 | ||
2401 | return 1; | |
2402 | } | |
2403 | ||
2404 | return 0; | |
2405 | } | |
2406 | ||
a06ea964 NC |
2407 | /* The instruction written: |
2408 | LSL <Xd>, <Xn>, #<shift> | |
2409 | is equivalent to: | |
2410 | UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>). */ | |
2411 | ||
2412 | static int | |
2413 | convert_ubfm_to_lsl (aarch64_inst *inst) | |
2414 | { | |
2415 | int64_t immr = inst->operands[2].imm.value; | |
2416 | int64_t imms = inst->operands[3].imm.value; | |
2417 | int64_t val | |
2418 | = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63; | |
2419 | ||
2420 | if ((immr == 0 && imms == val) || immr == imms + 1) | |
2421 | { | |
2422 | inst->operands[3].type = AARCH64_OPND_NIL; | |
2423 | inst->operands[2].imm.value = val - imms; | |
2424 | return 1; | |
2425 | } | |
2426 | ||
2427 | return 0; | |
2428 | } | |
2429 | ||
2430 | /* CINC <Wd>, <Wn>, <cond> | |
2431 | is equivalent to: | |
68a64283 YZ |
2432 | CSINC <Wd>, <Wn>, <Wn>, invert(<cond>) |
2433 | where <cond> is not AL or NV. */ | |
a06ea964 NC |
2434 | |
2435 | static int | |
2436 | convert_from_csel (aarch64_inst *inst) | |
2437 | { | |
68a64283 YZ |
2438 | if (inst->operands[1].reg.regno == inst->operands[2].reg.regno |
2439 | && (inst->operands[3].cond->value & 0xe) != 0xe) | |
a06ea964 NC |
2440 | { |
2441 | copy_operand_info (inst, 2, 3); | |
2442 | inst->operands[2].cond = get_inverted_cond (inst->operands[3].cond); | |
2443 | inst->operands[3].type = AARCH64_OPND_NIL; | |
2444 | return 1; | |
2445 | } | |
2446 | return 0; | |
2447 | } | |
2448 | ||
2449 | /* CSET <Wd>, <cond> | |
2450 | is equivalent to: | |
68a64283 YZ |
2451 | CSINC <Wd>, WZR, WZR, invert(<cond>) |
2452 | where <cond> is not AL or NV. */ | |
a06ea964 NC |
2453 | |
2454 | static int | |
2455 | convert_csinc_to_cset (aarch64_inst *inst) | |
2456 | { | |
2457 | if (inst->operands[1].reg.regno == 0x1f | |
68a64283 YZ |
2458 | && inst->operands[2].reg.regno == 0x1f |
2459 | && (inst->operands[3].cond->value & 0xe) != 0xe) | |
a06ea964 NC |
2460 | { |
2461 | copy_operand_info (inst, 1, 3); | |
2462 | inst->operands[1].cond = get_inverted_cond (inst->operands[3].cond); | |
2463 | inst->operands[3].type = AARCH64_OPND_NIL; | |
2464 | inst->operands[2].type = AARCH64_OPND_NIL; | |
2465 | return 1; | |
2466 | } | |
2467 | return 0; | |
2468 | } | |
2469 | ||
2470 | /* MOV <Wd>, #<imm> | |
2471 | is equivalent to: | |
2472 | MOVZ <Wd>, #<imm16>, LSL #<shift>. | |
2473 | ||
2474 | A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when | |
2475 | ORR has an immediate that could be generated by a MOVZ or MOVN instruction, | |
2476 | or where a MOVN has an immediate that could be encoded by MOVZ, or where | |
2477 | MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the | |
2478 | machine-instruction mnemonic must be used. */ | |
2479 | ||
2480 | static int | |
2481 | convert_movewide_to_mov (aarch64_inst *inst) | |
2482 | { | |
2483 | uint64_t value = inst->operands[1].imm.value; | |
2484 | /* MOVZ/MOVN #0 have a shift amount other than LSL #0. */ | |
2485 | if (value == 0 && inst->operands[1].shifter.amount != 0) | |
2486 | return 0; | |
2487 | inst->operands[1].type = AARCH64_OPND_IMM_MOV; | |
2488 | inst->operands[1].shifter.kind = AARCH64_MOD_NONE; | |
2489 | value <<= inst->operands[1].shifter.amount; | |
2490 | /* As an alias convertor, it has to be clear that the INST->OPCODE | |
2491 | is the opcode of the real instruction. */ | |
2492 | if (inst->opcode->op == OP_MOVN) | |
2493 | { | |
2494 | int is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W; | |
2495 | value = ~value; | |
2496 | /* A MOVN has an immediate that could be encoded by MOVZ. */ | |
535b785f | 2497 | if (aarch64_wide_constant_p (value, is32, NULL)) |
a06ea964 NC |
2498 | return 0; |
2499 | } | |
2500 | inst->operands[1].imm.value = value; | |
2501 | inst->operands[1].shifter.amount = 0; | |
2502 | return 1; | |
2503 | } | |
2504 | ||
2505 | /* MOV <Wd>, #<imm> | |
2506 | is equivalent to: | |
2507 | ORR <Wd>, WZR, #<imm>. | |
2508 | ||
2509 | A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when | |
2510 | ORR has an immediate that could be generated by a MOVZ or MOVN instruction, | |
2511 | or where a MOVN has an immediate that could be encoded by MOVZ, or where | |
2512 | MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the | |
2513 | machine-instruction mnemonic must be used. */ | |
2514 | ||
2515 | static int | |
2516 | convert_movebitmask_to_mov (aarch64_inst *inst) | |
2517 | { | |
2518 | int is32; | |
2519 | uint64_t value; | |
2520 | ||
2521 | /* Should have been assured by the base opcode value. */ | |
2522 | assert (inst->operands[1].reg.regno == 0x1f); | |
2523 | copy_operand_info (inst, 1, 2); | |
2524 | is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W; | |
2525 | inst->operands[1].type = AARCH64_OPND_IMM_MOV; | |
2526 | value = inst->operands[1].imm.value; | |
2527 | /* ORR has an immediate that could be generated by a MOVZ or MOVN | |
2528 | instruction. */ | |
2529 | if (inst->operands[0].reg.regno != 0x1f | |
535b785f AM |
2530 | && (aarch64_wide_constant_p (value, is32, NULL) |
2531 | || aarch64_wide_constant_p (~value, is32, NULL))) | |
a06ea964 NC |
2532 | return 0; |
2533 | ||
2534 | inst->operands[2].type = AARCH64_OPND_NIL; | |
2535 | return 1; | |
2536 | } | |
2537 | ||
2538 | /* Some alias opcodes are disassembled by being converted from their real-form. | |
2539 | N.B. INST->OPCODE is the real opcode rather than the alias. */ | |
2540 | ||
2541 | static int | |
2542 | convert_to_alias (aarch64_inst *inst, const aarch64_opcode *alias) | |
2543 | { | |
2544 | switch (alias->op) | |
2545 | { | |
2546 | case OP_ASR_IMM: | |
2547 | case OP_LSR_IMM: | |
2548 | return convert_bfm_to_sr (inst); | |
2549 | case OP_LSL_IMM: | |
2550 | return convert_ubfm_to_lsl (inst); | |
2551 | case OP_CINC: | |
2552 | case OP_CINV: | |
2553 | case OP_CNEG: | |
2554 | return convert_from_csel (inst); | |
2555 | case OP_CSET: | |
2556 | case OP_CSETM: | |
2557 | return convert_csinc_to_cset (inst); | |
2558 | case OP_UBFX: | |
2559 | case OP_BFXIL: | |
2560 | case OP_SBFX: | |
2561 | return convert_bfm_to_bfx (inst); | |
2562 | case OP_SBFIZ: | |
2563 | case OP_BFI: | |
2564 | case OP_UBFIZ: | |
2565 | return convert_bfm_to_bfi (inst); | |
d685192a MW |
2566 | case OP_BFC: |
2567 | return convert_bfm_to_bfc (inst); | |
a06ea964 NC |
2568 | case OP_MOV_V: |
2569 | return convert_orr_to_mov (inst); | |
2570 | case OP_MOV_IMM_WIDE: | |
2571 | case OP_MOV_IMM_WIDEN: | |
2572 | return convert_movewide_to_mov (inst); | |
2573 | case OP_MOV_IMM_LOG: | |
2574 | return convert_movebitmask_to_mov (inst); | |
2575 | case OP_ROR_IMM: | |
2576 | return convert_extr_to_ror (inst); | |
e30181a5 YZ |
2577 | case OP_SXTL: |
2578 | case OP_SXTL2: | |
2579 | case OP_UXTL: | |
2580 | case OP_UXTL2: | |
2581 | return convert_shll_to_xtl (inst); | |
a06ea964 NC |
2582 | default: |
2583 | return 0; | |
2584 | } | |
2585 | } | |
2586 | ||
561a72d4 TC |
2587 | static bfd_boolean |
2588 | aarch64_opcode_decode (const aarch64_opcode *, const aarch64_insn, | |
2589 | aarch64_inst *, int, aarch64_operand_error *errors); | |
a06ea964 NC |
2590 | |
2591 | /* Given the instruction information in *INST, check if the instruction has | |
2592 | any alias form that can be used to represent *INST. If the answer is yes, | |
2593 | update *INST to be in the form of the determined alias. */ | |
2594 | ||
2595 | /* In the opcode description table, the following flags are used in opcode | |
2596 | entries to help establish the relations between the real and alias opcodes: | |
2597 | ||
2598 | F_ALIAS: opcode is an alias | |
2599 | F_HAS_ALIAS: opcode has alias(es) | |
2600 | F_P1 | |
2601 | F_P2 | |
2602 | F_P3: Disassembly preference priority 1-3 (the larger the | |
2603 | higher). If nothing is specified, it is the priority | |
2604 | 0 by default, i.e. the lowest priority. | |
2605 | ||
2606 | Although the relation between the machine and the alias instructions are not | |
2607 | explicitly described, it can be easily determined from the base opcode | |
2608 | values, masks and the flags F_ALIAS and F_HAS_ALIAS in their opcode | |
2609 | description entries: | |
2610 | ||
2611 | The mask of an alias opcode must be equal to or a super-set (i.e. more | |
2612 | constrained) of that of the aliased opcode; so is the base opcode value. | |
2613 | ||
2614 | if (opcode_has_alias (real) && alias_opcode_p (opcode) | |
2615 | && (opcode->mask & real->mask) == real->mask | |
2616 | && (real->mask & opcode->opcode) == (real->mask & real->opcode)) | |
2617 | then OPCODE is an alias of, and only of, the REAL instruction | |
2618 | ||
2619 | The alias relationship is forced flat-structured to keep related algorithm | |
2620 | simple; an opcode entry cannot be flagged with both F_ALIAS and F_HAS_ALIAS. | |
2621 | ||
2622 | During the disassembling, the decoding decision tree (in | |
2623 | opcodes/aarch64-dis-2.c) always returns an machine instruction opcode entry; | |
2624 | if the decoding of such a machine instruction succeeds (and -Mno-aliases is | |
2625 | not specified), the disassembler will check whether there is any alias | |
2626 | instruction exists for this real instruction. If there is, the disassembler | |
2627 | will try to disassemble the 32-bit binary again using the alias's rule, or | |
2628 | try to convert the IR to the form of the alias. In the case of the multiple | |
2629 | aliases, the aliases are tried one by one from the highest priority | |
2630 | (currently the flag F_P3) to the lowest priority (no priority flag), and the | |
2631 | first succeeds first adopted. | |
2632 | ||
2633 | You may ask why there is a need for the conversion of IR from one form to | |
2634 | another in handling certain aliases. This is because on one hand it avoids | |
2635 | adding more operand code to handle unusual encoding/decoding; on other | |
2636 | hand, during the disassembling, the conversion is an effective approach to | |
2637 | check the condition of an alias (as an alias may be adopted only if certain | |
2638 | conditions are met). | |
2639 | ||
2640 | In order to speed up the alias opcode lookup, aarch64-gen has preprocessed | |
2641 | aarch64_opcode_table and generated aarch64_find_alias_opcode and | |
2642 | aarch64_find_next_alias_opcode (in opcodes/aarch64-dis-2.c) to help. */ | |
2643 | ||
2644 | static void | |
561a72d4 TC |
2645 | determine_disassembling_preference (struct aarch64_inst *inst, |
2646 | aarch64_operand_error *errors) | |
a06ea964 NC |
2647 | { |
2648 | const aarch64_opcode *opcode; | |
2649 | const aarch64_opcode *alias; | |
2650 | ||
2651 | opcode = inst->opcode; | |
2652 | ||
2653 | /* This opcode does not have an alias, so use itself. */ | |
535b785f | 2654 | if (!opcode_has_alias (opcode)) |
a06ea964 NC |
2655 | return; |
2656 | ||
2657 | alias = aarch64_find_alias_opcode (opcode); | |
2658 | assert (alias); | |
2659 | ||
2660 | #ifdef DEBUG_AARCH64 | |
2661 | if (debug_dump) | |
2662 | { | |
2663 | const aarch64_opcode *tmp = alias; | |
2664 | printf ("#### LIST orderd: "); | |
2665 | while (tmp) | |
2666 | { | |
2667 | printf ("%s, ", tmp->name); | |
2668 | tmp = aarch64_find_next_alias_opcode (tmp); | |
2669 | } | |
2670 | printf ("\n"); | |
2671 | } | |
2672 | #endif /* DEBUG_AARCH64 */ | |
2673 | ||
2674 | for (; alias; alias = aarch64_find_next_alias_opcode (alias)) | |
2675 | { | |
2676 | DEBUG_TRACE ("try %s", alias->name); | |
35822b38 | 2677 | assert (alias_opcode_p (alias) || opcode_has_alias (opcode)); |
a06ea964 NC |
2678 | |
2679 | /* An alias can be a pseudo opcode which will never be used in the | |
2680 | disassembly, e.g. BIC logical immediate is such a pseudo opcode | |
2681 | aliasing AND. */ | |
2682 | if (pseudo_opcode_p (alias)) | |
2683 | { | |
2684 | DEBUG_TRACE ("skip pseudo %s", alias->name); | |
2685 | continue; | |
2686 | } | |
2687 | ||
2688 | if ((inst->value & alias->mask) != alias->opcode) | |
2689 | { | |
2690 | DEBUG_TRACE ("skip %s as base opcode not match", alias->name); | |
2691 | continue; | |
2692 | } | |
2693 | /* No need to do any complicated transformation on operands, if the alias | |
2694 | opcode does not have any operand. */ | |
2695 | if (aarch64_num_of_operands (alias) == 0 && alias->opcode == inst->value) | |
2696 | { | |
2697 | DEBUG_TRACE ("succeed with 0-operand opcode %s", alias->name); | |
2698 | aarch64_replace_opcode (inst, alias); | |
2699 | return; | |
2700 | } | |
2701 | if (alias->flags & F_CONV) | |
2702 | { | |
2703 | aarch64_inst copy; | |
2704 | memcpy (©, inst, sizeof (aarch64_inst)); | |
2705 | /* ALIAS is the preference as long as the instruction can be | |
2706 | successfully converted to the form of ALIAS. */ | |
2707 | if (convert_to_alias (©, alias) == 1) | |
2708 | { | |
2709 | aarch64_replace_opcode (©, alias); | |
2710 | assert (aarch64_match_operands_constraint (©, NULL)); | |
2711 | DEBUG_TRACE ("succeed with %s via conversion", alias->name); | |
2712 | memcpy (inst, ©, sizeof (aarch64_inst)); | |
2713 | return; | |
2714 | } | |
2715 | } | |
2716 | else | |
2717 | { | |
2718 | /* Directly decode the alias opcode. */ | |
2719 | aarch64_inst temp; | |
2720 | memset (&temp, '\0', sizeof (aarch64_inst)); | |
561a72d4 | 2721 | if (aarch64_opcode_decode (alias, inst->value, &temp, 1, errors) == 1) |
a06ea964 NC |
2722 | { |
2723 | DEBUG_TRACE ("succeed with %s via direct decoding", alias->name); | |
2724 | memcpy (inst, &temp, sizeof (aarch64_inst)); | |
2725 | return; | |
2726 | } | |
2727 | } | |
2728 | } | |
2729 | } | |
2730 | ||
116b6019 RS |
2731 | /* Some instructions (including all SVE ones) use the instruction class |
2732 | to describe how a qualifiers_list index is represented in the instruction | |
2733 | encoding. If INST is such an instruction, decode the appropriate fields | |
2734 | and fill in the operand qualifiers accordingly. Return true if no | |
2735 | problems are found. */ | |
2736 | ||
2737 | static bfd_boolean | |
2738 | aarch64_decode_variant_using_iclass (aarch64_inst *inst) | |
2739 | { | |
2740 | int i, variant; | |
2741 | ||
2742 | variant = 0; | |
2743 | switch (inst->opcode->iclass) | |
2744 | { | |
2745 | case sve_cpy: | |
2746 | variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_14); | |
2747 | break; | |
2748 | ||
2749 | case sve_index: | |
582e12bf RS |
2750 | i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5); |
2751 | if ((i & 31) == 0) | |
116b6019 RS |
2752 | return FALSE; |
2753 | while ((i & 1) == 0) | |
2754 | { | |
2755 | i >>= 1; | |
2756 | variant += 1; | |
2757 | } | |
2758 | break; | |
2759 | ||
2760 | case sve_limm: | |
2761 | /* Pick the smallest applicable element size. */ | |
2762 | if ((inst->value & 0x20600) == 0x600) | |
2763 | variant = 0; | |
2764 | else if ((inst->value & 0x20400) == 0x400) | |
2765 | variant = 1; | |
2766 | else if ((inst->value & 0x20000) == 0) | |
2767 | variant = 2; | |
2768 | else | |
2769 | variant = 3; | |
2770 | break; | |
2771 | ||
2772 | case sve_misc: | |
2773 | /* sve_misc instructions have only a single variant. */ | |
2774 | break; | |
2775 | ||
2776 | case sve_movprfx: | |
2777 | variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_16); | |
2778 | break; | |
2779 | ||
2780 | case sve_pred_zm: | |
2781 | variant = extract_field (FLD_SVE_M_4, inst->value, 0); | |
2782 | break; | |
2783 | ||
2784 | case sve_shift_pred: | |
2785 | i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_8); | |
2786 | sve_shift: | |
2787 | if (i == 0) | |
2788 | return FALSE; | |
2789 | while (i != 1) | |
2790 | { | |
2791 | i >>= 1; | |
2792 | variant += 1; | |
2793 | } | |
2794 | break; | |
2795 | ||
2796 | case sve_shift_unpred: | |
2797 | i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_19); | |
2798 | goto sve_shift; | |
2799 | ||
2800 | case sve_size_bhs: | |
2801 | variant = extract_field (FLD_size, inst->value, 0); | |
2802 | if (variant >= 3) | |
2803 | return FALSE; | |
2804 | break; | |
2805 | ||
2806 | case sve_size_bhsd: | |
2807 | variant = extract_field (FLD_size, inst->value, 0); | |
2808 | break; | |
2809 | ||
2810 | case sve_size_hsd: | |
2811 | i = extract_field (FLD_size, inst->value, 0); | |
2812 | if (i < 1) | |
2813 | return FALSE; | |
2814 | variant = i - 1; | |
2815 | break; | |
2816 | ||
3c705960 | 2817 | case sve_size_bh: |
116b6019 RS |
2818 | case sve_size_sd: |
2819 | variant = extract_field (FLD_SVE_sz, inst->value, 0); | |
2820 | break; | |
2821 | ||
0a57e14f MM |
2822 | case sve_size_sd2: |
2823 | variant = extract_field (FLD_SVE_sz2, inst->value, 0); | |
2824 | break; | |
2825 | ||
3bd82c86 MM |
2826 | case sve_size_hsd2: |
2827 | i = extract_field (FLD_SVE_size, inst->value, 0); | |
2828 | if (i < 1) | |
2829 | return FALSE; | |
2830 | variant = i - 1; | |
2831 | break; | |
2832 | ||
41be57ca MM |
2833 | case sve_size_13: |
2834 | /* Ignore low bit of this field since that is set in the opcode for | |
2835 | instructions of this iclass. */ | |
2836 | i = (extract_field (FLD_size, inst->value, 0) & 2); | |
2837 | variant = (i >> 1); | |
cd50a87a MM |
2838 | break; |
2839 | ||
1be5f94f MM |
2840 | case sve_shift_tsz_bhsd: |
2841 | i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_19); | |
2842 | if (i == 0) | |
2843 | return FALSE; | |
2844 | while (i != 1) | |
2845 | { | |
2846 | i >>= 1; | |
2847 | variant += 1; | |
2848 | } | |
2849 | break; | |
2850 | ||
fd1dc4a0 MM |
2851 | case sve_size_tsz_bhs: |
2852 | i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19); | |
9d48687b AM |
2853 | if (i == 0) |
2854 | return FALSE; | |
fd1dc4a0 MM |
2855 | while (i != 1) |
2856 | { | |
2857 | if (i & 1) | |
2858 | return FALSE; | |
2859 | i >>= 1; | |
2860 | variant += 1; | |
2861 | } | |
2862 | break; | |
2863 | ||
3c17238b MM |
2864 | case sve_shift_tsz_hsd: |
2865 | i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19); | |
2866 | if (i == 0) | |
2867 | return FALSE; | |
2868 | while (i != 1) | |
2869 | { | |
2870 | i >>= 1; | |
2871 | variant += 1; | |
2872 | } | |
2873 | break; | |
2874 | ||
116b6019 RS |
2875 | default: |
2876 | /* No mapping between instruction class and qualifiers. */ | |
2877 | return TRUE; | |
2878 | } | |
2879 | ||
2880 | for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) | |
2881 | inst->operands[i].qualifier = inst->opcode->qualifiers_list[variant][i]; | |
2882 | return TRUE; | |
2883 | } | |
a06ea964 NC |
2884 | /* Decode the CODE according to OPCODE; fill INST. Return 0 if the decoding |
2885 | fails, which meanes that CODE is not an instruction of OPCODE; otherwise | |
2886 | return 1. | |
2887 | ||
2888 | If OPCODE has alias(es) and NOALIASES_P is 0, an alias opcode may be | |
2889 | determined and used to disassemble CODE; this is done just before the | |
2890 | return. */ | |
2891 | ||
561a72d4 | 2892 | static bfd_boolean |
a06ea964 | 2893 | aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code, |
561a72d4 TC |
2894 | aarch64_inst *inst, int noaliases_p, |
2895 | aarch64_operand_error *errors) | |
a06ea964 NC |
2896 | { |
2897 | int i; | |
2898 | ||
2899 | DEBUG_TRACE ("enter with %s", opcode->name); | |
2900 | ||
2901 | assert (opcode && inst); | |
2902 | ||
b3ac5c6c TC |
2903 | /* Clear inst. */ |
2904 | memset (inst, '\0', sizeof (aarch64_inst)); | |
2905 | ||
a06ea964 NC |
2906 | /* Check the base opcode. */ |
2907 | if ((code & opcode->mask) != (opcode->opcode & opcode->mask)) | |
2908 | { | |
2909 | DEBUG_TRACE ("base opcode match FAIL"); | |
2910 | goto decode_fail; | |
2911 | } | |
2912 | ||
a06ea964 NC |
2913 | inst->opcode = opcode; |
2914 | inst->value = code; | |
2915 | ||
2916 | /* Assign operand codes and indexes. */ | |
2917 | for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) | |
2918 | { | |
2919 | if (opcode->operands[i] == AARCH64_OPND_NIL) | |
2920 | break; | |
2921 | inst->operands[i].type = opcode->operands[i]; | |
2922 | inst->operands[i].idx = i; | |
2923 | } | |
2924 | ||
2925 | /* Call the opcode decoder indicated by flags. */ | |
2926 | if (opcode_has_special_coder (opcode) && do_special_decoding (inst) == 0) | |
2927 | { | |
2928 | DEBUG_TRACE ("opcode flag-based decoder FAIL"); | |
2929 | goto decode_fail; | |
2930 | } | |
2931 | ||
116b6019 RS |
2932 | /* Possibly use the instruction class to determine the correct |
2933 | qualifier. */ | |
2934 | if (!aarch64_decode_variant_using_iclass (inst)) | |
2935 | { | |
2936 | DEBUG_TRACE ("iclass-based decoder FAIL"); | |
2937 | goto decode_fail; | |
2938 | } | |
2939 | ||
a06ea964 NC |
2940 | /* Call operand decoders. */ |
2941 | for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) | |
2942 | { | |
2943 | const aarch64_operand *opnd; | |
2944 | enum aarch64_opnd type; | |
4bd13cde | 2945 | |
a06ea964 NC |
2946 | type = opcode->operands[i]; |
2947 | if (type == AARCH64_OPND_NIL) | |
2948 | break; | |
2949 | opnd = &aarch64_operands[type]; | |
2950 | if (operand_has_extractor (opnd) | |
561a72d4 TC |
2951 | && (! aarch64_extract_operand (opnd, &inst->operands[i], code, inst, |
2952 | errors))) | |
a06ea964 NC |
2953 | { |
2954 | DEBUG_TRACE ("operand decoder FAIL at operand %d", i); | |
2955 | goto decode_fail; | |
2956 | } | |
2957 | } | |
2958 | ||
4bd13cde | 2959 | /* If the opcode has a verifier, then check it now. */ |
755b748f TC |
2960 | if (opcode->verifier |
2961 | && opcode->verifier (inst, code, 0, FALSE, errors, NULL) != ERR_OK) | |
4bd13cde NC |
2962 | { |
2963 | DEBUG_TRACE ("operand verifier FAIL"); | |
2964 | goto decode_fail; | |
2965 | } | |
2966 | ||
a06ea964 NC |
2967 | /* Match the qualifiers. */ |
2968 | if (aarch64_match_operands_constraint (inst, NULL) == 1) | |
2969 | { | |
2970 | /* Arriving here, the CODE has been determined as a valid instruction | |
2971 | of OPCODE and *INST has been filled with information of this OPCODE | |
2972 | instruction. Before the return, check if the instruction has any | |
2973 | alias and should be disassembled in the form of its alias instead. | |
2974 | If the answer is yes, *INST will be updated. */ | |
2975 | if (!noaliases_p) | |
561a72d4 | 2976 | determine_disassembling_preference (inst, errors); |
a06ea964 | 2977 | DEBUG_TRACE ("SUCCESS"); |
561a72d4 | 2978 | return TRUE; |
a06ea964 NC |
2979 | } |
2980 | else | |
2981 | { | |
2982 | DEBUG_TRACE ("constraint matching FAIL"); | |
2983 | } | |
2984 | ||
dc1e8a47 | 2985 | decode_fail: |
561a72d4 | 2986 | return FALSE; |
a06ea964 NC |
2987 | } |
2988 | \f | |
2989 | /* This does some user-friendly fix-up to *INST. It is currently focus on | |
2990 | the adjustment of qualifiers to help the printed instruction | |
2991 | recognized/understood more easily. */ | |
2992 | ||
2993 | static void | |
2994 | user_friendly_fixup (aarch64_inst *inst) | |
2995 | { | |
2996 | switch (inst->opcode->iclass) | |
2997 | { | |
2998 | case testbranch: | |
2999 | /* TBNZ Xn|Wn, #uimm6, label | |
3000 | Test and Branch Not Zero: conditionally jumps to label if bit number | |
3001 | uimm6 in register Xn is not zero. The bit number implies the width of | |
3002 | the register, which may be written and should be disassembled as Wn if | |
3003 | uimm is less than 32. Limited to a branch offset range of +/- 32KiB. | |
3004 | */ | |
3005 | if (inst->operands[1].imm.value < 32) | |
3006 | inst->operands[0].qualifier = AARCH64_OPND_QLF_W; | |
3007 | break; | |
3008 | default: break; | |
3009 | } | |
3010 | } | |
3011 | ||
43cdf5ae YQ |
3012 | /* Decode INSN and fill in *INST the instruction information. An alias |
3013 | opcode may be filled in *INSN if NOALIASES_P is FALSE. Return zero on | |
3014 | success. */ | |
a06ea964 | 3015 | |
1d482394 | 3016 | enum err_type |
43cdf5ae | 3017 | aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst, |
561a72d4 TC |
3018 | bfd_boolean noaliases_p, |
3019 | aarch64_operand_error *errors) | |
a06ea964 NC |
3020 | { |
3021 | const aarch64_opcode *opcode = aarch64_opcode_lookup (insn); | |
3022 | ||
3023 | #ifdef DEBUG_AARCH64 | |
3024 | if (debug_dump) | |
3025 | { | |
3026 | const aarch64_opcode *tmp = opcode; | |
3027 | printf ("\n"); | |
3028 | DEBUG_TRACE ("opcode lookup:"); | |
3029 | while (tmp != NULL) | |
3030 | { | |
3031 | aarch64_verbose (" %s", tmp->name); | |
3032 | tmp = aarch64_find_next_opcode (tmp); | |
3033 | } | |
3034 | } | |
3035 | #endif /* DEBUG_AARCH64 */ | |
3036 | ||
3037 | /* A list of opcodes may have been found, as aarch64_opcode_lookup cannot | |
3038 | distinguish some opcodes, e.g. SSHR and MOVI, which almost share the same | |
3039 | opcode field and value, apart from the difference that one of them has an | |
3040 | extra field as part of the opcode, but such a field is used for operand | |
3041 | encoding in other opcode(s) ('immh' in the case of the example). */ | |
3042 | while (opcode != NULL) | |
3043 | { | |
3044 | /* But only one opcode can be decoded successfully for, as the | |
3045 | decoding routine will check the constraint carefully. */ | |
561a72d4 | 3046 | if (aarch64_opcode_decode (opcode, insn, inst, noaliases_p, errors) == 1) |
a06ea964 NC |
3047 | return ERR_OK; |
3048 | opcode = aarch64_find_next_opcode (opcode); | |
3049 | } | |
3050 | ||
3051 | return ERR_UND; | |
3052 | } | |
3053 | ||
3054 | /* Print operands. */ | |
3055 | ||
3056 | static void | |
3057 | print_operands (bfd_vma pc, const aarch64_opcode *opcode, | |
bde90be2 TC |
3058 | const aarch64_opnd_info *opnds, struct disassemble_info *info, |
3059 | bfd_boolean *has_notes) | |
a06ea964 | 3060 | { |
7d02540a | 3061 | char *notes = NULL; |
bde90be2 | 3062 | int i, pcrel_p, num_printed; |
a06ea964 NC |
3063 | for (i = 0, num_printed = 0; i < AARCH64_MAX_OPND_NUM; ++i) |
3064 | { | |
0d2f91fe | 3065 | char str[128]; |
a06ea964 NC |
3066 | /* We regard the opcode operand info more, however we also look into |
3067 | the inst->operands to support the disassembling of the optional | |
3068 | operand. | |
3069 | The two operand code should be the same in all cases, apart from | |
3070 | when the operand can be optional. */ | |
3071 | if (opcode->operands[i] == AARCH64_OPND_NIL | |
3072 | || opnds[i].type == AARCH64_OPND_NIL) | |
3073 | break; | |
3074 | ||
3075 | /* Generate the operand string in STR. */ | |
0d2f91fe | 3076 | aarch64_print_operand (str, sizeof (str), pc, opcode, opnds, i, &pcrel_p, |
7d02540a | 3077 | &info->target, ¬es); |
a06ea964 NC |
3078 | |
3079 | /* Print the delimiter (taking account of omitted operand(s)). */ | |
3080 | if (str[0] != '\0') | |
3081 | (*info->fprintf_func) (info->stream, "%s", | |
3082 | num_printed++ == 0 ? "\t" : ", "); | |
3083 | ||
3084 | /* Print the operand. */ | |
3085 | if (pcrel_p) | |
3086 | (*info->print_address_func) (info->target, info); | |
3087 | else | |
3088 | (*info->fprintf_func) (info->stream, "%s", str); | |
3089 | } | |
7d02540a TC |
3090 | |
3091 | if (notes && !no_notes) | |
bde90be2 TC |
3092 | { |
3093 | *has_notes = TRUE; | |
3094 | (*info->fprintf_func) (info->stream, " // note: %s", notes); | |
3095 | } | |
a06ea964 NC |
3096 | } |
3097 | ||
bb7eff52 RS |
3098 | /* Set NAME to a copy of INST's mnemonic with the "." suffix removed. */ |
3099 | ||
3100 | static void | |
3101 | remove_dot_suffix (char *name, const aarch64_inst *inst) | |
3102 | { | |
3103 | char *ptr; | |
3104 | size_t len; | |
3105 | ||
3106 | ptr = strchr (inst->opcode->name, '.'); | |
3107 | assert (ptr && inst->cond); | |
3108 | len = ptr - inst->opcode->name; | |
3109 | assert (len < 8); | |
3110 | strncpy (name, inst->opcode->name, len); | |
3111 | name[len] = '\0'; | |
3112 | } | |
3113 | ||
a06ea964 NC |
3114 | /* Print the instruction mnemonic name. */ |
3115 | ||
3116 | static void | |
3117 | print_mnemonic_name (const aarch64_inst *inst, struct disassemble_info *info) | |
3118 | { | |
3119 | if (inst->opcode->flags & F_COND) | |
3120 | { | |
3121 | /* For instructions that are truly conditionally executed, e.g. b.cond, | |
3122 | prepare the full mnemonic name with the corresponding condition | |
3123 | suffix. */ | |
bb7eff52 RS |
3124 | char name[8]; |
3125 | ||
3126 | remove_dot_suffix (name, inst); | |
a06ea964 NC |
3127 | (*info->fprintf_func) (info->stream, "%s.%s", name, inst->cond->names[0]); |
3128 | } | |
3129 | else | |
3130 | (*info->fprintf_func) (info->stream, "%s", inst->opcode->name); | |
3131 | } | |
3132 | ||
bb7eff52 RS |
3133 | /* Decide whether we need to print a comment after the operands of |
3134 | instruction INST. */ | |
3135 | ||
3136 | static void | |
3137 | print_comment (const aarch64_inst *inst, struct disassemble_info *info) | |
3138 | { | |
3139 | if (inst->opcode->flags & F_COND) | |
3140 | { | |
3141 | char name[8]; | |
3142 | unsigned int i, num_conds; | |
3143 | ||
3144 | remove_dot_suffix (name, inst); | |
3145 | num_conds = ARRAY_SIZE (inst->cond->names); | |
3146 | for (i = 1; i < num_conds && inst->cond->names[i]; ++i) | |
3147 | (*info->fprintf_func) (info->stream, "%s %s.%s", | |
3148 | i == 1 ? " //" : ",", | |
3149 | name, inst->cond->names[i]); | |
3150 | } | |
3151 | } | |
3152 | ||
bde90be2 TC |
3153 | /* Build notes from verifiers into a string for printing. */ |
3154 | ||
3155 | static void | |
3156 | print_verifier_notes (aarch64_operand_error *detail, | |
3157 | struct disassemble_info *info) | |
3158 | { | |
3159 | if (no_notes) | |
3160 | return; | |
3161 | ||
3162 | /* The output of the verifier cannot be a fatal error, otherwise the assembly | |
3163 | would not have succeeded. We can safely ignore these. */ | |
3164 | assert (detail->non_fatal); | |
3165 | assert (detail->error); | |
3166 | ||
3167 | /* If there are multiple verifier messages, concat them up to 1k. */ | |
3168 | (*info->fprintf_func) (info->stream, " // note: %s", detail->error); | |
3169 | if (detail->index >= 0) | |
3170 | (*info->fprintf_func) (info->stream, " at operand %d", detail->index + 1); | |
3171 | } | |
3172 | ||
a06ea964 NC |
3173 | /* Print the instruction according to *INST. */ |
3174 | ||
3175 | static void | |
3176 | print_aarch64_insn (bfd_vma pc, const aarch64_inst *inst, | |
bde90be2 TC |
3177 | const aarch64_insn code, |
3178 | struct disassemble_info *info, | |
3179 | aarch64_operand_error *mismatch_details) | |
a06ea964 | 3180 | { |
bde90be2 TC |
3181 | bfd_boolean has_notes = FALSE; |
3182 | ||
a06ea964 | 3183 | print_mnemonic_name (inst, info); |
bde90be2 | 3184 | print_operands (pc, inst->opcode, inst->operands, info, &has_notes); |
bb7eff52 | 3185 | print_comment (inst, info); |
bde90be2 TC |
3186 | |
3187 | /* We've already printed a note, not enough space to print more so exit. | |
3188 | Usually notes shouldn't overlap so it shouldn't happen that we have a note | |
3189 | from a register and instruction at the same time. */ | |
3190 | if (has_notes) | |
3191 | return; | |
3192 | ||
3193 | /* Always run constraint verifiers, this is needed because constraints need to | |
3194 | maintain a global state regardless of whether the instruction has the flag | |
3195 | set or not. */ | |
3196 | enum err_type result = verify_constraints (inst, code, pc, FALSE, | |
3197 | mismatch_details, &insn_sequence); | |
3198 | switch (result) | |
3199 | { | |
3200 | case ERR_UND: | |
3201 | case ERR_UNP: | |
3202 | case ERR_NYI: | |
3203 | assert (0); | |
3204 | case ERR_VFI: | |
3205 | print_verifier_notes (mismatch_details, info); | |
3206 | break; | |
3207 | default: | |
3208 | break; | |
3209 | } | |
a06ea964 NC |
3210 | } |
3211 | ||
3212 | /* Entry-point of the instruction disassembler and printer. */ | |
3213 | ||
3214 | static void | |
3215 | print_insn_aarch64_word (bfd_vma pc, | |
3216 | uint32_t word, | |
561a72d4 TC |
3217 | struct disassemble_info *info, |
3218 | aarch64_operand_error *errors) | |
a06ea964 | 3219 | { |
1d482394 | 3220 | static const char *err_msg[ERR_NR_ENTRIES+1] = |
a06ea964 | 3221 | { |
1d482394 TC |
3222 | [ERR_OK] = "_", |
3223 | [ERR_UND] = "undefined", | |
3224 | [ERR_UNP] = "unpredictable", | |
3225 | [ERR_NYI] = "NYI" | |
a06ea964 NC |
3226 | }; |
3227 | ||
1d482394 | 3228 | enum err_type ret; |
a06ea964 NC |
3229 | aarch64_inst inst; |
3230 | ||
3231 | info->insn_info_valid = 1; | |
3232 | info->branch_delay_insns = 0; | |
3233 | info->data_size = 0; | |
3234 | info->target = 0; | |
3235 | info->target2 = 0; | |
3236 | ||
3237 | if (info->flags & INSN_HAS_RELOC) | |
3238 | /* If the instruction has a reloc associated with it, then | |
3239 | the offset field in the instruction will actually be the | |
3240 | addend for the reloc. (If we are using REL type relocs). | |
3241 | In such cases, we can ignore the pc when computing | |
3242 | addresses, since the addend is not currently pc-relative. */ | |
3243 | pc = 0; | |
3244 | ||
561a72d4 | 3245 | ret = aarch64_decode_insn (word, &inst, no_aliases, errors); |
a06ea964 NC |
3246 | |
3247 | if (((word >> 21) & 0x3ff) == 1) | |
3248 | { | |
3249 | /* RESERVED for ALES. */ | |
3250 | assert (ret != ERR_OK); | |
3251 | ret = ERR_NYI; | |
3252 | } | |
3253 | ||
3254 | switch (ret) | |
3255 | { | |
3256 | case ERR_UND: | |
3257 | case ERR_UNP: | |
3258 | case ERR_NYI: | |
3259 | /* Handle undefined instructions. */ | |
3260 | info->insn_type = dis_noninsn; | |
3261 | (*info->fprintf_func) (info->stream,".inst\t0x%08x ; %s", | |
1d482394 | 3262 | word, err_msg[ret]); |
a06ea964 NC |
3263 | break; |
3264 | case ERR_OK: | |
3265 | user_friendly_fixup (&inst); | |
bde90be2 | 3266 | print_aarch64_insn (pc, &inst, word, info, errors); |
a06ea964 NC |
3267 | break; |
3268 | default: | |
3269 | abort (); | |
3270 | } | |
3271 | } | |
3272 | ||
3273 | /* Disallow mapping symbols ($x, $d etc) from | |
3274 | being displayed in symbol relative addresses. */ | |
3275 | ||
3276 | bfd_boolean | |
3277 | aarch64_symbol_is_valid (asymbol * sym, | |
3278 | struct disassemble_info * info ATTRIBUTE_UNUSED) | |
3279 | { | |
3280 | const char * name; | |
3281 | ||
3282 | if (sym == NULL) | |
3283 | return FALSE; | |
3284 | ||
3285 | name = bfd_asymbol_name (sym); | |
3286 | ||
3287 | return name | |
3288 | && (name[0] != '$' | |
3289 | || (name[1] != 'x' && name[1] != 'd') | |
3290 | || (name[2] != '\0' && name[2] != '.')); | |
3291 | } | |
3292 | ||
3293 | /* Print data bytes on INFO->STREAM. */ | |
3294 | ||
3295 | static void | |
3296 | print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, | |
3297 | uint32_t word, | |
561a72d4 TC |
3298 | struct disassemble_info *info, |
3299 | aarch64_operand_error *errors ATTRIBUTE_UNUSED) | |
a06ea964 NC |
3300 | { |
3301 | switch (info->bytes_per_chunk) | |
3302 | { | |
3303 | case 1: | |
3304 | info->fprintf_func (info->stream, ".byte\t0x%02x", word); | |
3305 | break; | |
3306 | case 2: | |
3307 | info->fprintf_func (info->stream, ".short\t0x%04x", word); | |
3308 | break; | |
3309 | case 4: | |
3310 | info->fprintf_func (info->stream, ".word\t0x%08x", word); | |
3311 | break; | |
3312 | default: | |
3313 | abort (); | |
3314 | } | |
3315 | } | |
3316 | ||
3317 | /* Try to infer the code or data type from a symbol. | |
3318 | Returns nonzero if *MAP_TYPE was set. */ | |
3319 | ||
3320 | static int | |
3321 | get_sym_code_type (struct disassemble_info *info, int n, | |
3322 | enum map_type *map_type) | |
3323 | { | |
3324 | elf_symbol_type *es; | |
3325 | unsigned int type; | |
3326 | const char *name; | |
3327 | ||
4c5ae11b RL |
3328 | /* If the symbol is in a different section, ignore it. */ |
3329 | if (info->section != NULL && info->section != info->symtab[n]->section) | |
3330 | return FALSE; | |
3331 | ||
a06ea964 NC |
3332 | es = *(elf_symbol_type **)(info->symtab + n); |
3333 | type = ELF_ST_TYPE (es->internal_elf_sym.st_info); | |
3334 | ||
3335 | /* If the symbol has function type then use that. */ | |
3336 | if (type == STT_FUNC) | |
3337 | { | |
3338 | *map_type = MAP_INSN; | |
3339 | return TRUE; | |
3340 | } | |
3341 | ||
3342 | /* Check for mapping symbols. */ | |
3343 | name = bfd_asymbol_name(info->symtab[n]); | |
3344 | if (name[0] == '$' | |
3345 | && (name[1] == 'x' || name[1] == 'd') | |
3346 | && (name[2] == '\0' || name[2] == '.')) | |
3347 | { | |
3348 | *map_type = (name[1] == 'x' ? MAP_INSN : MAP_DATA); | |
3349 | return TRUE; | |
3350 | } | |
3351 | ||
3352 | return FALSE; | |
3353 | } | |
3354 | ||
3355 | /* Entry-point of the AArch64 disassembler. */ | |
3356 | ||
3357 | int | |
3358 | print_insn_aarch64 (bfd_vma pc, | |
3359 | struct disassemble_info *info) | |
3360 | { | |
3361 | bfd_byte buffer[INSNLEN]; | |
3362 | int status; | |
561a72d4 TC |
3363 | void (*printer) (bfd_vma, uint32_t, struct disassemble_info *, |
3364 | aarch64_operand_error *); | |
a06ea964 NC |
3365 | bfd_boolean found = FALSE; |
3366 | unsigned int size = 4; | |
3367 | unsigned long data; | |
561a72d4 | 3368 | aarch64_operand_error errors; |
a06ea964 NC |
3369 | |
3370 | if (info->disassembler_options) | |
3371 | { | |
3372 | set_default_aarch64_dis_options (info); | |
3373 | ||
3374 | parse_aarch64_dis_options (info->disassembler_options); | |
3375 | ||
3376 | /* To avoid repeated parsing of these options, we remove them here. */ | |
3377 | info->disassembler_options = NULL; | |
3378 | } | |
3379 | ||
3380 | /* Aarch64 instructions are always little-endian */ | |
3381 | info->endian_code = BFD_ENDIAN_LITTLE; | |
3382 | ||
51457761 TC |
3383 | /* Default to DATA. A text section is required by the ABI to contain an |
3384 | INSN mapping symbol at the start. A data section has no such | |
3385 | requirement, hence if no mapping symbol is found the section must | |
3386 | contain only data. This however isn't very useful if the user has | |
3387 | fully stripped the binaries. If this is the case use the section | |
3388 | attributes to determine the default. If we have no section default to | |
3389 | INSN as well, as we may be disassembling some raw bytes on a baremetal | |
3390 | HEX file or similar. */ | |
3391 | enum map_type type = MAP_DATA; | |
3392 | if ((info->section && info->section->flags & SEC_CODE) || !info->section) | |
3393 | type = MAP_INSN; | |
3394 | ||
a06ea964 NC |
3395 | /* First check the full symtab for a mapping symbol, even if there |
3396 | are no usable non-mapping symbols for this address. */ | |
3397 | if (info->symtab_size != 0 | |
3398 | && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) | |
3399 | { | |
a06ea964 | 3400 | int last_sym = -1; |
51457761 TC |
3401 | bfd_vma addr, section_vma = 0; |
3402 | bfd_boolean can_use_search_opt_p; | |
a06ea964 NC |
3403 | int n; |
3404 | ||
3405 | if (pc <= last_mapping_addr) | |
3406 | last_mapping_sym = -1; | |
3407 | ||
3408 | /* Start scanning at the start of the function, or wherever | |
3409 | we finished last time. */ | |
3410 | n = info->symtab_pos + 1; | |
51457761 | 3411 | |
53b2f36b TC |
3412 | /* If the last stop offset is different from the current one it means we |
3413 | are disassembling a different glob of bytes. As such the optimization | |
3414 | would not be safe and we should start over. */ | |
51457761 TC |
3415 | can_use_search_opt_p = last_mapping_sym >= 0 |
3416 | && info->stop_offset == last_stop_offset; | |
3417 | ||
3418 | if (n >= last_mapping_sym && can_use_search_opt_p) | |
a06ea964 NC |
3419 | n = last_mapping_sym; |
3420 | ||
51457761 TC |
3421 | /* Look down while we haven't passed the location being disassembled. |
3422 | The reason for this is that there's no defined order between a symbol | |
3423 | and an mapping symbol that may be at the same address. We may have to | |
3424 | look at least one position ahead. */ | |
a06ea964 NC |
3425 | for (; n < info->symtab_size; n++) |
3426 | { | |
3427 | addr = bfd_asymbol_value (info->symtab[n]); | |
3428 | if (addr > pc) | |
3429 | break; | |
4c5ae11b | 3430 | if (get_sym_code_type (info, n, &type)) |
a06ea964 NC |
3431 | { |
3432 | last_sym = n; | |
3433 | found = TRUE; | |
3434 | } | |
3435 | } | |
3436 | ||
3437 | if (!found) | |
3438 | { | |
3439 | n = info->symtab_pos; | |
51457761 | 3440 | if (n >= last_mapping_sym && can_use_search_opt_p) |
a06ea964 NC |
3441 | n = last_mapping_sym; |
3442 | ||
3443 | /* No mapping symbol found at this address. Look backwards | |
51457761 TC |
3444 | for a preceeding one, but don't go pass the section start |
3445 | otherwise a data section with no mapping symbol can pick up | |
3446 | a text mapping symbol of a preceeding section. The documentation | |
3447 | says section can be NULL, in which case we will seek up all the | |
3448 | way to the top. */ | |
3449 | if (info->section) | |
3450 | section_vma = info->section->vma; | |
3451 | ||
a06ea964 NC |
3452 | for (; n >= 0; n--) |
3453 | { | |
51457761 TC |
3454 | addr = bfd_asymbol_value (info->symtab[n]); |
3455 | if (addr < section_vma) | |
3456 | break; | |
3457 | ||
a06ea964 NC |
3458 | if (get_sym_code_type (info, n, &type)) |
3459 | { | |
3460 | last_sym = n; | |
3461 | found = TRUE; | |
3462 | break; | |
3463 | } | |
3464 | } | |
3465 | } | |
3466 | ||
3467 | last_mapping_sym = last_sym; | |
3468 | last_type = type; | |
53b2f36b | 3469 | last_stop_offset = info->stop_offset; |
a06ea964 NC |
3470 | |
3471 | /* Look a little bit ahead to see if we should print out | |
3472 | less than four bytes of data. If there's a symbol, | |
3473 | mapping or otherwise, after two bytes then don't | |
3474 | print more. */ | |
3475 | if (last_type == MAP_DATA) | |
3476 | { | |
3477 | size = 4 - (pc & 3); | |
3478 | for (n = last_sym + 1; n < info->symtab_size; n++) | |
3479 | { | |
3480 | addr = bfd_asymbol_value (info->symtab[n]); | |
3481 | if (addr > pc) | |
3482 | { | |
3483 | if (addr - pc < size) | |
3484 | size = addr - pc; | |
3485 | break; | |
3486 | } | |
3487 | } | |
3488 | /* If the next symbol is after three bytes, we need to | |
3489 | print only part of the data, so that we can use either | |
3490 | .byte or .short. */ | |
3491 | if (size == 3) | |
3492 | size = (pc & 1) ? 1 : 2; | |
3493 | } | |
3494 | } | |
51457761 TC |
3495 | else |
3496 | last_type = type; | |
a06ea964 | 3497 | |
60df3720 TC |
3498 | /* PR 10263: Disassemble data if requested to do so by the user. */ |
3499 | if (last_type == MAP_DATA && ((info->flags & DISASSEMBLE_DATA) == 0)) | |
a06ea964 NC |
3500 | { |
3501 | /* size was set above. */ | |
3502 | info->bytes_per_chunk = size; | |
3503 | info->display_endian = info->endian; | |
3504 | printer = print_insn_data; | |
3505 | } | |
3506 | else | |
3507 | { | |
3508 | info->bytes_per_chunk = size = INSNLEN; | |
3509 | info->display_endian = info->endian_code; | |
3510 | printer = print_insn_aarch64_word; | |
3511 | } | |
3512 | ||
3513 | status = (*info->read_memory_func) (pc, buffer, size, info); | |
3514 | if (status != 0) | |
3515 | { | |
3516 | (*info->memory_error_func) (status, pc, info); | |
3517 | return -1; | |
3518 | } | |
3519 | ||
3520 | data = bfd_get_bits (buffer, size * 8, | |
3521 | info->display_endian == BFD_ENDIAN_BIG); | |
3522 | ||
561a72d4 | 3523 | (*printer) (pc, data, info, &errors); |
a06ea964 NC |
3524 | |
3525 | return size; | |
3526 | } | |
3527 | \f | |
3528 | void | |
3529 | print_aarch64_disassembler_options (FILE *stream) | |
3530 | { | |
3531 | fprintf (stream, _("\n\ | |
3532 | The following AARCH64 specific disassembler options are supported for use\n\ | |
3533 | with the -M switch (multiple options should be separated by commas):\n")); | |
3534 | ||
3535 | fprintf (stream, _("\n\ | |
3536 | no-aliases Don't print instruction aliases.\n")); | |
3537 | ||
3538 | fprintf (stream, _("\n\ | |
3539 | aliases Do print instruction aliases.\n")); | |
3540 | ||
7d02540a TC |
3541 | fprintf (stream, _("\n\ |
3542 | no-notes Don't print instruction notes.\n")); | |
3543 | ||
3544 | fprintf (stream, _("\n\ | |
3545 | notes Do print instruction notes.\n")); | |
3546 | ||
a06ea964 NC |
3547 | #ifdef DEBUG_AARCH64 |
3548 | fprintf (stream, _("\n\ | |
3549 | debug_dump Temp switch for debug trace.\n")); | |
3550 | #endif /* DEBUG_AARCH64 */ | |
3551 | ||
3552 | fprintf (stream, _("\n")); | |
3553 | } |