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AArch64: Wire through instr_sequence
[deliverable/binutils-gdb.git] / opcodes / aarch64-dis.c
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a06ea964 1/* aarch64-dis.c -- AArch64 disassembler.
219d1afa 2 Copyright (C) 2009-2018 Free Software Foundation, Inc.
a06ea964
NC		 3 Contributed by ARM Ltd.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21#include "sysdep.h"
22#include "bfd_stdint.h"
6394c606 23#include "disassemble.h"
a06ea964
NC		 24#include "libiberty.h"
25#include "opintl.h"
26#include "aarch64-dis.h"
a06ea964 27#include "elf-bfd.h"
a06ea964
NC		 28
29#define ERR_OK 0
30#define ERR_UND -1
31#define ERR_UNP -3
32#define ERR_NYI -5
33
34#define INSNLEN 4
35
36/* Cached mapping symbol state. */
37enum map_type
38{
39 MAP_INSN,
40 MAP_DATA
41};
42
43static enum map_type last_type;
44static int last_mapping_sym = -1;
45static bfd_vma last_mapping_addr = 0;
46
47/* Other options */
48static int no_aliases = 0; /* If set disassemble as most general inst. */
7d02540a
TC		 49\fstatic int no_notes = 1; /* If set do not print disassemble notes in the
50 output as comments. */
a06ea964 51
7e84b55d
TC		 52/* Currently active instruction sequence. */
53static aarch64_instr_sequence insn_sequence ATTRIBUTE_UNUSED;
54
a06ea964
NC		 55static void
56set_default_aarch64_dis_options (struct disassemble_info *info ATTRIBUTE_UNUSED)
57{
58}
59
60static void
61parse_aarch64_dis_option (const char *option, unsigned int len ATTRIBUTE_UNUSED)
62{
63 /* Try to match options that are simple flags */
64 if (CONST_STRNEQ (option, "no-aliases"))
65 {
66 no_aliases = 1;
67 return;
68 }
69
70 if (CONST_STRNEQ (option, "aliases"))
71 {
72 no_aliases = 0;
73 return;
74 }
75
7d02540a
TC		 76 if (CONST_STRNEQ (option, "no-notes"))
77 {
78 no_notes = 1;
79 return;
80 }
81
82 if (CONST_STRNEQ (option, "notes"))
83 {
84 no_notes = 0;
85 return;
86 }
87
a06ea964
NC		 88#ifdef DEBUG_AARCH64
89 if (CONST_STRNEQ (option, "debug_dump"))
90 {
91 debug_dump = 1;
92 return;
93 }
94#endif /* DEBUG_AARCH64 */
95
96 /* Invalid option. */
a6743a54 97 opcodes_error_handler (_("unrecognised disassembler option: %s"), option);
a06ea964
NC		 98}
99
100static void
101parse_aarch64_dis_options (const char *options)
102{
103 const char *option_end;
104
105 if (options == NULL)
106 return;
107
108 while (*options != '\0')
109 {
110 /* Skip empty options. */
111 if (*options == ',')
112 {
113 options++;
114 continue;
115 }
116
117 /* We know that *options is neither NUL or a comma. */
118 option_end = options + 1;
119 while (*option_end != ',' && *option_end != '\0')
120 option_end++;
121
122 parse_aarch64_dis_option (options, option_end - options);
123
124 /* Go on to the next one. If option_end points to a comma, it
125 will be skipped above. */
126 options = option_end;
127 }
128}
129\f
130/* Functions doing the instruction disassembling. */
131
132/* The unnamed arguments consist of the number of fields and information about
133 these fields where the VALUE will be extracted from CODE and returned.
134 MASK can be zero or the base mask of the opcode.
135
136 N.B. the fields are required to be in such an order than the most signficant
137 field for VALUE comes the first, e.g. the <index> in
138 SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
9aff4b7a 139 is encoded in H:L:M in some cases, the fields H:L:M should be passed in
a06ea964
NC		 140 the order of H, L, M. */
141
c0890d26 142aarch64_insn
a06ea964
NC		 143extract_fields (aarch64_insn code, aarch64_insn mask, ...)
144{
145 uint32_t num;
146 const aarch64_field *field;
147 enum aarch64_field_kind kind;
148 va_list va;
149
150 va_start (va, mask);
151 num = va_arg (va, uint32_t);
152 assert (num <= 5);
153 aarch64_insn value = 0x0;
154 while (num--)
155 {
156 kind = va_arg (va, enum aarch64_field_kind);
157 field = &fields[kind];
158 value <<= field->width;
159 value |= extract_field (kind, code, mask);
160 }
161 return value;
162}
163
b5464a68
RS		 164/* Extract the value of all fields in SELF->fields from instruction CODE.
165 The least significant bit comes from the final field. */
166
167static aarch64_insn
168extract_all_fields (const aarch64_operand *self, aarch64_insn code)
169{
170 aarch64_insn value;
171 unsigned int i;
172 enum aarch64_field_kind kind;
173
174 value = 0;
175 for (i = 0; i < ARRAY_SIZE (self->fields) && self->fields[i] != FLD_NIL; ++i)
176 {
177 kind = self->fields[i];
178 value <<= fields[kind].width;
179 value |= extract_field (kind, code, 0);
180 }
181 return value;
182}
183
a06ea964
NC		 184/* Sign-extend bit I of VALUE. */
185static inline int32_t
186sign_extend (aarch64_insn value, unsigned i)
187{
188 uint32_t ret = value;
189
190 assert (i < 32);
191 if ((value >> i) & 0x1)
192 {
193 uint32_t val = (uint32_t)(-1) << i;
194 ret = ret | val;
195 }
196 return (int32_t) ret;
197}
198
199/* N.B. the following inline helpfer functions create a dependency on the
200 order of operand qualifier enumerators. */
201
202/* Given VALUE, return qualifier for a general purpose register. */
203static inline enum aarch64_opnd_qualifier
204get_greg_qualifier_from_value (aarch64_insn value)
205{
206 enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_W + value;
207 assert (value <= 0x1
208 && aarch64_get_qualifier_standard_value (qualifier) == value);
209 return qualifier;
210}
211
3067d3b9
MW		 212/* Given VALUE, return qualifier for a vector register. This does not support
213 decoding instructions that accept the 2H vector type. */
214
a06ea964
NC		 215static inline enum aarch64_opnd_qualifier
216get_vreg_qualifier_from_value (aarch64_insn value)
217{
218 enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_V_8B + value;
219
3067d3b9
MW		 220 /* Instructions using vector type 2H should not call this function. Skip over
221 the 2H qualifier. */
222 if (qualifier >= AARCH64_OPND_QLF_V_2H)
223 qualifier += 1;
224
a06ea964
NC		 225 assert (value <= 0x8
226 && aarch64_get_qualifier_standard_value (qualifier) == value);
227 return qualifier;
228}
229
230/* Given VALUE, return qualifier for an FP or AdvSIMD scalar register. */
231static inline enum aarch64_opnd_qualifier
232get_sreg_qualifier_from_value (aarch64_insn value)
233{
234 enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_S_B + value;
235
236 assert (value <= 0x4
237 && aarch64_get_qualifier_standard_value (qualifier) == value);
238 return qualifier;
239}
240
241/* Given the instruction in *INST which is probably half way through the
242 decoding and our caller wants to know the expected qualifier for operand
243 I. Return such a qualifier if we can establish it; otherwise return
244 AARCH64_OPND_QLF_NIL. */
245
246static aarch64_opnd_qualifier_t
247get_expected_qualifier (const aarch64_inst *inst, int i)
248{
249 aarch64_opnd_qualifier_seq_t qualifiers;
250 /* Should not be called if the qualifier is known. */
251 assert (inst->operands[i].qualifier == AARCH64_OPND_QLF_NIL);
252 if (aarch64_find_best_match (inst, inst->opcode->qualifiers_list,
253 i, qualifiers))
254 return qualifiers[i];
255 else
256 return AARCH64_OPND_QLF_NIL;
257}
258
259/* Operand extractors. */
260
561a72d4 261bfd_boolean
a06ea964
NC		 262aarch64_ext_regno (const aarch64_operand *self, aarch64_opnd_info *info,
263 const aarch64_insn code,
561a72d4
TC		 264 const aarch64_inst *inst ATTRIBUTE_UNUSED,
265 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 266{
267 info->reg.regno = extract_field (self->fields[0], code, 0);
561a72d4 268 return TRUE;
a06ea964
NC		 269}
270
561a72d4 271bfd_boolean
ee804238
JW		 272aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info,
273 const aarch64_insn code ATTRIBUTE_UNUSED,
561a72d4
TC		 274 const aarch64_inst *inst ATTRIBUTE_UNUSED,
275 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
ee804238
JW		 276{
277 assert (info->idx == 1
278 || info->idx ==3);
279 info->reg.regno = inst->operands[info->idx - 1].reg.regno + 1;
561a72d4 280 return TRUE;
ee804238
JW		 281}
282
a06ea964 283/* e.g. IC <ic_op>{, <Xt>}. */
561a72d4 284bfd_boolean
a06ea964
NC		 285aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info,
286 const aarch64_insn code,
561a72d4
TC		 287 const aarch64_inst *inst ATTRIBUTE_UNUSED,
288 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 289{
290 info->reg.regno = extract_field (self->fields[0], code, 0);
291 assert (info->idx == 1
292 && (aarch64_get_operand_class (inst->operands[0].type)
293 == AARCH64_OPND_CLASS_SYSTEM));
294 /* This will make the constraint checking happy and more importantly will
295 help the disassembler determine whether this operand is optional or
296 not. */
ea2deeec 297 info->present = aarch64_sys_ins_reg_has_xt (inst->operands[0].sysins_op);
a06ea964 298
561a72d4 299 return TRUE;
a06ea964
NC		 300}
301
302/* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
561a72d4 303bfd_boolean
a06ea964
NC		 304aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info,
305 const aarch64_insn code,
561a72d4
TC		 306 const aarch64_inst *inst ATTRIBUTE_UNUSED,
307 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 308{
309 /* regno */
310 info->reglane.regno = extract_field (self->fields[0], code,
311 inst->opcode->mask);
312
313 /* Index and/or type. */
314 if (inst->opcode->iclass == asisdone
315 || inst->opcode->iclass == asimdins)
316 {
317 if (info->type == AARCH64_OPND_En
318 && inst->opcode->operands[0] == AARCH64_OPND_Ed)
319 {
320 unsigned shift;
321 /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */
322 assert (info->idx == 1); /* Vn */
323 aarch64_insn value = extract_field (FLD_imm4, code, 0);
324 /* Depend on AARCH64_OPND_Ed to determine the qualifier. */
325 info->qualifier = get_expected_qualifier (inst, info->idx);
326 shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
327 info->reglane.index = value >> shift;
328 }
329 else
330 {
331 /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>].
332 imm5<3:0> <V>
333 0000 RESERVED
334 xxx1 B
335 xx10 H
336 x100 S
337 1000 D */
338 int pos = -1;
339 aarch64_insn value = extract_field (FLD_imm5, code, 0);
340 while (++pos <= 3 && (value & 0x1) == 0)
341 value >>= 1;
342 if (pos > 3)
561a72d4 343 return FALSE;
a06ea964
NC		 344 info->qualifier = get_sreg_qualifier_from_value (pos);
345 info->reglane.index = (unsigned) (value >> 1);
346 }
347 }
65a55fbb
TC		 348 else if (inst->opcode->iclass == dotproduct)
349 {
350 /* Need information in other operand(s) to help decoding. */
351 info->qualifier = get_expected_qualifier (inst, info->idx);
352 switch (info->qualifier)
353 {
00c2093f 354 case AARCH64_OPND_QLF_S_4B:
65a55fbb
TC		 355 /* L:H */
356 info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
357 info->reglane.regno &= 0x1f;
358 break;
359 default:
561a72d4 360 return FALSE;
65a55fbb
TC		 361 }
362 }
f42f1a1d
TC		 363 else if (inst->opcode->iclass == cryptosm3)
364 {
365 /* index for e.g. SM3TT2A <Vd>.4S, <Vn>.4S, <Vm>S[<imm2>]. */
366 info->reglane.index = extract_field (FLD_SM3_imm2, code, 0);
367 }
a06ea964
NC		 368 else
369 {
370 /* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
371 or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
372
373 /* Need information in other operand(s) to help decoding. */
374 info->qualifier = get_expected_qualifier (inst, info->idx);
375 switch (info->qualifier)
376 {
377 case AARCH64_OPND_QLF_S_H:
369c9167
TC		 378 if (info->type == AARCH64_OPND_Em16)
379 {
380 /* h:l:m */
381 info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L,
382 FLD_M);
383 info->reglane.regno &= 0xf;
384 }
385 else
386 {
387 /* h:l */
388 info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
389 }
a06ea964
NC		 390 break;
391 case AARCH64_OPND_QLF_S_S:
392 /* h:l */
393 info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
394 break;
395 case AARCH64_OPND_QLF_S_D:
396 /* H */
397 info->reglane.index = extract_field (FLD_H, code, 0);
398 break;
399 default:
561a72d4 400 return FALSE;
a06ea964 401 }
c2c4ff8d 402
369c9167
TC		 403 if (inst->opcode->op == OP_FCMLA_ELEM
404 && info->qualifier != AARCH64_OPND_QLF_S_H)
c2c4ff8d
SN		 405 {
406 /* Complex operand takes two elements. */
407 if (info->reglane.index & 1)
561a72d4 408 return FALSE;
c2c4ff8d
SN		 409 info->reglane.index /= 2;
410 }
a06ea964
NC		 411 }
412
561a72d4 413 return TRUE;
a06ea964
NC		 414}
415
561a72d4 416bfd_boolean
a06ea964
NC		 417aarch64_ext_reglist (const aarch64_operand *self, aarch64_opnd_info *info,
418 const aarch64_insn code,
561a72d4
TC		 419 const aarch64_inst *inst ATTRIBUTE_UNUSED,
420 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 421{
422 /* R */
423 info->reglist.first_regno = extract_field (self->fields[0], code, 0);
424 /* len */
425 info->reglist.num_regs = extract_field (FLD_len, code, 0) + 1;
561a72d4 426 return TRUE;
a06ea964
NC		 427}
428
429/* Decode Rt and opcode fields of Vt in AdvSIMD load/store instructions. */
561a72d4 430bfd_boolean
a06ea964
NC		 431aarch64_ext_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
432 aarch64_opnd_info *info, const aarch64_insn code,
561a72d4
TC		 433 const aarch64_inst *inst,
434 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 435{
436 aarch64_insn value;
437 /* Number of elements in each structure to be loaded/stored. */
438 unsigned expected_num = get_opcode_dependent_value (inst->opcode);
439
440 struct
441 {
442 unsigned is_reserved;
443 unsigned num_regs;
444 unsigned num_elements;
445 } data [] =
446 { {0, 4, 4},
447 {1, 4, 4},
448 {0, 4, 1},
449 {0, 4, 2},
450 {0, 3, 3},
451 {1, 3, 3},
452 {0, 3, 1},
453 {0, 1, 1},
454 {0, 2, 2},
455 {1, 2, 2},
456 {0, 2, 1},
457 };
458
459 /* Rt */
460 info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
461 /* opcode */
462 value = extract_field (FLD_opcode, code, 0);
cd3ea7c6
NC		 463 /* PR 21595: Check for a bogus value. */
464 if (value >= ARRAY_SIZE (data))
561a72d4 465 return FALSE;
a06ea964 466 if (expected_num != data[value].num_elements || data[value].is_reserved)
561a72d4 467 return FALSE;
a06ea964
NC		 468 info->reglist.num_regs = data[value].num_regs;
469
561a72d4 470 return TRUE;
a06ea964
NC		 471}
472
473/* Decode Rt and S fields of Vt in AdvSIMD load single structure to all
474 lanes instructions. */
561a72d4 475bfd_boolean
a06ea964
NC		 476aarch64_ext_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED,
477 aarch64_opnd_info *info, const aarch64_insn code,
561a72d4
TC		 478 const aarch64_inst *inst,
479 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 480{
481 aarch64_insn value;
482
483 /* Rt */
484 info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
485 /* S */
486 value = extract_field (FLD_S, code, 0);
487
488 /* Number of registers is equal to the number of elements in
489 each structure to be loaded/stored. */
490 info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
491 assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4);
492
493 /* Except when it is LD1R. */
494 if (info->reglist.num_regs == 1 && value == (aarch64_insn) 1)
495 info->reglist.num_regs = 2;
496
561a72d4 497 return TRUE;
a06ea964
NC		 498}
499
500/* Decode Q, opcode<2:1>, S, size and Rt fields of Vt in AdvSIMD
501 load/store single element instructions. */
561a72d4 502bfd_boolean
a06ea964
NC		 503aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
504 aarch64_opnd_info *info, const aarch64_insn code,
561a72d4
TC		 505 const aarch64_inst *inst ATTRIBUTE_UNUSED,
506 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 507{
508 aarch64_field field = {0, 0};
509 aarch64_insn QSsize; /* fields Q:S:size. */
510 aarch64_insn opcodeh2; /* opcode<2:1> */
511
512 /* Rt */
513 info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
514
515 /* Decode the index, opcode<2:1> and size. */
516 gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field);
517 opcodeh2 = extract_field_2 (&field, code, 0);
518 QSsize = extract_fields (code, 0, 3, FLD_Q, FLD_S, FLD_vldst_size);
519 switch (opcodeh2)
520 {
521 case 0x0:
522 info->qualifier = AARCH64_OPND_QLF_S_B;
523 /* Index encoded in "Q:S:size". */
524 info->reglist.index = QSsize;
525 break;
526 case 0x1:
76dfed02
YZ		 527 if (QSsize & 0x1)
528 /* UND. */
561a72d4 529 return FALSE;
a06ea964
NC		 530 info->qualifier = AARCH64_OPND_QLF_S_H;
531 /* Index encoded in "Q:S:size<1>". */
532 info->reglist.index = QSsize >> 1;
533 break;
534 case 0x2:
76dfed02
YZ		 535 if ((QSsize >> 1) & 0x1)
536 /* UND. */
561a72d4 537 return FALSE;
a06ea964
NC		 538 if ((QSsize & 0x1) == 0)
539 {
540 info->qualifier = AARCH64_OPND_QLF_S_S;
541 /* Index encoded in "Q:S". */
542 info->reglist.index = QSsize >> 2;
543 }
544 else
545 {
a06ea964
NC		 546 if (extract_field (FLD_S, code, 0))
547 /* UND */
561a72d4 548 return FALSE;
76dfed02
YZ		 549 info->qualifier = AARCH64_OPND_QLF_S_D;
550 /* Index encoded in "Q". */
551 info->reglist.index = QSsize >> 3;
a06ea964
NC		 552 }
553 break;
554 default:
561a72d4 555 return FALSE;
a06ea964
NC		 556 }
557
558 info->reglist.has_index = 1;
559 info->reglist.num_regs = 0;
560 /* Number of registers is equal to the number of elements in
561 each structure to be loaded/stored. */
562 info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
563 assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4);
564
561a72d4 565 return TRUE;
a06ea964
NC		 566}
567
568/* Decode fields immh:immb and/or Q for e.g.
569 SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
570 or SSHR <V><d>, <V><n>, #<shift>. */
571
561a72d4 572bfd_boolean
a06ea964
NC		 573aarch64_ext_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED,
574 aarch64_opnd_info *info, const aarch64_insn code,
561a72d4
TC		 575 const aarch64_inst *inst,
576 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 577{
578 int pos;
579 aarch64_insn Q, imm, immh;
580 enum aarch64_insn_class iclass = inst->opcode->iclass;
581
582 immh = extract_field (FLD_immh, code, 0);
583 if (immh == 0)
561a72d4 584 return FALSE;
a06ea964
NC		 585 imm = extract_fields (code, 0, 2, FLD_immh, FLD_immb);
586 pos = 4;
587 /* Get highest set bit in immh. */
588 while (--pos >= 0 && (immh & 0x8) == 0)
589 immh <<= 1;
590
591 assert ((iclass == asimdshf || iclass == asisdshf)
592 && (info->type == AARCH64_OPND_IMM_VLSR
593 || info->type == AARCH64_OPND_IMM_VLSL));
594
595 if (iclass == asimdshf)
596 {
597 Q = extract_field (FLD_Q, code, 0);
598 /* immh Q <T>
599 0000 x SEE AdvSIMD modified immediate
600 0001 0 8B
601 0001 1 16B
602 001x 0 4H
603 001x 1 8H
604 01xx 0 2S
605 01xx 1 4S
606 1xxx 0 RESERVED
607 1xxx 1 2D */
608 info->qualifier =
609 get_vreg_qualifier_from_value ((pos << 1) | (int) Q);
610 }
611 else
612 info->qualifier = get_sreg_qualifier_from_value (pos);
613
614 if (info->type == AARCH64_OPND_IMM_VLSR)
615 /* immh <shift>
616 0000 SEE AdvSIMD modified immediate
617 0001 (16-UInt(immh:immb))
618 001x (32-UInt(immh:immb))
619 01xx (64-UInt(immh:immb))
620 1xxx (128-UInt(immh:immb)) */
621 info->imm.value = (16 << pos) - imm;
622 else
623 /* immh:immb
624 immh <shift>
625 0000 SEE AdvSIMD modified immediate
626 0001 (UInt(immh:immb)-8)
627 001x (UInt(immh:immb)-16)
628 01xx (UInt(immh:immb)-32)
629 1xxx (UInt(immh:immb)-64) */
630 info->imm.value = imm - (8 << pos);
631
561a72d4 632 return TRUE;
a06ea964
NC		 633}
634
635/* Decode shift immediate for e.g. sshr (imm). */
561a72d4 636bfd_boolean
a06ea964
NC		 637aarch64_ext_shll_imm (const aarch64_operand *self ATTRIBUTE_UNUSED,
638 aarch64_opnd_info *info, const aarch64_insn code,
561a72d4
TC		 639 const aarch64_inst *inst ATTRIBUTE_UNUSED,
640 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 641{
642 int64_t imm;
643 aarch64_insn val;
644 val = extract_field (FLD_size, code, 0);
645 switch (val)
646 {
647 case 0: imm = 8; break;
648 case 1: imm = 16; break;
649 case 2: imm = 32; break;
561a72d4 650 default: return FALSE;
a06ea964
NC		 651 }
652 info->imm.value = imm;
561a72d4 653 return TRUE;
a06ea964
NC		 654}
655
656/* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
657 value in the field(s) will be extracted as unsigned immediate value. */
561a72d4 658bfd_boolean
a06ea964
NC		 659aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info,
660 const aarch64_insn code,
561a72d4
TC		 661 const aarch64_inst *inst ATTRIBUTE_UNUSED,
662 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 663{
664 int64_t imm;
a06ea964 665
b5464a68 666 imm = extract_all_fields (self, code);
a06ea964 667
a06ea964
NC		 668 if (operand_need_sign_extension (self))
669 imm = sign_extend (imm, get_operand_fields_width (self) - 1);
670
671 if (operand_need_shift_by_two (self))
672 imm <<= 2;
673
674 if (info->type == AARCH64_OPND_ADDR_ADRP)
675 imm <<= 12;
676
677 info->imm.value = imm;
561a72d4 678 return TRUE;
a06ea964
NC		 679}
680
681/* Decode imm and its shifter for e.g. MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */
561a72d4 682bfd_boolean
a06ea964
NC		 683aarch64_ext_imm_half (const aarch64_operand *self, aarch64_opnd_info *info,
684 const aarch64_insn code,
561a72d4
TC		 685 const aarch64_inst *inst ATTRIBUTE_UNUSED,
686 aarch64_operand_error *errors)
a06ea964 687{
561a72d4 688 aarch64_ext_imm (self, info, code, inst, errors);
a06ea964
NC		 689 info->shifter.kind = AARCH64_MOD_LSL;
690 info->shifter.amount = extract_field (FLD_hw, code, 0) << 4;
561a72d4 691 return TRUE;
a06ea964
NC		 692}
693
694/* Decode cmode and "a:b:c:d:e:f:g:h" for e.g.
695 MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */
561a72d4 696bfd_boolean
a06ea964
NC		 697aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
698 aarch64_opnd_info *info,
699 const aarch64_insn code,
561a72d4
TC		 700 const aarch64_inst *inst ATTRIBUTE_UNUSED,
701 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 702{
703 uint64_t imm;
704 enum aarch64_opnd_qualifier opnd0_qualifier = inst->operands[0].qualifier;
705 aarch64_field field = {0, 0};
706
707 assert (info->idx == 1);
708
709 if (info->type == AARCH64_OPND_SIMD_FPIMM)
710 info->imm.is_fp = 1;
711
712 /* a:b:c:d:e:f:g:h */
713 imm = extract_fields (code, 0, 2, FLD_abc, FLD_defgh);
714 if (!info->imm.is_fp && aarch64_get_qualifier_esize (opnd0_qualifier) == 8)
715 {
716 /* Either MOVI <Dd>, #<imm>
717 or MOVI <Vd>.2D, #<imm>.
718 <imm> is a 64-bit immediate
719 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh',
720 encoded in "a:b:c:d:e:f:g:h". */
721 int i;
722 unsigned abcdefgh = imm;
723 for (imm = 0ull, i = 0; i < 8; i++)
724 if (((abcdefgh >> i) & 0x1) != 0)
725 imm |= 0xffull << (8 * i);
726 }
727 info->imm.value = imm;
728
729 /* cmode */
730 info->qualifier = get_expected_qualifier (inst, info->idx);
731 switch (info->qualifier)
732 {
733 case AARCH64_OPND_QLF_NIL:
734 /* no shift */
735 info->shifter.kind = AARCH64_MOD_NONE;
736 return 1;
737 case AARCH64_OPND_QLF_LSL:
738 /* shift zeros */
739 info->shifter.kind = AARCH64_MOD_LSL;
740 switch (aarch64_get_qualifier_esize (opnd0_qualifier))
741 {
742 case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break; /* per word */
743 case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break; /* per half */
f5555712 744 case 1: gen_sub_field (FLD_cmode, 1, 0, &field); break; /* per byte */
561a72d4 745 default: assert (0); return FALSE;
a06ea964
NC		 746 }
747 /* 00: 0; 01: 8; 10:16; 11:24. */
748 info->shifter.amount = extract_field_2 (&field, code, 0) << 3;
749 break;
750 case AARCH64_OPND_QLF_MSL:
751 /* shift ones */
752 info->shifter.kind = AARCH64_MOD_MSL;
753 gen_sub_field (FLD_cmode, 0, 1, &field); /* per word */
754 info->shifter.amount = extract_field_2 (&field, code, 0) ? 16 : 8;
755 break;
756 default:
757 assert (0);
561a72d4 758 return FALSE;
a06ea964
NC		 759 }
760
561a72d4 761 return TRUE;
a06ea964
NC		 762}
763
aa2aa4c6 764/* Decode an 8-bit floating-point immediate. */
561a72d4 765bfd_boolean
aa2aa4c6
RS		 766aarch64_ext_fpimm (const aarch64_operand *self, aarch64_opnd_info *info,
767 const aarch64_insn code,
561a72d4
TC		 768 const aarch64_inst *inst ATTRIBUTE_UNUSED,
769 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
aa2aa4c6
RS		 770{
771 info->imm.value = extract_all_fields (self, code);
772 info->imm.is_fp = 1;
561a72d4 773 return TRUE;
aa2aa4c6
RS		 774}
775
582e12bf 776/* Decode a 1-bit rotate immediate (#90 or #270). */
561a72d4 777bfd_boolean
582e12bf
RS		 778aarch64_ext_imm_rotate1 (const aarch64_operand *self, aarch64_opnd_info *info,
779 const aarch64_insn code,
561a72d4
TC		 780 const aarch64_inst *inst ATTRIBUTE_UNUSED,
781 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
c2c4ff8d
SN		 782{
783 uint64_t rot = extract_field (self->fields[0], code, 0);
582e12bf
RS		 784 assert (rot < 2U);
785 info->imm.value = rot * 180 + 90;
561a72d4 786 return TRUE;
582e12bf 787}
c2c4ff8d 788
582e12bf 789/* Decode a 2-bit rotate immediate (#0, #90, #180 or #270). */
561a72d4 790bfd_boolean
582e12bf
RS		 791aarch64_ext_imm_rotate2 (const aarch64_operand *self, aarch64_opnd_info *info,
792 const aarch64_insn code,
561a72d4
TC		 793 const aarch64_inst *inst ATTRIBUTE_UNUSED,
794 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
582e12bf
RS		 795{
796 uint64_t rot = extract_field (self->fields[0], code, 0);
797 assert (rot < 4U);
c2c4ff8d 798 info->imm.value = rot * 90;
561a72d4 799 return TRUE;
c2c4ff8d
SN		 800}
801
a06ea964 802/* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
561a72d4 803bfd_boolean
a06ea964
NC		 804aarch64_ext_fbits (const aarch64_operand *self ATTRIBUTE_UNUSED,
805 aarch64_opnd_info *info, const aarch64_insn code,
561a72d4
TC		 806 const aarch64_inst *inst ATTRIBUTE_UNUSED,
807 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 808{
809 info->imm.value = 64- extract_field (FLD_scale, code, 0);
561a72d4 810 return TRUE;
a06ea964
NC		 811}
812
813/* Decode arithmetic immediate for e.g.
814 SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */
561a72d4 815bfd_boolean
a06ea964
NC		 816aarch64_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED,
817 aarch64_opnd_info *info, const aarch64_insn code,
561a72d4
TC		 818 const aarch64_inst *inst ATTRIBUTE_UNUSED,
819 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 820{
821 aarch64_insn value;
822
823 info->shifter.kind = AARCH64_MOD_LSL;
824 /* shift */
825 value = extract_field (FLD_shift, code, 0);
826 if (value >= 2)
561a72d4 827 return FALSE;
a06ea964
NC		 828 info->shifter.amount = value ? 12 : 0;
829 /* imm12 (unsigned) */
830 info->imm.value = extract_field (FLD_imm12, code, 0);
831
561a72d4 832 return TRUE;
a06ea964
NC		 833}
834
e950b345
RS		 835/* Return true if VALUE is a valid logical immediate encoding, storing the
836 decoded value in *RESULT if so. ESIZE is the number of bytes in the
837 decoded immediate. */
561a72d4 838static bfd_boolean
e950b345 839decode_limm (uint32_t esize, aarch64_insn value, int64_t *result)
a06ea964
NC		 840{
841 uint64_t imm, mask;
a06ea964
NC		 842 uint32_t N, R, S;
843 unsigned simd_size;
a06ea964
NC		 844
845 /* value is N:immr:imms. */
846 S = value & 0x3f;
847 R = (value >> 6) & 0x3f;
848 N = (value >> 12) & 0x1;
849
a06ea964
NC		 850 /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R
851 (in other words, right rotated by R), then replicated. */
852 if (N != 0)
853 {
854 simd_size = 64;
855 mask = 0xffffffffffffffffull;
856 }
857 else
858 {
859 switch (S)
860 {
861 case 0x00 ... 0x1f: /* 0xxxxx */ simd_size = 32; break;
862 case 0x20 ... 0x2f: /* 10xxxx */ simd_size = 16; S &= 0xf; break;
863 case 0x30 ... 0x37: /* 110xxx */ simd_size = 8; S &= 0x7; break;
864 case 0x38 ... 0x3b: /* 1110xx */ simd_size = 4; S &= 0x3; break;
865 case 0x3c ... 0x3d: /* 11110x */ simd_size = 2; S &= 0x1; break;
561a72d4 866 default: return FALSE;
a06ea964
NC		 867 }
868 mask = (1ull << simd_size) - 1;
869 /* Top bits are IGNORED. */
870 R &= simd_size - 1;
871 }
e950b345
RS		 872
873 if (simd_size > esize * 8)
561a72d4 874 return FALSE;
e950b345 875
a06ea964
NC		 876 /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */
877 if (S == simd_size - 1)
561a72d4 878 return FALSE;
a06ea964
NC		 879 /* S+1 consecutive bits to 1. */
880 /* NOTE: S can't be 63 due to detection above. */
881 imm = (1ull << (S + 1)) - 1;
882 /* Rotate to the left by simd_size - R. */
883 if (R != 0)
884 imm = ((imm << (simd_size - R)) & mask) | (imm >> R);
885 /* Replicate the value according to SIMD size. */
886 switch (simd_size)
887 {
888 case 2: imm = (imm << 2) | imm;
1a0670f3 889 /* Fall through. */
a06ea964 890 case 4: imm = (imm << 4) | imm;
1a0670f3 891 /* Fall through. */
a06ea964 892 case 8: imm = (imm << 8) | imm;
1a0670f3 893 /* Fall through. */
a06ea964 894 case 16: imm = (imm << 16) | imm;
1a0670f3 895 /* Fall through. */
a06ea964 896 case 32: imm = (imm << 32) | imm;
1a0670f3 897 /* Fall through. */
a06ea964
NC		 898 case 64: break;
899 default: assert (0); return 0;
900 }
901
e950b345
RS		 902 *result = imm & ~((uint64_t) -1 << (esize * 4) << (esize * 4));
903
561a72d4 904 return TRUE;
e950b345
RS		 905}
906
907/* Decode a logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>. */
561a72d4 908bfd_boolean
e950b345
RS		 909aarch64_ext_limm (const aarch64_operand *self,
910 aarch64_opnd_info *info, const aarch64_insn code,
561a72d4
TC		 911 const aarch64_inst *inst,
912 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
e950b345
RS		 913{
914 uint32_t esize;
915 aarch64_insn value;
916
917 value = extract_fields (code, 0, 3, self->fields[0], self->fields[1],
918 self->fields[2]);
919 esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
920 return decode_limm (esize, value, &info->imm.value);
921}
a06ea964 922
e950b345 923/* Decode a logical immediate for the BIC alias of AND (etc.). */
561a72d4 924bfd_boolean
e950b345
RS		 925aarch64_ext_inv_limm (const aarch64_operand *self,
926 aarch64_opnd_info *info, const aarch64_insn code,
561a72d4
TC		 927 const aarch64_inst *inst,
928 aarch64_operand_error *errors)
e950b345 929{
561a72d4
TC		 930 if (!aarch64_ext_limm (self, info, code, inst, errors))
931 return FALSE;
e950b345 932 info->imm.value = ~info->imm.value;
561a72d4 933 return TRUE;
a06ea964
NC		 934}
935
936/* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
937 or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
561a72d4 938bfd_boolean
a06ea964
NC		 939aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED,
940 aarch64_opnd_info *info,
561a72d4
TC		 941 const aarch64_insn code, const aarch64_inst *inst,
942 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 943{
944 aarch64_insn value;
945
946 /* Rt */
947 info->reg.regno = extract_field (FLD_Rt, code, 0);
948
949 /* size */
950 value = extract_field (FLD_ldst_size, code, 0);
951 if (inst->opcode->iclass == ldstpair_indexed
952 || inst->opcode->iclass == ldstnapair_offs
953 || inst->opcode->iclass == ldstpair_off
954 || inst->opcode->iclass == loadlit)
955 {
956 enum aarch64_opnd_qualifier qualifier;
957 switch (value)
958 {
959 case 0: qualifier = AARCH64_OPND_QLF_S_S; break;
960 case 1: qualifier = AARCH64_OPND_QLF_S_D; break;
961 case 2: qualifier = AARCH64_OPND_QLF_S_Q; break;
561a72d4 962 default: return FALSE;
a06ea964
NC		 963 }
964 info->qualifier = qualifier;
965 }
966 else
967 {
968 /* opc1:size */
969 value = extract_fields (code, 0, 2, FLD_opc1, FLD_ldst_size);
970 if (value > 0x4)
561a72d4 971 return FALSE;
a06ea964
NC		 972 info->qualifier = get_sreg_qualifier_from_value (value);
973 }
974
561a72d4 975 return TRUE;
a06ea964
NC		 976}
977
978/* Decode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
561a72d4 979bfd_boolean
a06ea964
NC		 980aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
981 aarch64_opnd_info *info,
982 aarch64_insn code,
561a72d4
TC		 983 const aarch64_inst *inst ATTRIBUTE_UNUSED,
984 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 985{
986 /* Rn */
987 info->addr.base_regno = extract_field (FLD_Rn, code, 0);
561a72d4 988 return TRUE;
a06ea964
NC		 989}
990
f42f1a1d
TC		 991/* Decode the address operand for e.g.
992 stlur <Xt>, [<Xn|SP>{, <amount>}]. */
561a72d4 993bfd_boolean
f42f1a1d
TC		 994aarch64_ext_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
995 aarch64_opnd_info *info,
561a72d4
TC		 996 aarch64_insn code, const aarch64_inst *inst,
997 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
f42f1a1d
TC		 998{
999 info->qualifier = get_expected_qualifier (inst, info->idx);
1000
1001 /* Rn */
1002 info->addr.base_regno = extract_field (self->fields[0], code, 0);
1003
1004 /* simm9 */
1005 aarch64_insn imm = extract_fields (code, 0, 1, self->fields[1]);
1006 info->addr.offset.imm = sign_extend (imm, 8);
1007 if (extract_field (self->fields[2], code, 0) == 1) {
1008 info->addr.writeback = 1;
1009 info->addr.preind = 1;
1010 }
561a72d4 1011 return TRUE;
f42f1a1d
TC		 1012}
1013
a06ea964
NC		 1014/* Decode the address operand for e.g.
1015 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
561a72d4 1016bfd_boolean
a06ea964
NC		 1017aarch64_ext_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
1018 aarch64_opnd_info *info,
561a72d4
TC		 1019 aarch64_insn code, const aarch64_inst *inst,
1020 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 1021{
1022 aarch64_insn S, value;
1023
1024 /* Rn */
1025 info->addr.base_regno = extract_field (FLD_Rn, code, 0);
1026 /* Rm */
1027 info->addr.offset.regno = extract_field (FLD_Rm, code, 0);
1028 /* option */
1029 value = extract_field (FLD_option, code, 0);
1030 info->shifter.kind =
1031 aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */);
1032 /* Fix-up the shifter kind; although the table-driven approach is
1033 efficient, it is slightly inflexible, thus needing this fix-up. */
1034 if (info->shifter.kind == AARCH64_MOD_UXTX)
1035 info->shifter.kind = AARCH64_MOD_LSL;
1036 /* S */
1037 S = extract_field (FLD_S, code, 0);
1038 if (S == 0)
1039 {
1040 info->shifter.amount = 0;
1041 info->shifter.amount_present = 0;
1042 }
1043 else
1044 {
1045 int size;
1046 /* Need information in other operand(s) to help achieve the decoding
1047 from 'S' field. */
1048 info->qualifier = get_expected_qualifier (inst, info->idx);
1049 /* Get the size of the data element that is accessed, which may be
1050 different from that of the source register size, e.g. in strb/ldrb. */
1051 size = aarch64_get_qualifier_esize (info->qualifier);
1052 info->shifter.amount = get_logsz (size);
1053 info->shifter.amount_present = 1;
1054 }
1055
561a72d4 1056 return TRUE;
a06ea964
NC		 1057}
1058
1059/* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>], #<simm>. */
561a72d4 1060bfd_boolean
a06ea964 1061aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info,
561a72d4
TC		 1062 aarch64_insn code, const aarch64_inst *inst,
1063 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 1064{
1065 aarch64_insn imm;
1066 info->qualifier = get_expected_qualifier (inst, info->idx);
1067
1068 /* Rn */
1069 info->addr.base_regno = extract_field (FLD_Rn, code, 0);
1070 /* simm (imm9 or imm7) */
1071 imm = extract_field (self->fields[0], code, 0);
1072 info->addr.offset.imm = sign_extend (imm, fields[self->fields[0]].width - 1);
1073 if (self->fields[0] == FLD_imm7)
1074 /* scaled immediate in ld/st pair instructions. */
1075 info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier);
1076 /* qualifier */
1077 if (inst->opcode->iclass == ldst_unscaled
1078 || inst->opcode->iclass == ldstnapair_offs
1079 || inst->opcode->iclass == ldstpair_off
1080 || inst->opcode->iclass == ldst_unpriv)
1081 info->addr.writeback = 0;
1082 else
1083 {
1084 /* pre/post- index */
1085 info->addr.writeback = 1;
1086 if (extract_field (self->fields[1], code, 0) == 1)
1087 info->addr.preind = 1;
1088 else
1089 info->addr.postind = 1;
1090 }
1091
561a72d4 1092 return TRUE;
a06ea964
NC		 1093}
1094
1095/* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<simm>}]. */
561a72d4 1096bfd_boolean
a06ea964
NC		 1097aarch64_ext_addr_uimm12 (const aarch64_operand *self, aarch64_opnd_info *info,
1098 aarch64_insn code,
561a72d4
TC		 1099 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1100 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 1101{
1102 int shift;
1103 info->qualifier = get_expected_qualifier (inst, info->idx);
1104 shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
1105 /* Rn */
1106 info->addr.base_regno = extract_field (self->fields[0], code, 0);
1107 /* uimm12 */
1108 info->addr.offset.imm = extract_field (self->fields[1], code, 0) << shift;
561a72d4 1109 return TRUE;
a06ea964
NC		 1110}
1111
3f06e550 1112/* Decode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}]. */
561a72d4 1113bfd_boolean
3f06e550
SN		 1114aarch64_ext_addr_simm10 (const aarch64_operand *self, aarch64_opnd_info *info,
1115 aarch64_insn code,
561a72d4
TC		 1116 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1117 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
3f06e550
SN		 1118{
1119 aarch64_insn imm;
1120
1121 info->qualifier = get_expected_qualifier (inst, info->idx);
1122 /* Rn */
1123 info->addr.base_regno = extract_field (self->fields[0], code, 0);
1124 /* simm10 */
1125 imm = extract_fields (code, 0, 2, self->fields[1], self->fields[2]);
1126 info->addr.offset.imm = sign_extend (imm, 9) << 3;
1127 if (extract_field (self->fields[3], code, 0) == 1) {
1128 info->addr.writeback = 1;
1129 info->addr.preind = 1;
1130 }
561a72d4 1131 return TRUE;
3f06e550
SN		 1132}
1133
a06ea964
NC		 1134/* Decode the address operand for e.g.
1135 LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */
561a72d4 1136bfd_boolean
a06ea964
NC		 1137aarch64_ext_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED,
1138 aarch64_opnd_info *info,
561a72d4
TC		 1139 aarch64_insn code, const aarch64_inst *inst,
1140 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 1141{
1142 /* The opcode dependent area stores the number of elements in
1143 each structure to be loaded/stored. */
1144 int is_ld1r = get_opcode_dependent_value (inst->opcode) == 1;
1145
1146 /* Rn */
1147 info->addr.base_regno = extract_field (FLD_Rn, code, 0);
1148 /* Rm | #<amount> */
1149 info->addr.offset.regno = extract_field (FLD_Rm, code, 0);
1150 if (info->addr.offset.regno == 31)
1151 {
1152 if (inst->opcode->operands[0] == AARCH64_OPND_LVt_AL)
1153 /* Special handling of loading single structure to all lane. */
1154 info->addr.offset.imm = (is_ld1r ? 1
1155 : inst->operands[0].reglist.num_regs)
1156 * aarch64_get_qualifier_esize (inst->operands[0].qualifier);
1157 else
1158 info->addr.offset.imm = inst->operands[0].reglist.num_regs
1159 * aarch64_get_qualifier_esize (inst->operands[0].qualifier)
1160 * aarch64_get_qualifier_nelem (inst->operands[0].qualifier);
1161 }
1162 else
1163 info->addr.offset.is_reg = 1;
1164 info->addr.writeback = 1;
1165
561a72d4 1166 return TRUE;
a06ea964
NC		 1167}
1168
1169/* Decode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */
561a72d4 1170bfd_boolean
a06ea964
NC		 1171aarch64_ext_cond (const aarch64_operand *self ATTRIBUTE_UNUSED,
1172 aarch64_opnd_info *info,
561a72d4
TC		 1173 aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED,
1174 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 1175{
1176 aarch64_insn value;
1177 /* cond */
1178 value = extract_field (FLD_cond, code, 0);
1179 info->cond = get_cond_from_value (value);
561a72d4 1180 return TRUE;
a06ea964
NC		 1181}
1182
1183/* Decode the system register operand for e.g. MRS <Xt>, <systemreg>. */
561a72d4 1184bfd_boolean
a06ea964
NC		 1185aarch64_ext_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
1186 aarch64_opnd_info *info,
1187 aarch64_insn code,
561a72d4
TC		 1188 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1189 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 1190{
1191 /* op0:op1:CRn:CRm:op2 */
561a72d4
TC		 1192 info->sysreg.value = extract_fields (code, 0, 5, FLD_op0, FLD_op1, FLD_CRn,
1193 FLD_CRm, FLD_op2);
f9830ec1
TC		 1194 info->sysreg.flags = 0;
1195
1196 /* If a system instruction, check which restrictions should be on the register
1197 value during decoding, these will be enforced then. */
1198 if (inst->opcode->iclass == ic_system)
1199 {
1200 /* Check to see if it's read-only, else check if it's write only.
1201 if it's both or unspecified don't care. */
1202 if ((inst->opcode->flags & (F_SYS_READ | F_SYS_WRITE)) == F_SYS_READ)
1203 info->sysreg.flags = F_REG_READ;
1204 else if ((inst->opcode->flags & (F_SYS_READ | F_SYS_WRITE))
1205 == F_SYS_WRITE)
1206 info->sysreg.flags = F_REG_WRITE;
1207 }
1208
1209 return TRUE;
a06ea964
NC		 1210}
1211
1212/* Decode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */
561a72d4 1213bfd_boolean
a06ea964
NC		 1214aarch64_ext_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
1215 aarch64_opnd_info *info, aarch64_insn code,
561a72d4
TC		 1216 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1217 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 1218{
1219 int i;
1220 /* op1:op2 */
1221 info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2);
1222 for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
1223 if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield)
561a72d4 1224 return TRUE;
a06ea964 1225 /* Reserved value in <pstatefield>. */
561a72d4 1226 return FALSE;
a06ea964
NC		 1227}
1228
1229/* Decode the system instruction op operand for e.g. AT <at_op>, <Xt>. */
561a72d4 1230bfd_boolean
a06ea964
NC		 1231aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
1232 aarch64_opnd_info *info,
1233 aarch64_insn code,
561a72d4
TC		 1234 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1235 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 1236{
1237 int i;
1238 aarch64_insn value;
1239 const aarch64_sys_ins_reg *sysins_ops;
1240 /* op0:op1:CRn:CRm:op2 */
1241 value = extract_fields (code, 0, 5,
1242 FLD_op0, FLD_op1, FLD_CRn,
1243 FLD_CRm, FLD_op2);
1244
1245 switch (info->type)
1246 {
1247 case AARCH64_OPND_SYSREG_AT: sysins_ops = aarch64_sys_regs_at; break;
1248 case AARCH64_OPND_SYSREG_DC: sysins_ops = aarch64_sys_regs_dc; break;
1249 case AARCH64_OPND_SYSREG_IC: sysins_ops = aarch64_sys_regs_ic; break;
1250 case AARCH64_OPND_SYSREG_TLBI: sysins_ops = aarch64_sys_regs_tlbi; break;
561a72d4 1251 default: assert (0); return FALSE;
a06ea964
NC		 1252 }
1253
875880c6 1254 for (i = 0; sysins_ops[i].name != NULL; ++i)
a06ea964
NC		 1255 if (sysins_ops[i].value == value)
1256 {
1257 info->sysins_op = sysins_ops + i;
1258 DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.",
875880c6 1259 info->sysins_op->name,
a06ea964 1260 (unsigned)info->sysins_op->value,
ea2deeec 1261 aarch64_sys_ins_reg_has_xt (info->sysins_op), i);
561a72d4 1262 return TRUE;
a06ea964
NC		 1263 }
1264
561a72d4 1265 return FALSE;
a06ea964
NC		 1266}
1267
1268/* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>. */
1269
561a72d4 1270bfd_boolean
a06ea964
NC		 1271aarch64_ext_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED,
1272 aarch64_opnd_info *info,
1273 aarch64_insn code,
561a72d4
TC		 1274 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1275 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 1276{
1277 /* CRm */
1278 info->barrier = aarch64_barrier_options + extract_field (FLD_CRm, code, 0);
561a72d4 1279 return TRUE;
a06ea964
NC		 1280}
1281
1282/* Decode the prefetch operation option operand for e.g.
1283 PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
1284
561a72d4 1285bfd_boolean
a06ea964
NC		 1286aarch64_ext_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
1287 aarch64_opnd_info *info,
561a72d4
TC		 1288 aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED,
1289 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 1290{
1291 /* prfop in Rt */
1292 info->prfop = aarch64_prfops + extract_field (FLD_Rt, code, 0);
561a72d4 1293 return TRUE;
a06ea964
NC		 1294}
1295
9ed608f9
MW		 1296/* Decode the hint number for an alias taking an operand. Set info->hint_option
1297 to the matching name/value pair in aarch64_hint_options. */
1298
561a72d4 1299bfd_boolean
9ed608f9
MW		 1300aarch64_ext_hint (const aarch64_operand *self ATTRIBUTE_UNUSED,
1301 aarch64_opnd_info *info,
1302 aarch64_insn code,
561a72d4
TC		 1303 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1304 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
9ed608f9
MW		 1305{
1306 /* CRm:op2. */
1307 unsigned hint_number;
1308 int i;
1309
1310 hint_number = extract_fields (code, 0, 2, FLD_CRm, FLD_op2);
1311
1312 for (i = 0; aarch64_hint_options[i].name != NULL; i++)
1313 {
1314 if (hint_number == aarch64_hint_options[i].value)
1315 {
1316 info->hint_option = &(aarch64_hint_options[i]);
561a72d4 1317 return TRUE;
9ed608f9
MW		 1318 }
1319 }
1320
561a72d4 1321 return FALSE;
9ed608f9
MW		 1322}
1323
a06ea964
NC		 1324/* Decode the extended register operand for e.g.
1325 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
561a72d4 1326bfd_boolean
a06ea964
NC		 1327aarch64_ext_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
1328 aarch64_opnd_info *info,
1329 aarch64_insn code,
561a72d4
TC		 1330 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1331 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 1332{
1333 aarch64_insn value;
1334
1335 /* Rm */
1336 info->reg.regno = extract_field (FLD_Rm, code, 0);
1337 /* option */
1338 value = extract_field (FLD_option, code, 0);
1339 info->shifter.kind =
1340 aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */);
1341 /* imm3 */
1342 info->shifter.amount = extract_field (FLD_imm3, code, 0);
1343
1344 /* This makes the constraint checking happy. */
1345 info->shifter.operator_present = 1;
1346
1347 /* Assume inst->operands[0].qualifier has been resolved. */
1348 assert (inst->operands[0].qualifier != AARCH64_OPND_QLF_NIL);
1349 info->qualifier = AARCH64_OPND_QLF_W;
1350 if (inst->operands[0].qualifier == AARCH64_OPND_QLF_X
1351 && (info->shifter.kind == AARCH64_MOD_UXTX
1352 || info->shifter.kind == AARCH64_MOD_SXTX))
1353 info->qualifier = AARCH64_OPND_QLF_X;
1354
561a72d4 1355 return TRUE;
a06ea964
NC		 1356}
1357
1358/* Decode the shifted register operand for e.g.
1359 SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */
561a72d4 1360bfd_boolean
a06ea964
NC		 1361aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
1362 aarch64_opnd_info *info,
1363 aarch64_insn code,
561a72d4
TC		 1364 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1365 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 1366{
1367 aarch64_insn value;
1368
1369 /* Rm */
1370 info->reg.regno = extract_field (FLD_Rm, code, 0);
1371 /* shift */
1372 value = extract_field (FLD_shift, code, 0);
1373 info->shifter.kind =
1374 aarch64_get_operand_modifier_from_value (value, FALSE /* extend_p */);
1375 if (info->shifter.kind == AARCH64_MOD_ROR
1376 && inst->opcode->iclass != log_shift)
1377 /* ROR is not available for the shifted register operand in arithmetic
1378 instructions. */
561a72d4 1379 return FALSE;
a06ea964
NC		 1380 /* imm6 */
1381 info->shifter.amount = extract_field (FLD_imm6, code, 0);
1382
1383 /* This makes the constraint checking happy. */
1384 info->shifter.operator_present = 1;
1385
561a72d4 1386 return TRUE;
a06ea964 1387}
f11ad6bc 1388
98907a70
RS		 1389/* Decode an SVE address [<base>, #<offset>*<factor>, MUL VL],
1390 where <offset> is given by the OFFSET parameter and where <factor> is
1391 1 plus SELF's operand-dependent value. fields[0] specifies the field
1392 that holds <base>. */
561a72d4 1393static bfd_boolean
98907a70
RS		 1394aarch64_ext_sve_addr_reg_mul_vl (const aarch64_operand *self,
1395 aarch64_opnd_info *info, aarch64_insn code,
1396 int64_t offset)
1397{
1398 info->addr.base_regno = extract_field (self->fields[0], code, 0);
1399 info->addr.offset.imm = offset * (1 + get_operand_specific_data (self));
1400 info->addr.offset.is_reg = FALSE;
1401 info->addr.writeback = FALSE;
1402 info->addr.preind = TRUE;
1403 if (offset != 0)
1404 info->shifter.kind = AARCH64_MOD_MUL_VL;
1405 info->shifter.amount = 1;
1406 info->shifter.operator_present = (info->addr.offset.imm != 0);
1407 info->shifter.amount_present = FALSE;
561a72d4 1408 return TRUE;
98907a70
RS		 1409}
1410
1411/* Decode an SVE address [<base>, #<simm4>*<factor>, MUL VL],
1412 where <simm4> is a 4-bit signed value and where <factor> is 1 plus
1413 SELF's operand-dependent value. fields[0] specifies the field that
1414 holds <base>. <simm4> is encoded in the SVE_imm4 field. */
561a72d4 1415bfd_boolean
98907a70
RS		 1416aarch64_ext_sve_addr_ri_s4xvl (const aarch64_operand *self,
1417 aarch64_opnd_info *info, aarch64_insn code,
561a72d4
TC		 1418 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1419 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
98907a70
RS		 1420{
1421 int offset;
1422
1423 offset = extract_field (FLD_SVE_imm4, code, 0);
1424 offset = ((offset + 8) & 15) - 8;
1425 return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
1426}
1427
1428/* Decode an SVE address [<base>, #<simm6>*<factor>, MUL VL],
1429 where <simm6> is a 6-bit signed value and where <factor> is 1 plus
1430 SELF's operand-dependent value. fields[0] specifies the field that
1431 holds <base>. <simm6> is encoded in the SVE_imm6 field. */
561a72d4 1432bfd_boolean
98907a70
RS		 1433aarch64_ext_sve_addr_ri_s6xvl (const aarch64_operand *self,
1434 aarch64_opnd_info *info, aarch64_insn code,
561a72d4
TC		 1435 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1436 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
98907a70
RS		 1437{
1438 int offset;
1439
1440 offset = extract_field (FLD_SVE_imm6, code, 0);
1441 offset = (((offset + 32) & 63) - 32);
1442 return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
1443}
1444
1445/* Decode an SVE address [<base>, #<simm9>*<factor>, MUL VL],
1446 where <simm9> is a 9-bit signed value and where <factor> is 1 plus
1447 SELF's operand-dependent value. fields[0] specifies the field that
1448 holds <base>. <simm9> is encoded in the concatenation of the SVE_imm6
1449 and imm3 fields, with imm3 being the less-significant part. */
561a72d4 1450bfd_boolean
98907a70
RS		 1451aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand *self,
1452 aarch64_opnd_info *info,
1453 aarch64_insn code,
561a72d4
TC		 1454 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1455 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
98907a70
RS		 1456{
1457 int offset;
1458
1459 offset = extract_fields (code, 0, 2, FLD_SVE_imm6, FLD_imm3);
1460 offset = (((offset + 256) & 511) - 256);
1461 return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
1462}
1463
4df068de
RS		 1464/* Decode an SVE address [<base>, #<offset> << <shift>], where <offset>
1465 is given by the OFFSET parameter and where <shift> is SELF's operand-
1466 dependent value. fields[0] specifies the base register field <base>. */
561a72d4 1467static bfd_boolean
4df068de
RS		 1468aarch64_ext_sve_addr_reg_imm (const aarch64_operand *self,
1469 aarch64_opnd_info *info, aarch64_insn code,
1470 int64_t offset)
1471{
1472 info->addr.base_regno = extract_field (self->fields[0], code, 0);
1473 info->addr.offset.imm = offset * (1 << get_operand_specific_data (self));
1474 info->addr.offset.is_reg = FALSE;
1475 info->addr.writeback = FALSE;
1476 info->addr.preind = TRUE;
1477 info->shifter.operator_present = FALSE;
1478 info->shifter.amount_present = FALSE;
561a72d4 1479 return TRUE;
4df068de
RS		 1480}
1481
582e12bf
RS		 1482/* Decode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4>
1483 is a 4-bit signed number and where <shift> is SELF's operand-dependent
1484 value. fields[0] specifies the base register field. */
561a72d4 1485bfd_boolean
582e12bf
RS		 1486aarch64_ext_sve_addr_ri_s4 (const aarch64_operand *self,
1487 aarch64_opnd_info *info, aarch64_insn code,
561a72d4
TC		 1488 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1489 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
582e12bf
RS		 1490{
1491 int offset = sign_extend (extract_field (FLD_SVE_imm4, code, 0), 3);
1492 return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
1493}
1494
4df068de
RS		 1495/* Decode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
1496 is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
1497 value. fields[0] specifies the base register field. */
561a72d4 1498bfd_boolean
4df068de
RS		 1499aarch64_ext_sve_addr_ri_u6 (const aarch64_operand *self,
1500 aarch64_opnd_info *info, aarch64_insn code,
561a72d4
TC		 1501 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1502 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
4df068de
RS		 1503{
1504 int offset = extract_field (FLD_SVE_imm6, code, 0);
1505 return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
1506}
1507
1508/* Decode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift>
1509 is SELF's operand-dependent value. fields[0] specifies the base
1510 register field and fields[1] specifies the offset register field. */
561a72d4 1511bfd_boolean
4df068de
RS		 1512aarch64_ext_sve_addr_rr_lsl (const aarch64_operand *self,
1513 aarch64_opnd_info *info, aarch64_insn code,
561a72d4
TC		 1514 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1515 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
4df068de 1516{
eaf02703 1517 int index_regno;
4df068de 1518
eaf02703
MR		 1519 index_regno = extract_field (self->fields[1], code, 0);
1520 if (index_regno == 31 && (self->flags & OPD_F_NO_ZR) != 0)
561a72d4 1521 return FALSE;
4df068de
RS		 1522
1523 info->addr.base_regno = extract_field (self->fields[0], code, 0);
eaf02703 1524 info->addr.offset.regno = index_regno;
4df068de
RS		 1525 info->addr.offset.is_reg = TRUE;
1526 info->addr.writeback = FALSE;
1527 info->addr.preind = TRUE;
1528 info->shifter.kind = AARCH64_MOD_LSL;
1529 info->shifter.amount = get_operand_specific_data (self);
1530 info->shifter.operator_present = (info->shifter.amount != 0);
1531 info->shifter.amount_present = (info->shifter.amount != 0);
561a72d4 1532 return TRUE;
4df068de
RS		 1533}
1534
1535/* Decode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where
1536 <shift> is SELF's operand-dependent value. fields[0] specifies the
1537 base register field, fields[1] specifies the offset register field and
1538 fields[2] is a single-bit field that selects SXTW over UXTW. */
561a72d4 1539bfd_boolean
4df068de
RS		 1540aarch64_ext_sve_addr_rz_xtw (const aarch64_operand *self,
1541 aarch64_opnd_info *info, aarch64_insn code,
561a72d4
TC		 1542 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1543 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
4df068de
RS		 1544{
1545 info->addr.base_regno = extract_field (self->fields[0], code, 0);
1546 info->addr.offset.regno = extract_field (self->fields[1], code, 0);
1547 info->addr.offset.is_reg = TRUE;
1548 info->addr.writeback = FALSE;
1549 info->addr.preind = TRUE;
1550 if (extract_field (self->fields[2], code, 0))
1551 info->shifter.kind = AARCH64_MOD_SXTW;
1552 else
1553 info->shifter.kind = AARCH64_MOD_UXTW;
1554 info->shifter.amount = get_operand_specific_data (self);
1555 info->shifter.operator_present = TRUE;
1556 info->shifter.amount_present = (info->shifter.amount != 0);
561a72d4 1557 return TRUE;
4df068de
RS		 1558}
1559
1560/* Decode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a
1561 5-bit unsigned number and where <shift> is SELF's operand-dependent value.
1562 fields[0] specifies the base register field. */
561a72d4 1563bfd_boolean
4df068de
RS		 1564aarch64_ext_sve_addr_zi_u5 (const aarch64_operand *self,
1565 aarch64_opnd_info *info, aarch64_insn code,
561a72d4
TC		 1566 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1567 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
4df068de
RS		 1568{
1569 int offset = extract_field (FLD_imm5, code, 0);
1570 return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
1571}
1572
1573/* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, <modifier> {#<msz>}}],
1574 where <modifier> is given by KIND and where <msz> is a 2-bit unsigned
1575 number. fields[0] specifies the base register field and fields[1]
1576 specifies the offset register field. */
561a72d4 1577static bfd_boolean
4df068de
RS		 1578aarch64_ext_sve_addr_zz (const aarch64_operand *self, aarch64_opnd_info *info,
1579 aarch64_insn code, enum aarch64_modifier_kind kind)
1580{
1581 info->addr.base_regno = extract_field (self->fields[0], code, 0);
1582 info->addr.offset.regno = extract_field (self->fields[1], code, 0);
1583 info->addr.offset.is_reg = TRUE;
1584 info->addr.writeback = FALSE;
1585 info->addr.preind = TRUE;
1586 info->shifter.kind = kind;
1587 info->shifter.amount = extract_field (FLD_SVE_msz, code, 0);
1588 info->shifter.operator_present = (kind != AARCH64_MOD_LSL
1589 || info->shifter.amount != 0);
1590 info->shifter.amount_present = (info->shifter.amount != 0);
561a72d4 1591 return TRUE;
4df068de
RS		 1592}
1593
1594/* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where
1595 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1596 field and fields[1] specifies the offset register field. */
561a72d4 1597bfd_boolean
4df068de
RS		 1598aarch64_ext_sve_addr_zz_lsl (const aarch64_operand *self,
1599 aarch64_opnd_info *info, aarch64_insn code,
561a72d4
TC		 1600 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1601 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
4df068de
RS		 1602{
1603 return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_LSL);
1604}
1605
1606/* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where
1607 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1608 field and fields[1] specifies the offset register field. */
561a72d4 1609bfd_boolean
4df068de
RS		 1610aarch64_ext_sve_addr_zz_sxtw (const aarch64_operand *self,
1611 aarch64_opnd_info *info, aarch64_insn code,
561a72d4
TC		 1612 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1613 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
4df068de
RS		 1614{
1615 return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_SXTW);
1616}
1617
1618/* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where
1619 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1620 field and fields[1] specifies the offset register field. */
561a72d4 1621bfd_boolean
4df068de
RS		 1622aarch64_ext_sve_addr_zz_uxtw (const aarch64_operand *self,
1623 aarch64_opnd_info *info, aarch64_insn code,
561a72d4
TC		 1624 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1625 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
4df068de
RS		 1626{
1627 return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_UXTW);
1628}
1629
e950b345
RS		 1630/* Finish decoding an SVE arithmetic immediate, given that INFO already
1631 has the raw field value and that the low 8 bits decode to VALUE. */
561a72d4 1632static bfd_boolean
e950b345
RS		 1633decode_sve_aimm (aarch64_opnd_info *info, int64_t value)
1634{
1635 info->shifter.kind = AARCH64_MOD_LSL;
1636 info->shifter.amount = 0;
1637 if (info->imm.value & 0x100)
1638 {
1639 if (value == 0)
1640 /* Decode 0x100 as #0, LSL #8. */
1641 info->shifter.amount = 8;
1642 else
1643 value *= 256;
1644 }
1645 info->shifter.operator_present = (info->shifter.amount != 0);
1646 info->shifter.amount_present = (info->shifter.amount != 0);
1647 info->imm.value = value;
561a72d4 1648 return TRUE;
e950b345
RS		 1649}
1650
1651/* Decode an SVE ADD/SUB immediate. */
561a72d4 1652bfd_boolean
e950b345
RS		 1653aarch64_ext_sve_aimm (const aarch64_operand *self,
1654 aarch64_opnd_info *info, const aarch64_insn code,
561a72d4
TC		 1655 const aarch64_inst *inst,
1656 aarch64_operand_error *errors)
e950b345 1657{
561a72d4 1658 return (aarch64_ext_imm (self, info, code, inst, errors)
e950b345
RS		 1659 && decode_sve_aimm (info, (uint8_t) info->imm.value));
1660}
1661
1662/* Decode an SVE CPY/DUP immediate. */
561a72d4 1663bfd_boolean
e950b345
RS		 1664aarch64_ext_sve_asimm (const aarch64_operand *self,
1665 aarch64_opnd_info *info, const aarch64_insn code,
561a72d4
TC		 1666 const aarch64_inst *inst,
1667 aarch64_operand_error *errors)
e950b345 1668{
561a72d4 1669 return (aarch64_ext_imm (self, info, code, inst, errors)
e950b345
RS		 1670 && decode_sve_aimm (info, (int8_t) info->imm.value));
1671}
1672
165d4950
RS		 1673/* Decode a single-bit immediate that selects between #0.5 and #1.0.
1674 The fields array specifies which field to use. */
561a72d4 1675bfd_boolean
165d4950
RS		 1676aarch64_ext_sve_float_half_one (const aarch64_operand *self,
1677 aarch64_opnd_info *info, aarch64_insn code,
561a72d4
TC		 1678 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1679 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
165d4950
RS		 1680{
1681 if (extract_field (self->fields[0], code, 0))
1682 info->imm.value = 0x3f800000;
1683 else
1684 info->imm.value = 0x3f000000;
1685 info->imm.is_fp = TRUE;
561a72d4 1686 return TRUE;
165d4950
RS		 1687}
1688
1689/* Decode a single-bit immediate that selects between #0.5 and #2.0.
1690 The fields array specifies which field to use. */
561a72d4 1691bfd_boolean
165d4950
RS		 1692aarch64_ext_sve_float_half_two (const aarch64_operand *self,
1693 aarch64_opnd_info *info, aarch64_insn code,
561a72d4
TC		 1694 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1695 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
165d4950
RS		 1696{
1697 if (extract_field (self->fields[0], code, 0))
1698 info->imm.value = 0x40000000;
1699 else
1700 info->imm.value = 0x3f000000;
1701 info->imm.is_fp = TRUE;
561a72d4 1702 return TRUE;
165d4950
RS		 1703}
1704
1705/* Decode a single-bit immediate that selects between #0.0 and #1.0.
1706 The fields array specifies which field to use. */
561a72d4 1707bfd_boolean
165d4950
RS		 1708aarch64_ext_sve_float_zero_one (const aarch64_operand *self,
1709 aarch64_opnd_info *info, aarch64_insn code,
561a72d4
TC		 1710 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1711 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
165d4950
RS		 1712{
1713 if (extract_field (self->fields[0], code, 0))
1714 info->imm.value = 0x3f800000;
1715 else
1716 info->imm.value = 0x0;
1717 info->imm.is_fp = TRUE;
561a72d4 1718 return TRUE;
165d4950
RS		 1719}
1720
f11ad6bc
RS		 1721/* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields
1722 array specifies which field to use for Zn. MM is encoded in the
1723 concatenation of imm5 and SVE_tszh, with imm5 being the less
1724 significant part. */
561a72d4 1725bfd_boolean
f11ad6bc
RS		 1726aarch64_ext_sve_index (const aarch64_operand *self,
1727 aarch64_opnd_info *info, aarch64_insn code,
561a72d4
TC		 1728 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1729 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
f11ad6bc
RS		 1730{
1731 int val;
1732
1733 info->reglane.regno = extract_field (self->fields[0], code, 0);
1734 val = extract_fields (code, 0, 2, FLD_SVE_tszh, FLD_imm5);
582e12bf 1735 if ((val & 31) == 0)
f11ad6bc
RS		 1736 return 0;
1737 while ((val & 1) == 0)
1738 val /= 2;
1739 info->reglane.index = val / 2;
561a72d4 1740 return TRUE;
f11ad6bc
RS		 1741}
1742
e950b345 1743/* Decode a logical immediate for the MOV alias of SVE DUPM. */
561a72d4 1744bfd_boolean
e950b345
RS		 1745aarch64_ext_sve_limm_mov (const aarch64_operand *self,
1746 aarch64_opnd_info *info, const aarch64_insn code,
561a72d4
TC		 1747 const aarch64_inst *inst,
1748 aarch64_operand_error *errors)
e950b345
RS		 1749{
1750 int esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
561a72d4 1751 return (aarch64_ext_limm (self, info, code, inst, errors)
e950b345
RS		 1752 && aarch64_sve_dupm_mov_immediate_p (info->imm.value, esize));
1753}
1754
582e12bf
RS		 1755/* Decode Zn[MM], where Zn occupies the least-significant part of the field
1756 and where MM occupies the most-significant part. The operand-dependent
1757 value specifies the number of bits in Zn. */
561a72d4 1758bfd_boolean
582e12bf
RS		 1759aarch64_ext_sve_quad_index (const aarch64_operand *self,
1760 aarch64_opnd_info *info, aarch64_insn code,
561a72d4
TC		 1761 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1762 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
582e12bf
RS		 1763{
1764 unsigned int reg_bits = get_operand_specific_data (self);
1765 unsigned int val = extract_all_fields (self, code);
1766 info->reglane.regno = val & ((1 << reg_bits) - 1);
1767 info->reglane.index = val >> reg_bits;
561a72d4 1768 return TRUE;
582e12bf
RS		 1769}
1770
f11ad6bc
RS		 1771/* Decode {Zn.<T> - Zm.<T>}. The fields array specifies which field
1772 to use for Zn. The opcode-dependent value specifies the number
1773 of registers in the list. */
561a72d4 1774bfd_boolean
f11ad6bc
RS		 1775aarch64_ext_sve_reglist (const aarch64_operand *self,
1776 aarch64_opnd_info *info, aarch64_insn code,
561a72d4
TC		 1777 const aarch64_inst *inst ATTRIBUTE_UNUSED,
1778 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
f11ad6bc
RS		 1779{
1780 info->reglist.first_regno = extract_field (self->fields[0], code, 0);
1781 info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
561a72d4 1782 return TRUE;
f11ad6bc 1783}
2442d846
RS		 1784
1785/* Decode <pattern>{, MUL #<amount>}. The fields array specifies which
1786 fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
1787 field. */
561a72d4 1788bfd_boolean
2442d846
RS		 1789aarch64_ext_sve_scale (const aarch64_operand *self,
1790 aarch64_opnd_info *info, aarch64_insn code,
561a72d4 1791 const aarch64_inst *inst, aarch64_operand_error *errors)
2442d846
RS		 1792{
1793 int val;
1794
561a72d4
TC		 1795 if (!aarch64_ext_imm (self, info, code, inst, errors))
1796 return FALSE;
2442d846
RS		 1797 val = extract_field (FLD_SVE_imm4, code, 0);
1798 info->shifter.kind = AARCH64_MOD_MUL;
1799 info->shifter.amount = val + 1;
1800 info->shifter.operator_present = (val != 0);
1801 info->shifter.amount_present = (val != 0);
561a72d4 1802 return TRUE;
2442d846 1803}
e950b345
RS		 1804
1805/* Return the top set bit in VALUE, which is expected to be relatively
1806 small. */
1807static uint64_t
1808get_top_bit (uint64_t value)
1809{
1810 while ((value & -value) != value)
1811 value -= value & -value;
1812 return value;
1813}
1814
1815/* Decode an SVE shift-left immediate. */
561a72d4 1816bfd_boolean
e950b345
RS		 1817aarch64_ext_sve_shlimm (const aarch64_operand *self,
1818 aarch64_opnd_info *info, const aarch64_insn code,
561a72d4 1819 const aarch64_inst *inst, aarch64_operand_error *errors)
e950b345 1820{
561a72d4 1821 if (!aarch64_ext_imm (self, info, code, inst, errors)
e950b345 1822 || info->imm.value == 0)
561a72d4 1823 return FALSE;
e950b345
RS		 1824
1825 info->imm.value -= get_top_bit (info->imm.value);
561a72d4 1826 return TRUE;
e950b345
RS		 1827}
1828
1829/* Decode an SVE shift-right immediate. */
561a72d4 1830bfd_boolean
e950b345
RS		 1831aarch64_ext_sve_shrimm (const aarch64_operand *self,
1832 aarch64_opnd_info *info, const aarch64_insn code,
561a72d4 1833 const aarch64_inst *inst, aarch64_operand_error *errors)
e950b345 1834{
561a72d4 1835 if (!aarch64_ext_imm (self, info, code, inst, errors)
e950b345 1836 || info->imm.value == 0)
561a72d4 1837 return FALSE;
e950b345
RS		 1838
1839 info->imm.value = get_top_bit (info->imm.value) * 2 - info->imm.value;
561a72d4 1840 return TRUE;
e950b345 1841}
a06ea964
NC		 1842\f
1843/* Bitfields that are commonly used to encode certain operands' information
1844 may be partially used as part of the base opcode in some instructions.
1845 For example, the bit 1 of the field 'size' in
1846 FCVTXN <Vb><d>, <Va><n>
1847 is actually part of the base opcode, while only size<0> is available
1848 for encoding the register type. Another example is the AdvSIMD
1849 instruction ORR (register), in which the field 'size' is also used for
1850 the base opcode, leaving only the field 'Q' available to encode the
1851 vector register arrangement specifier '8B' or '16B'.
1852
1853 This function tries to deduce the qualifier from the value of partially
1854 constrained field(s). Given the VALUE of such a field or fields, the
1855 qualifiers CANDIDATES and the MASK (indicating which bits are valid for
1856 operand encoding), the function returns the matching qualifier or
1857 AARCH64_OPND_QLF_NIL if nothing matches.
1858
1859 N.B. CANDIDATES is a group of possible qualifiers that are valid for
1860 one operand; it has a maximum of AARCH64_MAX_QLF_SEQ_NUM qualifiers and
1861 may end with AARCH64_OPND_QLF_NIL. */
1862
1863static enum aarch64_opnd_qualifier
1864get_qualifier_from_partial_encoding (aarch64_insn value,
1865 const enum aarch64_opnd_qualifier* \
1866 candidates,
1867 aarch64_insn mask)
1868{
1869 int i;
1870 DEBUG_TRACE ("enter with value: %d, mask: %d", (int)value, (int)mask);
1871 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
1872 {
1873 aarch64_insn standard_value;
1874 if (candidates[i] == AARCH64_OPND_QLF_NIL)
1875 break;
1876 standard_value = aarch64_get_qualifier_standard_value (candidates[i]);
1877 if ((standard_value & mask) == (value & mask))
1878 return candidates[i];
1879 }
1880 return AARCH64_OPND_QLF_NIL;
1881}
1882
1883/* Given a list of qualifier sequences, return all possible valid qualifiers
1884 for operand IDX in QUALIFIERS.
1885 Assume QUALIFIERS is an array whose length is large enough. */
1886
1887static void
1888get_operand_possible_qualifiers (int idx,
1889 const aarch64_opnd_qualifier_seq_t *list,
1890 enum aarch64_opnd_qualifier *qualifiers)
1891{
1892 int i;
1893 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
1894 if ((qualifiers[i] = list[i][idx]) == AARCH64_OPND_QLF_NIL)
1895 break;
1896}
1897
1898/* Decode the size Q field for e.g. SHADD.
1899 We tag one operand with the qualifer according to the code;
1900 whether the qualifier is valid for this opcode or not, it is the
1901 duty of the semantic checking. */
1902
1903static int
1904decode_sizeq (aarch64_inst *inst)
1905{
1906 int idx;
1907 enum aarch64_opnd_qualifier qualifier;
1908 aarch64_insn code;
1909 aarch64_insn value, mask;
1910 enum aarch64_field_kind fld_sz;
1911 enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM];
1912
1913 if (inst->opcode->iclass == asisdlse
1914 || inst->opcode->iclass == asisdlsep
1915 || inst->opcode->iclass == asisdlso
1916 || inst->opcode->iclass == asisdlsop)
1917 fld_sz = FLD_vldst_size;
1918 else
1919 fld_sz = FLD_size;
1920
1921 code = inst->value;
1922 value = extract_fields (code, inst->opcode->mask, 2, fld_sz, FLD_Q);
1923 /* Obtain the info that which bits of fields Q and size are actually
1924 available for operand encoding. Opcodes like FMAXNM and FMLA have
1925 size[1] unavailable. */
1926 mask = extract_fields (~inst->opcode->mask, 0, 2, fld_sz, FLD_Q);
1927
1928 /* The index of the operand we are going to tag a qualifier and the qualifer
1929 itself are reasoned from the value of the size and Q fields and the
1930 possible valid qualifier lists. */
1931 idx = aarch64_select_operand_for_sizeq_field_coding (inst->opcode);
1932 DEBUG_TRACE ("key idx: %d", idx);
1933
1934 /* For most related instruciton, size:Q are fully available for operand
1935 encoding. */
1936 if (mask == 0x7)
1937 {
1938 inst->operands[idx].qualifier = get_vreg_qualifier_from_value (value);
1939 return 1;
1940 }
1941
1942 get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list,
1943 candidates);
1944#ifdef DEBUG_AARCH64
1945 if (debug_dump)
1946 {
1947 int i;
1948 for (i = 0; candidates[i] != AARCH64_OPND_QLF_NIL
1949 && i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
1950 DEBUG_TRACE ("qualifier %d: %s", i,
1951 aarch64_get_qualifier_name(candidates[i]));
1952 DEBUG_TRACE ("%d, %d", (int)value, (int)mask);
1953 }
1954#endif /* DEBUG_AARCH64 */
1955
1956 qualifier = get_qualifier_from_partial_encoding (value, candidates, mask);
1957
1958 if (qualifier == AARCH64_OPND_QLF_NIL)
1959 return 0;
1960
1961 inst->operands[idx].qualifier = qualifier;
1962 return 1;
1963}
1964
1965/* Decode size[0]:Q, i.e. bit 22 and bit 30, for
1966 e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1967
1968static int
1969decode_asimd_fcvt (aarch64_inst *inst)
1970{
1971 aarch64_field field = {0, 0};
1972 aarch64_insn value;
1973 enum aarch64_opnd_qualifier qualifier;
1974
1975 gen_sub_field (FLD_size, 0, 1, &field);
1976 value = extract_field_2 (&field, inst->value, 0);
1977 qualifier = value == 0 ? AARCH64_OPND_QLF_V_4S
1978 : AARCH64_OPND_QLF_V_2D;
1979 switch (inst->opcode->op)
1980 {
1981 case OP_FCVTN:
1982 case OP_FCVTN2:
1983 /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1984 inst->operands[1].qualifier = qualifier;
1985 break;
1986 case OP_FCVTL:
1987 case OP_FCVTL2:
1988 /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
1989 inst->operands[0].qualifier = qualifier;
1990 break;
1991 default:
1992 assert (0);
1993 return 0;
1994 }
1995
1996 return 1;
1997}
1998
1999/* Decode size[0], i.e. bit 22, for
2000 e.g. FCVTXN <Vb><d>, <Va><n>. */
2001
2002static int
2003decode_asisd_fcvtxn (aarch64_inst *inst)
2004{
2005 aarch64_field field = {0, 0};
2006 gen_sub_field (FLD_size, 0, 1, &field);
2007 if (!extract_field_2 (&field, inst->value, 0))
2008 return 0;
2009 inst->operands[0].qualifier = AARCH64_OPND_QLF_S_S;
2010 return 1;
2011}
2012
2013/* Decode the 'opc' field for e.g. FCVT <Dd>, <Sn>. */
2014static int
2015decode_fcvt (aarch64_inst *inst)
2016{
2017 enum aarch64_opnd_qualifier qualifier;
2018 aarch64_insn value;
2019 const aarch64_field field = {15, 2};
2020
2021 /* opc dstsize */
2022 value = extract_field_2 (&field, inst->value, 0);
2023 switch (value)
2024 {
2025 case 0: qualifier = AARCH64_OPND_QLF_S_S; break;
2026 case 1: qualifier = AARCH64_OPND_QLF_S_D; break;
2027 case 3: qualifier = AARCH64_OPND_QLF_S_H; break;
2028 default: return 0;
2029 }
2030 inst->operands[0].qualifier = qualifier;
2031
2032 return 1;
2033}
2034
2035/* Do miscellaneous decodings that are not common enough to be driven by
2036 flags. */
2037
2038static int
2039do_misc_decoding (aarch64_inst *inst)
2040{
c0890d26 2041 unsigned int value;
a06ea964
NC		 2042 switch (inst->opcode->op)
2043 {
2044 case OP_FCVT:
2045 return decode_fcvt (inst);
c0890d26 2046
a06ea964
NC		 2047 case OP_FCVTN:
2048 case OP_FCVTN2:
2049 case OP_FCVTL:
2050 case OP_FCVTL2:
2051 return decode_asimd_fcvt (inst);
c0890d26 2052
a06ea964
NC		 2053 case OP_FCVTXN_S:
2054 return decode_asisd_fcvtxn (inst);
c0890d26
RS		 2055
2056 case OP_MOV_P_P:
2057 case OP_MOVS_P_P:
2058 value = extract_field (FLD_SVE_Pn, inst->value, 0);
2059 return (value == extract_field (FLD_SVE_Pm, inst->value, 0)
2060 && value == extract_field (FLD_SVE_Pg4_10, inst->value, 0));
2061
2062 case OP_MOV_Z_P_Z:
2063 return (extract_field (FLD_SVE_Zd, inst->value, 0)
2064 == extract_field (FLD_SVE_Zm_16, inst->value, 0));
2065
2066 case OP_MOV_Z_V:
2067 /* Index must be zero. */
2068 value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
582e12bf 2069 return value > 0 && value <= 16 && value == (value & -value);
c0890d26
RS		 2070
2071 case OP_MOV_Z_Z:
2072 return (extract_field (FLD_SVE_Zn, inst->value, 0)
2073 == extract_field (FLD_SVE_Zm_16, inst->value, 0));
2074
2075 case OP_MOV_Z_Zi:
2076 /* Index must be nonzero. */
2077 value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
582e12bf 2078 return value > 0 && value != (value & -value);
c0890d26
RS		 2079
2080 case OP_MOVM_P_P_P:
2081 return (extract_field (FLD_SVE_Pd, inst->value, 0)
2082 == extract_field (FLD_SVE_Pm, inst->value, 0));
2083
2084 case OP_MOVZS_P_P_P:
2085 case OP_MOVZ_P_P_P:
2086 return (extract_field (FLD_SVE_Pn, inst->value, 0)
2087 == extract_field (FLD_SVE_Pm, inst->value, 0));
2088
2089 case OP_NOTS_P_P_P_Z:
2090 case OP_NOT_P_P_P_Z:
2091 return (extract_field (FLD_SVE_Pm, inst->value, 0)
2092 == extract_field (FLD_SVE_Pg4_10, inst->value, 0));
2093
a06ea964
NC		 2094 default:
2095 return 0;
2096 }
2097}
2098
2099/* Opcodes that have fields shared by multiple operands are usually flagged
2100 with flags. In this function, we detect such flags, decode the related
2101 field(s) and store the information in one of the related operands. The
2102 'one' operand is not any operand but one of the operands that can
2103 accommadate all the information that has been decoded. */
2104
2105static int
2106do_special_decoding (aarch64_inst *inst)
2107{
2108 int idx;
2109 aarch64_insn value;
2110 /* Condition for truly conditional executed instructions, e.g. b.cond. */
2111 if (inst->opcode->flags & F_COND)
2112 {
2113 value = extract_field (FLD_cond2, inst->value, 0);
2114 inst->cond = get_cond_from_value (value);
2115 }
2116 /* 'sf' field. */
2117 if (inst->opcode->flags & F_SF)
2118 {
2119 idx = select_operand_for_sf_field_coding (inst->opcode);
2120 value = extract_field (FLD_sf, inst->value, 0);
2121 inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
2122 if ((inst->opcode->flags & F_N)
2123 && extract_field (FLD_N, inst->value, 0) != value)
2124 return 0;
2125 }
ee804238
JW		 2126 /* 'sf' field. */
2127 if (inst->opcode->flags & F_LSE_SZ)
2128 {
2129 idx = select_operand_for_sf_field_coding (inst->opcode);
2130 value = extract_field (FLD_lse_sz, inst->value, 0);
2131 inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
2132 }
a06ea964
NC		 2133 /* size:Q fields. */
2134 if (inst->opcode->flags & F_SIZEQ)
2135 return decode_sizeq (inst);
2136
2137 if (inst->opcode->flags & F_FPTYPE)
2138 {
2139 idx = select_operand_for_fptype_field_coding (inst->opcode);
2140 value = extract_field (FLD_type, inst->value, 0);
2141 switch (value)
2142 {
2143 case 0: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_S; break;
2144 case 1: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_D; break;
2145 case 3: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_H; break;
2146 default: return 0;
2147 }
2148 }
2149
2150 if (inst->opcode->flags & F_SSIZE)
2151 {
2152 /* N.B. some opcodes like FCMGT <V><d>, <V><n>, #0 have the size[1] as part
2153 of the base opcode. */
2154 aarch64_insn mask;
2155 enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM];
2156 idx = select_operand_for_scalar_size_field_coding (inst->opcode);
2157 value = extract_field (FLD_size, inst->value, inst->opcode->mask);
2158 mask = extract_field (FLD_size, ~inst->opcode->mask, 0);
2159 /* For most related instruciton, the 'size' field is fully available for
2160 operand encoding. */
2161 if (mask == 0x3)
2162 inst->operands[idx].qualifier = get_sreg_qualifier_from_value (value);
2163 else
2164 {
2165 get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list,
2166 candidates);
2167 inst->operands[idx].qualifier
2168 = get_qualifier_from_partial_encoding (value, candidates, mask);
2169 }
2170 }
2171
2172 if (inst->opcode->flags & F_T)
2173 {
2174 /* Num of consecutive '0's on the right side of imm5<3:0>. */
2175 int num = 0;
2176 unsigned val, Q;
2177 assert (aarch64_get_operand_class (inst->opcode->operands[0])
2178 == AARCH64_OPND_CLASS_SIMD_REG);
2179 /* imm5<3:0> q <t>
2180 0000 x reserved
2181 xxx1 0 8b
2182 xxx1 1 16b
2183 xx10 0 4h
2184 xx10 1 8h
2185 x100 0 2s
2186 x100 1 4s
2187 1000 0 reserved
2188 1000 1 2d */
2189 val = extract_field (FLD_imm5, inst->value, 0);
2190 while ((val & 0x1) == 0 && ++num <= 3)
2191 val >>= 1;
2192 if (num > 3)
2193 return 0;
2194 Q = (unsigned) extract_field (FLD_Q, inst->value, inst->opcode->mask);
2195 inst->operands[0].qualifier =
2196 get_vreg_qualifier_from_value ((num << 1) | Q);
2197 }
2198
2199 if (inst->opcode->flags & F_GPRSIZE_IN_Q)
2200 {
2201 /* Use Rt to encode in the case of e.g.
2202 STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
2203 idx = aarch64_operand_index (inst->opcode->operands, AARCH64_OPND_Rt);
2204 if (idx == -1)
2205 {
2206 /* Otherwise use the result operand, which has to be a integer
2207 register. */
2208 assert (aarch64_get_operand_class (inst->opcode->operands[0])
2209 == AARCH64_OPND_CLASS_INT_REG);
2210 idx = 0;
2211 }
2212 assert (idx == 0 || idx == 1);
2213 value = extract_field (FLD_Q, inst->value, 0);
2214 inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
2215 }
2216
2217 if (inst->opcode->flags & F_LDS_SIZE)
2218 {
2219 aarch64_field field = {0, 0};
2220 assert (aarch64_get_operand_class (inst->opcode->operands[0])
2221 == AARCH64_OPND_CLASS_INT_REG);
2222 gen_sub_field (FLD_opc, 0, 1, &field);
2223 value = extract_field_2 (&field, inst->value, 0);
2224 inst->operands[0].qualifier
2225 = value ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X;
2226 }
2227
2228 /* Miscellaneous decoding; done as the last step. */
2229 if (inst->opcode->flags & F_MISC)
2230 return do_misc_decoding (inst);
2231
2232 return 1;
2233}
2234
2235/* Converters converting a real opcode instruction to its alias form. */
2236
2237/* ROR <Wd>, <Ws>, #<shift>
2238 is equivalent to:
2239 EXTR <Wd>, <Ws>, <Ws>, #<shift>. */
2240static int
2241convert_extr_to_ror (aarch64_inst *inst)
2242{
2243 if (inst->operands[1].reg.regno == inst->operands[2].reg.regno)
2244 {
2245 copy_operand_info (inst, 2, 3);
2246 inst->operands[3].type = AARCH64_OPND_NIL;
2247 return 1;
2248 }
2249 return 0;
2250}
2251
e30181a5
YZ		 2252/* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
2253 is equivalent to:
2254 USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */
2255static int
2256convert_shll_to_xtl (aarch64_inst *inst)
2257{
2258 if (inst->operands[2].imm.value == 0)
2259 {
2260 inst->operands[2].type = AARCH64_OPND_NIL;
2261 return 1;
2262 }
2263 return 0;
2264}
2265
a06ea964
NC		 2266/* Convert
2267 UBFM <Xd>, <Xn>, #<shift>, #63.
2268 to
2269 LSR <Xd>, <Xn>, #<shift>. */
2270static int
2271convert_bfm_to_sr (aarch64_inst *inst)
2272{
2273 int64_t imms, val;
2274
2275 imms = inst->operands[3].imm.value;
2276 val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63;
2277 if (imms == val)
2278 {
2279 inst->operands[3].type = AARCH64_OPND_NIL;
2280 return 1;
2281 }
2282
2283 return 0;
2284}
2285
2286/* Convert MOV to ORR. */
2287static int
2288convert_orr_to_mov (aarch64_inst *inst)
2289{
2290 /* MOV <Vd>.<T>, <Vn>.<T>
2291 is equivalent to:
2292 ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>. */
2293 if (inst->operands[1].reg.regno == inst->operands[2].reg.regno)
2294 {
2295 inst->operands[2].type = AARCH64_OPND_NIL;
2296 return 1;
2297 }
2298 return 0;
2299}
2300
2301/* When <imms> >= <immr>, the instruction written:
2302 SBFX <Xd>, <Xn>, #<lsb>, #<width>
2303 is equivalent to:
2304 SBFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1). */
2305
2306static int
2307convert_bfm_to_bfx (aarch64_inst *inst)
2308{
2309 int64_t immr, imms;
2310
2311 immr = inst->operands[2].imm.value;
2312 imms = inst->operands[3].imm.value;
2313 if (imms >= immr)
2314 {
2315 int64_t lsb = immr;
2316 inst->operands[2].imm.value = lsb;
2317 inst->operands[3].imm.value = imms + 1 - lsb;
2318 /* The two opcodes have different qualifiers for
2319 the immediate operands; reset to help the checking. */
2320 reset_operand_qualifier (inst, 2);
2321 reset_operand_qualifier (inst, 3);
2322 return 1;
2323 }
2324
2325 return 0;
2326}
2327
2328/* When <imms> < <immr>, the instruction written:
2329 SBFIZ <Xd>, <Xn>, #<lsb>, #<width>
2330 is equivalent to:
2331 SBFM <Xd>, <Xn>, #((64-<lsb>)&0x3f), #(<width>-1). */
2332
2333static int
2334convert_bfm_to_bfi (aarch64_inst *inst)
2335{
2336 int64_t immr, imms, val;
2337
2338 immr = inst->operands[2].imm.value;
2339 imms = inst->operands[3].imm.value;
2340 val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64;
2341 if (imms < immr)
2342 {
2343 inst->operands[2].imm.value = (val - immr) & (val - 1);
2344 inst->operands[3].imm.value = imms + 1;
2345 /* The two opcodes have different qualifiers for
2346 the immediate operands; reset to help the checking. */
2347 reset_operand_qualifier (inst, 2);
2348 reset_operand_qualifier (inst, 3);
2349 return 1;
2350 }
2351
2352 return 0;
2353}
2354
d685192a
MW		 2355/* The instruction written:
2356 BFC <Xd>, #<lsb>, #<width>
2357 is equivalent to:
2358 BFM <Xd>, XZR, #((64-<lsb>)&0x3f), #(<width>-1). */
2359
2360static int
2361convert_bfm_to_bfc (aarch64_inst *inst)
2362{
2363 int64_t immr, imms, val;
2364
2365 /* Should have been assured by the base opcode value. */
2366 assert (inst->operands[1].reg.regno == 0x1f);
2367
2368 immr = inst->operands[2].imm.value;
2369 imms = inst->operands[3].imm.value;
2370 val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64;
2371 if (imms < immr)
2372 {
2373 /* Drop XZR from the second operand. */
2374 copy_operand_info (inst, 1, 2);
2375 copy_operand_info (inst, 2, 3);
2376 inst->operands[3].type = AARCH64_OPND_NIL;
2377
2378 /* Recalculate the immediates. */
2379 inst->operands[1].imm.value = (val - immr) & (val - 1);
2380 inst->operands[2].imm.value = imms + 1;
2381
2382 /* The two opcodes have different qualifiers for the operands; reset to
2383 help the checking. */
2384 reset_operand_qualifier (inst, 1);
2385 reset_operand_qualifier (inst, 2);
2386 reset_operand_qualifier (inst, 3);
2387
2388 return 1;
2389 }
2390
2391 return 0;
2392}
2393
a06ea964
NC		 2394/* The instruction written:
2395 LSL <Xd>, <Xn>, #<shift>
2396 is equivalent to:
2397 UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>). */
2398
2399static int
2400convert_ubfm_to_lsl (aarch64_inst *inst)
2401{
2402 int64_t immr = inst->operands[2].imm.value;
2403 int64_t imms = inst->operands[3].imm.value;
2404 int64_t val
2405 = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63;
2406
2407 if ((immr == 0 && imms == val) || immr == imms + 1)
2408 {
2409 inst->operands[3].type = AARCH64_OPND_NIL;
2410 inst->operands[2].imm.value = val - imms;
2411 return 1;
2412 }
2413
2414 return 0;
2415}
2416
2417/* CINC <Wd>, <Wn>, <cond>
2418 is equivalent to:
68a64283
YZ		 2419 CSINC <Wd>, <Wn>, <Wn>, invert(<cond>)
2420 where <cond> is not AL or NV. */
a06ea964
NC		 2421
2422static int
2423convert_from_csel (aarch64_inst *inst)
2424{
68a64283
YZ		 2425 if (inst->operands[1].reg.regno == inst->operands[2].reg.regno
2426 && (inst->operands[3].cond->value & 0xe) != 0xe)
a06ea964
NC		 2427 {
2428 copy_operand_info (inst, 2, 3);
2429 inst->operands[2].cond = get_inverted_cond (inst->operands[3].cond);
2430 inst->operands[3].type = AARCH64_OPND_NIL;
2431 return 1;
2432 }
2433 return 0;
2434}
2435
2436/* CSET <Wd>, <cond>
2437 is equivalent to:
68a64283
YZ		 2438 CSINC <Wd>, WZR, WZR, invert(<cond>)
2439 where <cond> is not AL or NV. */
a06ea964
NC		 2440
2441static int
2442convert_csinc_to_cset (aarch64_inst *inst)
2443{
2444 if (inst->operands[1].reg.regno == 0x1f
68a64283
YZ		 2445 && inst->operands[2].reg.regno == 0x1f
2446 && (inst->operands[3].cond->value & 0xe) != 0xe)
a06ea964
NC		 2447 {
2448 copy_operand_info (inst, 1, 3);
2449 inst->operands[1].cond = get_inverted_cond (inst->operands[3].cond);
2450 inst->operands[3].type = AARCH64_OPND_NIL;
2451 inst->operands[2].type = AARCH64_OPND_NIL;
2452 return 1;
2453 }
2454 return 0;
2455}
2456
2457/* MOV <Wd>, #<imm>
2458 is equivalent to:
2459 MOVZ <Wd>, #<imm16>, LSL #<shift>.
2460
2461 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
2462 ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
2463 or where a MOVN has an immediate that could be encoded by MOVZ, or where
2464 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
2465 machine-instruction mnemonic must be used. */
2466
2467static int
2468convert_movewide_to_mov (aarch64_inst *inst)
2469{
2470 uint64_t value = inst->operands[1].imm.value;
2471 /* MOVZ/MOVN #0 have a shift amount other than LSL #0. */
2472 if (value == 0 && inst->operands[1].shifter.amount != 0)
2473 return 0;
2474 inst->operands[1].type = AARCH64_OPND_IMM_MOV;
2475 inst->operands[1].shifter.kind = AARCH64_MOD_NONE;
2476 value <<= inst->operands[1].shifter.amount;
2477 /* As an alias convertor, it has to be clear that the INST->OPCODE
2478 is the opcode of the real instruction. */
2479 if (inst->opcode->op == OP_MOVN)
2480 {
2481 int is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
2482 value = ~value;
2483 /* A MOVN has an immediate that could be encoded by MOVZ. */
535b785f 2484 if (aarch64_wide_constant_p (value, is32, NULL))
a06ea964
NC		 2485 return 0;
2486 }
2487 inst->operands[1].imm.value = value;
2488 inst->operands[1].shifter.amount = 0;
2489 return 1;
2490}
2491
2492/* MOV <Wd>, #<imm>
2493 is equivalent to:
2494 ORR <Wd>, WZR, #<imm>.
2495
2496 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
2497 ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
2498 or where a MOVN has an immediate that could be encoded by MOVZ, or where
2499 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
2500 machine-instruction mnemonic must be used. */
2501
2502static int
2503convert_movebitmask_to_mov (aarch64_inst *inst)
2504{
2505 int is32;
2506 uint64_t value;
2507
2508 /* Should have been assured by the base opcode value. */
2509 assert (inst->operands[1].reg.regno == 0x1f);
2510 copy_operand_info (inst, 1, 2);
2511 is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
2512 inst->operands[1].type = AARCH64_OPND_IMM_MOV;
2513 value = inst->operands[1].imm.value;
2514 /* ORR has an immediate that could be generated by a MOVZ or MOVN
2515 instruction. */
2516 if (inst->operands[0].reg.regno != 0x1f
535b785f
AM		 2517 && (aarch64_wide_constant_p (value, is32, NULL)
2518 || aarch64_wide_constant_p (~value, is32, NULL)))
a06ea964
NC		 2519 return 0;
2520
2521 inst->operands[2].type = AARCH64_OPND_NIL;
2522 return 1;
2523}
2524
2525/* Some alias opcodes are disassembled by being converted from their real-form.
2526 N.B. INST->OPCODE is the real opcode rather than the alias. */
2527
2528static int
2529convert_to_alias (aarch64_inst *inst, const aarch64_opcode *alias)
2530{
2531 switch (alias->op)
2532 {
2533 case OP_ASR_IMM:
2534 case OP_LSR_IMM:
2535 return convert_bfm_to_sr (inst);
2536 case OP_LSL_IMM:
2537 return convert_ubfm_to_lsl (inst);
2538 case OP_CINC:
2539 case OP_CINV:
2540 case OP_CNEG:
2541 return convert_from_csel (inst);
2542 case OP_CSET:
2543 case OP_CSETM:
2544 return convert_csinc_to_cset (inst);
2545 case OP_UBFX:
2546 case OP_BFXIL:
2547 case OP_SBFX:
2548 return convert_bfm_to_bfx (inst);
2549 case OP_SBFIZ:
2550 case OP_BFI:
2551 case OP_UBFIZ:
2552 return convert_bfm_to_bfi (inst);
d685192a
MW		 2553 case OP_BFC:
2554 return convert_bfm_to_bfc (inst);
a06ea964
NC		 2555 case OP_MOV_V:
2556 return convert_orr_to_mov (inst);
2557 case OP_MOV_IMM_WIDE:
2558 case OP_MOV_IMM_WIDEN:
2559 return convert_movewide_to_mov (inst);
2560 case OP_MOV_IMM_LOG:
2561 return convert_movebitmask_to_mov (inst);
2562 case OP_ROR_IMM:
2563 return convert_extr_to_ror (inst);
e30181a5
YZ		 2564 case OP_SXTL:
2565 case OP_SXTL2:
2566 case OP_UXTL:
2567 case OP_UXTL2:
2568 return convert_shll_to_xtl (inst);
a06ea964
NC		 2569 default:
2570 return 0;
2571 }
2572}
2573
561a72d4
TC		 2574static bfd_boolean
2575aarch64_opcode_decode (const aarch64_opcode *, const aarch64_insn,
2576 aarch64_inst *, int, aarch64_operand_error *errors);
a06ea964
NC		 2577
2578/* Given the instruction information in *INST, check if the instruction has
2579 any alias form that can be used to represent *INST. If the answer is yes,
2580 update *INST to be in the form of the determined alias. */
2581
2582/* In the opcode description table, the following flags are used in opcode
2583 entries to help establish the relations between the real and alias opcodes:
2584
2585 F_ALIAS: opcode is an alias
2586 F_HAS_ALIAS: opcode has alias(es)
2587 F_P1
2588 F_P2
2589 F_P3: Disassembly preference priority 1-3 (the larger the
2590 higher). If nothing is specified, it is the priority
2591 0 by default, i.e. the lowest priority.
2592
2593 Although the relation between the machine and the alias instructions are not
2594 explicitly described, it can be easily determined from the base opcode
2595 values, masks and the flags F_ALIAS and F_HAS_ALIAS in their opcode
2596 description entries:
2597
2598 The mask of an alias opcode must be equal to or a super-set (i.e. more
2599 constrained) of that of the aliased opcode; so is the base opcode value.
2600
2601 if (opcode_has_alias (real) && alias_opcode_p (opcode)
2602 && (opcode->mask & real->mask) == real->mask
2603 && (real->mask & opcode->opcode) == (real->mask & real->opcode))
2604 then OPCODE is an alias of, and only of, the REAL instruction
2605
2606 The alias relationship is forced flat-structured to keep related algorithm
2607 simple; an opcode entry cannot be flagged with both F_ALIAS and F_HAS_ALIAS.
2608
2609 During the disassembling, the decoding decision tree (in
2610 opcodes/aarch64-dis-2.c) always returns an machine instruction opcode entry;
2611 if the decoding of such a machine instruction succeeds (and -Mno-aliases is
2612 not specified), the disassembler will check whether there is any alias
2613 instruction exists for this real instruction. If there is, the disassembler
2614 will try to disassemble the 32-bit binary again using the alias's rule, or
2615 try to convert the IR to the form of the alias. In the case of the multiple
2616 aliases, the aliases are tried one by one from the highest priority
2617 (currently the flag F_P3) to the lowest priority (no priority flag), and the
2618 first succeeds first adopted.
2619
2620 You may ask why there is a need for the conversion of IR from one form to
2621 another in handling certain aliases. This is because on one hand it avoids
2622 adding more operand code to handle unusual encoding/decoding; on other
2623 hand, during the disassembling, the conversion is an effective approach to
2624 check the condition of an alias (as an alias may be adopted only if certain
2625 conditions are met).
2626
2627 In order to speed up the alias opcode lookup, aarch64-gen has preprocessed
2628 aarch64_opcode_table and generated aarch64_find_alias_opcode and
2629 aarch64_find_next_alias_opcode (in opcodes/aarch64-dis-2.c) to help. */
2630
2631static void
561a72d4
TC		 2632determine_disassembling_preference (struct aarch64_inst *inst,
2633 aarch64_operand_error *errors)
a06ea964
NC		 2634{
2635 const aarch64_opcode *opcode;
2636 const aarch64_opcode *alias;
2637
2638 opcode = inst->opcode;
2639
2640 /* This opcode does not have an alias, so use itself. */
535b785f 2641 if (!opcode_has_alias (opcode))
a06ea964
NC		 2642 return;
2643
2644 alias = aarch64_find_alias_opcode (opcode);
2645 assert (alias);
2646
2647#ifdef DEBUG_AARCH64
2648 if (debug_dump)
2649 {
2650 const aarch64_opcode *tmp = alias;
2651 printf ("#### LIST orderd: ");
2652 while (tmp)
2653 {
2654 printf ("%s, ", tmp->name);
2655 tmp = aarch64_find_next_alias_opcode (tmp);
2656 }
2657 printf ("\n");
2658 }
2659#endif /* DEBUG_AARCH64 */
2660
2661 for (; alias; alias = aarch64_find_next_alias_opcode (alias))
2662 {
2663 DEBUG_TRACE ("try %s", alias->name);
35822b38 2664 assert (alias_opcode_p (alias) || opcode_has_alias (opcode));
a06ea964
NC		 2665
2666 /* An alias can be a pseudo opcode which will never be used in the
2667 disassembly, e.g. BIC logical immediate is such a pseudo opcode
2668 aliasing AND. */
2669 if (pseudo_opcode_p (alias))
2670 {
2671 DEBUG_TRACE ("skip pseudo %s", alias->name);
2672 continue;
2673 }
2674
2675 if ((inst->value & alias->mask) != alias->opcode)
2676 {
2677 DEBUG_TRACE ("skip %s as base opcode not match", alias->name);
2678 continue;
2679 }
2680 /* No need to do any complicated transformation on operands, if the alias
2681 opcode does not have any operand. */
2682 if (aarch64_num_of_operands (alias) == 0 && alias->opcode == inst->value)
2683 {
2684 DEBUG_TRACE ("succeed with 0-operand opcode %s", alias->name);
2685 aarch64_replace_opcode (inst, alias);
2686 return;
2687 }
2688 if (alias->flags & F_CONV)
2689 {
2690 aarch64_inst copy;
2691 memcpy (&copy, inst, sizeof (aarch64_inst));
2692 /* ALIAS is the preference as long as the instruction can be
2693 successfully converted to the form of ALIAS. */
2694 if (convert_to_alias (&copy, alias) == 1)
2695 {
2696 aarch64_replace_opcode (&copy, alias);
2697 assert (aarch64_match_operands_constraint (&copy, NULL));
2698 DEBUG_TRACE ("succeed with %s via conversion", alias->name);
2699 memcpy (inst, &copy, sizeof (aarch64_inst));
2700 return;
2701 }
2702 }
2703 else
2704 {
2705 /* Directly decode the alias opcode. */
2706 aarch64_inst temp;
2707 memset (&temp, '\0', sizeof (aarch64_inst));
561a72d4 2708 if (aarch64_opcode_decode (alias, inst->value, &temp, 1, errors) == 1)
a06ea964
NC		 2709 {
2710 DEBUG_TRACE ("succeed with %s via direct decoding", alias->name);
2711 memcpy (inst, &temp, sizeof (aarch64_inst));
2712 return;
2713 }
2714 }
2715 }
2716}
2717
116b6019
RS		 2718/* Some instructions (including all SVE ones) use the instruction class
2719 to describe how a qualifiers_list index is represented in the instruction
2720 encoding. If INST is such an instruction, decode the appropriate fields
2721 and fill in the operand qualifiers accordingly. Return true if no
2722 problems are found. */
2723
2724static bfd_boolean
2725aarch64_decode_variant_using_iclass (aarch64_inst *inst)
2726{
2727 int i, variant;
2728
2729 variant = 0;
2730 switch (inst->opcode->iclass)
2731 {
2732 case sve_cpy:
2733 variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_14);
2734 break;
2735
2736 case sve_index:
582e12bf
RS		 2737 i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
2738 if ((i & 31) == 0)
116b6019
RS		 2739 return FALSE;
2740 while ((i & 1) == 0)
2741 {
2742 i >>= 1;
2743 variant += 1;
2744 }
2745 break;
2746
2747 case sve_limm:
2748 /* Pick the smallest applicable element size. */
2749 if ((inst->value & 0x20600) == 0x600)
2750 variant = 0;
2751 else if ((inst->value & 0x20400) == 0x400)
2752 variant = 1;
2753 else if ((inst->value & 0x20000) == 0)
2754 variant = 2;
2755 else
2756 variant = 3;
2757 break;
2758
2759 case sve_misc:
2760 /* sve_misc instructions have only a single variant. */
2761 break;
2762
2763 case sve_movprfx:
2764 variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_16);
2765 break;
2766
2767 case sve_pred_zm:
2768 variant = extract_field (FLD_SVE_M_4, inst->value, 0);
2769 break;
2770
2771 case sve_shift_pred:
2772 i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_8);
2773 sve_shift:
2774 if (i == 0)
2775 return FALSE;
2776 while (i != 1)
2777 {
2778 i >>= 1;
2779 variant += 1;
2780 }
2781 break;
2782
2783 case sve_shift_unpred:
2784 i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_19);
2785 goto sve_shift;
2786
2787 case sve_size_bhs:
2788 variant = extract_field (FLD_size, inst->value, 0);
2789 if (variant >= 3)
2790 return FALSE;
2791 break;
2792
2793 case sve_size_bhsd:
2794 variant = extract_field (FLD_size, inst->value, 0);
2795 break;
2796
2797 case sve_size_hsd:
2798 i = extract_field (FLD_size, inst->value, 0);
2799 if (i < 1)
2800 return FALSE;
2801 variant = i - 1;
2802 break;
2803
2804 case sve_size_sd:
2805 variant = extract_field (FLD_SVE_sz, inst->value, 0);
2806 break;
2807
2808 default:
2809 /* No mapping between instruction class and qualifiers. */
2810 return TRUE;
2811 }
2812
2813 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2814 inst->operands[i].qualifier = inst->opcode->qualifiers_list[variant][i];
2815 return TRUE;
2816}
a06ea964
NC		 2817/* Decode the CODE according to OPCODE; fill INST. Return 0 if the decoding
2818 fails, which meanes that CODE is not an instruction of OPCODE; otherwise
2819 return 1.
2820
2821 If OPCODE has alias(es) and NOALIASES_P is 0, an alias opcode may be
2822 determined and used to disassemble CODE; this is done just before the
2823 return. */
2824
561a72d4 2825static bfd_boolean
a06ea964 2826aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code,
561a72d4
TC		 2827 aarch64_inst *inst, int noaliases_p,
2828 aarch64_operand_error *errors)
a06ea964
NC		 2829{
2830 int i;
2831
2832 DEBUG_TRACE ("enter with %s", opcode->name);
2833
2834 assert (opcode && inst);
2835
b3ac5c6c
TC		 2836 /* Clear inst. */
2837 memset (inst, '\0', sizeof (aarch64_inst));
2838
a06ea964
NC		 2839 /* Check the base opcode. */
2840 if ((code & opcode->mask) != (opcode->opcode & opcode->mask))
2841 {
2842 DEBUG_TRACE ("base opcode match FAIL");
2843 goto decode_fail;
2844 }
2845
a06ea964
NC		 2846 inst->opcode = opcode;
2847 inst->value = code;
2848
2849 /* Assign operand codes and indexes. */
2850 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2851 {
2852 if (opcode->operands[i] == AARCH64_OPND_NIL)
2853 break;
2854 inst->operands[i].type = opcode->operands[i];
2855 inst->operands[i].idx = i;
2856 }
2857
2858 /* Call the opcode decoder indicated by flags. */
2859 if (opcode_has_special_coder (opcode) && do_special_decoding (inst) == 0)
2860 {
2861 DEBUG_TRACE ("opcode flag-based decoder FAIL");
2862 goto decode_fail;
2863 }
2864
116b6019
RS		 2865 /* Possibly use the instruction class to determine the correct
2866 qualifier. */
2867 if (!aarch64_decode_variant_using_iclass (inst))
2868 {
2869 DEBUG_TRACE ("iclass-based decoder FAIL");
2870 goto decode_fail;
2871 }
2872
a06ea964
NC		 2873 /* Call operand decoders. */
2874 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2875 {
2876 const aarch64_operand *opnd;
2877 enum aarch64_opnd type;
4bd13cde 2878
a06ea964
NC		 2879 type = opcode->operands[i];
2880 if (type == AARCH64_OPND_NIL)
2881 break;
2882 opnd = &aarch64_operands[type];
2883 if (operand_has_extractor (opnd)
561a72d4
TC		 2884 && (! aarch64_extract_operand (opnd, &inst->operands[i], code, inst,
2885 errors)))
a06ea964
NC		 2886 {
2887 DEBUG_TRACE ("operand decoder FAIL at operand %d", i);
2888 goto decode_fail;
2889 }
2890 }
2891
4bd13cde
NC		 2892 /* If the opcode has a verifier, then check it now. */
2893 if (opcode->verifier && ! opcode->verifier (opcode, code))
2894 {
2895 DEBUG_TRACE ("operand verifier FAIL");
2896 goto decode_fail;
2897 }
2898
a06ea964
NC		 2899 /* Match the qualifiers. */
2900 if (aarch64_match_operands_constraint (inst, NULL) == 1)
2901 {
2902 /* Arriving here, the CODE has been determined as a valid instruction
2903 of OPCODE and *INST has been filled with information of this OPCODE
2904 instruction. Before the return, check if the instruction has any
2905 alias and should be disassembled in the form of its alias instead.
2906 If the answer is yes, *INST will be updated. */
2907 if (!noaliases_p)
561a72d4 2908 determine_disassembling_preference (inst, errors);
a06ea964 2909 DEBUG_TRACE ("SUCCESS");
561a72d4 2910 return TRUE;
a06ea964
NC		 2911 }
2912 else
2913 {
2914 DEBUG_TRACE ("constraint matching FAIL");
2915 }
2916
2917decode_fail:
561a72d4 2918 return FALSE;
a06ea964
NC		 2919}
2920\f
2921/* This does some user-friendly fix-up to *INST. It is currently focus on
2922 the adjustment of qualifiers to help the printed instruction
2923 recognized/understood more easily. */
2924
2925static void
2926user_friendly_fixup (aarch64_inst *inst)
2927{
2928 switch (inst->opcode->iclass)
2929 {
2930 case testbranch:
2931 /* TBNZ Xn|Wn, #uimm6, label
2932 Test and Branch Not Zero: conditionally jumps to label if bit number
2933 uimm6 in register Xn is not zero. The bit number implies the width of
2934 the register, which may be written and should be disassembled as Wn if
2935 uimm is less than 32. Limited to a branch offset range of +/- 32KiB.
2936 */
2937 if (inst->operands[1].imm.value < 32)
2938 inst->operands[0].qualifier = AARCH64_OPND_QLF_W;
2939 break;
2940 default: break;
2941 }
2942}
2943
43cdf5ae
YQ		 2944/* Decode INSN and fill in *INST the instruction information. An alias
2945 opcode may be filled in *INSN if NOALIASES_P is FALSE. Return zero on
2946 success. */
a06ea964 2947
36f4aab1 2948int
43cdf5ae 2949aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst,
561a72d4
TC		 2950 bfd_boolean noaliases_p,
2951 aarch64_operand_error *errors)
a06ea964
NC		 2952{
2953 const aarch64_opcode *opcode = aarch64_opcode_lookup (insn);
2954
2955#ifdef DEBUG_AARCH64
2956 if (debug_dump)
2957 {
2958 const aarch64_opcode *tmp = opcode;
2959 printf ("\n");
2960 DEBUG_TRACE ("opcode lookup:");
2961 while (tmp != NULL)
2962 {
2963 aarch64_verbose (" %s", tmp->name);
2964 tmp = aarch64_find_next_opcode (tmp);
2965 }
2966 }
2967#endif /* DEBUG_AARCH64 */
2968
2969 /* A list of opcodes may have been found, as aarch64_opcode_lookup cannot
2970 distinguish some opcodes, e.g. SSHR and MOVI, which almost share the same
2971 opcode field and value, apart from the difference that one of them has an
2972 extra field as part of the opcode, but such a field is used for operand
2973 encoding in other opcode(s) ('immh' in the case of the example). */
2974 while (opcode != NULL)
2975 {
2976 /* But only one opcode can be decoded successfully for, as the
2977 decoding routine will check the constraint carefully. */
561a72d4 2978 if (aarch64_opcode_decode (opcode, insn, inst, noaliases_p, errors) == 1)
a06ea964
NC		 2979 return ERR_OK;
2980 opcode = aarch64_find_next_opcode (opcode);
2981 }
2982
2983 return ERR_UND;
2984}
2985
2986/* Print operands. */
2987
2988static void
2989print_operands (bfd_vma pc, const aarch64_opcode *opcode,
2990 const aarch64_opnd_info *opnds, struct disassemble_info *info)
2991{
2992 int i, pcrel_p, num_printed;
7d02540a 2993 char *notes = NULL;
a06ea964
NC		 2994 for (i = 0, num_printed = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2995 {
0d2f91fe 2996 char str[128];
a06ea964
NC		 2997 /* We regard the opcode operand info more, however we also look into
2998 the inst->operands to support the disassembling of the optional
2999 operand.
3000 The two operand code should be the same in all cases, apart from
3001 when the operand can be optional. */
3002 if (opcode->operands[i] == AARCH64_OPND_NIL
3003 || opnds[i].type == AARCH64_OPND_NIL)
3004 break;
3005
3006 /* Generate the operand string in STR. */
0d2f91fe 3007 aarch64_print_operand (str, sizeof (str), pc, opcode, opnds, i, &pcrel_p,
7d02540a 3008 &info->target, &notes);
a06ea964
NC		 3009
3010 /* Print the delimiter (taking account of omitted operand(s)). */
3011 if (str[0] != '\0')
3012 (*info->fprintf_func) (info->stream, "%s",
3013 num_printed++ == 0 ? "\t" : ", ");
3014
3015 /* Print the operand. */
3016 if (pcrel_p)
3017 (*info->print_address_func) (info->target, info);
3018 else
3019 (*info->fprintf_func) (info->stream, "%s", str);
3020 }
7d02540a
TC		 3021
3022 if (notes && !no_notes)
3023 (*info->fprintf_func) (info->stream, "\t; note: %s", notes);
a06ea964
NC		 3024}
3025
bb7eff52
RS		 3026/* Set NAME to a copy of INST's mnemonic with the "." suffix removed. */
3027
3028static void
3029remove_dot_suffix (char *name, const aarch64_inst *inst)
3030{
3031 char *ptr;
3032 size_t len;
3033
3034 ptr = strchr (inst->opcode->name, '.');
3035 assert (ptr && inst->cond);
3036 len = ptr - inst->opcode->name;
3037 assert (len < 8);
3038 strncpy (name, inst->opcode->name, len);
3039 name[len] = '\0';
3040}
3041
a06ea964
NC		 3042/* Print the instruction mnemonic name. */
3043
3044static void
3045print_mnemonic_name (const aarch64_inst *inst, struct disassemble_info *info)
3046{
3047 if (inst->opcode->flags & F_COND)
3048 {
3049 /* For instructions that are truly conditionally executed, e.g. b.cond,
3050 prepare the full mnemonic name with the corresponding condition
3051 suffix. */
bb7eff52
RS		 3052 char name[8];
3053
3054 remove_dot_suffix (name, inst);
a06ea964
NC		 3055 (*info->fprintf_func) (info->stream, "%s.%s", name, inst->cond->names[0]);
3056 }
3057 else
3058 (*info->fprintf_func) (info->stream, "%s", inst->opcode->name);
3059}
3060
bb7eff52
RS		 3061/* Decide whether we need to print a comment after the operands of
3062 instruction INST. */
3063
3064static void
3065print_comment (const aarch64_inst *inst, struct disassemble_info *info)
3066{
3067 if (inst->opcode->flags & F_COND)
3068 {
3069 char name[8];
3070 unsigned int i, num_conds;
3071
3072 remove_dot_suffix (name, inst);
3073 num_conds = ARRAY_SIZE (inst->cond->names);
3074 for (i = 1; i < num_conds && inst->cond->names[i]; ++i)
3075 (*info->fprintf_func) (info->stream, "%s %s.%s",
3076 i == 1 ? " //" : ",",
3077 name, inst->cond->names[i]);
3078 }
3079}
3080
a06ea964
NC		 3081/* Print the instruction according to *INST. */
3082
3083static void
3084print_aarch64_insn (bfd_vma pc, const aarch64_inst *inst,
3085 struct disassemble_info *info)
3086{
3087 print_mnemonic_name (inst, info);
3088 print_operands (pc, inst->opcode, inst->operands, info);
bb7eff52 3089 print_comment (inst, info);
a06ea964
NC		 3090}
3091
3092/* Entry-point of the instruction disassembler and printer. */
3093
3094static void
3095print_insn_aarch64_word (bfd_vma pc,
3096 uint32_t word,
561a72d4
TC		 3097 struct disassemble_info *info,
3098 aarch64_operand_error *errors)
a06ea964
NC		 3099{
3100 static const char *err_msg[6] =
3101 {
3102 [ERR_OK] = "_",
3103 [-ERR_UND] = "undefined",
3104 [-ERR_UNP] = "unpredictable",
3105 [-ERR_NYI] = "NYI"
3106 };
3107
3108 int ret;
3109 aarch64_inst inst;
3110
3111 info->insn_info_valid = 1;
3112 info->branch_delay_insns = 0;
3113 info->data_size = 0;
3114 info->target = 0;
3115 info->target2 = 0;
3116
3117 if (info->flags & INSN_HAS_RELOC)
3118 /* If the instruction has a reloc associated with it, then
3119 the offset field in the instruction will actually be the
3120 addend for the reloc. (If we are using REL type relocs).
3121 In such cases, we can ignore the pc when computing
3122 addresses, since the addend is not currently pc-relative. */
3123 pc = 0;
3124
561a72d4 3125 ret = aarch64_decode_insn (word, &inst, no_aliases, errors);
a06ea964
NC		 3126
3127 if (((word >> 21) & 0x3ff) == 1)
3128 {
3129 /* RESERVED for ALES. */
3130 assert (ret != ERR_OK);
3131 ret = ERR_NYI;
3132 }
3133
3134 switch (ret)
3135 {
3136 case ERR_UND:
3137 case ERR_UNP:
3138 case ERR_NYI:
3139 /* Handle undefined instructions. */
3140 info->insn_type = dis_noninsn;
3141 (*info->fprintf_func) (info->stream,".inst\t0x%08x ; %s",
3142 word, err_msg[-ret]);
3143 break;
3144 case ERR_OK:
3145 user_friendly_fixup (&inst);
3146 print_aarch64_insn (pc, &inst, info);
3147 break;
3148 default:
3149 abort ();
3150 }
3151}
3152
3153/* Disallow mapping symbols ($x, $d etc) from
3154 being displayed in symbol relative addresses. */
3155
3156bfd_boolean
3157aarch64_symbol_is_valid (asymbol * sym,
3158 struct disassemble_info * info ATTRIBUTE_UNUSED)
3159{
3160 const char * name;
3161
3162 if (sym == NULL)
3163 return FALSE;
3164
3165 name = bfd_asymbol_name (sym);
3166
3167 return name
3168 && (name[0] != '$'
3169 || (name[1] != 'x' && name[1] != 'd')
3170 || (name[2] != '\0' && name[2] != '.'));
3171}
3172
3173/* Print data bytes on INFO->STREAM. */
3174
3175static void
3176print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
3177 uint32_t word,
561a72d4
TC		 3178 struct disassemble_info *info,
3179 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
a06ea964
NC		 3180{
3181 switch (info->bytes_per_chunk)
3182 {
3183 case 1:
3184 info->fprintf_func (info->stream, ".byte\t0x%02x", word);
3185 break;
3186 case 2:
3187 info->fprintf_func (info->stream, ".short\t0x%04x", word);
3188 break;
3189 case 4:
3190 info->fprintf_func (info->stream, ".word\t0x%08x", word);
3191 break;
3192 default:
3193 abort ();
3194 }
3195}
3196
3197/* Try to infer the code or data type from a symbol.
3198 Returns nonzero if *MAP_TYPE was set. */
3199
3200static int
3201get_sym_code_type (struct disassemble_info *info, int n,
3202 enum map_type *map_type)
3203{
3204 elf_symbol_type *es;
3205 unsigned int type;
3206 const char *name;
3207
4c5ae11b
RL		 3208 /* If the symbol is in a different section, ignore it. */
3209 if (info->section != NULL && info->section != info->symtab[n]->section)
3210 return FALSE;
3211
a06ea964
NC		 3212 es = *(elf_symbol_type **)(info->symtab + n);
3213 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
3214
3215 /* If the symbol has function type then use that. */
3216 if (type == STT_FUNC)
3217 {
3218 *map_type = MAP_INSN;
3219 return TRUE;
3220 }
3221
3222 /* Check for mapping symbols. */
3223 name = bfd_asymbol_name(info->symtab[n]);
3224 if (name[0] == '$'
3225 && (name[1] == 'x' || name[1] == 'd')
3226 && (name[2] == '\0' || name[2] == '.'))
3227 {
3228 *map_type = (name[1] == 'x' ? MAP_INSN : MAP_DATA);
3229 return TRUE;
3230 }
3231
3232 return FALSE;
3233}
3234
3235/* Entry-point of the AArch64 disassembler. */
3236
3237int
3238print_insn_aarch64 (bfd_vma pc,
3239 struct disassemble_info *info)
3240{
3241 bfd_byte buffer[INSNLEN];
3242 int status;
561a72d4
TC		 3243 void (*printer) (bfd_vma, uint32_t, struct disassemble_info *,
3244 aarch64_operand_error *);
a06ea964
NC		 3245 bfd_boolean found = FALSE;
3246 unsigned int size = 4;
3247 unsigned long data;
561a72d4 3248 aarch64_operand_error errors;
a06ea964
NC		 3249
3250 if (info->disassembler_options)
3251 {
3252 set_default_aarch64_dis_options (info);
3253
3254 parse_aarch64_dis_options (info->disassembler_options);
3255
3256 /* To avoid repeated parsing of these options, we remove them here. */
3257 info->disassembler_options = NULL;
3258 }
3259
3260 /* Aarch64 instructions are always little-endian */
3261 info->endian_code = BFD_ENDIAN_LITTLE;
3262
3263 /* First check the full symtab for a mapping symbol, even if there
3264 are no usable non-mapping symbols for this address. */
3265 if (info->symtab_size != 0
3266 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
3267 {
3268 enum map_type type = MAP_INSN;
3269 int last_sym = -1;
3270 bfd_vma addr;
3271 int n;
3272
3273 if (pc <= last_mapping_addr)
3274 last_mapping_sym = -1;
3275
3276 /* Start scanning at the start of the function, or wherever
3277 we finished last time. */
3278 n = info->symtab_pos + 1;
3279 if (n < last_mapping_sym)
3280 n = last_mapping_sym;
3281
3282 /* Scan up to the location being disassembled. */
3283 for (; n < info->symtab_size; n++)
3284 {
3285 addr = bfd_asymbol_value (info->symtab[n]);
3286 if (addr > pc)
3287 break;
4c5ae11b 3288 if (get_sym_code_type (info, n, &type))
a06ea964
NC		 3289 {
3290 last_sym = n;
3291 found = TRUE;
3292 }
3293 }
3294
3295 if (!found)
3296 {
3297 n = info->symtab_pos;
3298 if (n < last_mapping_sym)
3299 n = last_mapping_sym;
3300
3301 /* No mapping symbol found at this address. Look backwards
3302 for a preceeding one. */
3303 for (; n >= 0; n--)
3304 {
3305 if (get_sym_code_type (info, n, &type))
3306 {
3307 last_sym = n;
3308 found = TRUE;
3309 break;
3310 }
3311 }
3312 }
3313
3314 last_mapping_sym = last_sym;
3315 last_type = type;
3316
3317 /* Look a little bit ahead to see if we should print out
3318 less than four bytes of data. If there's a symbol,
3319 mapping or otherwise, after two bytes then don't
3320 print more. */
3321 if (last_type == MAP_DATA)
3322 {
3323 size = 4 - (pc & 3);
3324 for (n = last_sym + 1; n < info->symtab_size; n++)
3325 {
3326 addr = bfd_asymbol_value (info->symtab[n]);
3327 if (addr > pc)
3328 {
3329 if (addr - pc < size)
3330 size = addr - pc;
3331 break;
3332 }
3333 }
3334 /* If the next symbol is after three bytes, we need to
3335 print only part of the data, so that we can use either
3336 .byte or .short. */
3337 if (size == 3)
3338 size = (pc & 1) ? 1 : 2;
3339 }
3340 }
3341
3342 if (last_type == MAP_DATA)
3343 {
3344 /* size was set above. */
3345 info->bytes_per_chunk = size;
3346 info->display_endian = info->endian;
3347 printer = print_insn_data;
3348 }
3349 else
3350 {
3351 info->bytes_per_chunk = size = INSNLEN;
3352 info->display_endian = info->endian_code;
3353 printer = print_insn_aarch64_word;
3354 }
3355
3356 status = (*info->read_memory_func) (pc, buffer, size, info);
3357 if (status != 0)
3358 {
3359 (*info->memory_error_func) (status, pc, info);
3360 return -1;
3361 }
3362
3363 data = bfd_get_bits (buffer, size * 8,
3364 info->display_endian == BFD_ENDIAN_BIG);
3365
561a72d4 3366 (*printer) (pc, data, info, &errors);
a06ea964
NC		 3367
3368 return size;
3369}
3370\f
3371void
3372print_aarch64_disassembler_options (FILE *stream)
3373{
3374 fprintf (stream, _("\n\
3375The following AARCH64 specific disassembler options are supported for use\n\
3376with the -M switch (multiple options should be separated by commas):\n"));
3377
3378 fprintf (stream, _("\n\
3379 no-aliases Don't print instruction aliases.\n"));
3380
3381 fprintf (stream, _("\n\
3382 aliases Do print instruction aliases.\n"));
3383
7d02540a
TC		 3384 fprintf (stream, _("\n\
3385 no-notes Don't print instruction notes.\n"));
3386
3387 fprintf (stream, _("\n\
3388 notes Do print instruction notes.\n"));
3389
a06ea964
NC		 3390#ifdef DEBUG_AARCH64
3391 fprintf (stream, _("\n\
3392 debug_dump Temp switch for debug trace.\n"));
3393#endif /* DEBUG_AARCH64 */
3394
3395 fprintf (stream, _("\n"));
3396}
GDB Binutils - Deliverables
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