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[BINUTILS, AARCH64, 3/8] Add Pointer Arithmetic instructions in Memory Tagging Extension
[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.c
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a06ea964 1/* aarch64-opc.c -- AArch64 opcode support.
219d1afa 2 Copyright (C) 2009-2018 Free Software Foundation, Inc.
a06ea964
NC		 3 Contributed by ARM Ltd.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21#include "sysdep.h"
22#include <assert.h>
23#include <stdlib.h>
24#include <stdio.h>
25#include <stdint.h>
26#include <stdarg.h>
27#include <inttypes.h>
28
29#include "opintl.h"
245d2e3f 30#include "libiberty.h"
a06ea964
NC		 31
32#include "aarch64-opc.h"
33
34#ifdef DEBUG_AARCH64
35int debug_dump = FALSE;
36#endif /* DEBUG_AARCH64 */
37
245d2e3f
RS		 38/* The enumeration strings associated with each value of a 5-bit SVE
39 pattern operand. A null entry indicates a reserved meaning. */
40const char *const aarch64_sve_pattern_array[32] = {
41 /* 0-7. */
42 "pow2",
43 "vl1",
44 "vl2",
45 "vl3",
46 "vl4",
47 "vl5",
48 "vl6",
49 "vl7",
50 /* 8-15. */
51 "vl8",
52 "vl16",
53 "vl32",
54 "vl64",
55 "vl128",
56 "vl256",
57 0,
58 0,
59 /* 16-23. */
60 0,
61 0,
62 0,
63 0,
64 0,
65 0,
66 0,
67 0,
68 /* 24-31. */
69 0,
70 0,
71 0,
72 0,
73 0,
74 "mul4",
75 "mul3",
76 "all"
77};
78
79/* The enumeration strings associated with each value of a 4-bit SVE
80 prefetch operand. A null entry indicates a reserved meaning. */
81const char *const aarch64_sve_prfop_array[16] = {
82 /* 0-7. */
83 "pldl1keep",
84 "pldl1strm",
85 "pldl2keep",
86 "pldl2strm",
87 "pldl3keep",
88 "pldl3strm",
89 0,
90 0,
91 /* 8-15. */
92 "pstl1keep",
93 "pstl1strm",
94 "pstl2keep",
95 "pstl2strm",
96 "pstl3keep",
97 "pstl3strm",
98 0,
99 0
100};
101
a06ea964
NC		 102/* Helper functions to determine which operand to be used to encode/decode
103 the size:Q fields for AdvSIMD instructions. */
104
105static inline bfd_boolean
106vector_qualifier_p (enum aarch64_opnd_qualifier qualifier)
107{
108 return ((qualifier >= AARCH64_OPND_QLF_V_8B
109 && qualifier <= AARCH64_OPND_QLF_V_1Q) ? TRUE
110 : FALSE);
111}
112
113static inline bfd_boolean
114fp_qualifier_p (enum aarch64_opnd_qualifier qualifier)
115{
116 return ((qualifier >= AARCH64_OPND_QLF_S_B
117 && qualifier <= AARCH64_OPND_QLF_S_Q) ? TRUE
118 : FALSE);
119}
120
121enum data_pattern
122{
123 DP_UNKNOWN,
124 DP_VECTOR_3SAME,
125 DP_VECTOR_LONG,
126 DP_VECTOR_WIDE,
127 DP_VECTOR_ACROSS_LANES,
128};
129
130static const char significant_operand_index [] =
131{
132 0, /* DP_UNKNOWN, by default using operand 0. */
133 0, /* DP_VECTOR_3SAME */
134 1, /* DP_VECTOR_LONG */
135 2, /* DP_VECTOR_WIDE */
136 1, /* DP_VECTOR_ACROSS_LANES */
137};
138
139/* Given a sequence of qualifiers in QUALIFIERS, determine and return
140 the data pattern.
141 N.B. QUALIFIERS is a possible sequence of qualifiers each of which
142 corresponds to one of a sequence of operands. */
143
144static enum data_pattern
145get_data_pattern (const aarch64_opnd_qualifier_seq_t qualifiers)
146{
147 if (vector_qualifier_p (qualifiers[0]) == TRUE)
148 {
149 /* e.g. v.4s, v.4s, v.4s
150 or v.4h, v.4h, v.h[3]. */
151 if (qualifiers[0] == qualifiers[1]
152 && vector_qualifier_p (qualifiers[2]) == TRUE
153 && (aarch64_get_qualifier_esize (qualifiers[0])
154 == aarch64_get_qualifier_esize (qualifiers[1]))
155 && (aarch64_get_qualifier_esize (qualifiers[0])
156 == aarch64_get_qualifier_esize (qualifiers[2])))
157 return DP_VECTOR_3SAME;
158 /* e.g. v.8h, v.8b, v.8b.
159 or v.4s, v.4h, v.h[2].
160 or v.8h, v.16b. */
161 if (vector_qualifier_p (qualifiers[1]) == TRUE
162 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
163 && (aarch64_get_qualifier_esize (qualifiers[0])
164 == aarch64_get_qualifier_esize (qualifiers[1]) << 1))
165 return DP_VECTOR_LONG;
166 /* e.g. v.8h, v.8h, v.8b. */
167 if (qualifiers[0] == qualifiers[1]
168 && vector_qualifier_p (qualifiers[2]) == TRUE
169 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
170 && (aarch64_get_qualifier_esize (qualifiers[0])
171 == aarch64_get_qualifier_esize (qualifiers[2]) << 1)
172 && (aarch64_get_qualifier_esize (qualifiers[0])
173 == aarch64_get_qualifier_esize (qualifiers[1])))
174 return DP_VECTOR_WIDE;
175 }
176 else if (fp_qualifier_p (qualifiers[0]) == TRUE)
177 {
178 /* e.g. SADDLV <V><d>, <Vn>.<T>. */
179 if (vector_qualifier_p (qualifiers[1]) == TRUE
180 && qualifiers[2] == AARCH64_OPND_QLF_NIL)
181 return DP_VECTOR_ACROSS_LANES;
182 }
183
184 return DP_UNKNOWN;
185}
186
187/* Select the operand to do the encoding/decoding of the 'size:Q' fields in
188 the AdvSIMD instructions. */
189/* N.B. it is possible to do some optimization that doesn't call
190 get_data_pattern each time when we need to select an operand. We can
191 either buffer the caculated the result or statically generate the data,
192 however, it is not obvious that the optimization will bring significant
193 benefit. */
194
195int
196aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode)
197{
198 return
199 significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])];
200}
201\f
202const aarch64_field fields[] =
203{
204 { 0, 0 }, /* NIL. */
205 { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
206 { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
207 { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
208 { 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
209 { 5, 19 }, /* imm19: e.g. in CBZ. */
210 { 5, 19 }, /* immhi: e.g. in ADRP. */
211 { 29, 2 }, /* immlo: e.g. in ADRP. */
212 { 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
213 { 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
214 { 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
215 { 30, 1 }, /* Q: in most AdvSIMD instructions. */
216 { 0, 5 }, /* Rt: in load/store instructions. */
217 { 0, 5 }, /* Rd: in many integer instructions. */
218 { 5, 5 }, /* Rn: in many integer instructions. */
219 { 10, 5 }, /* Rt2: in load/store pair instructions. */
220 { 10, 5 }, /* Ra: in fp instructions. */
221 { 5, 3 }, /* op2: in the system instructions. */
222 { 8, 4 }, /* CRm: in the system instructions. */
223 { 12, 4 }, /* CRn: in the system instructions. */
224 { 16, 3 }, /* op1: in the system instructions. */
225 { 19, 2 }, /* op0: in the system instructions. */
226 { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
227 { 12, 4 }, /* cond: condition flags as a source operand. */
228 { 12, 4 }, /* opcode: in advsimd load/store instructions. */
229 { 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
230 { 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
231 { 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
232 { 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
233 { 16, 5 }, /* Rs: in load/store exclusive instructions. */
234 { 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
235 { 12, 1 }, /* S: in load/store reg offset instructions. */
236 { 21, 2 }, /* hw: in move wide constant instructions. */
237 { 22, 2 }, /* opc: in load/store reg offset instructions. */
238 { 23, 1 }, /* opc1: in load/store reg offset instructions. */
239 { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
240 { 22, 2 }, /* type: floating point type field in fp data inst. */
241 { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
242 { 10, 6 }, /* imm6: in add/sub reg shifted instructions. */
f42f1a1d 243 { 15, 6 }, /* imm6_2: in rmif instructions. */
a06ea964 244 { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
f42f1a1d 245 { 0, 4 }, /* imm4_2: in rmif instructions. */
193614f2 246 { 10, 4 }, /* imm4_3: in adddg/subg instructions. */
a06ea964
NC		 247 { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
248 { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
249 { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
250 { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
251 { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
252 { 5, 14 }, /* imm14: in test bit and branch instructions. */
253 { 5, 16 }, /* imm16: in exception instructions. */
254 { 0, 26 }, /* imm26: in unconditional branch instructions. */
255 { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
256 { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
257 { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
258 { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
3f06e550 259 { 22, 1 }, /* S: in LDRAA and LDRAB instructions. */
a06ea964
NC		 260 { 22, 1 }, /* N: in logical (immediate) instructions. */
261 { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
262 { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
263 { 31, 1 }, /* sf: in integer data processing instructions. */
ee804238 264 { 30, 1 }, /* lse_size: in LSE extension atomic instructions. */
a06ea964
NC		 265 { 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
266 { 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
267 { 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
268 { 31, 1 }, /* b5: in the test bit and branch instructions. */
269 { 19, 5 }, /* b40: in the test bit and branch instructions. */
270 { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
116b6019
RS		 271 { 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */
272 { 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */
273 { 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */
e950b345 274 { 17, 1 }, /* SVE_N: SVE equivalent of N. */
f11ad6bc
RS		 275 { 0, 4 }, /* SVE_Pd: p0-p15, bits [3,0]. */
276 { 10, 3 }, /* SVE_Pg3: p0-p7, bits [12,10]. */
277 { 5, 4 }, /* SVE_Pg4_5: p0-p15, bits [8,5]. */
278 { 10, 4 }, /* SVE_Pg4_10: p0-p15, bits [13,10]. */
279 { 16, 4 }, /* SVE_Pg4_16: p0-p15, bits [19,16]. */
280 { 16, 4 }, /* SVE_Pm: p0-p15, bits [19,16]. */
281 { 5, 4 }, /* SVE_Pn: p0-p15, bits [8,5]. */
282 { 0, 4 }, /* SVE_Pt: p0-p15, bits [3,0]. */
047cd301
RS		 283 { 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
284 { 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
285 { 0, 5 }, /* SVE_Vd: Scalar SIMD&FP register, bits [4,0]. */
286 { 5, 5 }, /* SVE_Vm: Scalar SIMD&FP register, bits [9,5]. */
287 { 5, 5 }, /* SVE_Vn: Scalar SIMD&FP register, bits [9,5]. */
f11ad6bc
RS		 288 { 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
289 { 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
290 { 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
291 { 5, 5 }, /* SVE_Zm_5: SVE vector register, bits [9,5]. */
292 { 16, 5 }, /* SVE_Zm_16: SVE vector register, bits [20,16]. */
293 { 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
294 { 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
165d4950 295 { 5, 1 }, /* SVE_i1: single-bit immediate. */
582e12bf 296 { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
e950b345 297 { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
2442d846 298 { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
e950b345
RS		 299 { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
300 { 16, 5 }, /* SVE_imm5b: secondary 5-bit immediate field. */
4df068de 301 { 16, 6 }, /* SVE_imm6: 6-bit immediate field. */
e950b345
RS		 302 { 14, 7 }, /* SVE_imm7: 7-bit immediate field. */
303 { 5, 8 }, /* SVE_imm8: 8-bit immediate field. */
304 { 5, 9 }, /* SVE_imm9: 9-bit immediate field. */
305 { 11, 6 }, /* SVE_immr: SVE equivalent of immr. */
306 { 5, 6 }, /* SVE_imms: SVE equivalent of imms. */
4df068de 307 { 10, 2 }, /* SVE_msz: 2-bit shift amount for ADR. */
245d2e3f
RS		 308 { 5, 5 }, /* SVE_pattern: vector pattern enumeration. */
309 { 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
582e12bf
RS		 310 { 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
311 { 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
116b6019
RS		 312 { 22, 1 }, /* SVE_sz: 1-bit element size select. */
313 { 16, 4 }, /* SVE_tsz: triangular size select. */
f11ad6bc 314 { 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
116b6019
RS		 315 { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */
316 { 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */
4df068de 317 { 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
c2c4ff8d
SN		 318 { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
319 { 11, 2 }, /* rotate1: FCMLA immediate rotate. */
320 { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
321 { 12, 1 }, /* rotate3: FCADD immediate rotate. */
f42f1a1d 322 { 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */
a06ea964
NC		 323};
324
325enum aarch64_operand_class
326aarch64_get_operand_class (enum aarch64_opnd type)
327{
328 return aarch64_operands[type].op_class;
329}
330
331const char *
332aarch64_get_operand_name (enum aarch64_opnd type)
333{
334 return aarch64_operands[type].name;
335}
336
337/* Get operand description string.
338 This is usually for the diagnosis purpose. */
339const char *
340aarch64_get_operand_desc (enum aarch64_opnd type)
341{
342 return aarch64_operands[type].desc;
343}
344
345/* Table of all conditional affixes. */
346const aarch64_cond aarch64_conds[16] =
347{
bb7eff52
RS		 348 {{"eq", "none"}, 0x0},
349 {{"ne", "any"}, 0x1},
350 {{"cs", "hs", "nlast"}, 0x2},
351 {{"cc", "lo", "ul", "last"}, 0x3},
352 {{"mi", "first"}, 0x4},
353 {{"pl", "nfrst"}, 0x5},
a06ea964
NC		 354 {{"vs"}, 0x6},
355 {{"vc"}, 0x7},
bb7eff52
RS		 356 {{"hi", "pmore"}, 0x8},
357 {{"ls", "plast"}, 0x9},
358 {{"ge", "tcont"}, 0xa},
359 {{"lt", "tstop"}, 0xb},
a06ea964
NC		 360 {{"gt"}, 0xc},
361 {{"le"}, 0xd},
362 {{"al"}, 0xe},
363 {{"nv"}, 0xf},
364};
365
366const aarch64_cond *
367get_cond_from_value (aarch64_insn value)
368{
369 assert (value < 16);
370 return &aarch64_conds[(unsigned int) value];
371}
372
373const aarch64_cond *
374get_inverted_cond (const aarch64_cond *cond)
375{
376 return &aarch64_conds[cond->value ^ 0x1];
377}
378
379/* Table describing the operand extension/shifting operators; indexed by
380 enum aarch64_modifier_kind.
381
382 The value column provides the most common values for encoding modifiers,
383 which enables table-driven encoding/decoding for the modifiers. */
384const struct aarch64_name_value_pair aarch64_operand_modifiers [] =
385{
386 {"none", 0x0},
387 {"msl", 0x0},
388 {"ror", 0x3},
389 {"asr", 0x2},
390 {"lsr", 0x1},
391 {"lsl", 0x0},
392 {"uxtb", 0x0},
393 {"uxth", 0x1},
394 {"uxtw", 0x2},
395 {"uxtx", 0x3},
396 {"sxtb", 0x4},
397 {"sxth", 0x5},
398 {"sxtw", 0x6},
399 {"sxtx", 0x7},
2442d846 400 {"mul", 0x0},
98907a70 401 {"mul vl", 0x0},
a06ea964
NC		 402 {NULL, 0},
403};
404
405enum aarch64_modifier_kind
406aarch64_get_operand_modifier (const struct aarch64_name_value_pair *desc)
407{
408 return desc - aarch64_operand_modifiers;
409}
410
411aarch64_insn
412aarch64_get_operand_modifier_value (enum aarch64_modifier_kind kind)
413{
414 return aarch64_operand_modifiers[kind].value;
415}
416
417enum aarch64_modifier_kind
418aarch64_get_operand_modifier_from_value (aarch64_insn value,
419 bfd_boolean extend_p)
420{
421 if (extend_p == TRUE)
422 return AARCH64_MOD_UXTB + value;
423 else
424 return AARCH64_MOD_LSL - value;
425}
426
427bfd_boolean
428aarch64_extend_operator_p (enum aarch64_modifier_kind kind)
429{
430 return (kind > AARCH64_MOD_LSL && kind <= AARCH64_MOD_SXTX)
431 ? TRUE : FALSE;
432}
433
434static inline bfd_boolean
435aarch64_shift_operator_p (enum aarch64_modifier_kind kind)
436{
437 return (kind >= AARCH64_MOD_ROR && kind <= AARCH64_MOD_LSL)
438 ? TRUE : FALSE;
439}
440
441const struct aarch64_name_value_pair aarch64_barrier_options[16] =
442{
443 { "#0x00", 0x0 },
444 { "oshld", 0x1 },
445 { "oshst", 0x2 },
446 { "osh", 0x3 },
447 { "#0x04", 0x4 },
448 { "nshld", 0x5 },
449 { "nshst", 0x6 },
450 { "nsh", 0x7 },
451 { "#0x08", 0x8 },
452 { "ishld", 0x9 },
453 { "ishst", 0xa },
454 { "ish", 0xb },
455 { "#0x0c", 0xc },
456 { "ld", 0xd },
457 { "st", 0xe },
458 { "sy", 0xf },
459};
460
9ed608f9
MW		 461/* Table describing the operands supported by the aliases of the HINT
462 instruction.
463
464 The name column is the operand that is accepted for the alias. The value
465 column is the hint number of the alias. The list of operands is terminated
466 by NULL in the name column. */
467
468const struct aarch64_name_value_pair aarch64_hint_options[] =
469{
ff605452
SD		 470 /* BTI. This is also the F_DEFAULT entry for AARCH64_OPND_BTI_TARGET. */
471 { " ", HINT_ENCODE (HINT_OPD_F_NOPRINT, 0x20) },
472 { "csync", HINT_OPD_CSYNC }, /* PSB CSYNC. */
473 { "c", HINT_OPD_C }, /* BTI C. */
474 { "j", HINT_OPD_J }, /* BTI J. */
475 { "jc", HINT_OPD_JC }, /* BTI JC. */
476 { NULL, HINT_OPD_NULL },
9ed608f9
MW		 477};
478
a32c3ff8 479/* op -> op: load = 0 instruction = 1 store = 2
a06ea964
NC		 480 l -> level: 1-3
481 t -> temporal: temporal (retained) = 0 non-temporal (streaming) = 1 */
a32c3ff8 482#define B(op,l,t) (((op) << 3) | (((l) - 1) << 1) | (t))
a06ea964
NC		 483const struct aarch64_name_value_pair aarch64_prfops[32] =
484{
485 { "pldl1keep", B(0, 1, 0) },
486 { "pldl1strm", B(0, 1, 1) },
487 { "pldl2keep", B(0, 2, 0) },
488 { "pldl2strm", B(0, 2, 1) },
489 { "pldl3keep", B(0, 3, 0) },
490 { "pldl3strm", B(0, 3, 1) },
a1ccaec9
YZ		 491 { NULL, 0x06 },
492 { NULL, 0x07 },
a32c3ff8
NC		 493 { "plil1keep", B(1, 1, 0) },
494 { "plil1strm", B(1, 1, 1) },
495 { "plil2keep", B(1, 2, 0) },
496 { "plil2strm", B(1, 2, 1) },
497 { "plil3keep", B(1, 3, 0) },
498 { "plil3strm", B(1, 3, 1) },
a1ccaec9
YZ		 499 { NULL, 0x0e },
500 { NULL, 0x0f },
a32c3ff8
NC		 501 { "pstl1keep", B(2, 1, 0) },
502 { "pstl1strm", B(2, 1, 1) },
503 { "pstl2keep", B(2, 2, 0) },
504 { "pstl2strm", B(2, 2, 1) },
505 { "pstl3keep", B(2, 3, 0) },
506 { "pstl3strm", B(2, 3, 1) },
a1ccaec9
YZ		 507 { NULL, 0x16 },
508 { NULL, 0x17 },
509 { NULL, 0x18 },
510 { NULL, 0x19 },
511 { NULL, 0x1a },
512 { NULL, 0x1b },
513 { NULL, 0x1c },
514 { NULL, 0x1d },
515 { NULL, 0x1e },
516 { NULL, 0x1f },
a06ea964
NC		 517};
518#undef B
519\f
520/* Utilities on value constraint. */
521
522static inline int
523value_in_range_p (int64_t value, int low, int high)
524{
525 return (value >= low && value <= high) ? 1 : 0;
526}
527
98907a70 528/* Return true if VALUE is a multiple of ALIGN. */
a06ea964
NC		 529static inline int
530value_aligned_p (int64_t value, int align)
531{
98907a70 532 return (value % align) == 0;
a06ea964
NC		 533}
534
535/* A signed value fits in a field. */
536static inline int
537value_fit_signed_field_p (int64_t value, unsigned width)
538{
539 assert (width < 32);
540 if (width < sizeof (value) * 8)
541 {
542 int64_t lim = (int64_t)1 << (width - 1);
543 if (value >= -lim && value < lim)
544 return 1;
545 }
546 return 0;
547}
548
549/* An unsigned value fits in a field. */
550static inline int
551value_fit_unsigned_field_p (int64_t value, unsigned width)
552{
553 assert (width < 32);
554 if (width < sizeof (value) * 8)
555 {
556 int64_t lim = (int64_t)1 << width;
557 if (value >= 0 && value < lim)
558 return 1;
559 }
560 return 0;
561}
562
563/* Return 1 if OPERAND is SP or WSP. */
564int
565aarch64_stack_pointer_p (const aarch64_opnd_info *operand)
566{
567 return ((aarch64_get_operand_class (operand->type)
568 == AARCH64_OPND_CLASS_INT_REG)
569 && operand_maybe_stack_pointer (aarch64_operands + operand->type)
570 && operand->reg.regno == 31);
571}
572
573/* Return 1 if OPERAND is XZR or WZP. */
574int
575aarch64_zero_register_p (const aarch64_opnd_info *operand)
576{
577 return ((aarch64_get_operand_class (operand->type)
578 == AARCH64_OPND_CLASS_INT_REG)
579 && !operand_maybe_stack_pointer (aarch64_operands + operand->type)
580 && operand->reg.regno == 31);
581}
582
583/* Return true if the operand *OPERAND that has the operand code
584 OPERAND->TYPE and been qualified by OPERAND->QUALIFIER can be also
585 qualified by the qualifier TARGET. */
586
587static inline int
588operand_also_qualified_p (const struct aarch64_opnd_info *operand,
589 aarch64_opnd_qualifier_t target)
590{
591 switch (operand->qualifier)
592 {
593 case AARCH64_OPND_QLF_W:
594 if (target == AARCH64_OPND_QLF_WSP && aarch64_stack_pointer_p (operand))
595 return 1;
596 break;
597 case AARCH64_OPND_QLF_X:
598 if (target == AARCH64_OPND_QLF_SP && aarch64_stack_pointer_p (operand))
599 return 1;
600 break;
601 case AARCH64_OPND_QLF_WSP:
602 if (target == AARCH64_OPND_QLF_W
603 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
604 return 1;
605 break;
606 case AARCH64_OPND_QLF_SP:
607 if (target == AARCH64_OPND_QLF_X
608 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
609 return 1;
610 break;
611 default:
612 break;
613 }
614
615 return 0;
616}
617
618/* Given qualifier sequence list QSEQ_LIST and the known qualifier KNOWN_QLF
619 for operand KNOWN_IDX, return the expected qualifier for operand IDX.
620
621 Return NIL if more than one expected qualifiers are found. */
622
623aarch64_opnd_qualifier_t
624aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *qseq_list,
625 int idx,
626 const aarch64_opnd_qualifier_t known_qlf,
627 int known_idx)
628{
629 int i, saved_i;
630
631 /* Special case.
632
633 When the known qualifier is NIL, we have to assume that there is only
634 one qualifier sequence in the *QSEQ_LIST and return the corresponding
635 qualifier directly. One scenario is that for instruction
636 PRFM <prfop>, [<Xn|SP>, #:lo12:<symbol>]
637 which has only one possible valid qualifier sequence
638 NIL, S_D
639 the caller may pass NIL in KNOWN_QLF to obtain S_D so that it can
640 determine the correct relocation type (i.e. LDST64_LO12) for PRFM.
641
642 Because the qualifier NIL has dual roles in the qualifier sequence:
643 it can mean no qualifier for the operand, or the qualifer sequence is
644 not in use (when all qualifiers in the sequence are NILs), we have to
645 handle this special case here. */
646 if (known_qlf == AARCH64_OPND_NIL)
647 {
648 assert (qseq_list[0][known_idx] == AARCH64_OPND_NIL);
649 return qseq_list[0][idx];
650 }
651
652 for (i = 0, saved_i = -1; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
653 {
654 if (qseq_list[i][known_idx] == known_qlf)
655 {
656 if (saved_i != -1)
657 /* More than one sequences are found to have KNOWN_QLF at
658 KNOWN_IDX. */
659 return AARCH64_OPND_NIL;
660 saved_i = i;
661 }
662 }
663
664 return qseq_list[saved_i][idx];
665}
666
667enum operand_qualifier_kind
668{
669 OQK_NIL,
670 OQK_OPD_VARIANT,
671 OQK_VALUE_IN_RANGE,
672 OQK_MISC,
673};
674
675/* Operand qualifier description. */
676struct operand_qualifier_data
677{
678 /* The usage of the three data fields depends on the qualifier kind. */
679 int data0;
680 int data1;
681 int data2;
682 /* Description. */
683 const char *desc;
684 /* Kind. */
685 enum operand_qualifier_kind kind;
686};
687
688/* Indexed by the operand qualifier enumerators. */
689struct operand_qualifier_data aarch64_opnd_qualifiers[] =
690{
691 {0, 0, 0, "NIL", OQK_NIL},
692
693 /* Operand variant qualifiers.
694 First 3 fields:
695 element size, number of elements and common value for encoding. */
696
697 {4, 1, 0x0, "w", OQK_OPD_VARIANT},
698 {8, 1, 0x1, "x", OQK_OPD_VARIANT},
699 {4, 1, 0x0, "wsp", OQK_OPD_VARIANT},
700 {8, 1, 0x1, "sp", OQK_OPD_VARIANT},
701
702 {1, 1, 0x0, "b", OQK_OPD_VARIANT},
703 {2, 1, 0x1, "h", OQK_OPD_VARIANT},
704 {4, 1, 0x2, "s", OQK_OPD_VARIANT},
705 {8, 1, 0x3, "d", OQK_OPD_VARIANT},
706 {16, 1, 0x4, "q", OQK_OPD_VARIANT},
66e6f0b7 707 {4, 1, 0x0, "4b", OQK_OPD_VARIANT},
a06ea964 708
a3b3345a 709 {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
a06ea964
NC		 710 {1, 8, 0x0, "8b", OQK_OPD_VARIANT},
711 {1, 16, 0x1, "16b", OQK_OPD_VARIANT},
3067d3b9 712 {2, 2, 0x0, "2h", OQK_OPD_VARIANT},
a06ea964
NC		 713 {2, 4, 0x2, "4h", OQK_OPD_VARIANT},
714 {2, 8, 0x3, "8h", OQK_OPD_VARIANT},
715 {4, 2, 0x4, "2s", OQK_OPD_VARIANT},
716 {4, 4, 0x5, "4s", OQK_OPD_VARIANT},
717 {8, 1, 0x6, "1d", OQK_OPD_VARIANT},
718 {8, 2, 0x7, "2d", OQK_OPD_VARIANT},
719 {16, 1, 0x8, "1q", OQK_OPD_VARIANT},
720
d50c751e
RS		 721 {0, 0, 0, "z", OQK_OPD_VARIANT},
722 {0, 0, 0, "m", OQK_OPD_VARIANT},
723
a06ea964
NC		 724 /* Qualifiers constraining the value range.
725 First 3 fields:
726 Lower bound, higher bound, unused. */
727
a6a51754 728 {0, 15, 0, "CR", OQK_VALUE_IN_RANGE},
a06ea964
NC		 729 {0, 7, 0, "imm_0_7" , OQK_VALUE_IN_RANGE},
730 {0, 15, 0, "imm_0_15", OQK_VALUE_IN_RANGE},
731 {0, 31, 0, "imm_0_31", OQK_VALUE_IN_RANGE},
732 {0, 63, 0, "imm_0_63", OQK_VALUE_IN_RANGE},
733 {1, 32, 0, "imm_1_32", OQK_VALUE_IN_RANGE},
734 {1, 64, 0, "imm_1_64", OQK_VALUE_IN_RANGE},
735
736 /* Qualifiers for miscellaneous purpose.
737 First 3 fields:
738 unused, unused and unused. */
739
740 {0, 0, 0, "lsl", 0},
741 {0, 0, 0, "msl", 0},
742
743 {0, 0, 0, "retrieving", 0},
744};
745
746static inline bfd_boolean
747operand_variant_qualifier_p (aarch64_opnd_qualifier_t qualifier)
748{
749 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_OPD_VARIANT)
750 ? TRUE : FALSE;
751}
752
753static inline bfd_boolean
754qualifier_value_in_range_constraint_p (aarch64_opnd_qualifier_t qualifier)
755{
756 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_VALUE_IN_RANGE)
757 ? TRUE : FALSE;
758}
759
760const char*
761aarch64_get_qualifier_name (aarch64_opnd_qualifier_t qualifier)
762{
763 return aarch64_opnd_qualifiers[qualifier].desc;
764}
765
766/* Given an operand qualifier, return the expected data element size
767 of a qualified operand. */
768unsigned char
769aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t qualifier)
770{
771 assert (operand_variant_qualifier_p (qualifier) == TRUE);
772 return aarch64_opnd_qualifiers[qualifier].data0;
773}
774
775unsigned char
776aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t qualifier)
777{
778 assert (operand_variant_qualifier_p (qualifier) == TRUE);
779 return aarch64_opnd_qualifiers[qualifier].data1;
780}
781
782aarch64_insn
783aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t qualifier)
784{
785 assert (operand_variant_qualifier_p (qualifier) == TRUE);
786 return aarch64_opnd_qualifiers[qualifier].data2;
787}
788
789static int
790get_lower_bound (aarch64_opnd_qualifier_t qualifier)
791{
792 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
793 return aarch64_opnd_qualifiers[qualifier].data0;
794}
795
796static int
797get_upper_bound (aarch64_opnd_qualifier_t qualifier)
798{
799 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
800 return aarch64_opnd_qualifiers[qualifier].data1;
801}
802
803#ifdef DEBUG_AARCH64
804void
805aarch64_verbose (const char *str, ...)
806{
807 va_list ap;
808 va_start (ap, str);
809 printf ("#### ");
810 vprintf (str, ap);
811 printf ("\n");
812 va_end (ap);
813}
814
815static inline void
816dump_qualifier_sequence (const aarch64_opnd_qualifier_t *qualifier)
817{
818 int i;
819 printf ("#### \t");
820 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i, ++qualifier)
821 printf ("%s,", aarch64_get_qualifier_name (*qualifier));
822 printf ("\n");
823}
824
825static void
826dump_match_qualifiers (const struct aarch64_opnd_info *opnd,
827 const aarch64_opnd_qualifier_t *qualifier)
828{
829 int i;
830 aarch64_opnd_qualifier_t curr[AARCH64_MAX_OPND_NUM];
831
832 aarch64_verbose ("dump_match_qualifiers:");
833 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
834 curr[i] = opnd[i].qualifier;
835 dump_qualifier_sequence (curr);
836 aarch64_verbose ("against");
837 dump_qualifier_sequence (qualifier);
838}
839#endif /* DEBUG_AARCH64 */
840
a68f4cd2
TC		 841/* This function checks if the given instruction INSN is a destructive
842 instruction based on the usage of the registers. It does not recognize
843 unary destructive instructions. */
844bfd_boolean
845aarch64_is_destructive_by_operands (const aarch64_opcode *opcode)
846{
847 int i = 0;
848 const enum aarch64_opnd *opnds = opcode->operands;
849
850 if (opnds[0] == AARCH64_OPND_NIL)
851 return FALSE;
852
853 while (opnds[++i] != AARCH64_OPND_NIL)
854 if (opnds[i] == opnds[0])
855 return TRUE;
856
857 return FALSE;
858}
859
a06ea964
NC		 860/* TODO improve this, we can have an extra field at the runtime to
861 store the number of operands rather than calculating it every time. */
862
863int
864aarch64_num_of_operands (const aarch64_opcode *opcode)
865{
866 int i = 0;
867 const enum aarch64_opnd *opnds = opcode->operands;
868 while (opnds[i++] != AARCH64_OPND_NIL)
869 ;
870 --i;
871 assert (i >= 0 && i <= AARCH64_MAX_OPND_NUM);
872 return i;
873}
874
875/* Find the best matched qualifier sequence in *QUALIFIERS_LIST for INST.
876 If succeeds, fill the found sequence in *RET, return 1; otherwise return 0.
877
878 N.B. on the entry, it is very likely that only some operands in *INST
879 have had their qualifiers been established.
880
881 If STOP_AT is not -1, the function will only try to match
882 the qualifier sequence for operands before and including the operand
883 of index STOP_AT; and on success *RET will only be filled with the first
884 (STOP_AT+1) qualifiers.
885
886 A couple examples of the matching algorithm:
887
888 X,W,NIL should match
889 X,W,NIL
890
891 NIL,NIL should match
892 X ,NIL
893
894 Apart from serving the main encoding routine, this can also be called
895 during or after the operand decoding. */
896
897int
898aarch64_find_best_match (const aarch64_inst *inst,
899 const aarch64_opnd_qualifier_seq_t *qualifiers_list,
900 int stop_at, aarch64_opnd_qualifier_t *ret)
901{
902 int found = 0;
903 int i, num_opnds;
904 const aarch64_opnd_qualifier_t *qualifiers;
905
906 num_opnds = aarch64_num_of_operands (inst->opcode);
907 if (num_opnds == 0)
908 {
909 DEBUG_TRACE ("SUCCEED: no operand");
910 return 1;
911 }
912
913 if (stop_at < 0 || stop_at >= num_opnds)
914 stop_at = num_opnds - 1;
915
916 /* For each pattern. */
917 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
918 {
919 int j;
920 qualifiers = *qualifiers_list;
921
922 /* Start as positive. */
923 found = 1;
924
925 DEBUG_TRACE ("%d", i);
926#ifdef DEBUG_AARCH64
927 if (debug_dump)
928 dump_match_qualifiers (inst->operands, qualifiers);
929#endif
930
931 /* Most opcodes has much fewer patterns in the list.
932 First NIL qualifier indicates the end in the list. */
933 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
934 {
935 DEBUG_TRACE_IF (i == 0, "SUCCEED: empty qualifier list");
936 if (i)
937 found = 0;
938 break;
939 }
940
941 for (j = 0; j < num_opnds && j <= stop_at; ++j, ++qualifiers)
942 {
943 if (inst->operands[j].qualifier == AARCH64_OPND_QLF_NIL)
944 {
945 /* Either the operand does not have qualifier, or the qualifier
946 for the operand needs to be deduced from the qualifier
947 sequence.
948 In the latter case, any constraint checking related with
949 the obtained qualifier should be done later in
950 operand_general_constraint_met_p. */
951 continue;
952 }
953 else if (*qualifiers != inst->operands[j].qualifier)
954 {
955 /* Unless the target qualifier can also qualify the operand
956 (which has already had a non-nil qualifier), non-equal
957 qualifiers are generally un-matched. */
958 if (operand_also_qualified_p (inst->operands + j, *qualifiers))
959 continue;
960 else
961 {
962 found = 0;
963 break;
964 }
965 }
966 else
967 continue; /* Equal qualifiers are certainly matched. */
968 }
969
970 /* Qualifiers established. */
971 if (found == 1)
972 break;
973 }
974
975 if (found == 1)
976 {
977 /* Fill the result in *RET. */
978 int j;
979 qualifiers = *qualifiers_list;
980
981 DEBUG_TRACE ("complete qualifiers using list %d", i);
982#ifdef DEBUG_AARCH64
983 if (debug_dump)
984 dump_qualifier_sequence (qualifiers);
985#endif
986
987 for (j = 0; j <= stop_at; ++j, ++qualifiers)
988 ret[j] = *qualifiers;
989 for (; j < AARCH64_MAX_OPND_NUM; ++j)
990 ret[j] = AARCH64_OPND_QLF_NIL;
991
992 DEBUG_TRACE ("SUCCESS");
993 return 1;
994 }
995
996 DEBUG_TRACE ("FAIL");
997 return 0;
998}
999
1000/* Operand qualifier matching and resolving.
1001
1002 Return 1 if the operand qualifier(s) in *INST match one of the qualifier
1003 sequences in INST->OPCODE->qualifiers_list; otherwise return 0.
1004
1005 if UPDATE_P == TRUE, update the qualifier(s) in *INST after the matching
1006 succeeds. */
1007
1008static int
1009match_operands_qualifier (aarch64_inst *inst, bfd_boolean update_p)
1010{
4989adac 1011 int i, nops;
a06ea964
NC		 1012 aarch64_opnd_qualifier_seq_t qualifiers;
1013
1014 if (!aarch64_find_best_match (inst, inst->opcode->qualifiers_list, -1,
1015 qualifiers))
1016 {
1017 DEBUG_TRACE ("matching FAIL");
1018 return 0;
1019 }
1020
4989adac
RS		 1021 if (inst->opcode->flags & F_STRICT)
1022 {
1023 /* Require an exact qualifier match, even for NIL qualifiers. */
1024 nops = aarch64_num_of_operands (inst->opcode);
1025 for (i = 0; i < nops; ++i)
1026 if (inst->operands[i].qualifier != qualifiers[i])
1027 return FALSE;
1028 }
1029
a06ea964
NC		 1030 /* Update the qualifiers. */
1031 if (update_p == TRUE)
1032 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
1033 {
1034 if (inst->opcode->operands[i] == AARCH64_OPND_NIL)
1035 break;
1036 DEBUG_TRACE_IF (inst->operands[i].qualifier != qualifiers[i],
1037 "update %s with %s for operand %d",
1038 aarch64_get_qualifier_name (inst->operands[i].qualifier),
1039 aarch64_get_qualifier_name (qualifiers[i]), i);
1040 inst->operands[i].qualifier = qualifiers[i];
1041 }
1042
1043 DEBUG_TRACE ("matching SUCCESS");
1044 return 1;
1045}
1046
1047/* Return TRUE if VALUE is a wide constant that can be moved into a general
1048 register by MOVZ.
1049
1050 IS32 indicates whether value is a 32-bit immediate or not.
1051 If SHIFT_AMOUNT is not NULL, on the return of TRUE, the logical left shift
1052 amount will be returned in *SHIFT_AMOUNT. */
1053
1054bfd_boolean
1055aarch64_wide_constant_p (int64_t value, int is32, unsigned int *shift_amount)
1056{
1057 int amount;
1058
1059 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1060
1061 if (is32)
1062 {
1063 /* Allow all zeros or all ones in top 32-bits, so that
1064 32-bit constant expressions like ~0x80000000 are
1065 permitted. */
1066 uint64_t ext = value;
1067 if (ext >> 32 != 0 && ext >> 32 != (uint64_t) 0xffffffff)
1068 /* Immediate out of range. */
1069 return FALSE;
1070 value &= (int64_t) 0xffffffff;
1071 }
1072
1073 /* first, try movz then movn */
1074 amount = -1;
1075 if ((value & ((int64_t) 0xffff << 0)) == value)
1076 amount = 0;
1077 else if ((value & ((int64_t) 0xffff << 16)) == value)
1078 amount = 16;
1079 else if (!is32 && (value & ((int64_t) 0xffff << 32)) == value)
1080 amount = 32;
1081 else if (!is32 && (value & ((int64_t) 0xffff << 48)) == value)
1082 amount = 48;
1083
1084 if (amount == -1)
1085 {
1086 DEBUG_TRACE ("exit FALSE with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1087 return FALSE;
1088 }
1089
1090 if (shift_amount != NULL)
1091 *shift_amount = amount;
1092
1093 DEBUG_TRACE ("exit TRUE with amount %d", amount);
1094
1095 return TRUE;
1096}
1097
1098/* Build the accepted values for immediate logical SIMD instructions.
1099
1100 The standard encodings of the immediate value are:
1101 N imms immr SIMD size R S
1102 1 ssssss rrrrrr 64 UInt(rrrrrr) UInt(ssssss)
1103 0 0sssss 0rrrrr 32 UInt(rrrrr) UInt(sssss)
1104 0 10ssss 00rrrr 16 UInt(rrrr) UInt(ssss)
1105 0 110sss 000rrr 8 UInt(rrr) UInt(sss)
1106 0 1110ss 0000rr 4 UInt(rr) UInt(ss)
1107 0 11110s 00000r 2 UInt(r) UInt(s)
1108 where all-ones value of S is reserved.
1109
1110 Let's call E the SIMD size.
1111
1112 The immediate value is: S+1 bits '1' rotated to the right by R.
1113
1114 The total of valid encodings is 64*63 + 32*31 + ... + 2*1 = 5334
1115 (remember S != E - 1). */
1116
1117#define TOTAL_IMM_NB 5334
1118
1119typedef struct
1120{
1121 uint64_t imm;
1122 aarch64_insn encoding;
1123} simd_imm_encoding;
1124
1125static simd_imm_encoding simd_immediates[TOTAL_IMM_NB];
1126
1127static int
1128simd_imm_encoding_cmp(const void *i1, const void *i2)
1129{
1130 const simd_imm_encoding *imm1 = (const simd_imm_encoding *)i1;
1131 const simd_imm_encoding *imm2 = (const simd_imm_encoding *)i2;
1132
1133 if (imm1->imm < imm2->imm)
1134 return -1;
1135 if (imm1->imm > imm2->imm)
1136 return +1;
1137 return 0;
1138}
1139
1140/* immediate bitfield standard encoding
1141 imm13<12> imm13<5:0> imm13<11:6> SIMD size R S
1142 1 ssssss rrrrrr 64 rrrrrr ssssss
1143 0 0sssss 0rrrrr 32 rrrrr sssss
1144 0 10ssss 00rrrr 16 rrrr ssss
1145 0 110sss 000rrr 8 rrr sss
1146 0 1110ss 0000rr 4 rr ss
1147 0 11110s 00000r 2 r s */
1148static inline int
1149encode_immediate_bitfield (int is64, uint32_t s, uint32_t r)
1150{
1151 return (is64 << 12) | (r << 6) | s;
1152}
1153
1154static void
1155build_immediate_table (void)
1156{
1157 uint32_t log_e, e, s, r, s_mask;
1158 uint64_t mask, imm;
1159 int nb_imms;
1160 int is64;
1161
1162 nb_imms = 0;
1163 for (log_e = 1; log_e <= 6; log_e++)
1164 {
1165 /* Get element size. */
1166 e = 1u << log_e;
1167 if (log_e == 6)
1168 {
1169 is64 = 1;
1170 mask = 0xffffffffffffffffull;
1171 s_mask = 0;
1172 }
1173 else
1174 {
1175 is64 = 0;
1176 mask = (1ull << e) - 1;
1177 /* log_e s_mask
1178 1 ((1 << 4) - 1) << 2 = 111100
1179 2 ((1 << 3) - 1) << 3 = 111000
1180 3 ((1 << 2) - 1) << 4 = 110000
1181 4 ((1 << 1) - 1) << 5 = 100000
1182 5 ((1 << 0) - 1) << 6 = 000000 */
1183 s_mask = ((1u << (5 - log_e)) - 1) << (log_e + 1);
1184 }
1185 for (s = 0; s < e - 1; s++)
1186 for (r = 0; r < e; r++)
1187 {
1188 /* s+1 consecutive bits to 1 (s < 63) */
1189 imm = (1ull << (s + 1)) - 1;
1190 /* rotate right by r */
1191 if (r != 0)
1192 imm = (imm >> r) | ((imm << (e - r)) & mask);
1193 /* replicate the constant depending on SIMD size */
1194 switch (log_e)
1195 {
1196 case 1: imm = (imm << 2) | imm;
1a0670f3 1197 /* Fall through. */
a06ea964 1198 case 2: imm = (imm << 4) | imm;
1a0670f3 1199 /* Fall through. */
a06ea964 1200 case 3: imm = (imm << 8) | imm;
1a0670f3 1201 /* Fall through. */
a06ea964 1202 case 4: imm = (imm << 16) | imm;
1a0670f3 1203 /* Fall through. */
a06ea964 1204 case 5: imm = (imm << 32) | imm;
1a0670f3 1205 /* Fall through. */
a06ea964
NC		 1206 case 6: break;
1207 default: abort ();
1208 }
1209 simd_immediates[nb_imms].imm = imm;
1210 simd_immediates[nb_imms].encoding =
1211 encode_immediate_bitfield(is64, s | s_mask, r);
1212 nb_imms++;
1213 }
1214 }
1215 assert (nb_imms == TOTAL_IMM_NB);
1216 qsort(simd_immediates, nb_imms,
1217 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1218}
1219
1220/* Return TRUE if VALUE is a valid logical immediate, i.e. bitmask, that can
1221 be accepted by logical (immediate) instructions
1222 e.g. ORR <Xd|SP>, <Xn>, #<imm>.
1223
42408347 1224 ESIZE is the number of bytes in the decoded immediate value.
a06ea964
NC		 1225 If ENCODING is not NULL, on the return of TRUE, the standard encoding for
1226 VALUE will be returned in *ENCODING. */
1227
1228bfd_boolean
42408347 1229aarch64_logical_immediate_p (uint64_t value, int esize, aarch64_insn *encoding)
a06ea964
NC		 1230{
1231 simd_imm_encoding imm_enc;
1232 const simd_imm_encoding *imm_encoding;
1233 static bfd_boolean initialized = FALSE;
42408347
RS		 1234 uint64_t upper;
1235 int i;
a06ea964 1236
957f6b39
TC		 1237 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 "), esize: %d", value,
1238 value, esize);
a06ea964 1239
535b785f 1240 if (!initialized)
a06ea964
NC		 1241 {
1242 build_immediate_table ();
1243 initialized = TRUE;
1244 }
1245
42408347
RS		 1246 /* Allow all zeros or all ones in top bits, so that
1247 constant expressions like ~1 are permitted. */
1248 upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
1249 if ((value & ~upper) != value && (value | upper) != value)
1250 return FALSE;
7e105031 1251
42408347
RS		 1252 /* Replicate to a full 64-bit value. */
1253 value &= ~upper;
1254 for (i = esize * 8; i < 64; i *= 2)
1255 value |= (value << i);
a06ea964
NC		 1256
1257 imm_enc.imm = value;
1258 imm_encoding = (const simd_imm_encoding *)
1259 bsearch(&imm_enc, simd_immediates, TOTAL_IMM_NB,
1260 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1261 if (imm_encoding == NULL)
1262 {
1263 DEBUG_TRACE ("exit with FALSE");
1264 return FALSE;
1265 }
1266 if (encoding != NULL)
1267 *encoding = imm_encoding->encoding;
1268 DEBUG_TRACE ("exit with TRUE");
1269 return TRUE;
1270}
1271
1272/* If 64-bit immediate IMM is in the format of
1273 "aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh",
1274 where a, b, c, d, e, f, g and h are independently 0 or 1, return an integer
1275 of value "abcdefgh". Otherwise return -1. */
1276int
1277aarch64_shrink_expanded_imm8 (uint64_t imm)
1278{
1279 int i, ret;
1280 uint32_t byte;
1281
1282 ret = 0;
1283 for (i = 0; i < 8; i++)
1284 {
1285 byte = (imm >> (8 * i)) & 0xff;
1286 if (byte == 0xff)
1287 ret |= 1 << i;
1288 else if (byte != 0x00)
1289 return -1;
1290 }
1291 return ret;
1292}
1293
1294/* Utility inline functions for operand_general_constraint_met_p. */
1295
1296static inline void
1297set_error (aarch64_operand_error *mismatch_detail,
1298 enum aarch64_operand_error_kind kind, int idx,
1299 const char* error)
1300{
1301 if (mismatch_detail == NULL)
1302 return;
1303 mismatch_detail->kind = kind;
1304 mismatch_detail->index = idx;
1305 mismatch_detail->error = error;
1306}
1307
4e50d5f8
YZ		 1308static inline void
1309set_syntax_error (aarch64_operand_error *mismatch_detail, int idx,
1310 const char* error)
1311{
1312 if (mismatch_detail == NULL)
1313 return;
1314 set_error (mismatch_detail, AARCH64_OPDE_SYNTAX_ERROR, idx, error);
1315}
1316
a06ea964
NC		 1317static inline void
1318set_out_of_range_error (aarch64_operand_error *mismatch_detail,
1319 int idx, int lower_bound, int upper_bound,
1320 const char* error)
1321{
1322 if (mismatch_detail == NULL)
1323 return;
1324 set_error (mismatch_detail, AARCH64_OPDE_OUT_OF_RANGE, idx, error);
1325 mismatch_detail->data[0] = lower_bound;
1326 mismatch_detail->data[1] = upper_bound;
1327}
1328
1329static inline void
1330set_imm_out_of_range_error (aarch64_operand_error *mismatch_detail,
1331 int idx, int lower_bound, int upper_bound)
1332{
1333 if (mismatch_detail == NULL)
1334 return;
1335 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1336 _("immediate value"));
1337}
1338
1339static inline void
1340set_offset_out_of_range_error (aarch64_operand_error *mismatch_detail,
1341 int idx, int lower_bound, int upper_bound)
1342{
1343 if (mismatch_detail == NULL)
1344 return;
1345 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1346 _("immediate offset"));
1347}
1348
1349static inline void
1350set_regno_out_of_range_error (aarch64_operand_error *mismatch_detail,
1351 int idx, int lower_bound, int upper_bound)
1352{
1353 if (mismatch_detail == NULL)
1354 return;
1355 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1356 _("register number"));
1357}
1358
1359static inline void
1360set_elem_idx_out_of_range_error (aarch64_operand_error *mismatch_detail,
1361 int idx, int lower_bound, int upper_bound)
1362{
1363 if (mismatch_detail == NULL)
1364 return;
1365 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1366 _("register element index"));
1367}
1368
1369static inline void
1370set_sft_amount_out_of_range_error (aarch64_operand_error *mismatch_detail,
1371 int idx, int lower_bound, int upper_bound)
1372{
1373 if (mismatch_detail == NULL)
1374 return;
1375 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1376 _("shift amount"));
1377}
1378
2442d846
RS		 1379/* Report that the MUL modifier in operand IDX should be in the range
1380 [LOWER_BOUND, UPPER_BOUND]. */
1381static inline void
1382set_multiplier_out_of_range_error (aarch64_operand_error *mismatch_detail,
1383 int idx, int lower_bound, int upper_bound)
1384{
1385 if (mismatch_detail == NULL)
1386 return;
1387 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1388 _("multiplier"));
1389}
1390
a06ea964
NC		 1391static inline void
1392set_unaligned_error (aarch64_operand_error *mismatch_detail, int idx,
1393 int alignment)
1394{
1395 if (mismatch_detail == NULL)
1396 return;
1397 set_error (mismatch_detail, AARCH64_OPDE_UNALIGNED, idx, NULL);
1398 mismatch_detail->data[0] = alignment;
1399}
1400
1401static inline void
1402set_reg_list_error (aarch64_operand_error *mismatch_detail, int idx,
1403 int expected_num)
1404{
1405 if (mismatch_detail == NULL)
1406 return;
1407 set_error (mismatch_detail, AARCH64_OPDE_REG_LIST, idx, NULL);
1408 mismatch_detail->data[0] = expected_num;
1409}
1410
1411static inline void
1412set_other_error (aarch64_operand_error *mismatch_detail, int idx,
1413 const char* error)
1414{
1415 if (mismatch_detail == NULL)
1416 return;
1417 set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
1418}
1419
1420/* General constraint checking based on operand code.
1421
1422 Return 1 if OPNDS[IDX] meets the general constraint of operand code TYPE
1423 as the IDXth operand of opcode OPCODE. Otherwise return 0.
1424
1425 This function has to be called after the qualifiers for all operands
1426 have been resolved.
1427
1428 Mismatching error message is returned in *MISMATCH_DETAIL upon request,
1429 i.e. when MISMATCH_DETAIL is non-NULL. This avoids the generation
1430 of error message during the disassembling where error message is not
1431 wanted. We avoid the dynamic construction of strings of error messages
1432 here (i.e. in libopcodes), as it is costly and complicated; instead, we
1433 use a combination of error code, static string and some integer data to
1434 represent an error. */
1435
1436static int
1437operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
1438 enum aarch64_opnd type,
1439 const aarch64_opcode *opcode,
1440 aarch64_operand_error *mismatch_detail)
1441{
e950b345 1442 unsigned num, modifiers, shift;
a06ea964 1443 unsigned char size;
4df068de 1444 int64_t imm, min_value, max_value;
e950b345 1445 uint64_t uvalue, mask;
a06ea964
NC		 1446 const aarch64_opnd_info *opnd = opnds + idx;
1447 aarch64_opnd_qualifier_t qualifier = opnd->qualifier;
1448
1449 assert (opcode->operands[idx] == opnd->type && opnd->type == type);
1450
1451 switch (aarch64_operands[type].op_class)
1452 {
1453 case AARCH64_OPND_CLASS_INT_REG:
ee804238
JW		 1454 /* Check pair reg constraints for cas* instructions. */
1455 if (type == AARCH64_OPND_PAIRREG)
1456 {
1457 assert (idx == 1 || idx == 3);
1458 if (opnds[idx - 1].reg.regno % 2 != 0)
1459 {
1460 set_syntax_error (mismatch_detail, idx - 1,
1461 _("reg pair must start from even reg"));
1462 return 0;
1463 }
1464 if (opnds[idx].reg.regno != opnds[idx - 1].reg.regno + 1)
1465 {
1466 set_syntax_error (mismatch_detail, idx,
1467 _("reg pair must be contiguous"));
1468 return 0;
1469 }
1470 break;
1471 }
1472
a06ea964
NC		 1473 /* <Xt> may be optional in some IC and TLBI instructions. */
1474 if (type == AARCH64_OPND_Rt_SYS)
1475 {
1476 assert (idx == 1 && (aarch64_get_operand_class (opnds[0].type)
1477 == AARCH64_OPND_CLASS_SYSTEM));
ea2deeec
MW		 1478 if (opnds[1].present
1479 && !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
a06ea964
NC		 1480 {
1481 set_other_error (mismatch_detail, idx, _("extraneous register"));
1482 return 0;
1483 }
ea2deeec
MW		 1484 if (!opnds[1].present
1485 && aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
a06ea964
NC		 1486 {
1487 set_other_error (mismatch_detail, idx, _("missing register"));
1488 return 0;
1489 }
1490 }
1491 switch (qualifier)
1492 {
1493 case AARCH64_OPND_QLF_WSP:
1494 case AARCH64_OPND_QLF_SP:
1495 if (!aarch64_stack_pointer_p (opnd))
1496 {
1497 set_other_error (mismatch_detail, idx,
1498 _("stack pointer register expected"));
1499 return 0;
1500 }
1501 break;
1502 default:
1503 break;
1504 }
1505 break;
1506
f11ad6bc
RS		 1507 case AARCH64_OPND_CLASS_SVE_REG:
1508 switch (type)
1509 {
582e12bf
RS		 1510 case AARCH64_OPND_SVE_Zm3_INDEX:
1511 case AARCH64_OPND_SVE_Zm3_22_INDEX:
1512 case AARCH64_OPND_SVE_Zm4_INDEX:
1513 size = get_operand_fields_width (get_operand_from_code (type));
1514 shift = get_operand_specific_data (&aarch64_operands[type]);
1515 mask = (1 << shift) - 1;
1516 if (opnd->reg.regno > mask)
1517 {
1518 assert (mask == 7 || mask == 15);
1519 set_other_error (mismatch_detail, idx,
1520 mask == 15
1521 ? _("z0-z15 expected")
1522 : _("z0-z7 expected"));
1523 return 0;
1524 }
1525 mask = (1 << (size - shift)) - 1;
1526 if (!value_in_range_p (opnd->reglane.index, 0, mask))
1527 {
1528 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, mask);
1529 return 0;
1530 }
1531 break;
1532
f11ad6bc
RS		 1533 case AARCH64_OPND_SVE_Zn_INDEX:
1534 size = aarch64_get_qualifier_esize (opnd->qualifier);
1535 if (!value_in_range_p (opnd->reglane.index, 0, 64 / size - 1))
1536 {
1537 set_elem_idx_out_of_range_error (mismatch_detail, idx,
1538 0, 64 / size - 1);
1539 return 0;
1540 }
1541 break;
1542
1543 case AARCH64_OPND_SVE_ZnxN:
1544 case AARCH64_OPND_SVE_ZtxN:
1545 if (opnd->reglist.num_regs != get_opcode_dependent_value (opcode))
1546 {
1547 set_other_error (mismatch_detail, idx,
1548 _("invalid register list"));
1549 return 0;
1550 }
1551 break;
1552
1553 default:
1554 break;
1555 }
1556 break;
1557
1558 case AARCH64_OPND_CLASS_PRED_REG:
1559 if (opnd->reg.regno >= 8
1560 && get_operand_fields_width (get_operand_from_code (type)) == 3)
1561 {
1562 set_other_error (mismatch_detail, idx, _("p0-p7 expected"));
1563 return 0;
1564 }
1565 break;
1566
68a64283
YZ		 1567 case AARCH64_OPND_CLASS_COND:
1568 if (type == AARCH64_OPND_COND1
1569 && (opnds[idx].cond->value & 0xe) == 0xe)
1570 {
1571 /* Not allow AL or NV. */
1572 set_syntax_error (mismatch_detail, idx, NULL);
1573 }
1574 break;
1575
a06ea964
NC		 1576 case AARCH64_OPND_CLASS_ADDRESS:
1577 /* Check writeback. */
1578 switch (opcode->iclass)
1579 {
1580 case ldst_pos:
1581 case ldst_unscaled:
1582 case ldstnapair_offs:
1583 case ldstpair_off:
1584 case ldst_unpriv:
1585 if (opnd->addr.writeback == 1)
1586 {
4e50d5f8
YZ		 1587 set_syntax_error (mismatch_detail, idx,
1588 _("unexpected address writeback"));
a06ea964
NC		 1589 return 0;
1590 }
1591 break;
3f06e550
SN		 1592 case ldst_imm10:
1593 if (opnd->addr.writeback == 1 && opnd->addr.preind != 1)
1594 {
1595 set_syntax_error (mismatch_detail, idx,
1596 _("unexpected address writeback"));
1597 return 0;
1598 }
1599 break;
a06ea964
NC		 1600 case ldst_imm9:
1601 case ldstpair_indexed:
1602 case asisdlsep:
1603 case asisdlsop:
1604 if (opnd->addr.writeback == 0)
1605 {
4e50d5f8
YZ		 1606 set_syntax_error (mismatch_detail, idx,
1607 _("address writeback expected"));
a06ea964
NC		 1608 return 0;
1609 }
1610 break;
1611 default:
1612 assert (opnd->addr.writeback == 0);
1613 break;
1614 }
1615 switch (type)
1616 {
1617 case AARCH64_OPND_ADDR_SIMM7:
1618 /* Scaled signed 7 bits immediate offset. */
1619 /* Get the size of the data element that is accessed, which may be
1620 different from that of the source register size,
1621 e.g. in strb/ldrb. */
1622 size = aarch64_get_qualifier_esize (opnd->qualifier);
1623 if (!value_in_range_p (opnd->addr.offset.imm, -64 * size, 63 * size))
1624 {
1625 set_offset_out_of_range_error (mismatch_detail, idx,
1626 -64 * size, 63 * size);
1627 return 0;
1628 }
1629 if (!value_aligned_p (opnd->addr.offset.imm, size))
1630 {
1631 set_unaligned_error (mismatch_detail, idx, size);
1632 return 0;
1633 }
1634 break;
f42f1a1d 1635 case AARCH64_OPND_ADDR_OFFSET:
a06ea964
NC		 1636 case AARCH64_OPND_ADDR_SIMM9:
1637 /* Unscaled signed 9 bits immediate offset. */
1638 if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
1639 {
1640 set_offset_out_of_range_error (mismatch_detail, idx, -256, 255);
1641 return 0;
1642 }
1643 break;
1644
1645 case AARCH64_OPND_ADDR_SIMM9_2:
1646 /* Unscaled signed 9 bits immediate offset, which has to be negative
1647 or unaligned. */
1648 size = aarch64_get_qualifier_esize (qualifier);
1649 if ((value_in_range_p (opnd->addr.offset.imm, 0, 255)
1650 && !value_aligned_p (opnd->addr.offset.imm, size))
1651 || value_in_range_p (opnd->addr.offset.imm, -256, -1))
1652 return 1;
1653 set_other_error (mismatch_detail, idx,
1654 _("negative or unaligned offset expected"));
1655 return 0;
1656
3f06e550
SN		 1657 case AARCH64_OPND_ADDR_SIMM10:
1658 /* Scaled signed 10 bits immediate offset. */
1659 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088))
1660 {
1661 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4088);
1662 return 0;
1663 }
1664 if (!value_aligned_p (opnd->addr.offset.imm, 8))
1665 {
1666 set_unaligned_error (mismatch_detail, idx, 8);
1667 return 0;
1668 }
1669 break;
1670
a06ea964
NC		 1671 case AARCH64_OPND_SIMD_ADDR_POST:
1672 /* AdvSIMD load/store multiple structures, post-index. */
1673 assert (idx == 1);
1674 if (opnd->addr.offset.is_reg)
1675 {
1676 if (value_in_range_p (opnd->addr.offset.regno, 0, 30))
1677 return 1;
1678 else
1679 {
1680 set_other_error (mismatch_detail, idx,
1681 _("invalid register offset"));
1682 return 0;
1683 }
1684 }
1685 else
1686 {
1687 const aarch64_opnd_info *prev = &opnds[idx-1];
1688 unsigned num_bytes; /* total number of bytes transferred. */
1689 /* The opcode dependent area stores the number of elements in
1690 each structure to be loaded/stored. */
1691 int is_ld1r = get_opcode_dependent_value (opcode) == 1;
1692 if (opcode->operands[0] == AARCH64_OPND_LVt_AL)
1693 /* Special handling of loading single structure to all lane. */
1694 num_bytes = (is_ld1r ? 1 : prev->reglist.num_regs)
1695 * aarch64_get_qualifier_esize (prev->qualifier);
1696 else
1697 num_bytes = prev->reglist.num_regs
1698 * aarch64_get_qualifier_esize (prev->qualifier)
1699 * aarch64_get_qualifier_nelem (prev->qualifier);
1700 if ((int) num_bytes != opnd->addr.offset.imm)
1701 {
1702 set_other_error (mismatch_detail, idx,
1703 _("invalid post-increment amount"));
1704 return 0;
1705 }
1706 }
1707 break;
1708
1709 case AARCH64_OPND_ADDR_REGOFF:
1710 /* Get the size of the data element that is accessed, which may be
1711 different from that of the source register size,
1712 e.g. in strb/ldrb. */
1713 size = aarch64_get_qualifier_esize (opnd->qualifier);
1714 /* It is either no shift or shift by the binary logarithm of SIZE. */
1715 if (opnd->shifter.amount != 0
1716 && opnd->shifter.amount != (int)get_logsz (size))
1717 {
1718 set_other_error (mismatch_detail, idx,
1719 _("invalid shift amount"));
1720 return 0;
1721 }
1722 /* Only UXTW, LSL, SXTW and SXTX are the accepted extending
1723 operators. */
1724 switch (opnd->shifter.kind)
1725 {
1726 case AARCH64_MOD_UXTW:
1727 case AARCH64_MOD_LSL:
1728 case AARCH64_MOD_SXTW:
1729 case AARCH64_MOD_SXTX: break;
1730 default:
1731 set_other_error (mismatch_detail, idx,
1732 _("invalid extend/shift operator"));
1733 return 0;
1734 }
1735 break;
1736
1737 case AARCH64_OPND_ADDR_UIMM12:
1738 imm = opnd->addr.offset.imm;
1739 /* Get the size of the data element that is accessed, which may be
1740 different from that of the source register size,
1741 e.g. in strb/ldrb. */
1742 size = aarch64_get_qualifier_esize (qualifier);
1743 if (!value_in_range_p (opnd->addr.offset.imm, 0, 4095 * size))
1744 {
1745 set_offset_out_of_range_error (mismatch_detail, idx,
1746 0, 4095 * size);
1747 return 0;
1748 }
9de794e1 1749 if (!value_aligned_p (opnd->addr.offset.imm, size))
a06ea964
NC		 1750 {
1751 set_unaligned_error (mismatch_detail, idx, size);
1752 return 0;
1753 }
1754 break;
1755
1756 case AARCH64_OPND_ADDR_PCREL14:
1757 case AARCH64_OPND_ADDR_PCREL19:
1758 case AARCH64_OPND_ADDR_PCREL21:
1759 case AARCH64_OPND_ADDR_PCREL26:
1760 imm = opnd->imm.value;
1761 if (operand_need_shift_by_two (get_operand_from_code (type)))
1762 {
1763 /* The offset value in a PC-relative branch instruction is alway
1764 4-byte aligned and is encoded without the lowest 2 bits. */
1765 if (!value_aligned_p (imm, 4))
1766 {
1767 set_unaligned_error (mismatch_detail, idx, 4);
1768 return 0;
1769 }
1770 /* Right shift by 2 so that we can carry out the following check
1771 canonically. */
1772 imm >>= 2;
1773 }
1774 size = get_operand_fields_width (get_operand_from_code (type));
1775 if (!value_fit_signed_field_p (imm, size))
1776 {
1777 set_other_error (mismatch_detail, idx,
1778 _("immediate out of range"));
1779 return 0;
1780 }
1781 break;
1782
98907a70
RS		 1783 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
1784 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
1785 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
1786 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
1787 min_value = -8;
1788 max_value = 7;
1789 sve_imm_offset_vl:
1790 assert (!opnd->addr.offset.is_reg);
1791 assert (opnd->addr.preind);
1792 num = 1 + get_operand_specific_data (&aarch64_operands[type]);
1793 min_value *= num;
1794 max_value *= num;
1795 if ((opnd->addr.offset.imm != 0 && !opnd->shifter.operator_present)
1796 || (opnd->shifter.operator_present
1797 && opnd->shifter.kind != AARCH64_MOD_MUL_VL))
1798 {
1799 set_other_error (mismatch_detail, idx,
1800 _("invalid addressing mode"));
1801 return 0;
1802 }
1803 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1804 {
1805 set_offset_out_of_range_error (mismatch_detail, idx,
1806 min_value, max_value);
1807 return 0;
1808 }
1809 if (!value_aligned_p (opnd->addr.offset.imm, num))
1810 {
1811 set_unaligned_error (mismatch_detail, idx, num);
1812 return 0;
1813 }
1814 break;
1815
1816 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
1817 min_value = -32;
1818 max_value = 31;
1819 goto sve_imm_offset_vl;
1820
1821 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
1822 min_value = -256;
1823 max_value = 255;
1824 goto sve_imm_offset_vl;
1825
4df068de
RS		 1826 case AARCH64_OPND_SVE_ADDR_RI_U6:
1827 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
1828 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
1829 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
1830 min_value = 0;
1831 max_value = 63;
1832 sve_imm_offset:
1833 assert (!opnd->addr.offset.is_reg);
1834 assert (opnd->addr.preind);
1835 num = 1 << get_operand_specific_data (&aarch64_operands[type]);
1836 min_value *= num;
1837 max_value *= num;
1838 if (opnd->shifter.operator_present
1839 || opnd->shifter.amount_present)
1840 {
1841 set_other_error (mismatch_detail, idx,
1842 _("invalid addressing mode"));
1843 return 0;
1844 }
1845 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1846 {
1847 set_offset_out_of_range_error (mismatch_detail, idx,
1848 min_value, max_value);
1849 return 0;
1850 }
1851 if (!value_aligned_p (opnd->addr.offset.imm, num))
1852 {
1853 set_unaligned_error (mismatch_detail, idx, num);
1854 return 0;
1855 }
1856 break;
1857
582e12bf
RS		 1858 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
1859 min_value = -8;
1860 max_value = 7;
1861 goto sve_imm_offset;
1862
c8d59609 1863 case AARCH64_OPND_SVE_ADDR_R:
4df068de
RS		 1864 case AARCH64_OPND_SVE_ADDR_RR:
1865 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
1866 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
1867 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
1868 case AARCH64_OPND_SVE_ADDR_RX:
1869 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
1870 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
1871 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
1872 case AARCH64_OPND_SVE_ADDR_RZ:
1873 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
1874 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
1875 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
1876 modifiers = 1 << AARCH64_MOD_LSL;
1877 sve_rr_operand:
1878 assert (opnd->addr.offset.is_reg);
1879 assert (opnd->addr.preind);
1880 if ((aarch64_operands[type].flags & OPD_F_NO_ZR) != 0
1881 && opnd->addr.offset.regno == 31)
1882 {
1883 set_other_error (mismatch_detail, idx,
1884 _("index register xzr is not allowed"));
1885 return 0;
1886 }
1887 if (((1 << opnd->shifter.kind) & modifiers) == 0
1888 || (opnd->shifter.amount
1889 != get_operand_specific_data (&aarch64_operands[type])))
1890 {
1891 set_other_error (mismatch_detail, idx,
1892 _("invalid addressing mode"));
1893 return 0;
1894 }
1895 break;
1896
1897 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
1898 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
1899 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
1900 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
1901 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
1902 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
1903 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
1904 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
1905 modifiers = (1 << AARCH64_MOD_SXTW) | (1 << AARCH64_MOD_UXTW);
1906 goto sve_rr_operand;
1907
1908 case AARCH64_OPND_SVE_ADDR_ZI_U5:
1909 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
1910 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
1911 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
1912 min_value = 0;
1913 max_value = 31;
1914 goto sve_imm_offset;
1915
1916 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
1917 modifiers = 1 << AARCH64_MOD_LSL;
1918 sve_zz_operand:
1919 assert (opnd->addr.offset.is_reg);
1920 assert (opnd->addr.preind);
1921 if (((1 << opnd->shifter.kind) & modifiers) == 0
1922 || opnd->shifter.amount < 0
1923 || opnd->shifter.amount > 3)
1924 {
1925 set_other_error (mismatch_detail, idx,
1926 _("invalid addressing mode"));
1927 return 0;
1928 }
1929 break;
1930
1931 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
1932 modifiers = (1 << AARCH64_MOD_SXTW);
1933 goto sve_zz_operand;
1934
1935 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
1936 modifiers = 1 << AARCH64_MOD_UXTW;
1937 goto sve_zz_operand;
1938
a06ea964
NC		 1939 default:
1940 break;
1941 }
1942 break;
1943
1944 case AARCH64_OPND_CLASS_SIMD_REGLIST:
dab26bf4
RS		 1945 if (type == AARCH64_OPND_LEt)
1946 {
1947 /* Get the upper bound for the element index. */
1948 num = 16 / aarch64_get_qualifier_esize (qualifier) - 1;
1949 if (!value_in_range_p (opnd->reglist.index, 0, num))
1950 {
1951 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
1952 return 0;
1953 }
1954 }
a06ea964
NC		 1955 /* The opcode dependent area stores the number of elements in
1956 each structure to be loaded/stored. */
1957 num = get_opcode_dependent_value (opcode);
1958 switch (type)
1959 {
1960 case AARCH64_OPND_LVt:
1961 assert (num >= 1 && num <= 4);
1962 /* Unless LD1/ST1, the number of registers should be equal to that
1963 of the structure elements. */
1964 if (num != 1 && opnd->reglist.num_regs != num)
1965 {
1966 set_reg_list_error (mismatch_detail, idx, num);
1967 return 0;
1968 }
1969 break;
1970 case AARCH64_OPND_LVt_AL:
1971 case AARCH64_OPND_LEt:
1972 assert (num >= 1 && num <= 4);
1973 /* The number of registers should be equal to that of the structure
1974 elements. */
1975 if (opnd->reglist.num_regs != num)
1976 {
1977 set_reg_list_error (mismatch_detail, idx, num);
1978 return 0;
1979 }
1980 break;
1981 default:
1982 break;
1983 }
1984 break;
1985
1986 case AARCH64_OPND_CLASS_IMMEDIATE:
1987 /* Constraint check on immediate operand. */
1988 imm = opnd->imm.value;
1989 /* E.g. imm_0_31 constrains value to be 0..31. */
1990 if (qualifier_value_in_range_constraint_p (qualifier)
1991 && !value_in_range_p (imm, get_lower_bound (qualifier),
1992 get_upper_bound (qualifier)))
1993 {
1994 set_imm_out_of_range_error (mismatch_detail, idx,
1995 get_lower_bound (qualifier),
1996 get_upper_bound (qualifier));
1997 return 0;
1998 }
1999
2000 switch (type)
2001 {
2002 case AARCH64_OPND_AIMM:
2003 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2004 {
2005 set_other_error (mismatch_detail, idx,
2006 _("invalid shift operator"));
2007 return 0;
2008 }
2009 if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
2010 {
2011 set_other_error (mismatch_detail, idx,
ab3b8fcf 2012 _("shift amount must be 0 or 12"));
a06ea964
NC		 2013 return 0;
2014 }
2015 if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
2016 {
2017 set_other_error (mismatch_detail, idx,
2018 _("immediate out of range"));
2019 return 0;
2020 }
2021 break;
2022
2023 case AARCH64_OPND_HALF:
2024 assert (idx == 1 && opnds[0].type == AARCH64_OPND_Rd);
2025 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2026 {
2027 set_other_error (mismatch_detail, idx,
2028 _("invalid shift operator"));
2029 return 0;
2030 }
2031 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2032 if (!value_aligned_p (opnd->shifter.amount, 16))
2033 {
2034 set_other_error (mismatch_detail, idx,
ab3b8fcf 2035 _("shift amount must be a multiple of 16"));
a06ea964
NC		 2036 return 0;
2037 }
2038 if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
2039 {
2040 set_sft_amount_out_of_range_error (mismatch_detail, idx,
2041 0, size * 8 - 16);
2042 return 0;
2043 }
2044 if (opnd->imm.value < 0)
2045 {
2046 set_other_error (mismatch_detail, idx,
2047 _("negative immediate value not allowed"));
2048 return 0;
2049 }
2050 if (!value_fit_unsigned_field_p (opnd->imm.value, 16))
2051 {
2052 set_other_error (mismatch_detail, idx,
2053 _("immediate out of range"));
2054 return 0;
2055 }
2056 break;
2057
2058 case AARCH64_OPND_IMM_MOV:
2059 {
42408347 2060 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
a06ea964
NC		 2061 imm = opnd->imm.value;
2062 assert (idx == 1);
2063 switch (opcode->op)
2064 {
2065 case OP_MOV_IMM_WIDEN:
2066 imm = ~imm;
1a0670f3 2067 /* Fall through. */
a06ea964 2068 case OP_MOV_IMM_WIDE:
42408347 2069 if (!aarch64_wide_constant_p (imm, esize == 4, NULL))
a06ea964
NC		 2070 {
2071 set_other_error (mismatch_detail, idx,
2072 _("immediate out of range"));
2073 return 0;
2074 }
2075 break;
2076 case OP_MOV_IMM_LOG:
42408347 2077 if (!aarch64_logical_immediate_p (imm, esize, NULL))
a06ea964
NC		 2078 {
2079 set_other_error (mismatch_detail, idx,
2080 _("immediate out of range"));
2081 return 0;
2082 }
2083 break;
2084 default:
2085 assert (0);
2086 return 0;
2087 }
2088 }
2089 break;
2090
2091 case AARCH64_OPND_NZCV:
2092 case AARCH64_OPND_CCMP_IMM:
2093 case AARCH64_OPND_EXCEPTION:
2094 case AARCH64_OPND_UIMM4:
193614f2 2095 case AARCH64_OPND_UIMM4_ADDG:
a06ea964
NC		 2096 case AARCH64_OPND_UIMM7:
2097 case AARCH64_OPND_UIMM3_OP1:
2098 case AARCH64_OPND_UIMM3_OP2:
e950b345
RS		 2099 case AARCH64_OPND_SVE_UIMM3:
2100 case AARCH64_OPND_SVE_UIMM7:
2101 case AARCH64_OPND_SVE_UIMM8:
2102 case AARCH64_OPND_SVE_UIMM8_53:
a06ea964
NC		 2103 size = get_operand_fields_width (get_operand_from_code (type));
2104 assert (size < 32);
2105 if (!value_fit_unsigned_field_p (opnd->imm.value, size))
2106 {
2107 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2108 (1 << size) - 1);
2109 return 0;
2110 }
2111 break;
2112
193614f2
SD		 2113 case AARCH64_OPND_UIMM10:
2114 /* Scaled unsigned 10 bits immediate offset. */
2115 if (!value_in_range_p (opnd->imm.value, 0, 1008))
2116 {
2117 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1008);
2118 return 0;
2119 }
2120
2121 if (!value_aligned_p (opnd->imm.value, 16))
2122 {
2123 set_unaligned_error (mismatch_detail, idx, 16);
2124 return 0;
2125 }
2126 break;
2127
e950b345
RS		 2128 case AARCH64_OPND_SIMM5:
2129 case AARCH64_OPND_SVE_SIMM5:
2130 case AARCH64_OPND_SVE_SIMM5B:
2131 case AARCH64_OPND_SVE_SIMM6:
2132 case AARCH64_OPND_SVE_SIMM8:
2133 size = get_operand_fields_width (get_operand_from_code (type));
2134 assert (size < 32);
2135 if (!value_fit_signed_field_p (opnd->imm.value, size))
2136 {
2137 set_imm_out_of_range_error (mismatch_detail, idx,
2138 -(1 << (size - 1)),
2139 (1 << (size - 1)) - 1);
2140 return 0;
2141 }
2142 break;
2143
a06ea964 2144 case AARCH64_OPND_WIDTH:
d685192a 2145 assert (idx > 1 && opnds[idx-1].type == AARCH64_OPND_IMM
a06ea964
NC		 2146 && opnds[0].type == AARCH64_OPND_Rd);
2147 size = get_upper_bound (qualifier);
2148 if (opnd->imm.value + opnds[idx-1].imm.value > size)
2149 /* lsb+width <= reg.size */
2150 {
2151 set_imm_out_of_range_error (mismatch_detail, idx, 1,
2152 size - opnds[idx-1].imm.value);
2153 return 0;
2154 }
2155 break;
2156
2157 case AARCH64_OPND_LIMM:
e950b345 2158 case AARCH64_OPND_SVE_LIMM:
42408347
RS		 2159 {
2160 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2161 uint64_t uimm = opnd->imm.value;
2162 if (opcode->op == OP_BIC)
2163 uimm = ~uimm;
535b785f 2164 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
42408347
RS		 2165 {
2166 set_other_error (mismatch_detail, idx,
2167 _("immediate out of range"));
2168 return 0;
2169 }
2170 }
a06ea964
NC		 2171 break;
2172
2173 case AARCH64_OPND_IMM0:
2174 case AARCH64_OPND_FPIMM0:
2175 if (opnd->imm.value != 0)
2176 {
2177 set_other_error (mismatch_detail, idx,
2178 _("immediate zero expected"));
2179 return 0;
2180 }
2181 break;
2182
c2c4ff8d
SN		 2183 case AARCH64_OPND_IMM_ROT1:
2184 case AARCH64_OPND_IMM_ROT2:
582e12bf 2185 case AARCH64_OPND_SVE_IMM_ROT2:
c2c4ff8d
SN		 2186 if (opnd->imm.value != 0
2187 && opnd->imm.value != 90
2188 && opnd->imm.value != 180
2189 && opnd->imm.value != 270)
2190 {
2191 set_other_error (mismatch_detail, idx,
2192 _("rotate expected to be 0, 90, 180 or 270"));
2193 return 0;
2194 }
2195 break;
2196
2197 case AARCH64_OPND_IMM_ROT3:
582e12bf 2198 case AARCH64_OPND_SVE_IMM_ROT1:
c2c4ff8d
SN		 2199 if (opnd->imm.value != 90 && opnd->imm.value != 270)
2200 {
2201 set_other_error (mismatch_detail, idx,
2202 _("rotate expected to be 90 or 270"));
2203 return 0;
2204 }
2205 break;
2206
a06ea964
NC		 2207 case AARCH64_OPND_SHLL_IMM:
2208 assert (idx == 2);
2209 size = 8 * aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2210 if (opnd->imm.value != size)
2211 {
2212 set_other_error (mismatch_detail, idx,
2213 _("invalid shift amount"));
2214 return 0;
2215 }
2216 break;
2217
2218 case AARCH64_OPND_IMM_VLSL:
2219 size = aarch64_get_qualifier_esize (qualifier);
2220 if (!value_in_range_p (opnd->imm.value, 0, size * 8 - 1))
2221 {
2222 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2223 size * 8 - 1);
2224 return 0;
2225 }
2226 break;
2227
2228 case AARCH64_OPND_IMM_VLSR:
2229 size = aarch64_get_qualifier_esize (qualifier);
2230 if (!value_in_range_p (opnd->imm.value, 1, size * 8))
2231 {
2232 set_imm_out_of_range_error (mismatch_detail, idx, 1, size * 8);
2233 return 0;
2234 }
2235 break;
2236
2237 case AARCH64_OPND_SIMD_IMM:
2238 case AARCH64_OPND_SIMD_IMM_SFT:
2239 /* Qualifier check. */
2240 switch (qualifier)
2241 {
2242 case AARCH64_OPND_QLF_LSL:
2243 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2244 {
2245 set_other_error (mismatch_detail, idx,
2246 _("invalid shift operator"));
2247 return 0;
2248 }
2249 break;
2250 case AARCH64_OPND_QLF_MSL:
2251 if (opnd->shifter.kind != AARCH64_MOD_MSL)
2252 {
2253 set_other_error (mismatch_detail, idx,
2254 _("invalid shift operator"));
2255 return 0;
2256 }
2257 break;
2258 case AARCH64_OPND_QLF_NIL:
2259 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2260 {
2261 set_other_error (mismatch_detail, idx,
2262 _("shift is not permitted"));
2263 return 0;
2264 }
2265 break;
2266 default:
2267 assert (0);
2268 return 0;
2269 }
2270 /* Is the immediate valid? */
2271 assert (idx == 1);
2272 if (aarch64_get_qualifier_esize (opnds[0].qualifier) != 8)
2273 {
d2865ed3
YZ		 2274 /* uimm8 or simm8 */
2275 if (!value_in_range_p (opnd->imm.value, -128, 255))
a06ea964 2276 {
d2865ed3 2277 set_imm_out_of_range_error (mismatch_detail, idx, -128, 255);
a06ea964
NC		 2278 return 0;
2279 }
2280 }
2281 else if (aarch64_shrink_expanded_imm8 (opnd->imm.value) < 0)
2282 {
2283 /* uimm64 is not
2284 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeee
2285 ffffffffgggggggghhhhhhhh'. */
2286 set_other_error (mismatch_detail, idx,
2287 _("invalid value for immediate"));
2288 return 0;
2289 }
2290 /* Is the shift amount valid? */
2291 switch (opnd->shifter.kind)
2292 {
2293 case AARCH64_MOD_LSL:
2294 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
f5555712 2295 if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8))
a06ea964 2296 {
f5555712
YZ		 2297 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0,
2298 (size - 1) * 8);
a06ea964
NC		 2299 return 0;
2300 }
f5555712 2301 if (!value_aligned_p (opnd->shifter.amount, 8))
a06ea964 2302 {
f5555712 2303 set_unaligned_error (mismatch_detail, idx, 8);
a06ea964
NC		 2304 return 0;
2305 }
2306 break;
2307 case AARCH64_MOD_MSL:
2308 /* Only 8 and 16 are valid shift amount. */
2309 if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
2310 {
2311 set_other_error (mismatch_detail, idx,
ab3b8fcf 2312 _("shift amount must be 0 or 16"));
a06ea964
NC		 2313 return 0;
2314 }
2315 break;
2316 default:
2317 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2318 {
2319 set_other_error (mismatch_detail, idx,
2320 _("invalid shift operator"));
2321 return 0;
2322 }
2323 break;
2324 }
2325 break;
2326
2327 case AARCH64_OPND_FPIMM:
2328 case AARCH64_OPND_SIMD_FPIMM:
165d4950 2329 case AARCH64_OPND_SVE_FPIMM8:
a06ea964
NC		 2330 if (opnd->imm.is_fp == 0)
2331 {
2332 set_other_error (mismatch_detail, idx,
2333 _("floating-point immediate expected"));
2334 return 0;
2335 }
2336 /* The value is expected to be an 8-bit floating-point constant with
2337 sign, 3-bit exponent and normalized 4 bits of precision, encoded
2338 in "a:b:c:d:e:f:g:h" or FLD_imm8 (depending on the type of the
2339 instruction). */
2340 if (!value_in_range_p (opnd->imm.value, 0, 255))
2341 {
2342 set_other_error (mismatch_detail, idx,
2343 _("immediate out of range"));
2344 return 0;
2345 }
2346 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2347 {
2348 set_other_error (mismatch_detail, idx,
2349 _("invalid shift operator"));
2350 return 0;
2351 }
2352 break;
2353
e950b345
RS		 2354 case AARCH64_OPND_SVE_AIMM:
2355 min_value = 0;
2356 sve_aimm:
2357 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
2358 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2359 mask = ~((uint64_t) -1 << (size * 4) << (size * 4));
2360 uvalue = opnd->imm.value;
2361 shift = opnd->shifter.amount;
2362 if (size == 1)
2363 {
2364 if (shift != 0)
2365 {
2366 set_other_error (mismatch_detail, idx,
2367 _("no shift amount allowed for"
2368 " 8-bit constants"));
2369 return 0;
2370 }
2371 }
2372 else
2373 {
2374 if (shift != 0 && shift != 8)
2375 {
2376 set_other_error (mismatch_detail, idx,
2377 _("shift amount must be 0 or 8"));
2378 return 0;
2379 }
2380 if (shift == 0 && (uvalue & 0xff) == 0)
2381 {
2382 shift = 8;
2383 uvalue = (int64_t) uvalue / 256;
2384 }
2385 }
2386 mask >>= shift;
2387 if ((uvalue & mask) != uvalue && (uvalue | ~mask) != uvalue)
2388 {
2389 set_other_error (mismatch_detail, idx,
2390 _("immediate too big for element size"));
2391 return 0;
2392 }
2393 uvalue = (uvalue - min_value) & mask;
2394 if (uvalue > 0xff)
2395 {
2396 set_other_error (mismatch_detail, idx,
2397 _("invalid arithmetic immediate"));
2398 return 0;
2399 }
2400 break;
2401
2402 case AARCH64_OPND_SVE_ASIMM:
2403 min_value = -128;
2404 goto sve_aimm;
2405
165d4950
RS		 2406 case AARCH64_OPND_SVE_I1_HALF_ONE:
2407 assert (opnd->imm.is_fp);
2408 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x3f800000)
2409 {
2410 set_other_error (mismatch_detail, idx,
2411 _("floating-point value must be 0.5 or 1.0"));
2412 return 0;
2413 }
2414 break;
2415
2416 case AARCH64_OPND_SVE_I1_HALF_TWO:
2417 assert (opnd->imm.is_fp);
2418 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x40000000)
2419 {
2420 set_other_error (mismatch_detail, idx,
2421 _("floating-point value must be 0.5 or 2.0"));
2422 return 0;
2423 }
2424 break;
2425
2426 case AARCH64_OPND_SVE_I1_ZERO_ONE:
2427 assert (opnd->imm.is_fp);
2428 if (opnd->imm.value != 0 && opnd->imm.value != 0x3f800000)
2429 {
2430 set_other_error (mismatch_detail, idx,
2431 _("floating-point value must be 0.0 or 1.0"));
2432 return 0;
2433 }
2434 break;
2435
e950b345
RS		 2436 case AARCH64_OPND_SVE_INV_LIMM:
2437 {
2438 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2439 uint64_t uimm = ~opnd->imm.value;
2440 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2441 {
2442 set_other_error (mismatch_detail, idx,
2443 _("immediate out of range"));
2444 return 0;
2445 }
2446 }
2447 break;
2448
2449 case AARCH64_OPND_SVE_LIMM_MOV:
2450 {
2451 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2452 uint64_t uimm = opnd->imm.value;
2453 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2454 {
2455 set_other_error (mismatch_detail, idx,
2456 _("immediate out of range"));
2457 return 0;
2458 }
2459 if (!aarch64_sve_dupm_mov_immediate_p (uimm, esize))
2460 {
2461 set_other_error (mismatch_detail, idx,
2462 _("invalid replicated MOV immediate"));
2463 return 0;
2464 }
2465 }
2466 break;
2467
2442d846
RS		 2468 case AARCH64_OPND_SVE_PATTERN_SCALED:
2469 assert (opnd->shifter.kind == AARCH64_MOD_MUL);
2470 if (!value_in_range_p (opnd->shifter.amount, 1, 16))
2471 {
2472 set_multiplier_out_of_range_error (mismatch_detail, idx, 1, 16);
2473 return 0;
2474 }
2475 break;
2476
e950b345
RS		 2477 case AARCH64_OPND_SVE_SHLIMM_PRED:
2478 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
2479 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2480 if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
2481 {
2482 set_imm_out_of_range_error (mismatch_detail, idx,
2483 0, 8 * size - 1);
2484 return 0;
2485 }
2486 break;
2487
2488 case AARCH64_OPND_SVE_SHRIMM_PRED:
2489 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
2490 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2491 if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
2492 {
2493 set_imm_out_of_range_error (mismatch_detail, idx, 1, 8 * size);
2494 return 0;
2495 }
2496 break;
2497
a06ea964
NC		 2498 default:
2499 break;
2500 }
2501 break;
2502
a06ea964
NC		 2503 case AARCH64_OPND_CLASS_SYSTEM:
2504 switch (type)
2505 {
2506 case AARCH64_OPND_PSTATEFIELD:
2507 assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
0bff6e2d
MW		 2508 /* MSR UAO, #uimm4
2509 MSR PAN, #uimm4
104fefee 2510 MSR SSBS,#uimm4
c2825638 2511 The immediate must be #0 or #1. */
0bff6e2d 2512 if ((opnd->pstatefield == 0x03 /* UAO. */
793a1948 2513 || opnd->pstatefield == 0x04 /* PAN. */
104fefee 2514 || opnd->pstatefield == 0x19 /* SSBS. */
793a1948 2515 || opnd->pstatefield == 0x1a) /* DIT. */
c2825638
MW		 2516 && opnds[1].imm.value > 1)
2517 {
2518 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2519 return 0;
2520 }
a06ea964
NC		 2521 /* MSR SPSel, #uimm4
2522 Uses uimm4 as a control value to select the stack pointer: if
2523 bit 0 is set it selects the current exception level's stack
2524 pointer, if bit 0 is clear it selects shared EL0 stack pointer.
2525 Bits 1 to 3 of uimm4 are reserved and should be zero. */
2526 if (opnd->pstatefield == 0x05 /* spsel */ && opnds[1].imm.value > 1)
2527 {
2528 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2529 return 0;
2530 }
2531 break;
2532 default:
2533 break;
2534 }
2535 break;
2536
2537 case AARCH64_OPND_CLASS_SIMD_ELEMENT:
2538 /* Get the upper bound for the element index. */
c2c4ff8d
SN		 2539 if (opcode->op == OP_FCMLA_ELEM)
2540 /* FCMLA index range depends on the vector size of other operands
2541 and is halfed because complex numbers take two elements. */
2542 num = aarch64_get_qualifier_nelem (opnds[0].qualifier)
2543 * aarch64_get_qualifier_esize (opnds[0].qualifier) / 2;
2544 else
2545 num = 16;
2546 num = num / aarch64_get_qualifier_esize (qualifier) - 1;
66e6f0b7 2547 assert (aarch64_get_qualifier_nelem (qualifier) == 1);
c2c4ff8d 2548
a06ea964
NC		 2549 /* Index out-of-range. */
2550 if (!value_in_range_p (opnd->reglane.index, 0, num))
2551 {
2552 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
2553 return 0;
2554 }
2555 /* SMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>].
2556 <Vm> Is the vector register (V0-V31) or (V0-V15), whose
2557 number is encoded in "size:M:Rm":
2558 size <Vm>
2559 00 RESERVED
2560 01 0:Rm
2561 10 M:Rm
2562 11 RESERVED */
369c9167 2563 if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H
a06ea964
NC		 2564 && !value_in_range_p (opnd->reglane.regno, 0, 15))
2565 {
2566 set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
2567 return 0;
2568 }
2569 break;
2570
2571 case AARCH64_OPND_CLASS_MODIFIED_REG:
2572 assert (idx == 1 || idx == 2);
2573 switch (type)
2574 {
2575 case AARCH64_OPND_Rm_EXT:
535b785f 2576 if (!aarch64_extend_operator_p (opnd->shifter.kind)
a06ea964
NC		 2577 && opnd->shifter.kind != AARCH64_MOD_LSL)
2578 {
2579 set_other_error (mismatch_detail, idx,
2580 _("extend operator expected"));
2581 return 0;
2582 }
2583 /* It is not optional unless at least one of "Rd" or "Rn" is '11111'
2584 (i.e. SP), in which case it defaults to LSL. The LSL alias is
2585 only valid when "Rd" or "Rn" is '11111', and is preferred in that
2586 case. */
2587 if (!aarch64_stack_pointer_p (opnds + 0)
2588 && (idx != 2 || !aarch64_stack_pointer_p (opnds + 1)))
2589 {
2590 if (!opnd->shifter.operator_present)
2591 {
2592 set_other_error (mismatch_detail, idx,
2593 _("missing extend operator"));
2594 return 0;
2595 }
2596 else if (opnd->shifter.kind == AARCH64_MOD_LSL)
2597 {
2598 set_other_error (mismatch_detail, idx,
2599 _("'LSL' operator not allowed"));
2600 return 0;
2601 }
2602 }
2603 assert (opnd->shifter.operator_present /* Default to LSL. */
2604 || opnd->shifter.kind == AARCH64_MOD_LSL);
2605 if (!value_in_range_p (opnd->shifter.amount, 0, 4))
2606 {
2607 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, 4);
2608 return 0;
2609 }
2610 /* In the 64-bit form, the final register operand is written as Wm
2611 for all but the (possibly omitted) UXTX/LSL and SXTX
2612 operators.
2613 N.B. GAS allows X register to be used with any operator as a
2614 programming convenience. */
2615 if (qualifier == AARCH64_OPND_QLF_X
2616 && opnd->shifter.kind != AARCH64_MOD_LSL
2617 && opnd->shifter.kind != AARCH64_MOD_UXTX
2618 && opnd->shifter.kind != AARCH64_MOD_SXTX)
2619 {
2620 set_other_error (mismatch_detail, idx, _("W register expected"));
2621 return 0;
2622 }
2623 break;
2624
2625 case AARCH64_OPND_Rm_SFT:
2626 /* ROR is not available to the shifted register operand in
2627 arithmetic instructions. */
535b785f 2628 if (!aarch64_shift_operator_p (opnd->shifter.kind))
a06ea964
NC		 2629 {
2630 set_other_error (mismatch_detail, idx,
2631 _("shift operator expected"));
2632 return 0;
2633 }
2634 if (opnd->shifter.kind == AARCH64_MOD_ROR
2635 && opcode->iclass != log_shift)
2636 {
2637 set_other_error (mismatch_detail, idx,
2638 _("'ROR' operator not allowed"));
2639 return 0;
2640 }
2641 num = qualifier == AARCH64_OPND_QLF_W ? 31 : 63;
2642 if (!value_in_range_p (opnd->shifter.amount, 0, num))
2643 {
2644 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, num);
2645 return 0;
2646 }
2647 break;
2648
2649 default:
2650 break;
2651 }
2652 break;
2653
2654 default:
2655 break;
2656 }
2657
2658 return 1;
2659}
2660
2661/* Main entrypoint for the operand constraint checking.
2662
2663 Return 1 if operands of *INST meet the constraint applied by the operand
2664 codes and operand qualifiers; otherwise return 0 and if MISMATCH_DETAIL is
2665 not NULL, return the detail of the error in *MISMATCH_DETAIL. N.B. when
2666 adding more constraint checking, make sure MISMATCH_DETAIL->KIND is set
2667 with a proper error kind rather than AARCH64_OPDE_NIL (GAS asserts non-NIL
2668 error kind when it is notified that an instruction does not pass the check).
2669
2670 Un-determined operand qualifiers may get established during the process. */
2671
2672int
2673aarch64_match_operands_constraint (aarch64_inst *inst,
2674 aarch64_operand_error *mismatch_detail)
2675{
2676 int i;
2677
2678 DEBUG_TRACE ("enter");
2679
0c608d6b
RS		 2680 /* Check for cases where a source register needs to be the same as the
2681 destination register. Do this before matching qualifiers since if
2682 an instruction has both invalid tying and invalid qualifiers,
2683 the error about qualifiers would suggest several alternative
2684 instructions that also have invalid tying. */
2685 i = inst->opcode->tied_operand;
2686 if (i > 0 && (inst->operands[0].reg.regno != inst->operands[i].reg.regno))
2687 {
2688 if (mismatch_detail)
2689 {
2690 mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND;
2691 mismatch_detail->index = i;
2692 mismatch_detail->error = NULL;
2693 }
2694 return 0;
2695 }
2696
a06ea964
NC		 2697 /* Match operands' qualifier.
2698 *INST has already had qualifier establish for some, if not all, of
2699 its operands; we need to find out whether these established
2700 qualifiers match one of the qualifier sequence in
2701 INST->OPCODE->QUALIFIERS_LIST. If yes, we will assign each operand
2702 with the corresponding qualifier in such a sequence.
2703 Only basic operand constraint checking is done here; the more thorough
2704 constraint checking will carried out by operand_general_constraint_met_p,
2705 which has be to called after this in order to get all of the operands'
2706 qualifiers established. */
2707 if (match_operands_qualifier (inst, TRUE /* update_p */) == 0)
2708 {
2709 DEBUG_TRACE ("FAIL on operand qualifier matching");
2710 if (mismatch_detail)
2711 {
2712 /* Return an error type to indicate that it is the qualifier
2713 matching failure; we don't care about which operand as there
2714 are enough information in the opcode table to reproduce it. */
2715 mismatch_detail->kind = AARCH64_OPDE_INVALID_VARIANT;
2716 mismatch_detail->index = -1;
2717 mismatch_detail->error = NULL;
2718 }
2719 return 0;
2720 }
2721
2722 /* Match operands' constraint. */
2723 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2724 {
2725 enum aarch64_opnd type = inst->opcode->operands[i];
2726 if (type == AARCH64_OPND_NIL)
2727 break;
2728 if (inst->operands[i].skip)
2729 {
2730 DEBUG_TRACE ("skip the incomplete operand %d", i);
2731 continue;
2732 }
2733 if (operand_general_constraint_met_p (inst->operands, i, type,
2734 inst->opcode, mismatch_detail) == 0)
2735 {
2736 DEBUG_TRACE ("FAIL on operand %d", i);
2737 return 0;
2738 }
2739 }
2740
2741 DEBUG_TRACE ("PASS");
2742
2743 return 1;
2744}
2745
2746/* Replace INST->OPCODE with OPCODE and return the replaced OPCODE.
2747 Also updates the TYPE of each INST->OPERANDS with the corresponding
2748 value of OPCODE->OPERANDS.
2749
2750 Note that some operand qualifiers may need to be manually cleared by
2751 the caller before it further calls the aarch64_opcode_encode; by
2752 doing this, it helps the qualifier matching facilities work
2753 properly. */
2754
2755const aarch64_opcode*
2756aarch64_replace_opcode (aarch64_inst *inst, const aarch64_opcode *opcode)
2757{
2758 int i;
2759 const aarch64_opcode *old = inst->opcode;
2760
2761 inst->opcode = opcode;
2762
2763 /* Update the operand types. */
2764 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2765 {
2766 inst->operands[i].type = opcode->operands[i];
2767 if (opcode->operands[i] == AARCH64_OPND_NIL)
2768 break;
2769 }
2770
2771 DEBUG_TRACE ("replace %s with %s", old->name, opcode->name);
2772
2773 return old;
2774}
2775
2776int
2777aarch64_operand_index (const enum aarch64_opnd *operands, enum aarch64_opnd operand)
2778{
2779 int i;
2780 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2781 if (operands[i] == operand)
2782 return i;
2783 else if (operands[i] == AARCH64_OPND_NIL)
2784 break;
2785 return -1;
2786}
2787\f
72e9f319
RS		 2788/* R0...R30, followed by FOR31. */
2789#define BANK(R, FOR31) \
2790 { R (0), R (1), R (2), R (3), R (4), R (5), R (6), R (7), \
2791 R (8), R (9), R (10), R (11), R (12), R (13), R (14), R (15), \
2792 R (16), R (17), R (18), R (19), R (20), R (21), R (22), R (23), \
2793 R (24), R (25), R (26), R (27), R (28), R (29), R (30), FOR31 }
a06ea964
NC		 2794/* [0][0] 32-bit integer regs with sp Wn
2795 [0][1] 64-bit integer regs with sp Xn sf=1
2796 [1][0] 32-bit integer regs with #0 Wn
2797 [1][1] 64-bit integer regs with #0 Xn sf=1 */
2798static const char *int_reg[2][2][32] = {
72e9f319
RS		 2799#define R32(X) "w" #X
2800#define R64(X) "x" #X
2801 { BANK (R32, "wsp"), BANK (R64, "sp") },
2802 { BANK (R32, "wzr"), BANK (R64, "xzr") }
a06ea964
NC		 2803#undef R64
2804#undef R32
2805};
4df068de
RS		 2806
2807/* Names of the SVE vector registers, first with .S suffixes,
2808 then with .D suffixes. */
2809
2810static const char *sve_reg[2][32] = {
2811#define ZS(X) "z" #X ".s"
2812#define ZD(X) "z" #X ".d"
2813 BANK (ZS, ZS (31)), BANK (ZD, ZD (31))
2814#undef ZD
2815#undef ZS
2816};
72e9f319 2817#undef BANK
a06ea964
NC		 2818
2819/* Return the integer register name.
2820 if SP_REG_P is not 0, R31 is an SP reg, other R31 is the zero reg. */
2821
2822static inline const char *
2823get_int_reg_name (int regno, aarch64_opnd_qualifier_t qualifier, int sp_reg_p)
2824{
2825 const int has_zr = sp_reg_p ? 0 : 1;
2826 const int is_64 = aarch64_get_qualifier_esize (qualifier) == 4 ? 0 : 1;
2827 return int_reg[has_zr][is_64][regno];
2828}
2829
2830/* Like get_int_reg_name, but IS_64 is always 1. */
2831
2832static inline const char *
2833get_64bit_int_reg_name (int regno, int sp_reg_p)
2834{
2835 const int has_zr = sp_reg_p ? 0 : 1;
2836 return int_reg[has_zr][1][regno];
2837}
2838
01dbfe4c
RS		 2839/* Get the name of the integer offset register in OPND, using the shift type
2840 to decide whether it's a word or doubleword. */
2841
2842static inline const char *
2843get_offset_int_reg_name (const aarch64_opnd_info *opnd)
2844{
2845 switch (opnd->shifter.kind)
2846 {
2847 case AARCH64_MOD_UXTW:
2848 case AARCH64_MOD_SXTW:
2849 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_W, 0);
2850
2851 case AARCH64_MOD_LSL:
2852 case AARCH64_MOD_SXTX:
2853 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_X, 0);
2854
2855 default:
2856 abort ();
2857 }
2858}
2859
4df068de
RS		 2860/* Get the name of the SVE vector offset register in OPND, using the operand
2861 qualifier to decide whether the suffix should be .S or .D. */
2862
2863static inline const char *
2864get_addr_sve_reg_name (int regno, aarch64_opnd_qualifier_t qualifier)
2865{
2866 assert (qualifier == AARCH64_OPND_QLF_S_S
2867 || qualifier == AARCH64_OPND_QLF_S_D);
2868 return sve_reg[qualifier == AARCH64_OPND_QLF_S_D][regno];
2869}
2870
a06ea964
NC		 2871/* Types for expanding an encoded 8-bit value to a floating-point value. */
2872
2873typedef union
2874{
2875 uint64_t i;
2876 double d;
2877} double_conv_t;
2878
2879typedef union
2880{
2881 uint32_t i;
2882 float f;
2883} single_conv_t;
2884
cf86120b
MW		 2885typedef union
2886{
2887 uint32_t i;
2888 float f;
2889} half_conv_t;
2890
a06ea964
NC		 2891/* IMM8 is an 8-bit floating-point constant with sign, 3-bit exponent and
2892 normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h" or FLD_imm8
2893 (depending on the type of the instruction). IMM8 will be expanded to a
cf86120b
MW		 2894 single-precision floating-point value (SIZE == 4) or a double-precision
2895 floating-point value (SIZE == 8). A half-precision floating-point value
2896 (SIZE == 2) is expanded to a single-precision floating-point value. The
2897 expanded value is returned. */
a06ea964
NC		 2898
2899static uint64_t
cf86120b 2900expand_fp_imm (int size, uint32_t imm8)
a06ea964 2901{
57a024f4 2902 uint64_t imm = 0;
a06ea964
NC		 2903 uint32_t imm8_7, imm8_6_0, imm8_6, imm8_6_repl4;
2904
2905 imm8_7 = (imm8 >> 7) & 0x01; /* imm8<7> */
2906 imm8_6_0 = imm8 & 0x7f; /* imm8<6:0> */
2907 imm8_6 = imm8_6_0 >> 6; /* imm8<6> */
2908 imm8_6_repl4 = (imm8_6 << 3) | (imm8_6 << 2)
2909 | (imm8_6 << 1) | imm8_6; /* Replicate(imm8<6>,4) */
cf86120b 2910 if (size == 8)
a06ea964
NC		 2911 {
2912 imm = (imm8_7 << (63-32)) /* imm8<7> */
2913 | ((imm8_6 ^ 1) << (62-32)) /* NOT(imm8<6) */
2914 | (imm8_6_repl4 << (58-32)) | (imm8_6 << (57-32))
2915 | (imm8_6 << (56-32)) | (imm8_6 << (55-32)) /* Replicate(imm8<6>,7) */
2916 | (imm8_6_0 << (48-32)); /* imm8<6>:imm8<5:0> */
2917 imm <<= 32;
2918 }
cf86120b 2919 else if (size == 4 || size == 2)
a06ea964
NC		 2920 {
2921 imm = (imm8_7 << 31) /* imm8<7> */
2922 | ((imm8_6 ^ 1) << 30) /* NOT(imm8<6>) */
2923 | (imm8_6_repl4 << 26) /* Replicate(imm8<6>,4) */
2924 | (imm8_6_0 << 19); /* imm8<6>:imm8<5:0> */
2925 }
cf86120b
MW		 2926 else
2927 {
2928 /* An unsupported size. */
2929 assert (0);
2930 }
a06ea964
NC		 2931
2932 return imm;
2933}
2934
2935/* Produce the string representation of the register list operand *OPND
8a7f0c1b
RS		 2936 in the buffer pointed by BUF of size SIZE. PREFIX is the part of
2937 the register name that comes before the register number, such as "v". */
a06ea964 2938static void
8a7f0c1b
RS		 2939print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
2940 const char *prefix)
a06ea964
NC		 2941{
2942 const int num_regs = opnd->reglist.num_regs;
2943 const int first_reg = opnd->reglist.first_regno;
2944 const int last_reg = (first_reg + num_regs - 1) & 0x1f;
2945 const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
2946 char tb[8]; /* Temporary buffer. */
2947
2948 assert (opnd->type != AARCH64_OPND_LEt || opnd->reglist.has_index);
2949 assert (num_regs >= 1 && num_regs <= 4);
2950
2951 /* Prepare the index if any. */
2952 if (opnd->reglist.has_index)
1b7e3d2f
NC		 2953 /* PR 21096: The %100 is to silence a warning about possible truncation. */
2954 snprintf (tb, 8, "[%" PRIi64 "]", (opnd->reglist.index % 100));
a06ea964
NC		 2955 else
2956 tb[0] = '\0';
2957
2958 /* The hyphenated form is preferred for disassembly if there are
2959 more than two registers in the list, and the register numbers
2960 are monotonically increasing in increments of one. */
2961 if (num_regs > 2 && last_reg > first_reg)
8a7f0c1b
RS		 2962 snprintf (buf, size, "{%s%d.%s-%s%d.%s}%s", prefix, first_reg, qlf_name,
2963 prefix, last_reg, qlf_name, tb);
a06ea964
NC		 2964 else
2965 {
2966 const int reg0 = first_reg;
2967 const int reg1 = (first_reg + 1) & 0x1f;
2968 const int reg2 = (first_reg + 2) & 0x1f;
2969 const int reg3 = (first_reg + 3) & 0x1f;
2970
2971 switch (num_regs)
2972 {
2973 case 1:
8a7f0c1b 2974 snprintf (buf, size, "{%s%d.%s}%s", prefix, reg0, qlf_name, tb);
a06ea964
NC		 2975 break;
2976 case 2:
8a7f0c1b
RS		 2977 snprintf (buf, size, "{%s%d.%s, %s%d.%s}%s", prefix, reg0, qlf_name,
2978 prefix, reg1, qlf_name, tb);
a06ea964
NC		 2979 break;
2980 case 3:
8a7f0c1b
RS		 2981 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s}%s",
2982 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
2983 prefix, reg2, qlf_name, tb);
a06ea964
NC		 2984 break;
2985 case 4:
8a7f0c1b
RS		 2986 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s, %s%d.%s}%s",
2987 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
2988 prefix, reg2, qlf_name, prefix, reg3, qlf_name, tb);
a06ea964
NC		 2989 break;
2990 }
2991 }
2992}
2993
01dbfe4c
RS		 2994/* Print the register+immediate address in OPND to BUF, which has SIZE
2995 characters. BASE is the name of the base register. */
2996
2997static void
2998print_immediate_offset_address (char *buf, size_t size,
2999 const aarch64_opnd_info *opnd,
3000 const char *base)
3001{
3002 if (opnd->addr.writeback)
3003 {
3004 if (opnd->addr.preind)
ad43e107 3005 snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
01dbfe4c 3006 else
ad43e107 3007 snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
01dbfe4c
RS		 3008 }
3009 else
3010 {
98907a70
RS		 3011 if (opnd->shifter.operator_present)
3012 {
3013 assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL);
ad43e107 3014 snprintf (buf, size, "[%s, #%d, mul vl]",
98907a70
RS		 3015 base, opnd->addr.offset.imm);
3016 }
3017 else if (opnd->addr.offset.imm)
ad43e107 3018 snprintf (buf, size, "[%s, #%d]", base, opnd->addr.offset.imm);
01dbfe4c
RS		 3019 else
3020 snprintf (buf, size, "[%s]", base);
3021 }
3022}
3023
a06ea964 3024/* Produce the string representation of the register offset address operand
01dbfe4c
RS		 3025 *OPND in the buffer pointed by BUF of size SIZE. BASE and OFFSET are
3026 the names of the base and offset registers. */
a06ea964
NC		 3027static void
3028print_register_offset_address (char *buf, size_t size,
01dbfe4c
RS		 3029 const aarch64_opnd_info *opnd,
3030 const char *base, const char *offset)
a06ea964 3031{
0d2f91fe 3032 char tb[16]; /* Temporary buffer. */
a06ea964
NC		 3033 bfd_boolean print_extend_p = TRUE;
3034 bfd_boolean print_amount_p = TRUE;
3035 const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name;
3036
a06ea964
NC		 3037 if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B
3038 || !opnd->shifter.amount_present))
3039 {
3040 /* Not print the shift/extend amount when the amount is zero and
3041 when it is not the special case of 8-bit load/store instruction. */
3042 print_amount_p = FALSE;
3043 /* Likewise, no need to print the shift operator LSL in such a
3044 situation. */
01dbfe4c 3045 if (opnd->shifter.kind == AARCH64_MOD_LSL)
a06ea964
NC		 3046 print_extend_p = FALSE;
3047 }
3048
3049 /* Prepare for the extend/shift. */
3050 if (print_extend_p)
3051 {
3052 if (print_amount_p)
ad43e107 3053 snprintf (tb, sizeof (tb), ", %s #%" PRIi64, shift_name,
1b7e3d2f
NC		 3054 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3055 (opnd->shifter.amount % 100));
a06ea964 3056 else
ad43e107 3057 snprintf (tb, sizeof (tb), ", %s", shift_name);
a06ea964
NC		 3058 }
3059 else
3060 tb[0] = '\0';
3061
ad43e107 3062 snprintf (buf, size, "[%s, %s%s]", base, offset, tb);
a06ea964
NC		 3063}
3064
3065/* Generate the string representation of the operand OPNDS[IDX] for OPCODE
3066 in *BUF. The caller should pass in the maximum size of *BUF in SIZE.
3067 PC, PCREL_P and ADDRESS are used to pass in and return information about
3068 the PC-relative address calculation, where the PC value is passed in
3069 PC. If the operand is pc-relative related, *PCREL_P (if PCREL_P non-NULL)
3070 will return 1 and *ADDRESS (if ADDRESS non-NULL) will return the
3071 calculated address; otherwise, *PCREL_P (if PCREL_P non-NULL) returns 0.
3072
3073 The function serves both the disassembler and the assembler diagnostics
3074 issuer, which is the reason why it lives in this file. */
3075
3076void
3077aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
3078 const aarch64_opcode *opcode,
3079 const aarch64_opnd_info *opnds, int idx, int *pcrel_p,
bde90be2 3080 bfd_vma *address, char** notes)
a06ea964 3081{
bb7eff52 3082 unsigned int i, num_conds;
a06ea964
NC		 3083 const char *name = NULL;
3084 const aarch64_opnd_info *opnd = opnds + idx;
3085 enum aarch64_modifier_kind kind;
245d2e3f 3086 uint64_t addr, enum_value;
a06ea964
NC		 3087
3088 buf[0] = '\0';
3089 if (pcrel_p)
3090 *pcrel_p = 0;
3091
3092 switch (opnd->type)
3093 {
3094 case AARCH64_OPND_Rd:
3095 case AARCH64_OPND_Rn:
3096 case AARCH64_OPND_Rm:
3097 case AARCH64_OPND_Rt:
3098 case AARCH64_OPND_Rt2:
3099 case AARCH64_OPND_Rs:
3100 case AARCH64_OPND_Ra:
3101 case AARCH64_OPND_Rt_SYS:
ee804238 3102 case AARCH64_OPND_PAIRREG:
047cd301 3103 case AARCH64_OPND_SVE_Rm:
a06ea964 3104 /* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
de194d85 3105 the <ic_op>, therefore we use opnd->present to override the
a06ea964 3106 generic optional-ness information. */
362c0c4d
JW		 3107 if (opnd->type == AARCH64_OPND_Rt_SYS)
3108 {
3109 if (!opnd->present)
3110 break;
3111 }
a06ea964 3112 /* Omit the operand, e.g. RET. */
362c0c4d
JW		 3113 else if (optional_operand_p (opcode, idx)
3114 && (opnd->reg.regno
3115 == get_optional_operand_default_value (opcode)))
a06ea964
NC		 3116 break;
3117 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3118 || opnd->qualifier == AARCH64_OPND_QLF_X);
3119 snprintf (buf, size, "%s",
3120 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3121 break;
3122
3123 case AARCH64_OPND_Rd_SP:
3124 case AARCH64_OPND_Rn_SP:
047cd301 3125 case AARCH64_OPND_SVE_Rn_SP:
c84364ec 3126 case AARCH64_OPND_Rm_SP:
a06ea964
NC		 3127 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3128 || opnd->qualifier == AARCH64_OPND_QLF_WSP
3129 || opnd->qualifier == AARCH64_OPND_QLF_X
3130 || opnd->qualifier == AARCH64_OPND_QLF_SP);
3131 snprintf (buf, size, "%s",
3132 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 1));
3133 break;
3134
3135 case AARCH64_OPND_Rm_EXT:
3136 kind = opnd->shifter.kind;
3137 assert (idx == 1 || idx == 2);
3138 if ((aarch64_stack_pointer_p (opnds)
3139 || (idx == 2 && aarch64_stack_pointer_p (opnds + 1)))
3140 && ((opnd->qualifier == AARCH64_OPND_QLF_W
3141 && opnds[0].qualifier == AARCH64_OPND_QLF_W
3142 && kind == AARCH64_MOD_UXTW)
3143 || (opnd->qualifier == AARCH64_OPND_QLF_X
3144 && kind == AARCH64_MOD_UXTX)))
3145 {
3146 /* 'LSL' is the preferred form in this case. */
3147 kind = AARCH64_MOD_LSL;
3148 if (opnd->shifter.amount == 0)
3149 {
3150 /* Shifter omitted. */
3151 snprintf (buf, size, "%s",
3152 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3153 break;
3154 }
3155 }
3156 if (opnd->shifter.amount)
2442d846 3157 snprintf (buf, size, "%s, %s #%" PRIi64,
a06ea964
NC		 3158 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3159 aarch64_operand_modifiers[kind].name,
3160 opnd->shifter.amount);
3161 else
3162 snprintf (buf, size, "%s, %s",
3163 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3164 aarch64_operand_modifiers[kind].name);
3165 break;
3166
3167 case AARCH64_OPND_Rm_SFT:
3168 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3169 || opnd->qualifier == AARCH64_OPND_QLF_X);
3170 if (opnd->shifter.amount == 0 && opnd->shifter.kind == AARCH64_MOD_LSL)
3171 snprintf (buf, size, "%s",
3172 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3173 else
2442d846 3174 snprintf (buf, size, "%s, %s #%" PRIi64,
a06ea964
NC		 3175 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3176 aarch64_operand_modifiers[opnd->shifter.kind].name,
3177 opnd->shifter.amount);
3178 break;
3179
3180 case AARCH64_OPND_Fd:
3181 case AARCH64_OPND_Fn:
3182 case AARCH64_OPND_Fm:
3183 case AARCH64_OPND_Fa:
3184 case AARCH64_OPND_Ft:
3185 case AARCH64_OPND_Ft2:
3186 case AARCH64_OPND_Sd:
3187 case AARCH64_OPND_Sn:
3188 case AARCH64_OPND_Sm:
047cd301
RS		 3189 case AARCH64_OPND_SVE_VZn:
3190 case AARCH64_OPND_SVE_Vd:
3191 case AARCH64_OPND_SVE_Vm:
3192 case AARCH64_OPND_SVE_Vn:
a06ea964
NC		 3193 snprintf (buf, size, "%s%d", aarch64_get_qualifier_name (opnd->qualifier),
3194 opnd->reg.regno);
3195 break;
3196
f42f1a1d 3197 case AARCH64_OPND_Va:
a06ea964
NC		 3198 case AARCH64_OPND_Vd:
3199 case AARCH64_OPND_Vn:
3200 case AARCH64_OPND_Vm:
3201 snprintf (buf, size, "v%d.%s", opnd->reg.regno,
3202 aarch64_get_qualifier_name (opnd->qualifier));
3203 break;
3204
3205 case AARCH64_OPND_Ed:
3206 case AARCH64_OPND_En:
3207 case AARCH64_OPND_Em:
369c9167 3208 case AARCH64_OPND_Em16:
f42f1a1d 3209 case AARCH64_OPND_SM3_IMM2:
dab26bf4 3210 snprintf (buf, size, "v%d.%s[%" PRIi64 "]", opnd->reglane.regno,
a06ea964
NC		 3211 aarch64_get_qualifier_name (opnd->qualifier),
3212 opnd->reglane.index);
3213 break;
3214
3215 case AARCH64_OPND_VdD1:
3216 case AARCH64_OPND_VnD1:
3217 snprintf (buf, size, "v%d.d[1]", opnd->reg.regno);
3218 break;
3219
3220 case AARCH64_OPND_LVn:
3221 case AARCH64_OPND_LVt:
3222 case AARCH64_OPND_LVt_AL:
3223 case AARCH64_OPND_LEt:
8a7f0c1b 3224 print_register_list (buf, size, opnd, "v");
a06ea964
NC		 3225 break;
3226
f11ad6bc
RS		 3227 case AARCH64_OPND_SVE_Pd:
3228 case AARCH64_OPND_SVE_Pg3:
3229 case AARCH64_OPND_SVE_Pg4_5:
3230 case AARCH64_OPND_SVE_Pg4_10:
3231 case AARCH64_OPND_SVE_Pg4_16:
3232 case AARCH64_OPND_SVE_Pm:
3233 case AARCH64_OPND_SVE_Pn:
3234 case AARCH64_OPND_SVE_Pt:
3235 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3236 snprintf (buf, size, "p%d", opnd->reg.regno);
d50c751e
RS		 3237 else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
3238 || opnd->qualifier == AARCH64_OPND_QLF_P_M)
3239 snprintf (buf, size, "p%d/%s", opnd->reg.regno,
3240 aarch64_get_qualifier_name (opnd->qualifier));
f11ad6bc
RS		 3241 else
3242 snprintf (buf, size, "p%d.%s", opnd->reg.regno,
3243 aarch64_get_qualifier_name (opnd->qualifier));
3244 break;
3245
3246 case AARCH64_OPND_SVE_Za_5:
3247 case AARCH64_OPND_SVE_Za_16:
3248 case AARCH64_OPND_SVE_Zd:
3249 case AARCH64_OPND_SVE_Zm_5:
3250 case AARCH64_OPND_SVE_Zm_16:
3251 case AARCH64_OPND_SVE_Zn:
3252 case AARCH64_OPND_SVE_Zt:
3253 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3254 snprintf (buf, size, "z%d", opnd->reg.regno);
3255 else
3256 snprintf (buf, size, "z%d.%s", opnd->reg.regno,
3257 aarch64_get_qualifier_name (opnd->qualifier));
3258 break;
3259
3260 case AARCH64_OPND_SVE_ZnxN:
3261 case AARCH64_OPND_SVE_ZtxN:
3262 print_register_list (buf, size, opnd, "z");
3263 break;
3264
582e12bf
RS		 3265 case AARCH64_OPND_SVE_Zm3_INDEX:
3266 case AARCH64_OPND_SVE_Zm3_22_INDEX:
3267 case AARCH64_OPND_SVE_Zm4_INDEX:
f11ad6bc
RS		 3268 case AARCH64_OPND_SVE_Zn_INDEX:
3269 snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
3270 aarch64_get_qualifier_name (opnd->qualifier),
3271 opnd->reglane.index);
3272 break;
3273
a6a51754
RL		 3274 case AARCH64_OPND_CRn:
3275 case AARCH64_OPND_CRm:
3276 snprintf (buf, size, "C%" PRIi64, opnd->imm.value);
a06ea964
NC		 3277 break;
3278
3279 case AARCH64_OPND_IDX:
f42f1a1d 3280 case AARCH64_OPND_MASK:
a06ea964 3281 case AARCH64_OPND_IMM:
f42f1a1d 3282 case AARCH64_OPND_IMM_2:
a06ea964
NC		 3283 case AARCH64_OPND_WIDTH:
3284 case AARCH64_OPND_UIMM3_OP1:
3285 case AARCH64_OPND_UIMM3_OP2:
3286 case AARCH64_OPND_BIT_NUM:
3287 case AARCH64_OPND_IMM_VLSL:
3288 case AARCH64_OPND_IMM_VLSR:
3289 case AARCH64_OPND_SHLL_IMM:
3290 case AARCH64_OPND_IMM0:
3291 case AARCH64_OPND_IMMR:
3292 case AARCH64_OPND_IMMS:
3293 case AARCH64_OPND_FBITS:
e950b345
RS		 3294 case AARCH64_OPND_SIMM5:
3295 case AARCH64_OPND_SVE_SHLIMM_PRED:
3296 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
3297 case AARCH64_OPND_SVE_SHRIMM_PRED:
3298 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
3299 case AARCH64_OPND_SVE_SIMM5:
3300 case AARCH64_OPND_SVE_SIMM5B:
3301 case AARCH64_OPND_SVE_SIMM6:
3302 case AARCH64_OPND_SVE_SIMM8:
3303 case AARCH64_OPND_SVE_UIMM3:
3304 case AARCH64_OPND_SVE_UIMM7:
3305 case AARCH64_OPND_SVE_UIMM8:
3306 case AARCH64_OPND_SVE_UIMM8_53:
c2c4ff8d
SN		 3307 case AARCH64_OPND_IMM_ROT1:
3308 case AARCH64_OPND_IMM_ROT2:
3309 case AARCH64_OPND_IMM_ROT3:
582e12bf
RS		 3310 case AARCH64_OPND_SVE_IMM_ROT1:
3311 case AARCH64_OPND_SVE_IMM_ROT2:
a06ea964
NC		 3312 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3313 break;
3314
165d4950
RS		 3315 case AARCH64_OPND_SVE_I1_HALF_ONE:
3316 case AARCH64_OPND_SVE_I1_HALF_TWO:
3317 case AARCH64_OPND_SVE_I1_ZERO_ONE:
3318 {
3319 single_conv_t c;
3320 c.i = opnd->imm.value;
3321 snprintf (buf, size, "#%.1f", c.f);
3322 break;
3323 }
3324
245d2e3f
RS		 3325 case AARCH64_OPND_SVE_PATTERN:
3326 if (optional_operand_p (opcode, idx)
3327 && opnd->imm.value == get_optional_operand_default_value (opcode))
3328 break;
3329 enum_value = opnd->imm.value;
3330 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3331 if (aarch64_sve_pattern_array[enum_value])
3332 snprintf (buf, size, "%s", aarch64_sve_pattern_array[enum_value]);
3333 else
3334 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3335 break;
3336
2442d846
RS		 3337 case AARCH64_OPND_SVE_PATTERN_SCALED:
3338 if (optional_operand_p (opcode, idx)
3339 && !opnd->shifter.operator_present
3340 && opnd->imm.value == get_optional_operand_default_value (opcode))
3341 break;
3342 enum_value = opnd->imm.value;
3343 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3344 if (aarch64_sve_pattern_array[opnd->imm.value])
3345 snprintf (buf, size, "%s", aarch64_sve_pattern_array[opnd->imm.value]);
3346 else
3347 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3348 if (opnd->shifter.operator_present)
3349 {
3350 size_t len = strlen (buf);
3351 snprintf (buf + len, size - len, ", %s #%" PRIi64,
3352 aarch64_operand_modifiers[opnd->shifter.kind].name,
3353 opnd->shifter.amount);
3354 }
3355 break;
3356
245d2e3f
RS		 3357 case AARCH64_OPND_SVE_PRFOP:
3358 enum_value = opnd->imm.value;
3359 assert (enum_value < ARRAY_SIZE (aarch64_sve_prfop_array));
3360 if (aarch64_sve_prfop_array[enum_value])
3361 snprintf (buf, size, "%s", aarch64_sve_prfop_array[enum_value]);
3362 else
3363 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3364 break;
3365
fb098a1e
YZ		 3366 case AARCH64_OPND_IMM_MOV:
3367 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3368 {
3369 case 4: /* e.g. MOV Wd, #<imm32>. */
3370 {
3371 int imm32 = opnd->imm.value;
3372 snprintf (buf, size, "#0x%-20x\t// #%d", imm32, imm32);
3373 }
3374 break;
3375 case 8: /* e.g. MOV Xd, #<imm64>. */
3376 snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64,
3377 opnd->imm.value, opnd->imm.value);
3378 break;
3379 default: assert (0);
3380 }
3381 break;
3382
a06ea964
NC		 3383 case AARCH64_OPND_FPIMM0:
3384 snprintf (buf, size, "#0.0");
3385 break;
3386
3387 case AARCH64_OPND_LIMM:
3388 case AARCH64_OPND_AIMM:
3389 case AARCH64_OPND_HALF:
e950b345
RS		 3390 case AARCH64_OPND_SVE_INV_LIMM:
3391 case AARCH64_OPND_SVE_LIMM:
3392 case AARCH64_OPND_SVE_LIMM_MOV:
a06ea964 3393 if (opnd->shifter.amount)
2442d846 3394 snprintf (buf, size, "#0x%" PRIx64 ", lsl #%" PRIi64, opnd->imm.value,
a06ea964
NC		 3395 opnd->shifter.amount);
3396 else
3397 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3398 break;
3399
3400 case AARCH64_OPND_SIMD_IMM:
3401 case AARCH64_OPND_SIMD_IMM_SFT:
3402 if ((! opnd->shifter.amount && opnd->shifter.kind == AARCH64_MOD_LSL)
3403 || opnd->shifter.kind == AARCH64_MOD_NONE)
3404 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3405 else
2442d846 3406 snprintf (buf, size, "#0x%" PRIx64 ", %s #%" PRIi64, opnd->imm.value,
a06ea964
NC		 3407 aarch64_operand_modifiers[opnd->shifter.kind].name,
3408 opnd->shifter.amount);
3409 break;
3410
e950b345
RS		 3411 case AARCH64_OPND_SVE_AIMM:
3412 case AARCH64_OPND_SVE_ASIMM:
3413 if (opnd->shifter.amount)
3414 snprintf (buf, size, "#%" PRIi64 ", lsl #%" PRIi64, opnd->imm.value,
3415 opnd->shifter.amount);
3416 else
3417 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3418 break;
3419
a06ea964
NC		 3420 case AARCH64_OPND_FPIMM:
3421 case AARCH64_OPND_SIMD_FPIMM:
165d4950 3422 case AARCH64_OPND_SVE_FPIMM8:
a06ea964
NC		 3423 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3424 {
cf86120b
MW		 3425 case 2: /* e.g. FMOV <Hd>, #<imm>. */
3426 {
3427 half_conv_t c;
3428 c.i = expand_fp_imm (2, opnd->imm.value);
3429 snprintf (buf, size, "#%.18e", c.f);
3430 }
3431 break;
a06ea964
NC		 3432 case 4: /* e.g. FMOV <Vd>.4S, #<imm>. */
3433 {
3434 single_conv_t c;
cf86120b 3435 c.i = expand_fp_imm (4, opnd->imm.value);
a06ea964
NC		 3436 snprintf (buf, size, "#%.18e", c.f);
3437 }
3438 break;
3439 case 8: /* e.g. FMOV <Sd>, #<imm>. */
3440 {
3441 double_conv_t c;
cf86120b 3442 c.i = expand_fp_imm (8, opnd->imm.value);
a06ea964
NC		 3443 snprintf (buf, size, "#%.18e", c.d);
3444 }
3445 break;
3446 default: assert (0);
3447 }
3448 break;
3449
3450 case AARCH64_OPND_CCMP_IMM:
3451 case AARCH64_OPND_NZCV:
3452 case AARCH64_OPND_EXCEPTION:
3453 case AARCH64_OPND_UIMM4:
193614f2 3454 case AARCH64_OPND_UIMM4_ADDG:
a06ea964 3455 case AARCH64_OPND_UIMM7:
193614f2 3456 case AARCH64_OPND_UIMM10:
a06ea964
NC		 3457 if (optional_operand_p (opcode, idx) == TRUE
3458 && (opnd->imm.value ==
3459 (int64_t) get_optional_operand_default_value (opcode)))
3460 /* Omit the operand, e.g. DCPS1. */
3461 break;
3462 snprintf (buf, size, "#0x%x", (unsigned int)opnd->imm.value);
3463 break;
3464
3465 case AARCH64_OPND_COND:
68a64283 3466 case AARCH64_OPND_COND1:
a06ea964 3467 snprintf (buf, size, "%s", opnd->cond->names[0]);
bb7eff52
RS		 3468 num_conds = ARRAY_SIZE (opnd->cond->names);
3469 for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
3470 {
3471 size_t len = strlen (buf);
3472 if (i == 1)
3473 snprintf (buf + len, size - len, " // %s = %s",
3474 opnd->cond->names[0], opnd->cond->names[i]);
3475 else
3476 snprintf (buf + len, size - len, ", %s",
3477 opnd->cond->names[i]);
3478 }
a06ea964
NC		 3479 break;
3480
3481 case AARCH64_OPND_ADDR_ADRP:
3482 addr = ((pc + AARCH64_PCREL_OFFSET) & ~(uint64_t)0xfff)
3483 + opnd->imm.value;
3484 if (pcrel_p)
3485 *pcrel_p = 1;
3486 if (address)
3487 *address = addr;
3488 /* This is not necessary during the disassembling, as print_address_func
3489 in the disassemble_info will take care of the printing. But some
3490 other callers may be still interested in getting the string in *STR,
3491 so here we do snprintf regardless. */
3492 snprintf (buf, size, "#0x%" PRIx64, addr);
3493 break;
3494
3495 case AARCH64_OPND_ADDR_PCREL14:
3496 case AARCH64_OPND_ADDR_PCREL19:
3497 case AARCH64_OPND_ADDR_PCREL21:
3498 case AARCH64_OPND_ADDR_PCREL26:
3499 addr = pc + AARCH64_PCREL_OFFSET + opnd->imm.value;
3500 if (pcrel_p)
3501 *pcrel_p = 1;
3502 if (address)
3503 *address = addr;
3504 /* This is not necessary during the disassembling, as print_address_func
3505 in the disassemble_info will take care of the printing. But some
3506 other callers may be still interested in getting the string in *STR,
3507 so here we do snprintf regardless. */
3508 snprintf (buf, size, "#0x%" PRIx64, addr);
3509 break;
3510
3511 case AARCH64_OPND_ADDR_SIMPLE:
3512 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
3513 case AARCH64_OPND_SIMD_ADDR_POST:
3514 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3515 if (opnd->type == AARCH64_OPND_SIMD_ADDR_POST)
3516 {
3517 if (opnd->addr.offset.is_reg)
3518 snprintf (buf, size, "[%s], x%d", name, opnd->addr.offset.regno);
3519 else
3520 snprintf (buf, size, "[%s], #%d", name, opnd->addr.offset.imm);
3521 }
3522 else
3523 snprintf (buf, size, "[%s]", name);
3524 break;
3525
3526 case AARCH64_OPND_ADDR_REGOFF:
c8d59609 3527 case AARCH64_OPND_SVE_ADDR_R:
4df068de
RS		 3528 case AARCH64_OPND_SVE_ADDR_RR:
3529 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
3530 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
3531 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
3532 case AARCH64_OPND_SVE_ADDR_RX:
3533 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
3534 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
3535 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
01dbfe4c
RS		 3536 print_register_offset_address
3537 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3538 get_offset_int_reg_name (opnd));
a06ea964
NC		 3539 break;
3540
4df068de
RS		 3541 case AARCH64_OPND_SVE_ADDR_RZ:
3542 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
3543 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
3544 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
3545 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
3546 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
3547 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
3548 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
3549 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
3550 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
3551 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
3552 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
3553 print_register_offset_address
3554 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3555 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3556 break;
3557
a06ea964
NC		 3558 case AARCH64_OPND_ADDR_SIMM7:
3559 case AARCH64_OPND_ADDR_SIMM9:
3560 case AARCH64_OPND_ADDR_SIMM9_2:
3f06e550 3561 case AARCH64_OPND_ADDR_SIMM10:
f42f1a1d 3562 case AARCH64_OPND_ADDR_OFFSET:
582e12bf 3563 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
98907a70
RS		 3564 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
3565 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
3566 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
3567 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
3568 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
3569 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
4df068de
RS		 3570 case AARCH64_OPND_SVE_ADDR_RI_U6:
3571 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
3572 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
3573 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
01dbfe4c
RS		 3574 print_immediate_offset_address
3575 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1));
a06ea964
NC		 3576 break;
3577
4df068de
RS		 3578 case AARCH64_OPND_SVE_ADDR_ZI_U5:
3579 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
3580 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
3581 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
3582 print_immediate_offset_address
3583 (buf, size, opnd,
3584 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier));
3585 break;
3586
3587 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
3588 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
3589 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
3590 print_register_offset_address
3591 (buf, size, opnd,
3592 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
3593 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3594 break;
3595
a06ea964
NC		 3596 case AARCH64_OPND_ADDR_UIMM12:
3597 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3598 if (opnd->addr.offset.imm)
ad43e107 3599 snprintf (buf, size, "[%s, #%d]", name, opnd->addr.offset.imm);
a06ea964
NC		 3600 else
3601 snprintf (buf, size, "[%s]", name);
3602 break;
3603
3604 case AARCH64_OPND_SYSREG:
3605 for (i = 0; aarch64_sys_regs[i].name; ++i)
f9830ec1
TC		 3606 {
3607 bfd_boolean exact_match
3608 = (aarch64_sys_regs[i].flags & opnd->sysreg.flags)
3609 == opnd->sysreg.flags;
3610
3611 /* Try and find an exact match, But if that fails, return the first
3612 partial match that was found. */
3613 if (aarch64_sys_regs[i].value == opnd->sysreg.value
3614 && ! aarch64_sys_reg_deprecated_p (&aarch64_sys_regs[i])
3615 && (name == NULL || exact_match))
3616 {
3617 name = aarch64_sys_regs[i].name;
3618 if (exact_match)
3619 {
3620 if (notes)
3621 *notes = NULL;
3622 break;
3623 }
3624
3625 /* If we didn't match exactly, that means the presense of a flag
3626 indicates what we didn't want for this instruction. e.g. If
3627 F_REG_READ is there, that means we were looking for a write
3628 register. See aarch64_ext_sysreg. */
3629 if (aarch64_sys_regs[i].flags & F_REG_WRITE)
bde90be2 3630 *notes = _("reading from a write-only register");
f9830ec1 3631 else if (aarch64_sys_regs[i].flags & F_REG_READ)
bde90be2 3632 *notes = _("writing to a read-only register");
f9830ec1
TC		 3633 }
3634 }
3635
3636 if (name)
3637 snprintf (buf, size, "%s", name);
a06ea964
NC		 3638 else
3639 {
3640 /* Implementation defined system register. */
561a72d4 3641 unsigned int value = opnd->sysreg.value;
a06ea964
NC		 3642 snprintf (buf, size, "s%u_%u_c%u_c%u_%u", (value >> 14) & 0x3,
3643 (value >> 11) & 0x7, (value >> 7) & 0xf, (value >> 3) & 0xf,
3644 value & 0x7);
3645 }
3646 break;
3647
3648 case AARCH64_OPND_PSTATEFIELD:
3649 for (i = 0; aarch64_pstatefields[i].name; ++i)
3650 if (aarch64_pstatefields[i].value == opnd->pstatefield)
3651 break;
3652 assert (aarch64_pstatefields[i].name);
3653 snprintf (buf, size, "%s", aarch64_pstatefields[i].name);
3654 break;
3655
3656 case AARCH64_OPND_SYSREG_AT:
3657 case AARCH64_OPND_SYSREG_DC:
3658 case AARCH64_OPND_SYSREG_IC:
3659 case AARCH64_OPND_SYSREG_TLBI:
2ac435d4 3660 case AARCH64_OPND_SYSREG_SR:
875880c6 3661 snprintf (buf, size, "%s", opnd->sysins_op->name);
a06ea964
NC		 3662 break;
3663
3664 case AARCH64_OPND_BARRIER:
3665 snprintf (buf, size, "%s", opnd->barrier->name);
3666 break;
3667
3668 case AARCH64_OPND_BARRIER_ISB:
3669 /* Operand can be omitted, e.g. in DCPS1. */
3670 if (! optional_operand_p (opcode, idx)
3671 || (opnd->barrier->value
3672 != get_optional_operand_default_value (opcode)))
3673 snprintf (buf, size, "#0x%x", opnd->barrier->value);
3674 break;
3675
3676 case AARCH64_OPND_PRFOP:
a1ccaec9
YZ		 3677 if (opnd->prfop->name != NULL)
3678 snprintf (buf, size, "%s", opnd->prfop->name);
3679 else
3680 snprintf (buf, size, "#0x%02x", opnd->prfop->value);
a06ea964
NC		 3681 break;
3682
1e6f4800 3683 case AARCH64_OPND_BARRIER_PSB:
ff605452
SD		 3684 case AARCH64_OPND_BTI_TARGET:
3685 if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0)
3686 snprintf (buf, size, "%s", opnd->hint_option->name);
1e6f4800
MW		 3687 break;
3688
a06ea964
NC		 3689 default:
3690 assert (0);
3691 }
3692}
3693\f
3694#define CPENC(op0,op1,crn,crm,op2) \
3695 ((((op0) << 19) | ((op1) << 16) | ((crn) << 12) | ((crm) << 8) | ((op2) << 5)) >> 5)
3696 /* for 3.9.3 Instructions for Accessing Special Purpose Registers */
3697#define CPEN_(op1,crm,op2) CPENC(3,(op1),4,(crm),(op2))
3698 /* for 3.9.10 System Instructions */
3699#define CPENS(op1,crn,crm,op2) CPENC(1,(op1),(crn),(crm),(op2))
3700
3701#define C0 0
3702#define C1 1
3703#define C2 2
3704#define C3 3
3705#define C4 4
3706#define C5 5
3707#define C6 6
3708#define C7 7
3709#define C8 8
3710#define C9 9
3711#define C10 10
3712#define C11 11
3713#define C12 12
3714#define C13 13
3715#define C14 14
3716#define C15 15
3717
f9830ec1
TC		 3718/* TODO there is one more issues need to be resolved
3719 1. handle cpu-implementation-defined system registers. */
49eec193
YZ		 3720const aarch64_sys_reg aarch64_sys_regs [] =
3721{
3722 { "spsr_el1", CPEN_(0,C0,0), 0 }, /* = spsr_svc */
250aafa4 3723 { "spsr_el12", CPEN_ (5, C0, 0), F_ARCHEXT },
49eec193 3724 { "elr_el1", CPEN_(0,C0,1), 0 },
250aafa4 3725 { "elr_el12", CPEN_ (5, C0, 1), F_ARCHEXT },
49eec193
YZ		 3726 { "sp_el0", CPEN_(0,C1,0), 0 },
3727 { "spsel", CPEN_(0,C2,0), 0 },
3728 { "daif", CPEN_(3,C2,1), 0 },
f9830ec1 3729 { "currentel", CPEN_(0,C2,2), F_REG_READ }, /* RO */
f21cce2c 3730 { "pan", CPEN_(0,C2,3), F_ARCHEXT },
6479e48e 3731 { "uao", CPEN_ (0, C2, 4), F_ARCHEXT },
49eec193 3732 { "nzcv", CPEN_(3,C2,0), 0 },
104fefee 3733 { "ssbs", CPEN_(3,C2,6), F_ARCHEXT },
49eec193
YZ		 3734 { "fpcr", CPEN_(3,C4,0), 0 },
3735 { "fpsr", CPEN_(3,C4,1), 0 },
3736 { "dspsr_el0", CPEN_(3,C5,0), 0 },
3737 { "dlr_el0", CPEN_(3,C5,1), 0 },
3738 { "spsr_el2", CPEN_(4,C0,0), 0 }, /* = spsr_hyp */
3739 { "elr_el2", CPEN_(4,C0,1), 0 },
3740 { "sp_el1", CPEN_(4,C1,0), 0 },
3741 { "spsr_irq", CPEN_(4,C3,0), 0 },
3742 { "spsr_abt", CPEN_(4,C3,1), 0 },
3743 { "spsr_und", CPEN_(4,C3,2), 0 },
3744 { "spsr_fiq", CPEN_(4,C3,3), 0 },
3745 { "spsr_el3", CPEN_(6,C0,0), 0 },
3746 { "elr_el3", CPEN_(6,C0,1), 0 },
3747 { "sp_el2", CPEN_(6,C1,0), 0 },
3748 { "spsr_svc", CPEN_(0,C0,0), F_DEPRECATED }, /* = spsr_el1 */
3749 { "spsr_hyp", CPEN_(4,C0,0), F_DEPRECATED }, /* = spsr_el2 */
f9830ec1
TC		 3750 { "midr_el1", CPENC(3,0,C0,C0,0), F_REG_READ }, /* RO */
3751 { "ctr_el0", CPENC(3,3,C0,C0,1), F_REG_READ }, /* RO */
3752 { "mpidr_el1", CPENC(3,0,C0,C0,5), F_REG_READ }, /* RO */
3753 { "revidr_el1", CPENC(3,0,C0,C0,6), F_REG_READ }, /* RO */
3754 { "aidr_el1", CPENC(3,1,C0,C0,7), F_REG_READ }, /* RO */
3755 { "dczid_el0", CPENC(3,3,C0,C0,7), F_REG_READ }, /* RO */
3756 { "id_dfr0_el1", CPENC(3,0,C0,C1,2), F_REG_READ }, /* RO */
3757 { "id_pfr0_el1", CPENC(3,0,C0,C1,0), F_REG_READ }, /* RO */
3758 { "id_pfr1_el1", CPENC(3,0,C0,C1,1), F_REG_READ }, /* RO */
a97330e7 3759 { "id_pfr2_el1", CPENC(3,0,C0,C3,4), F_ARCHEXT | F_REG_READ}, /* RO */
f9830ec1
TC		 3760 { "id_afr0_el1", CPENC(3,0,C0,C1,3), F_REG_READ }, /* RO */
3761 { "id_mmfr0_el1", CPENC(3,0,C0,C1,4), F_REG_READ }, /* RO */
3762 { "id_mmfr1_el1", CPENC(3,0,C0,C1,5), F_REG_READ }, /* RO */
3763 { "id_mmfr2_el1", CPENC(3,0,C0,C1,6), F_REG_READ }, /* RO */
3764 { "id_mmfr3_el1", CPENC(3,0,C0,C1,7), F_REG_READ }, /* RO */
3765 { "id_mmfr4_el1", CPENC(3,0,C0,C2,6), F_REG_READ }, /* RO */
3766 { "id_isar0_el1", CPENC(3,0,C0,C2,0), F_REG_READ }, /* RO */
3767 { "id_isar1_el1", CPENC(3,0,C0,C2,1), F_REG_READ }, /* RO */
3768 { "id_isar2_el1", CPENC(3,0,C0,C2,2), F_REG_READ }, /* RO */
3769 { "id_isar3_el1", CPENC(3,0,C0,C2,3), F_REG_READ }, /* RO */
3770 { "id_isar4_el1", CPENC(3,0,C0,C2,4), F_REG_READ }, /* RO */
3771 { "id_isar5_el1", CPENC(3,0,C0,C2,5), F_REG_READ }, /* RO */
3772 { "mvfr0_el1", CPENC(3,0,C0,C3,0), F_REG_READ }, /* RO */
3773 { "mvfr1_el1", CPENC(3,0,C0,C3,1), F_REG_READ }, /* RO */
3774 { "mvfr2_el1", CPENC(3,0,C0,C3,2), F_REG_READ }, /* RO */
3775 { "ccsidr_el1", CPENC(3,1,C0,C0,0), F_REG_READ }, /* RO */
3776 { "id_aa64pfr0_el1", CPENC(3,0,C0,C4,0), F_REG_READ }, /* RO */
3777 { "id_aa64pfr1_el1", CPENC(3,0,C0,C4,1), F_REG_READ }, /* RO */
3778 { "id_aa64dfr0_el1", CPENC(3,0,C0,C5,0), F_REG_READ }, /* RO */
3779 { "id_aa64dfr1_el1", CPENC(3,0,C0,C5,1), F_REG_READ }, /* RO */
3780 { "id_aa64isar0_el1", CPENC(3,0,C0,C6,0), F_REG_READ }, /* RO */
3781 { "id_aa64isar1_el1", CPENC(3,0,C0,C6,1), F_REG_READ }, /* RO */
3782 { "id_aa64mmfr0_el1", CPENC(3,0,C0,C7,0), F_REG_READ }, /* RO */
3783 { "id_aa64mmfr1_el1", CPENC(3,0,C0,C7,1), F_REG_READ }, /* RO */
3784 { "id_aa64mmfr2_el1", CPENC (3, 0, C0, C7, 2), F_ARCHEXT | F_REG_READ }, /* RO */
3785 { "id_aa64afr0_el1", CPENC(3,0,C0,C5,4), F_REG_READ }, /* RO */
3786 { "id_aa64afr1_el1", CPENC(3,0,C0,C5,5), F_REG_READ }, /* RO */
3787 { "id_aa64zfr0_el1", CPENC (3, 0, C0, C4, 4), F_ARCHEXT | F_REG_READ }, /* RO */
3788 { "clidr_el1", CPENC(3,1,C0,C0,1), F_REG_READ }, /* RO */
cba05feb 3789 { "csselr_el1", CPENC(3,2,C0,C0,0), 0 },
49eec193
YZ		 3790 { "vpidr_el2", CPENC(3,4,C0,C0,0), 0 },
3791 { "vmpidr_el2", CPENC(3,4,C0,C0,5), 0 },
3792 { "sctlr_el1", CPENC(3,0,C1,C0,0), 0 },
3793 { "sctlr_el2", CPENC(3,4,C1,C0,0), 0 },
3794 { "sctlr_el3", CPENC(3,6,C1,C0,0), 0 },
250aafa4 3795 { "sctlr_el12", CPENC (3, 5, C1, C0, 0), F_ARCHEXT },
49eec193
YZ		 3796 { "actlr_el1", CPENC(3,0,C1,C0,1), 0 },
3797 { "actlr_el2", CPENC(3,4,C1,C0,1), 0 },
3798 { "actlr_el3", CPENC(3,6,C1,C0,1), 0 },
3799 { "cpacr_el1", CPENC(3,0,C1,C0,2), 0 },
250aafa4 3800 { "cpacr_el12", CPENC (3, 5, C1, C0, 2), F_ARCHEXT },
49eec193
YZ		 3801 { "cptr_el2", CPENC(3,4,C1,C1,2), 0 },
3802 { "cptr_el3", CPENC(3,6,C1,C1,2), 0 },
3803 { "scr_el3", CPENC(3,6,C1,C1,0), 0 },
3804 { "hcr_el2", CPENC(3,4,C1,C1,0), 0 },
3805 { "mdcr_el2", CPENC(3,4,C1,C1,1), 0 },
3806 { "mdcr_el3", CPENC(3,6,C1,C3,1), 0 },
3807 { "hstr_el2", CPENC(3,4,C1,C1,3), 0 },
3808 { "hacr_el2", CPENC(3,4,C1,C1,7), 0 },
773fb663
RS		 3809 { "zcr_el1", CPENC (3, 0, C1, C2, 0), F_ARCHEXT },
3810 { "zcr_el12", CPENC (3, 5, C1, C2, 0), F_ARCHEXT },
3811 { "zcr_el2", CPENC (3, 4, C1, C2, 0), F_ARCHEXT },
3812 { "zcr_el3", CPENC (3, 6, C1, C2, 0), F_ARCHEXT },
3813 { "zidr_el1", CPENC (3, 0, C0, C0, 7), F_ARCHEXT },
49eec193
YZ		 3814 { "ttbr0_el1", CPENC(3,0,C2,C0,0), 0 },
3815 { "ttbr1_el1", CPENC(3,0,C2,C0,1), 0 },
3816 { "ttbr0_el2", CPENC(3,4,C2,C0,0), 0 },
250aafa4 3817 { "ttbr1_el2", CPENC (3, 4, C2, C0, 1), F_ARCHEXT },
49eec193 3818 { "ttbr0_el3", CPENC(3,6,C2,C0,0), 0 },
250aafa4
MW		 3819 { "ttbr0_el12", CPENC (3, 5, C2, C0, 0), F_ARCHEXT },
3820 { "ttbr1_el12", CPENC (3, 5, C2, C0, 1), F_ARCHEXT },
49eec193
YZ		 3821 { "vttbr_el2", CPENC(3,4,C2,C1,0), 0 },
3822 { "tcr_el1", CPENC(3,0,C2,C0,2), 0 },
3823 { "tcr_el2", CPENC(3,4,C2,C0,2), 0 },
3824 { "tcr_el3", CPENC(3,6,C2,C0,2), 0 },
250aafa4 3825 { "tcr_el12", CPENC (3, 5, C2, C0, 2), F_ARCHEXT },
49eec193 3826 { "vtcr_el2", CPENC(3,4,C2,C1,2), 0 },
b0bfa7b5
SN		 3827 { "apiakeylo_el1", CPENC (3, 0, C2, C1, 0), F_ARCHEXT },
3828 { "apiakeyhi_el1", CPENC (3, 0, C2, C1, 1), F_ARCHEXT },
3829 { "apibkeylo_el1", CPENC (3, 0, C2, C1, 2), F_ARCHEXT },
3830 { "apibkeyhi_el1", CPENC (3, 0, C2, C1, 3), F_ARCHEXT },
3831 { "apdakeylo_el1", CPENC (3, 0, C2, C2, 0), F_ARCHEXT },
3832 { "apdakeyhi_el1", CPENC (3, 0, C2, C2, 1), F_ARCHEXT },
3833 { "apdbkeylo_el1", CPENC (3, 0, C2, C2, 2), F_ARCHEXT },
3834 { "apdbkeyhi_el1", CPENC (3, 0, C2, C2, 3), F_ARCHEXT },
3835 { "apgakeylo_el1", CPENC (3, 0, C2, C3, 0), F_ARCHEXT },
3836 { "apgakeyhi_el1", CPENC (3, 0, C2, C3, 1), F_ARCHEXT },
49eec193
YZ		 3837 { "afsr0_el1", CPENC(3,0,C5,C1,0), 0 },
3838 { "afsr1_el1", CPENC(3,0,C5,C1,1), 0 },
3839 { "afsr0_el2", CPENC(3,4,C5,C1,0), 0 },
3840 { "afsr1_el2", CPENC(3,4,C5,C1,1), 0 },
3841 { "afsr0_el3", CPENC(3,6,C5,C1,0), 0 },
250aafa4 3842 { "afsr0_el12", CPENC (3, 5, C5, C1, 0), F_ARCHEXT },
49eec193 3843 { "afsr1_el3", CPENC(3,6,C5,C1,1), 0 },
250aafa4 3844 { "afsr1_el12", CPENC (3, 5, C5, C1, 1), F_ARCHEXT },
49eec193
YZ		 3845 { "esr_el1", CPENC(3,0,C5,C2,0), 0 },
3846 { "esr_el2", CPENC(3,4,C5,C2,0), 0 },
3847 { "esr_el3", CPENC(3,6,C5,C2,0), 0 },
250aafa4 3848 { "esr_el12", CPENC (3, 5, C5, C2, 0), F_ARCHEXT },
cba05feb 3849 { "vsesr_el2", CPENC (3, 4, C5, C2, 3), F_ARCHEXT },
49eec193 3850 { "fpexc32_el2", CPENC(3,4,C5,C3,0), 0 },
f9830ec1 3851 { "erridr_el1", CPENC (3, 0, C5, C3, 0), F_ARCHEXT | F_REG_READ }, /* RO */
47f81142 3852 { "errselr_el1", CPENC (3, 0, C5, C3, 1), F_ARCHEXT },
f9830ec1 3853 { "erxfr_el1", CPENC (3, 0, C5, C4, 0), F_ARCHEXT | F_REG_READ }, /* RO */
47f81142
MW		 3854 { "erxctlr_el1", CPENC (3, 0, C5, C4, 1), F_ARCHEXT },
3855 { "erxstatus_el1", CPENC (3, 0, C5, C4, 2), F_ARCHEXT },
3856 { "erxaddr_el1", CPENC (3, 0, C5, C4, 3), F_ARCHEXT },
3857 { "erxmisc0_el1", CPENC (3, 0, C5, C5, 0), F_ARCHEXT },
3858 { "erxmisc1_el1", CPENC (3, 0, C5, C5, 1), F_ARCHEXT },
49eec193
YZ		 3859 { "far_el1", CPENC(3,0,C6,C0,0), 0 },
3860 { "far_el2", CPENC(3,4,C6,C0,0), 0 },
3861 { "far_el3", CPENC(3,6,C6,C0,0), 0 },
250aafa4 3862 { "far_el12", CPENC (3, 5, C6, C0, 0), F_ARCHEXT },
49eec193
YZ		 3863 { "hpfar_el2", CPENC(3,4,C6,C0,4), 0 },
3864 { "par_el1", CPENC(3,0,C7,C4,0), 0 },
3865 { "mair_el1", CPENC(3,0,C10,C2,0), 0 },
3866 { "mair_el2", CPENC(3,4,C10,C2,0), 0 },
3867 { "mair_el3", CPENC(3,6,C10,C2,0), 0 },
250aafa4 3868 { "mair_el12", CPENC (3, 5, C10, C2, 0), F_ARCHEXT },
49eec193
YZ		 3869 { "amair_el1", CPENC(3,0,C10,C3,0), 0 },
3870 { "amair_el2", CPENC(3,4,C10,C3,0), 0 },
3871 { "amair_el3", CPENC(3,6,C10,C3,0), 0 },
250aafa4 3872 { "amair_el12", CPENC (3, 5, C10, C3, 0), F_ARCHEXT },
49eec193
YZ		 3873 { "vbar_el1", CPENC(3,0,C12,C0,0), 0 },
3874 { "vbar_el2", CPENC(3,4,C12,C0,0), 0 },
3875 { "vbar_el3", CPENC(3,6,C12,C0,0), 0 },
250aafa4 3876 { "vbar_el12", CPENC (3, 5, C12, C0, 0), F_ARCHEXT },
f9830ec1
TC		 3877 { "rvbar_el1", CPENC(3,0,C12,C0,1), F_REG_READ }, /* RO */
3878 { "rvbar_el2", CPENC(3,4,C12,C0,1), F_REG_READ }, /* RO */
3879 { "rvbar_el3", CPENC(3,6,C12,C0,1), F_REG_READ }, /* RO */
49eec193
YZ		 3880 { "rmr_el1", CPENC(3,0,C12,C0,2), 0 },
3881 { "rmr_el2", CPENC(3,4,C12,C0,2), 0 },
3882 { "rmr_el3", CPENC(3,6,C12,C0,2), 0 },
f9830ec1 3883 { "isr_el1", CPENC(3,0,C12,C1,0), F_REG_READ }, /* RO */
47f81142
MW		 3884 { "disr_el1", CPENC (3, 0, C12, C1, 1), F_ARCHEXT },
3885 { "vdisr_el2", CPENC (3, 4, C12, C1, 1), F_ARCHEXT },
49eec193 3886 { "contextidr_el1", CPENC(3,0,C13,C0,1), 0 },
250aafa4
MW		 3887 { "contextidr_el2", CPENC (3, 4, C13, C0, 1), F_ARCHEXT },
3888 { "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
af4bcb4c
SD		 3889 { "rndr", CPENC(3,3,C2,C4,0), F_ARCHEXT | F_REG_READ }, /* RO */
3890 { "rndrrs", CPENC(3,3,C2,C4,1), F_ARCHEXT | F_REG_READ }, /* RO */
49eec193 3891 { "tpidr_el0", CPENC(3,3,C13,C0,2), 0 },
f9830ec1 3892 { "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RW */
49eec193
YZ		 3893 { "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
3894 { "tpidr_el2", CPENC(3,4,C13,C0,2), 0 },
3895 { "tpidr_el3", CPENC(3,6,C13,C0,2), 0 },
a97330e7
SD		 3896 { "scxtnum_el0", CPENC(3,3,C13,C0,7), F_ARCHEXT },
3897 { "scxtnum_el1", CPENC(3,0,C13,C0,7), F_ARCHEXT },
3898 { "scxtnum_el2", CPENC(3,4,C13,C0,7), F_ARCHEXT },
3899 { "scxtnum_el12", CPENC(3,5,C13,C0,7), F_ARCHEXT },
3900 { "scxtnum_el3", CPENC(3,6,C13,C0,7), F_ARCHEXT },
49eec193 3901 { "teecr32_el1", CPENC(2,2,C0, C0,0), 0 }, /* See section 3.9.7.1 */
f9830ec1
TC		 3902 { "cntfrq_el0", CPENC(3,3,C14,C0,0), 0 }, /* RW */
3903 { "cntpct_el0", CPENC(3,3,C14,C0,1), F_REG_READ }, /* RO */
3904 { "cntvct_el0", CPENC(3,3,C14,C0,2), F_REG_READ }, /* RO */
49eec193
YZ		 3905 { "cntvoff_el2", CPENC(3,4,C14,C0,3), 0 },
3906 { "cntkctl_el1", CPENC(3,0,C14,C1,0), 0 },
250aafa4 3907 { "cntkctl_el12", CPENC (3, 5, C14, C1, 0), F_ARCHEXT },
49eec193
YZ		 3908 { "cnthctl_el2", CPENC(3,4,C14,C1,0), 0 },
3909 { "cntp_tval_el0", CPENC(3,3,C14,C2,0), 0 },
250aafa4 3910 { "cntp_tval_el02", CPENC (3, 5, C14, C2, 0), F_ARCHEXT },
49eec193 3911 { "cntp_ctl_el0", CPENC(3,3,C14,C2,1), 0 },
250aafa4 3912 { "cntp_ctl_el02", CPENC (3, 5, C14, C2, 1), F_ARCHEXT },
49eec193 3913 { "cntp_cval_el0", CPENC(3,3,C14,C2,2), 0 },
250aafa4 3914 { "cntp_cval_el02", CPENC (3, 5, C14, C2, 2), F_ARCHEXT },
49eec193 3915 { "cntv_tval_el0", CPENC(3,3,C14,C3,0), 0 },
250aafa4 3916 { "cntv_tval_el02", CPENC (3, 5, C14, C3, 0), F_ARCHEXT },
49eec193 3917 { "cntv_ctl_el0", CPENC(3,3,C14,C3,1), 0 },
250aafa4 3918 { "cntv_ctl_el02", CPENC (3, 5, C14, C3, 1), F_ARCHEXT },
49eec193 3919 { "cntv_cval_el0", CPENC(3,3,C14,C3,2), 0 },
250aafa4 3920 { "cntv_cval_el02", CPENC (3, 5, C14, C3, 2), F_ARCHEXT },
49eec193
YZ		 3921 { "cnthp_tval_el2", CPENC(3,4,C14,C2,0), 0 },
3922 { "cnthp_ctl_el2", CPENC(3,4,C14,C2,1), 0 },
3923 { "cnthp_cval_el2", CPENC(3,4,C14,C2,2), 0 },
3924 { "cntps_tval_el1", CPENC(3,7,C14,C2,0), 0 },
3925 { "cntps_ctl_el1", CPENC(3,7,C14,C2,1), 0 },
3926 { "cntps_cval_el1", CPENC(3,7,C14,C2,2), 0 },
250aafa4
MW		 3927 { "cnthv_tval_el2", CPENC (3, 4, C14, C3, 0), F_ARCHEXT },
3928 { "cnthv_ctl_el2", CPENC (3, 4, C14, C3, 1), F_ARCHEXT },
3929 { "cnthv_cval_el2", CPENC (3, 4, C14, C3, 2), F_ARCHEXT },
49eec193
YZ		 3930 { "dacr32_el2", CPENC(3,4,C3,C0,0), 0 },
3931 { "ifsr32_el2", CPENC(3,4,C5,C0,1), 0 },
3932 { "teehbr32_el1", CPENC(2,2,C1,C0,0), 0 },
3933 { "sder32_el3", CPENC(3,6,C1,C1,1), 0 },
3934 { "mdscr_el1", CPENC(2,0,C0, C2, 2), 0 },
f9830ec1 3935 { "mdccsr_el0", CPENC(2,3,C0, C1, 0), F_REG_READ }, /* r */
49eec193
YZ		 3936 { "mdccint_el1", CPENC(2,0,C0, C2, 0), 0 },
3937 { "dbgdtr_el0", CPENC(2,3,C0, C4, 0), 0 },
f9830ec1
TC		 3938 { "dbgdtrrx_el0", CPENC(2,3,C0, C5, 0), F_REG_READ }, /* r */
3939 { "dbgdtrtx_el0", CPENC(2,3,C0, C5, 0), F_REG_WRITE }, /* w */
cba05feb
TC		 3940 { "osdtrrx_el1", CPENC(2,0,C0, C0, 2), 0 },
3941 { "osdtrtx_el1", CPENC(2,0,C0, C3, 2), 0 },
49eec193
YZ		 3942 { "oseccr_el1", CPENC(2,0,C0, C6, 2), 0 },
3943 { "dbgvcr32_el2", CPENC(2,4,C0, C7, 0), 0 },
3944 { "dbgbvr0_el1", CPENC(2,0,C0, C0, 4), 0 },
3945 { "dbgbvr1_el1", CPENC(2,0,C0, C1, 4), 0 },
3946 { "dbgbvr2_el1", CPENC(2,0,C0, C2, 4), 0 },
3947 { "dbgbvr3_el1", CPENC(2,0,C0, C3, 4), 0 },
3948 { "dbgbvr4_el1", CPENC(2,0,C0, C4, 4), 0 },
3949 { "dbgbvr5_el1", CPENC(2,0,C0, C5, 4), 0 },
3950 { "dbgbvr6_el1", CPENC(2,0,C0, C6, 4), 0 },
3951 { "dbgbvr7_el1", CPENC(2,0,C0, C7, 4), 0 },
3952 { "dbgbvr8_el1", CPENC(2,0,C0, C8, 4), 0 },
3953 { "dbgbvr9_el1", CPENC(2,0,C0, C9, 4), 0 },
3954 { "dbgbvr10_el1", CPENC(2,0,C0, C10,4), 0 },
3955 { "dbgbvr11_el1", CPENC(2,0,C0, C11,4), 0 },
3956 { "dbgbvr12_el1", CPENC(2,0,C0, C12,4), 0 },
3957 { "dbgbvr13_el1", CPENC(2,0,C0, C13,4), 0 },
3958 { "dbgbvr14_el1", CPENC(2,0,C0, C14,4), 0 },
3959 { "dbgbvr15_el1", CPENC(2,0,C0, C15,4), 0 },
3960 { "dbgbcr0_el1", CPENC(2,0,C0, C0, 5), 0 },
3961 { "dbgbcr1_el1", CPENC(2,0,C0, C1, 5), 0 },
3962 { "dbgbcr2_el1", CPENC(2,0,C0, C2, 5), 0 },
3963 { "dbgbcr3_el1", CPENC(2,0,C0, C3, 5), 0 },
3964 { "dbgbcr4_el1", CPENC(2,0,C0, C4, 5), 0 },
3965 { "dbgbcr5_el1", CPENC(2,0,C0, C5, 5), 0 },
3966 { "dbgbcr6_el1", CPENC(2,0,C0, C6, 5), 0 },
3967 { "dbgbcr7_el1", CPENC(2,0,C0, C7, 5), 0 },
3968 { "dbgbcr8_el1", CPENC(2,0,C0, C8, 5), 0 },
3969 { "dbgbcr9_el1", CPENC(2,0,C0, C9, 5), 0 },
3970 { "dbgbcr10_el1", CPENC(2,0,C0, C10,5), 0 },
3971 { "dbgbcr11_el1", CPENC(2,0,C0, C11,5), 0 },
3972 { "dbgbcr12_el1", CPENC(2,0,C0, C12,5), 0 },
3973 { "dbgbcr13_el1", CPENC(2,0,C0, C13,5), 0 },
3974 { "dbgbcr14_el1", CPENC(2,0,C0, C14,5), 0 },
3975 { "dbgbcr15_el1", CPENC(2,0,C0, C15,5), 0 },
3976 { "dbgwvr0_el1", CPENC(2,0,C0, C0, 6), 0 },
3977 { "dbgwvr1_el1", CPENC(2,0,C0, C1, 6), 0 },
3978 { "dbgwvr2_el1", CPENC(2,0,C0, C2, 6), 0 },
3979 { "dbgwvr3_el1", CPENC(2,0,C0, C3, 6), 0 },
3980 { "dbgwvr4_el1", CPENC(2,0,C0, C4, 6), 0 },
3981 { "dbgwvr5_el1", CPENC(2,0,C0, C5, 6), 0 },
3982 { "dbgwvr6_el1", CPENC(2,0,C0, C6, 6), 0 },
3983 { "dbgwvr7_el1", CPENC(2,0,C0, C7, 6), 0 },
3984 { "dbgwvr8_el1", CPENC(2,0,C0, C8, 6), 0 },
3985 { "dbgwvr9_el1", CPENC(2,0,C0, C9, 6), 0 },
3986 { "dbgwvr10_el1", CPENC(2,0,C0, C10,6), 0 },
3987 { "dbgwvr11_el1", CPENC(2,0,C0, C11,6), 0 },
3988 { "dbgwvr12_el1", CPENC(2,0,C0, C12,6), 0 },
3989 { "dbgwvr13_el1", CPENC(2,0,C0, C13,6), 0 },
3990 { "dbgwvr14_el1", CPENC(2,0,C0, C14,6), 0 },
3991 { "dbgwvr15_el1", CPENC(2,0,C0, C15,6), 0 },
3992 { "dbgwcr0_el1", CPENC(2,0,C0, C0, 7), 0 },
3993 { "dbgwcr1_el1", CPENC(2,0,C0, C1, 7), 0 },
3994 { "dbgwcr2_el1", CPENC(2,0,C0, C2, 7), 0 },
3995 { "dbgwcr3_el1", CPENC(2,0,C0, C3, 7), 0 },
3996 { "dbgwcr4_el1", CPENC(2,0,C0, C4, 7), 0 },
3997 { "dbgwcr5_el1", CPENC(2,0,C0, C5, 7), 0 },
3998 { "dbgwcr6_el1", CPENC(2,0,C0, C6, 7), 0 },
3999 { "dbgwcr7_el1", CPENC(2,0,C0, C7, 7), 0 },
4000 { "dbgwcr8_el1", CPENC(2,0,C0, C8, 7), 0 },
4001 { "dbgwcr9_el1", CPENC(2,0,C0, C9, 7), 0 },
4002 { "dbgwcr10_el1", CPENC(2,0,C0, C10,7), 0 },
4003 { "dbgwcr11_el1", CPENC(2,0,C0, C11,7), 0 },
4004 { "dbgwcr12_el1", CPENC(2,0,C0, C12,7), 0 },
4005 { "dbgwcr13_el1", CPENC(2,0,C0, C13,7), 0 },
4006 { "dbgwcr14_el1", CPENC(2,0,C0, C14,7), 0 },
4007 { "dbgwcr15_el1", CPENC(2,0,C0, C15,7), 0 },
f9830ec1
TC		 4008 { "mdrar_el1", CPENC(2,0,C1, C0, 0), F_REG_READ }, /* r */
4009 { "oslar_el1", CPENC(2,0,C1, C0, 4), F_REG_WRITE }, /* w */
4010 { "oslsr_el1", CPENC(2,0,C1, C1, 4), F_REG_READ }, /* r */
49eec193
YZ		 4011 { "osdlr_el1", CPENC(2,0,C1, C3, 4), 0 },
4012 { "dbgprcr_el1", CPENC(2,0,C1, C4, 4), 0 },
4013 { "dbgclaimset_el1", CPENC(2,0,C7, C8, 6), 0 },
4014 { "dbgclaimclr_el1", CPENC(2,0,C7, C9, 6), 0 },
f9830ec1 4015 { "dbgauthstatus_el1", CPENC(2,0,C7, C14,6), F_REG_READ }, /* r */
55c144e6
MW		 4016 { "pmblimitr_el1", CPENC (3, 0, C9, C10, 0), F_ARCHEXT }, /* rw */
4017 { "pmbptr_el1", CPENC (3, 0, C9, C10, 1), F_ARCHEXT }, /* rw */
4018 { "pmbsr_el1", CPENC (3, 0, C9, C10, 3), F_ARCHEXT }, /* rw */
f9830ec1 4019 { "pmbidr_el1", CPENC (3, 0, C9, C10, 7), F_ARCHEXT | F_REG_READ }, /* ro */
55c144e6
MW		 4020 { "pmscr_el1", CPENC (3, 0, C9, C9, 0), F_ARCHEXT }, /* rw */
4021 { "pmsicr_el1", CPENC (3, 0, C9, C9, 2), F_ARCHEXT }, /* rw */
4022 { "pmsirr_el1", CPENC (3, 0, C9, C9, 3), F_ARCHEXT }, /* rw */
4023 { "pmsfcr_el1", CPENC (3, 0, C9, C9, 4), F_ARCHEXT }, /* rw */
4024 { "pmsevfr_el1", CPENC (3, 0, C9, C9, 5), F_ARCHEXT }, /* rw */
4025 { "pmslatfr_el1", CPENC (3, 0, C9, C9, 6), F_ARCHEXT }, /* rw */
cba05feb 4026 { "pmsidr_el1", CPENC (3, 0, C9, C9, 7), F_ARCHEXT }, /* rw */
55c144e6
MW		 4027 { "pmscr_el2", CPENC (3, 4, C9, C9, 0), F_ARCHEXT }, /* rw */
4028 { "pmscr_el12", CPENC (3, 5, C9, C9, 0), F_ARCHEXT }, /* rw */
49eec193
YZ		 4029 { "pmcr_el0", CPENC(3,3,C9,C12, 0), 0 },
4030 { "pmcntenset_el0", CPENC(3,3,C9,C12, 1), 0 },
4031 { "pmcntenclr_el0", CPENC(3,3,C9,C12, 2), 0 },
4032 { "pmovsclr_el0", CPENC(3,3,C9,C12, 3), 0 },
f9830ec1 4033 { "pmswinc_el0", CPENC(3,3,C9,C12, 4), F_REG_WRITE }, /* w */
49eec193 4034 { "pmselr_el0", CPENC(3,3,C9,C12, 5), 0 },
f9830ec1
TC		 4035 { "pmceid0_el0", CPENC(3,3,C9,C12, 6), F_REG_READ }, /* r */
4036 { "pmceid1_el0", CPENC(3,3,C9,C12, 7), F_REG_READ }, /* r */
49eec193
YZ		 4037 { "pmccntr_el0", CPENC(3,3,C9,C13, 0), 0 },
4038 { "pmxevtyper_el0", CPENC(3,3,C9,C13, 1), 0 },
4039 { "pmxevcntr_el0", CPENC(3,3,C9,C13, 2), 0 },
4040 { "pmuserenr_el0", CPENC(3,3,C9,C14, 0), 0 },
4041 { "pmintenset_el1", CPENC(3,0,C9,C14, 1), 0 },
4042 { "pmintenclr_el1", CPENC(3,0,C9,C14, 2), 0 },
4043 { "pmovsset_el0", CPENC(3,3,C9,C14, 3), 0 },
4044 { "pmevcntr0_el0", CPENC(3,3,C14,C8, 0), 0 },
4045 { "pmevcntr1_el0", CPENC(3,3,C14,C8, 1), 0 },
4046 { "pmevcntr2_el0", CPENC(3,3,C14,C8, 2), 0 },
4047 { "pmevcntr3_el0", CPENC(3,3,C14,C8, 3), 0 },
4048 { "pmevcntr4_el0", CPENC(3,3,C14,C8, 4), 0 },
4049 { "pmevcntr5_el0", CPENC(3,3,C14,C8, 5), 0 },
4050 { "pmevcntr6_el0", CPENC(3,3,C14,C8, 6), 0 },
4051 { "pmevcntr7_el0", CPENC(3,3,C14,C8, 7), 0 },
4052 { "pmevcntr8_el0", CPENC(3,3,C14,C9, 0), 0 },
4053 { "pmevcntr9_el0", CPENC(3,3,C14,C9, 1), 0 },
4054 { "pmevcntr10_el0", CPENC(3,3,C14,C9, 2), 0 },
4055 { "pmevcntr11_el0", CPENC(3,3,C14,C9, 3), 0 },
4056 { "pmevcntr12_el0", CPENC(3,3,C14,C9, 4), 0 },
4057 { "pmevcntr13_el0", CPENC(3,3,C14,C9, 5), 0 },
4058 { "pmevcntr14_el0", CPENC(3,3,C14,C9, 6), 0 },
4059 { "pmevcntr15_el0", CPENC(3,3,C14,C9, 7), 0 },
4060 { "pmevcntr16_el0", CPENC(3,3,C14,C10,0), 0 },
4061 { "pmevcntr17_el0", CPENC(3,3,C14,C10,1), 0 },
4062 { "pmevcntr18_el0", CPENC(3,3,C14,C10,2), 0 },
4063 { "pmevcntr19_el0", CPENC(3,3,C14,C10,3), 0 },
4064 { "pmevcntr20_el0", CPENC(3,3,C14,C10,4), 0 },
4065 { "pmevcntr21_el0", CPENC(3,3,C14,C10,5), 0 },
4066 { "pmevcntr22_el0", CPENC(3,3,C14,C10,6), 0 },
4067 { "pmevcntr23_el0", CPENC(3,3,C14,C10,7), 0 },
4068 { "pmevcntr24_el0", CPENC(3,3,C14,C11,0), 0 },
4069 { "pmevcntr25_el0", CPENC(3,3,C14,C11,1), 0 },
4070 { "pmevcntr26_el0", CPENC(3,3,C14,C11,2), 0 },
4071 { "pmevcntr27_el0", CPENC(3,3,C14,C11,3), 0 },
4072 { "pmevcntr28_el0", CPENC(3,3,C14,C11,4), 0 },
4073 { "pmevcntr29_el0", CPENC(3,3,C14,C11,5), 0 },
4074 { "pmevcntr30_el0", CPENC(3,3,C14,C11,6), 0 },
4075 { "pmevtyper0_el0", CPENC(3,3,C14,C12,0), 0 },
4076 { "pmevtyper1_el0", CPENC(3,3,C14,C12,1), 0 },
4077 { "pmevtyper2_el0", CPENC(3,3,C14,C12,2), 0 },
4078 { "pmevtyper3_el0", CPENC(3,3,C14,C12,3), 0 },
4079 { "pmevtyper4_el0", CPENC(3,3,C14,C12,4), 0 },
4080 { "pmevtyper5_el0", CPENC(3,3,C14,C12,5), 0 },
4081 { "pmevtyper6_el0", CPENC(3,3,C14,C12,6), 0 },
4082 { "pmevtyper7_el0", CPENC(3,3,C14,C12,7), 0 },
4083 { "pmevtyper8_el0", CPENC(3,3,C14,C13,0), 0 },
4084 { "pmevtyper9_el0", CPENC(3,3,C14,C13,1), 0 },
4085 { "pmevtyper10_el0", CPENC(3,3,C14,C13,2), 0 },
4086 { "pmevtyper11_el0", CPENC(3,3,C14,C13,3), 0 },
4087 { "pmevtyper12_el0", CPENC(3,3,C14,C13,4), 0 },
4088 { "pmevtyper13_el0", CPENC(3,3,C14,C13,5), 0 },
4089 { "pmevtyper14_el0", CPENC(3,3,C14,C13,6), 0 },
4090 { "pmevtyper15_el0", CPENC(3,3,C14,C13,7), 0 },
4091 { "pmevtyper16_el0", CPENC(3,3,C14,C14,0), 0 },
4092 { "pmevtyper17_el0", CPENC(3,3,C14,C14,1), 0 },
4093 { "pmevtyper18_el0", CPENC(3,3,C14,C14,2), 0 },
4094 { "pmevtyper19_el0", CPENC(3,3,C14,C14,3), 0 },
4095 { "pmevtyper20_el0", CPENC(3,3,C14,C14,4), 0 },
4096 { "pmevtyper21_el0", CPENC(3,3,C14,C14,5), 0 },
4097 { "pmevtyper22_el0", CPENC(3,3,C14,C14,6), 0 },
4098 { "pmevtyper23_el0", CPENC(3,3,C14,C14,7), 0 },
4099 { "pmevtyper24_el0", CPENC(3,3,C14,C15,0), 0 },
4100 { "pmevtyper25_el0", CPENC(3,3,C14,C15,1), 0 },
4101 { "pmevtyper26_el0", CPENC(3,3,C14,C15,2), 0 },
4102 { "pmevtyper27_el0", CPENC(3,3,C14,C15,3), 0 },
4103 { "pmevtyper28_el0", CPENC(3,3,C14,C15,4), 0 },
4104 { "pmevtyper29_el0", CPENC(3,3,C14,C15,5), 0 },
4105 { "pmevtyper30_el0", CPENC(3,3,C14,C15,6), 0 },
4106 { "pmccfiltr_el0", CPENC(3,3,C14,C15,7), 0 },
793a1948
TC		 4107
4108 { "dit", CPEN_ (3, C2, 5), F_ARCHEXT },
4109 { "vstcr_el2", CPENC(3, 4, C2, C6, 2), F_ARCHEXT },
4110 { "vsttbr_el2", CPENC(3, 4, C2, C6, 0), F_ARCHEXT },
4111 { "cnthvs_tval_el2", CPENC(3, 4, C14, C4, 0), F_ARCHEXT },
4112 { "cnthvs_cval_el2", CPENC(3, 4, C14, C4, 2), F_ARCHEXT },
4113 { "cnthvs_ctl_el2", CPENC(3, 4, C14, C4, 1), F_ARCHEXT },
4114 { "cnthps_tval_el2", CPENC(3, 4, C14, C5, 0), F_ARCHEXT },
4115 { "cnthps_cval_el2", CPENC(3, 4, C14, C5, 2), F_ARCHEXT },
4116 { "cnthps_ctl_el2", CPENC(3, 4, C14, C5, 1), F_ARCHEXT },
4117 { "sder32_el2", CPENC(3, 4, C1, C3, 1), F_ARCHEXT },
4118 { "vncr_el2", CPENC(3, 4, C2, C2, 0), F_ARCHEXT },
49eec193 4119 { 0, CPENC(0,0,0,0,0), 0 },
a06ea964
NC		 4120};
4121
49eec193
YZ		 4122bfd_boolean
4123aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *reg)
4124{
4125 return (reg->flags & F_DEPRECATED) != 0;
4126}
4127
f21cce2c
MW		 4128bfd_boolean
4129aarch64_sys_reg_supported_p (const aarch64_feature_set features,
4130 const aarch64_sys_reg *reg)
4131{
4132 if (!(reg->flags & F_ARCHEXT))
4133 return TRUE;
4134
4135 /* PAN. Values are from aarch64_sys_regs. */
4136 if (reg->value == CPEN_(0,C2,3)
4137 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4138 return FALSE;
4139
a97330e7
SD		 4140 /* SCXTNUM_ELx registers. */
4141 if ((reg->value == CPENC (3, 3, C13, C0, 7)
4142 || reg->value == CPENC (3, 0, C13, C0, 7)
4143 || reg->value == CPENC (3, 4, C13, C0, 7)
4144 || reg->value == CPENC (3, 6, C13, C0, 7)
4145 || reg->value == CPENC (3, 5, C13, C0, 7))
4146 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SCXTNUM))
4147 return FALSE;
4148
4149 /* ID_PFR2_EL1 register. */
4150 if (reg->value == CPENC(3, 0, C0, C3, 4)
4151 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_ID_PFR2))
4152 return FALSE;
4153
104fefee
SD		 4154 /* SSBS. Values are from aarch64_sys_regs. */
4155 if (reg->value == CPEN_(3,C2,6)
4156 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
4157 return FALSE;
4158
250aafa4
MW		 4159 /* Virtualization host extensions: system registers. */
4160 if ((reg->value == CPENC (3, 4, C2, C0, 1)
4161 || reg->value == CPENC (3, 4, C13, C0, 1)
4162 || reg->value == CPENC (3, 4, C14, C3, 0)
4163 || reg->value == CPENC (3, 4, C14, C3, 1)
4164 || reg->value == CPENC (3, 4, C14, C3, 2))
4165 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4166 return FALSE;
4167
4168 /* Virtualization host extensions: *_el12 names of *_el1 registers. */
4169 if ((reg->value == CPEN_ (5, C0, 0)
4170 || reg->value == CPEN_ (5, C0, 1)
4171 || reg->value == CPENC (3, 5, C1, C0, 0)
4172 || reg->value == CPENC (3, 5, C1, C0, 2)
4173 || reg->value == CPENC (3, 5, C2, C0, 0)
4174 || reg->value == CPENC (3, 5, C2, C0, 1)
4175 || reg->value == CPENC (3, 5, C2, C0, 2)
4176 || reg->value == CPENC (3, 5, C5, C1, 0)
4177 || reg->value == CPENC (3, 5, C5, C1, 1)
4178 || reg->value == CPENC (3, 5, C5, C2, 0)
4179 || reg->value == CPENC (3, 5, C6, C0, 0)
4180 || reg->value == CPENC (3, 5, C10, C2, 0)
4181 || reg->value == CPENC (3, 5, C10, C3, 0)
4182 || reg->value == CPENC (3, 5, C12, C0, 0)
4183 || reg->value == CPENC (3, 5, C13, C0, 1)
4184 || reg->value == CPENC (3, 5, C14, C1, 0))
4185 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4186 return FALSE;
4187
4188 /* Virtualization host extensions: *_el02 names of *_el0 registers. */
4189 if ((reg->value == CPENC (3, 5, C14, C2, 0)
4190 || reg->value == CPENC (3, 5, C14, C2, 1)
4191 || reg->value == CPENC (3, 5, C14, C2, 2)
4192 || reg->value == CPENC (3, 5, C14, C3, 0)
4193 || reg->value == CPENC (3, 5, C14, C3, 1)
4194 || reg->value == CPENC (3, 5, C14, C3, 2))
4195 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
63511907 4196 return FALSE;
1a04d1a7
MW		 4197
4198 /* ARMv8.2 features. */
6479e48e
MW		 4199
4200 /* ID_AA64MMFR2_EL1. */
1a04d1a7
MW		 4201 if (reg->value == CPENC (3, 0, C0, C7, 2)
4202 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
250aafa4
MW		 4203 return FALSE;
4204
6479e48e
MW		 4205 /* PSTATE.UAO. */
4206 if (reg->value == CPEN_ (0, C2, 4)
4207 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4208 return FALSE;
4209
47f81142
MW		 4210 /* RAS extension. */
4211
651657fa
MW		 4212 /* ERRIDR_EL1, ERRSELR_EL1, ERXFR_EL1, ERXCTLR_EL1, ERXSTATUS_EL, ERXADDR_EL1,
4213 ERXMISC0_EL1 AND ERXMISC1_EL1. */
47f81142 4214 if ((reg->value == CPENC (3, 0, C5, C3, 0)
651657fa 4215 || reg->value == CPENC (3, 0, C5, C3, 1)
47f81142
MW		 4216 || reg->value == CPENC (3, 0, C5, C3, 2)
4217 || reg->value == CPENC (3, 0, C5, C3, 3)
651657fa
MW		 4218 || reg->value == CPENC (3, 0, C5, C4, 0)
4219 || reg->value == CPENC (3, 0, C5, C4, 1)
4220 || reg->value == CPENC (3, 0, C5, C4, 2)
4221 || reg->value == CPENC (3, 0, C5, C4, 3)
47f81142
MW		 4222 || reg->value == CPENC (3, 0, C5, C5, 0)
4223 || reg->value == CPENC (3, 0, C5, C5, 1))
4224 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4225 return FALSE;
4226
4227 /* VSESR_EL2, DISR_EL1 and VDISR_EL2. */
4228 if ((reg->value == CPENC (3, 4, C5, C2, 3)
4229 || reg->value == CPENC (3, 0, C12, C1, 1)
4230 || reg->value == CPENC (3, 4, C12, C1, 1))
4231 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4232 return FALSE;
4233
55c144e6
MW		 4234 /* Statistical Profiling extension. */
4235 if ((reg->value == CPENC (3, 0, C9, C10, 0)
4236 || reg->value == CPENC (3, 0, C9, C10, 1)
4237 || reg->value == CPENC (3, 0, C9, C10, 3)
4238 || reg->value == CPENC (3, 0, C9, C10, 7)
4239 || reg->value == CPENC (3, 0, C9, C9, 0)
4240 || reg->value == CPENC (3, 0, C9, C9, 2)
4241 || reg->value == CPENC (3, 0, C9, C9, 3)
4242 || reg->value == CPENC (3, 0, C9, C9, 4)
4243 || reg->value == CPENC (3, 0, C9, C9, 5)
4244 || reg->value == CPENC (3, 0, C9, C9, 6)
4245 || reg->value == CPENC (3, 0, C9, C9, 7)
4246 || reg->value == CPENC (3, 4, C9, C9, 0)
4247 || reg->value == CPENC (3, 5, C9, C9, 0))
4248 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PROFILE))
4249 return FALSE;
4250
b0bfa7b5
SN		 4251 /* ARMv8.3 Pointer authentication keys. */
4252 if ((reg->value == CPENC (3, 0, C2, C1, 0)
4253 || reg->value == CPENC (3, 0, C2, C1, 1)
4254 || reg->value == CPENC (3, 0, C2, C1, 2)
4255 || reg->value == CPENC (3, 0, C2, C1, 3)
4256 || reg->value == CPENC (3, 0, C2, C2, 0)
4257 || reg->value == CPENC (3, 0, C2, C2, 1)
4258 || reg->value == CPENC (3, 0, C2, C2, 2)
4259 || reg->value == CPENC (3, 0, C2, C2, 3)
4260 || reg->value == CPENC (3, 0, C2, C3, 0)
4261 || reg->value == CPENC (3, 0, C2, C3, 1))
4262 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_3))
4263 return FALSE;
4264
773fb663
RS		 4265 /* SVE. */
4266 if ((reg->value == CPENC (3, 0, C0, C4, 4)
4267 || reg->value == CPENC (3, 0, C1, C2, 0)
4268 || reg->value == CPENC (3, 4, C1, C2, 0)
4269 || reg->value == CPENC (3, 6, C1, C2, 0)
4270 || reg->value == CPENC (3, 5, C1, C2, 0)
4271 || reg->value == CPENC (3, 0, C0, C0, 7))
4272 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SVE))
4273 return FALSE;
4274
793a1948
TC		 4275 /* ARMv8.4 features. */
4276
4277 /* PSTATE.DIT. */
4278 if (reg->value == CPEN_ (3, C2, 5)
4279 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4280 return FALSE;
4281
4282 /* Virtualization extensions. */
4283 if ((reg->value == CPENC(3, 4, C2, C6, 2)
4284 || reg->value == CPENC(3, 4, C2, C6, 0)
4285 || reg->value == CPENC(3, 4, C14, C4, 0)
4286 || reg->value == CPENC(3, 4, C14, C4, 2)
4287 || reg->value == CPENC(3, 4, C14, C4, 1)
4288 || reg->value == CPENC(3, 4, C14, C5, 0)
4289 || reg->value == CPENC(3, 4, C14, C5, 2)
4290 || reg->value == CPENC(3, 4, C14, C5, 1)
4291 || reg->value == CPENC(3, 4, C1, C3, 1)
4292 || reg->value == CPENC(3, 4, C2, C2, 0))
4293 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4294 return FALSE;
4295
4296 /* ARMv8.4 TLB instructions. */
4297 if ((reg->value == CPENS (0, C8, C1, 0)
4298 || reg->value == CPENS (0, C8, C1, 1)
4299 || reg->value == CPENS (0, C8, C1, 2)
4300 || reg->value == CPENS (0, C8, C1, 3)
4301 || reg->value == CPENS (0, C8, C1, 5)
4302 || reg->value == CPENS (0, C8, C1, 7)
4303 || reg->value == CPENS (4, C8, C4, 0)
4304 || reg->value == CPENS (4, C8, C4, 4)
4305 || reg->value == CPENS (4, C8, C1, 1)
4306 || reg->value == CPENS (4, C8, C1, 5)
4307 || reg->value == CPENS (4, C8, C1, 6)
4308 || reg->value == CPENS (6, C8, C1, 1)
4309 || reg->value == CPENS (6, C8, C1, 5)
4310 || reg->value == CPENS (4, C8, C1, 0)
4311 || reg->value == CPENS (4, C8, C1, 4)
4312 || reg->value == CPENS (6, C8, C1, 0)
4313 || reg->value == CPENS (0, C8, C6, 1)
4314 || reg->value == CPENS (0, C8, C6, 3)
4315 || reg->value == CPENS (0, C8, C6, 5)
4316 || reg->value == CPENS (0, C8, C6, 7)
4317 || reg->value == CPENS (0, C8, C2, 1)
4318 || reg->value == CPENS (0, C8, C2, 3)
4319 || reg->value == CPENS (0, C8, C2, 5)
4320 || reg->value == CPENS (0, C8, C2, 7)
4321 || reg->value == CPENS (0, C8, C5, 1)
4322 || reg->value == CPENS (0, C8, C5, 3)
4323 || reg->value == CPENS (0, C8, C5, 5)
4324 || reg->value == CPENS (0, C8, C5, 7)
4325 || reg->value == CPENS (4, C8, C0, 2)
4326 || reg->value == CPENS (4, C8, C0, 6)
4327 || reg->value == CPENS (4, C8, C4, 2)
4328 || reg->value == CPENS (4, C8, C4, 6)
4329 || reg->value == CPENS (4, C8, C4, 3)
4330 || reg->value == CPENS (4, C8, C4, 7)
4331 || reg->value == CPENS (4, C8, C6, 1)
4332 || reg->value == CPENS (4, C8, C6, 5)
4333 || reg->value == CPENS (4, C8, C2, 1)
4334 || reg->value == CPENS (4, C8, C2, 5)
4335 || reg->value == CPENS (4, C8, C5, 1)
4336 || reg->value == CPENS (4, C8, C5, 5)
4337 || reg->value == CPENS (6, C8, C6, 1)
4338 || reg->value == CPENS (6, C8, C6, 5)
4339 || reg->value == CPENS (6, C8, C2, 1)
4340 || reg->value == CPENS (6, C8, C2, 5)
4341 || reg->value == CPENS (6, C8, C5, 1)
4342 || reg->value == CPENS (6, C8, C5, 5))
4343 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4344 return FALSE;
4345
af4bcb4c
SD		 4346 /* Random Number Instructions. For now they are available
4347 (and optional) only with ARMv8.5-A. */
4348 if ((reg->value == CPENC (3, 3, C2, C4, 0)
4349 || reg->value == CPENC (3, 3, C2, C4, 1))
4350 && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RNG)
4351 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_5)))
4352 return FALSE;
4353
f21cce2c
MW		 4354 return TRUE;
4355}
4356
793a1948
TC		 4357/* The CPENC below is fairly misleading, the fields
4358 here are not in CPENC form. They are in op2op1 form. The fields are encoded
4359 by ins_pstatefield, which just shifts the value by the width of the fields
4360 in a loop. So if you CPENC them only the first value will be set, the rest
4361 are masked out to 0. As an example. op2 = 3, op1=2. CPENC would produce a
4362 value of 0b110000000001000000 (0x30040) while what you want is
4363 0b011010 (0x1a). */
87b8eed7 4364const aarch64_sys_reg aarch64_pstatefields [] =
a06ea964 4365{
87b8eed7
YZ		 4366 { "spsel", 0x05, 0 },
4367 { "daifset", 0x1e, 0 },
4368 { "daifclr", 0x1f, 0 },
f21cce2c 4369 { "pan", 0x04, F_ARCHEXT },
6479e48e 4370 { "uao", 0x03, F_ARCHEXT },
104fefee 4371 { "ssbs", 0x19, F_ARCHEXT },
793a1948 4372 { "dit", 0x1a, F_ARCHEXT },
87b8eed7 4373 { 0, CPENC(0,0,0,0,0), 0 },
a06ea964
NC		 4374};
4375
f21cce2c
MW		 4376bfd_boolean
4377aarch64_pstatefield_supported_p (const aarch64_feature_set features,
4378 const aarch64_sys_reg *reg)
4379{
4380 if (!(reg->flags & F_ARCHEXT))
4381 return TRUE;
4382
4383 /* PAN. Values are from aarch64_pstatefields. */
4384 if (reg->value == 0x04
4385 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4386 return FALSE;
4387
6479e48e
MW		 4388 /* UAO. Values are from aarch64_pstatefields. */
4389 if (reg->value == 0x03
4390 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4391 return FALSE;
4392
104fefee
SD		 4393 /* SSBS. Values are from aarch64_pstatefields. */
4394 if (reg->value == 0x19
4395 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
4396 return FALSE;
4397
793a1948
TC		 4398 /* DIT. Values are from aarch64_pstatefields. */
4399 if (reg->value == 0x1a
4400 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4401 return FALSE;
4402
f21cce2c
MW		 4403 return TRUE;
4404}
4405
a06ea964
NC		 4406const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
4407{
4408 { "ialluis", CPENS(0,C7,C1,0), 0 },
4409 { "iallu", CPENS(0,C7,C5,0), 0 },
ea2deeec 4410 { "ivau", CPENS (3, C7, C5, 1), F_HASXT },
a06ea964
NC		 4411 { 0, CPENS(0,0,0,0), 0 }
4412};
4413
4414const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
4415{
ea2deeec
MW		 4416 { "zva", CPENS (3, C7, C4, 1), F_HASXT },
4417 { "ivac", CPENS (0, C7, C6, 1), F_HASXT },
4418 { "isw", CPENS (0, C7, C6, 2), F_HASXT },
4419 { "cvac", CPENS (3, C7, C10, 1), F_HASXT },
4420 { "csw", CPENS (0, C7, C10, 2), F_HASXT },
4421 { "cvau", CPENS (3, C7, C11, 1), F_HASXT },
d6bf7ce6 4422 { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
3fd229a4 4423 { "cvadp", CPENS (3, C7, C13, 1), F_HASXT | F_ARCHEXT },
ea2deeec
MW		 4424 { "civac", CPENS (3, C7, C14, 1), F_HASXT },
4425 { "cisw", CPENS (0, C7, C14, 2), F_HASXT },
a06ea964
NC		 4426 { 0, CPENS(0,0,0,0), 0 }
4427};
4428
4429const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
4430{
ea2deeec
MW		 4431 { "s1e1r", CPENS (0, C7, C8, 0), F_HASXT },
4432 { "s1e1w", CPENS (0, C7, C8, 1), F_HASXT },
4433 { "s1e0r", CPENS (0, C7, C8, 2), F_HASXT },
4434 { "s1e0w", CPENS (0, C7, C8, 3), F_HASXT },
4435 { "s12e1r", CPENS (4, C7, C8, 4), F_HASXT },
4436 { "s12e1w", CPENS (4, C7, C8, 5), F_HASXT },
4437 { "s12e0r", CPENS (4, C7, C8, 6), F_HASXT },
4438 { "s12e0w", CPENS (4, C7, C8, 7), F_HASXT },
4439 { "s1e2r", CPENS (4, C7, C8, 0), F_HASXT },
4440 { "s1e2w", CPENS (4, C7, C8, 1), F_HASXT },
4441 { "s1e3r", CPENS (6, C7, C8, 0), F_HASXT },
4442 { "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
22a5455c
MW		 4443 { "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
4444 { "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
a06ea964
NC		 4445 { 0, CPENS(0,0,0,0), 0 }
4446};
4447
4448const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
4449{
4450 { "vmalle1", CPENS(0,C8,C7,0), 0 },
ea2deeec
MW		 4451 { "vae1", CPENS (0, C8, C7, 1), F_HASXT },
4452 { "aside1", CPENS (0, C8, C7, 2), F_HASXT },
4453 { "vaae1", CPENS (0, C8, C7, 3), F_HASXT },
a06ea964 4454 { "vmalle1is", CPENS(0,C8,C3,0), 0 },
ea2deeec
MW		 4455 { "vae1is", CPENS (0, C8, C3, 1), F_HASXT },
4456 { "aside1is", CPENS (0, C8, C3, 2), F_HASXT },
4457 { "vaae1is", CPENS (0, C8, C3, 3), F_HASXT },
4458 { "ipas2e1is", CPENS (4, C8, C0, 1), F_HASXT },
4459 { "ipas2le1is",CPENS (4, C8, C0, 5), F_HASXT },
4460 { "ipas2e1", CPENS (4, C8, C4, 1), F_HASXT },
4461 { "ipas2le1", CPENS (4, C8, C4, 5), F_HASXT },
4462 { "vae2", CPENS (4, C8, C7, 1), F_HASXT },
4463 { "vae2is", CPENS (4, C8, C3, 1), F_HASXT },
a06ea964
NC		 4464 { "vmalls12e1",CPENS(4,C8,C7,6), 0 },
4465 { "vmalls12e1is",CPENS(4,C8,C3,6), 0 },
ea2deeec
MW		 4466 { "vae3", CPENS (6, C8, C7, 1), F_HASXT },
4467 { "vae3is", CPENS (6, C8, C3, 1), F_HASXT },
a06ea964
NC		 4468 { "alle2", CPENS(4,C8,C7,0), 0 },
4469 { "alle2is", CPENS(4,C8,C3,0), 0 },
4470 { "alle1", CPENS(4,C8,C7,4), 0 },
4471 { "alle1is", CPENS(4,C8,C3,4), 0 },
4472 { "alle3", CPENS(6,C8,C7,0), 0 },
4473 { "alle3is", CPENS(6,C8,C3,0), 0 },
ea2deeec
MW		 4474 { "vale1is", CPENS (0, C8, C3, 5), F_HASXT },
4475 { "vale2is", CPENS (4, C8, C3, 5), F_HASXT },
4476 { "vale3is", CPENS (6, C8, C3, 5), F_HASXT },
4477 { "vaale1is", CPENS (0, C8, C3, 7), F_HASXT },
4478 { "vale1", CPENS (0, C8, C7, 5), F_HASXT },
4479 { "vale2", CPENS (4, C8, C7, 5), F_HASXT },
4480 { "vale3", CPENS (6, C8, C7, 5), F_HASXT },
4481 { "vaale1", CPENS (0, C8, C7, 7), F_HASXT },
793a1948
TC		 4482
4483 { "vmalle1os", CPENS (0, C8, C1, 0), F_ARCHEXT },
4484 { "vae1os", CPENS (0, C8, C1, 1), F_HASXT | F_ARCHEXT },
4485 { "aside1os", CPENS (0, C8, C1, 2), F_HASXT | F_ARCHEXT },
4486 { "vaae1os", CPENS (0, C8, C1, 3), F_HASXT | F_ARCHEXT },
4487 { "vale1os", CPENS (0, C8, C1, 5), F_HASXT | F_ARCHEXT },
4488 { "vaale1os", CPENS (0, C8, C1, 7), F_HASXT | F_ARCHEXT },
4489 { "ipas2e1os", CPENS (4, C8, C4, 0), F_HASXT | F_ARCHEXT },
4490 { "ipas2le1os", CPENS (4, C8, C4, 4), F_HASXT | F_ARCHEXT },
4491 { "vae2os", CPENS (4, C8, C1, 1), F_HASXT | F_ARCHEXT },
4492 { "vale2os", CPENS (4, C8, C1, 5), F_HASXT | F_ARCHEXT },
4493 { "vmalls12e1os", CPENS (4, C8, C1, 6), F_ARCHEXT },
4494 { "vae3os", CPENS (6, C8, C1, 1), F_HASXT | F_ARCHEXT },
4495 { "vale3os", CPENS (6, C8, C1, 5), F_HASXT | F_ARCHEXT },
4496 { "alle2os", CPENS (4, C8, C1, 0), F_ARCHEXT },
4497 { "alle1os", CPENS (4, C8, C1, 4), F_ARCHEXT },
4498 { "alle3os", CPENS (6, C8, C1, 0), F_ARCHEXT },
4499
4500 { "rvae1", CPENS (0, C8, C6, 1), F_HASXT | F_ARCHEXT },
4501 { "rvaae1", CPENS (0, C8, C6, 3), F_HASXT | F_ARCHEXT },
4502 { "rvale1", CPENS (0, C8, C6, 5), F_HASXT | F_ARCHEXT },
4503 { "rvaale1", CPENS (0, C8, C6, 7), F_HASXT | F_ARCHEXT },
4504 { "rvae1is", CPENS (0, C8, C2, 1), F_HASXT | F_ARCHEXT },
4505 { "rvaae1is", CPENS (0, C8, C2, 3), F_HASXT | F_ARCHEXT },
4506 { "rvale1is", CPENS (0, C8, C2, 5), F_HASXT | F_ARCHEXT },
4507 { "rvaale1is", CPENS (0, C8, C2, 7), F_HASXT | F_ARCHEXT },
4508 { "rvae1os", CPENS (0, C8, C5, 1), F_HASXT | F_ARCHEXT },
4509 { "rvaae1os", CPENS (0, C8, C5, 3), F_HASXT | F_ARCHEXT },
4510 { "rvale1os", CPENS (0, C8, C5, 5), F_HASXT | F_ARCHEXT },
4511 { "rvaale1os", CPENS (0, C8, C5, 7), F_HASXT | F_ARCHEXT },
4512 { "ripas2e1is", CPENS (4, C8, C0, 2), F_HASXT | F_ARCHEXT },
4513 { "ripas2le1is",CPENS (4, C8, C0, 6), F_HASXT | F_ARCHEXT },
4514 { "ripas2e1", CPENS (4, C8, C4, 2), F_HASXT | F_ARCHEXT },
4515 { "ripas2le1", CPENS (4, C8, C4, 6), F_HASXT | F_ARCHEXT },
4516 { "ripas2e1os", CPENS (4, C8, C4, 3), F_HASXT | F_ARCHEXT },
4517 { "ripas2le1os",CPENS (4, C8, C4, 7), F_HASXT | F_ARCHEXT },
4518 { "rvae2", CPENS (4, C8, C6, 1), F_HASXT | F_ARCHEXT },
4519 { "rvale2", CPENS (4, C8, C6, 5), F_HASXT | F_ARCHEXT },
4520 { "rvae2is", CPENS (4, C8, C2, 1), F_HASXT | F_ARCHEXT },
4521 { "rvale2is", CPENS (4, C8, C2, 5), F_HASXT | F_ARCHEXT },
4522 { "rvae2os", CPENS (4, C8, C5, 1), F_HASXT | F_ARCHEXT },
4523 { "rvale2os", CPENS (4, C8, C5, 5), F_HASXT | F_ARCHEXT },
4524 { "rvae3", CPENS (6, C8, C6, 1), F_HASXT | F_ARCHEXT },
4525 { "rvale3", CPENS (6, C8, C6, 5), F_HASXT | F_ARCHEXT },
4526 { "rvae3is", CPENS (6, C8, C2, 1), F_HASXT | F_ARCHEXT },
4527 { "rvale3is", CPENS (6, C8, C2, 5), F_HASXT | F_ARCHEXT },
4528 { "rvae3os", CPENS (6, C8, C5, 1), F_HASXT | F_ARCHEXT },
4529 { "rvale3os", CPENS (6, C8, C5, 5), F_HASXT | F_ARCHEXT },
4530
a06ea964
NC		 4531 { 0, CPENS(0,0,0,0), 0 }
4532};
4533
2ac435d4
SD		 4534const aarch64_sys_ins_reg aarch64_sys_regs_sr[] =
4535{
4536 /* RCTX is somewhat unique in a way that it has different values
4537 (op2) based on the instruction in which it is used (cfp/dvp/cpp).
4538 Thus op2 is masked out and instead encoded directly in the
4539 aarch64_opcode_table entries for the respective instructions. */
4540 { "rctx", CPENS(3,C7,C3,0), F_HASXT | F_ARCHEXT | F_REG_WRITE}, /* WO */
4541
4542 { 0, CPENS(0,0,0,0), 0 }
4543};
4544
ea2deeec
MW		 4545bfd_boolean
4546aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
4547{
4548 return (sys_ins_reg->flags & F_HASXT) != 0;
4549}
4550
d6bf7ce6
MW		 4551extern bfd_boolean
4552aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
4553 const aarch64_sys_ins_reg *reg)
4554{
4555 if (!(reg->flags & F_ARCHEXT))
4556 return TRUE;
4557
4558 /* DC CVAP. Values are from aarch64_sys_regs_dc. */
4559 if (reg->value == CPENS (3, C7, C12, 1)
4560 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4561 return FALSE;
4562
3fd229a4
SD		 4563 /* DC CVADP. Values are from aarch64_sys_regs_dc. */
4564 if (reg->value == CPENS (3, C7, C13, 1)
4565 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP))
4566 return FALSE;
4567
63511907
MW		 4568 /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
4569 if ((reg->value == CPENS (0, C7, C9, 0)
4570 || reg->value == CPENS (0, C7, C9, 1))
4571 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4572 return FALSE;
4573
2ac435d4
SD		 4574 /* CFP/DVP/CPP RCTX : Value are from aarch64_sys_regs_sr. */
4575 if (reg->value == CPENS (3, C7, C3, 0)
4576 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PREDRES))
4577 return FALSE;
4578
d6bf7ce6
MW		 4579 return TRUE;
4580}
4581
a06ea964
NC		 4582#undef C0
4583#undef C1
4584#undef C2
4585#undef C3
4586#undef C4
4587#undef C5
4588#undef C6
4589#undef C7
4590#undef C8
4591#undef C9
4592#undef C10
4593#undef C11
4594#undef C12
4595#undef C13
4596#undef C14
4597#undef C15
4598
4bd13cde
NC		 4599#define BIT(INSN,BT) (((INSN) >> (BT)) & 1)
4600#define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
4601
755b748f
TC		 4602static enum err_type
4603verify_ldpsw (const struct aarch64_inst *inst ATTRIBUTE_UNUSED,
4604 const aarch64_insn insn, bfd_vma pc ATTRIBUTE_UNUSED,
4605 bfd_boolean encoding ATTRIBUTE_UNUSED,
4606 aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
a68f4cd2 4607 aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
4bd13cde
NC		 4608{
4609 int t = BITS (insn, 4, 0);
4610 int n = BITS (insn, 9, 5);
4611 int t2 = BITS (insn, 14, 10);
4612
4613 if (BIT (insn, 23))
4614 {
4615 /* Write back enabled. */
4616 if ((t == n || t2 == n) && n != 31)
755b748f 4617 return ERR_UND;
4bd13cde
NC		 4618 }
4619
4620 if (BIT (insn, 22))
4621 {
4622 /* Load */
4623 if (t == t2)
755b748f 4624 return ERR_UND;
4bd13cde
NC		 4625 }
4626
755b748f 4627 return ERR_OK;
4bd13cde
NC		 4628}
4629
a68f4cd2
TC		 4630/* Initialize an instruction sequence insn_sequence with the instruction INST.
4631 If INST is NULL the given insn_sequence is cleared and the sequence is left
4632 uninitialized. */
4633
4634void
4635init_insn_sequence (const struct aarch64_inst *inst,
4636 aarch64_instr_sequence *insn_sequence)
4637{
4638 int num_req_entries = 0;
4639 insn_sequence->next_insn = 0;
4640 insn_sequence->num_insns = num_req_entries;
4641 if (insn_sequence->instr)
4642 XDELETE (insn_sequence->instr);
4643 insn_sequence->instr = NULL;
4644
4645 if (inst)
4646 {
4647 insn_sequence->instr = XNEW (aarch64_inst);
4648 memcpy (insn_sequence->instr, inst, sizeof (aarch64_inst));
4649 }
4650
4651 /* Handle all the cases here. May need to think of something smarter than
4652 a giant if/else chain if this grows. At that time, a lookup table may be
4653 best. */
4654 if (inst && inst->opcode->constraints & C_SCAN_MOVPRFX)
4655 num_req_entries = 1;
4656
4657 if (insn_sequence->current_insns)
4658 XDELETEVEC (insn_sequence->current_insns);
4659 insn_sequence->current_insns = NULL;
4660
4661 if (num_req_entries != 0)
4662 {
4663 size_t size = num_req_entries * sizeof (aarch64_inst);
4664 insn_sequence->current_insns
4665 = (aarch64_inst**) XNEWVEC (aarch64_inst, num_req_entries);
4666 memset (insn_sequence->current_insns, 0, size);
4667 }
4668}
4669
4670
4671/* This function verifies that the instruction INST adheres to its specified
4672 constraints. If it does then ERR_OK is returned, if not then ERR_VFI is
4673 returned and MISMATCH_DETAIL contains the reason why verification failed.
4674
4675 The function is called both during assembly and disassembly. If assembling
4676 then ENCODING will be TRUE, else FALSE. If dissassembling PC will be set
4677 and will contain the PC of the current instruction w.r.t to the section.
4678
4679 If ENCODING and PC=0 then you are at a start of a section. The constraints
4680 are verified against the given state insn_sequence which is updated as it
4681 transitions through the verification. */
4682
4683enum err_type
4684verify_constraints (const struct aarch64_inst *inst,
4685 const aarch64_insn insn ATTRIBUTE_UNUSED,
4686 bfd_vma pc,
4687 bfd_boolean encoding,
4688 aarch64_operand_error *mismatch_detail,
4689 aarch64_instr_sequence *insn_sequence)
4690{
4691 assert (inst);
4692 assert (inst->opcode);
4693
4694 const struct aarch64_opcode *opcode = inst->opcode;
4695 if (!opcode->constraints && !insn_sequence->instr)
4696 return ERR_OK;
4697
4698 assert (insn_sequence);
4699
4700 enum err_type res = ERR_OK;
4701
4702 /* This instruction puts a constraint on the insn_sequence. */
4703 if (opcode->flags & F_SCAN)
4704 {
4705 if (insn_sequence->instr)
4706 {
4707 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4708 mismatch_detail->error = _("instruction opens new dependency "
4709 "sequence without ending previous one");
4710 mismatch_detail->index = -1;
4711 mismatch_detail->non_fatal = TRUE;
4712 res = ERR_VFI;
4713 }
4714
4715 init_insn_sequence (inst, insn_sequence);
4716 return res;
4717 }
4718
4719 /* Verify constraints on an existing sequence. */
4720 if (insn_sequence->instr)
4721 {
4722 const struct aarch64_opcode* inst_opcode = insn_sequence->instr->opcode;
4723 /* If we're decoding and we hit PC=0 with an open sequence then we haven't
4724 closed a previous one that we should have. */
4725 if (!encoding && pc == 0)
4726 {
4727 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4728 mismatch_detail->error = _("previous `movprfx' sequence not closed");
4729 mismatch_detail->index = -1;
4730 mismatch_detail->non_fatal = TRUE;
4731 res = ERR_VFI;
4732 /* Reset the sequence. */
4733 init_insn_sequence (NULL, insn_sequence);
4734 return res;
4735 }
4736
4737 /* Validate C_SCAN_MOVPRFX constraints. Move this to a lookup table. */
4738 if (inst_opcode->constraints & C_SCAN_MOVPRFX)
4739 {
4740 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4741 instruction for better error messages. */
4742 if (!opcode->avariant || !(*opcode->avariant & AARCH64_FEATURE_SVE))
4743 {
4744 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4745 mismatch_detail->error = _("SVE instruction expected after "
4746 "`movprfx'");
4747 mismatch_detail->index = -1;
4748 mismatch_detail->non_fatal = TRUE;
4749 res = ERR_VFI;
4750 goto done;
4751 }
4752
4753 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4754 instruction that is allowed to be used with a MOVPRFX. */
4755 if (!(opcode->constraints & C_SCAN_MOVPRFX))
4756 {
4757 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4758 mismatch_detail->error = _("SVE `movprfx' compatible instruction "
4759 "expected");
4760 mismatch_detail->index = -1;
4761 mismatch_detail->non_fatal = TRUE;
4762 res = ERR_VFI;
4763 goto done;
4764 }
4765
4766 /* Next check for usage of the predicate register. */
4767 aarch64_opnd_info blk_dest = insn_sequence->instr->operands[0];
780f601c
TC		 4768 aarch64_opnd_info blk_pred, inst_pred;
4769 memset (&blk_pred, 0, sizeof (aarch64_opnd_info));
4770 memset (&inst_pred, 0, sizeof (aarch64_opnd_info));
a68f4cd2
TC		 4771 bfd_boolean predicated = FALSE;
4772 assert (blk_dest.type == AARCH64_OPND_SVE_Zd);
4773
4774 /* Determine if the movprfx instruction used is predicated or not. */
4775 if (insn_sequence->instr->operands[1].type == AARCH64_OPND_SVE_Pg3)
4776 {
4777 predicated = TRUE;
4778 blk_pred = insn_sequence->instr->operands[1];
4779 }
4780
4781 unsigned char max_elem_size = 0;
4782 unsigned char current_elem_size;
4783 int num_op_used = 0, last_op_usage = 0;
4784 int i, inst_pred_idx = -1;
4785 int num_ops = aarch64_num_of_operands (opcode);
4786 for (i = 0; i < num_ops; i++)
4787 {
4788 aarch64_opnd_info inst_op = inst->operands[i];
4789 switch (inst_op.type)
4790 {
4791 case AARCH64_OPND_SVE_Zd:
4792 case AARCH64_OPND_SVE_Zm_5:
4793 case AARCH64_OPND_SVE_Zm_16:
4794 case AARCH64_OPND_SVE_Zn:
4795 case AARCH64_OPND_SVE_Zt:
4796 case AARCH64_OPND_SVE_Vm:
4797 case AARCH64_OPND_SVE_Vn:
4798 case AARCH64_OPND_Va:
4799 case AARCH64_OPND_Vn:
4800 case AARCH64_OPND_Vm:
4801 case AARCH64_OPND_Sn:
4802 case AARCH64_OPND_Sm:
4803 case AARCH64_OPND_Rn:
4804 case AARCH64_OPND_Rm:
4805 case AARCH64_OPND_Rn_SP:
4806 case AARCH64_OPND_Rm_SP:
4807 if (inst_op.reg.regno == blk_dest.reg.regno)
4808 {
4809 num_op_used++;
4810 last_op_usage = i;
4811 }
4812 current_elem_size
4813 = aarch64_get_qualifier_esize (inst_op.qualifier);
4814 if (current_elem_size > max_elem_size)
4815 max_elem_size = current_elem_size;
4816 break;
4817 case AARCH64_OPND_SVE_Pd:
4818 case AARCH64_OPND_SVE_Pg3:
4819 case AARCH64_OPND_SVE_Pg4_5:
4820 case AARCH64_OPND_SVE_Pg4_10:
4821 case AARCH64_OPND_SVE_Pg4_16:
4822 case AARCH64_OPND_SVE_Pm:
4823 case AARCH64_OPND_SVE_Pn:
4824 case AARCH64_OPND_SVE_Pt:
4825 inst_pred = inst_op;
4826 inst_pred_idx = i;
4827 break;
4828 default:
4829 break;
4830 }
4831 }
4832
4833 assert (max_elem_size != 0);
4834 aarch64_opnd_info inst_dest = inst->operands[0];
4835 /* Determine the size that should be used to compare against the
4836 movprfx size. */
4837 current_elem_size
4838 = opcode->constraints & C_MAX_ELEM
4839 ? max_elem_size
4840 : aarch64_get_qualifier_esize (inst_dest.qualifier);
4841
4842 /* If movprfx is predicated do some extra checks. */
4843 if (predicated)
4844 {
4845 /* The instruction must be predicated. */
4846 if (inst_pred_idx < 0)
4847 {
4848 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4849 mismatch_detail->error = _("predicated instruction expected "
4850 "after `movprfx'");
4851 mismatch_detail->index = -1;
4852 mismatch_detail->non_fatal = TRUE;
4853 res = ERR_VFI;
4854 goto done;
4855 }
4856
4857 /* The instruction must have a merging predicate. */
4858 if (inst_pred.qualifier != AARCH64_OPND_QLF_P_M)
4859 {
4860 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4861 mismatch_detail->error = _("merging predicate expected due "
4862 "to preceding `movprfx'");
4863 mismatch_detail->index = inst_pred_idx;
4864 mismatch_detail->non_fatal = TRUE;
4865 res = ERR_VFI;
4866 goto done;
4867 }
4868
4869 /* The same register must be used in instruction. */
4870 if (blk_pred.reg.regno != inst_pred.reg.regno)
4871 {
4872 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4873 mismatch_detail->error = _("predicate register differs "
4874 "from that in preceding "
4875 "`movprfx'");
4876 mismatch_detail->index = inst_pred_idx;
4877 mismatch_detail->non_fatal = TRUE;
4878 res = ERR_VFI;
4879 goto done;
4880 }
4881 }
4882
4883 /* Destructive operations by definition must allow one usage of the
4884 same register. */
4885 int allowed_usage
4886 = aarch64_is_destructive_by_operands (opcode) ? 2 : 1;
4887
4888 /* Operand is not used at all. */
4889 if (num_op_used == 0)
4890 {
4891 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4892 mismatch_detail->error = _("output register of preceding "
4893 "`movprfx' not used in current "
4894 "instruction");
4895 mismatch_detail->index = 0;
4896 mismatch_detail->non_fatal = TRUE;
4897 res = ERR_VFI;
4898 goto done;
4899 }
4900
4901 /* We now know it's used, now determine exactly where it's used. */
4902 if (blk_dest.reg.regno != inst_dest.reg.regno)
4903 {
4904 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4905 mismatch_detail->error = _("output register of preceding "
4906 "`movprfx' expected as output");
4907 mismatch_detail->index = 0;
4908 mismatch_detail->non_fatal = TRUE;
4909 res = ERR_VFI;
4910 goto done;
4911 }
4912
4913 /* Operand used more than allowed for the specific opcode type. */
4914 if (num_op_used > allowed_usage)
4915 {
4916 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4917 mismatch_detail->error = _("output register of preceding "
4918 "`movprfx' used as input");
4919 mismatch_detail->index = last_op_usage;
4920 mismatch_detail->non_fatal = TRUE;
4921 res = ERR_VFI;
4922 goto done;
4923 }
4924
4925 /* Now the only thing left is the qualifiers checks. The register
4926 must have the same maximum element size. */
4927 if (inst_dest.qualifier
4928 && blk_dest.qualifier
4929 && current_elem_size
4930 != aarch64_get_qualifier_esize (blk_dest.qualifier))
4931 {
4932 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4933 mismatch_detail->error = _("register size not compatible with "
4934 "previous `movprfx'");
4935 mismatch_detail->index = 0;
4936 mismatch_detail->non_fatal = TRUE;
4937 res = ERR_VFI;
4938 goto done;
4939 }
4940 }
4941
4942done:
4943 /* Add the new instruction to the sequence. */
4944 memcpy (insn_sequence->current_insns + insn_sequence->next_insn++,
4945 inst, sizeof (aarch64_inst));
4946
4947 /* Check if sequence is now full. */
4948 if (insn_sequence->next_insn >= insn_sequence->num_insns)
4949 {
4950 /* Sequence is full, but we don't have anything special to do for now,
4951 so clear and reset it. */
4952 init_insn_sequence (NULL, insn_sequence);
4953 }
4954 }
4955
4956 return res;
4957}
4958
4959
e950b345
RS		 4960/* Return true if VALUE cannot be moved into an SVE register using DUP
4961 (with any element size, not just ESIZE) and if using DUPM would
4962 therefore be OK. ESIZE is the number of bytes in the immediate. */
4963
4964bfd_boolean
4965aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue, int esize)
4966{
4967 int64_t svalue = uvalue;
4968 uint64_t upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
4969
4970 if ((uvalue & ~upper) != uvalue && (uvalue | upper) != uvalue)
4971 return FALSE;
4972 if (esize <= 4 || (uint32_t) uvalue == (uint32_t) (uvalue >> 32))
4973 {
4974 svalue = (int32_t) uvalue;
4975 if (esize <= 2 || (uint16_t) uvalue == (uint16_t) (uvalue >> 16))
4976 {
4977 svalue = (int16_t) uvalue;
4978 if (esize == 1 || (uint8_t) uvalue == (uint8_t) (uvalue >> 8))
4979 return FALSE;
4980 }
4981 }
4982 if ((svalue & 0xff) == 0)
4983 svalue /= 256;
4984 return svalue < -128 || svalue >= 128;
4985}
4986
a06ea964
NC		 4987/* Include the opcode description table as well as the operand description
4988 table. */
20f55f38 4989#define VERIFIER(x) verify_##x
a06ea964 4990#include "aarch64-tbl.h"
GDB Binutils - Deliverables
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