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a06ea964 | 1 | /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c. |
2571583a | 2 | Copyright (C) 2012-2017 Free Software Foundation, Inc. |
a06ea964 NC |
3 | Contributed by ARM Ltd. |
4 | ||
5 | This file is part of the GNU opcodes library. | |
6 | ||
7 | This library is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11 | ||
12 | It is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; see the file COPYING3. If not, | |
19 | see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #ifndef OPCODES_AARCH64_OPC_H | |
22 | #define OPCODES_AARCH64_OPC_H | |
23 | ||
24 | #include <string.h> | |
25 | #include "opcode/aarch64.h" | |
26 | ||
27 | /* Instruction fields. | |
28 | Keep synced with fields. */ | |
29 | enum aarch64_field_kind | |
30 | { | |
31 | FLD_NIL, | |
32 | FLD_cond2, | |
33 | FLD_nzcv, | |
34 | FLD_defgh, | |
35 | FLD_abc, | |
36 | FLD_imm19, | |
37 | FLD_immhi, | |
38 | FLD_immlo, | |
39 | FLD_size, | |
40 | FLD_vldst_size, | |
41 | FLD_op, | |
42 | FLD_Q, | |
43 | FLD_Rt, | |
44 | FLD_Rd, | |
45 | FLD_Rn, | |
46 | FLD_Rt2, | |
47 | FLD_Ra, | |
48 | FLD_op2, | |
49 | FLD_CRm, | |
50 | FLD_CRn, | |
51 | FLD_op1, | |
52 | FLD_op0, | |
53 | FLD_imm3, | |
54 | FLD_cond, | |
55 | FLD_opcode, | |
56 | FLD_cmode, | |
57 | FLD_asisdlso_opcode, | |
58 | FLD_len, | |
59 | FLD_Rm, | |
60 | FLD_Rs, | |
61 | FLD_option, | |
62 | FLD_S, | |
63 | FLD_hw, | |
64 | FLD_opc, | |
65 | FLD_opc1, | |
66 | FLD_shift, | |
67 | FLD_type, | |
68 | FLD_ldst_size, | |
69 | FLD_imm6, | |
70 | FLD_imm4, | |
71 | FLD_imm5, | |
72 | FLD_imm7, | |
73 | FLD_imm8, | |
74 | FLD_imm9, | |
75 | FLD_imm12, | |
76 | FLD_imm14, | |
77 | FLD_imm16, | |
78 | FLD_imm26, | |
79 | FLD_imms, | |
80 | FLD_immr, | |
81 | FLD_immb, | |
82 | FLD_immh, | |
3f06e550 | 83 | FLD_S_imm10, |
a06ea964 NC |
84 | FLD_N, |
85 | FLD_index, | |
86 | FLD_index2, | |
87 | FLD_sf, | |
ee804238 | 88 | FLD_lse_sz, |
a06ea964 NC |
89 | FLD_H, |
90 | FLD_L, | |
91 | FLD_M, | |
92 | FLD_b5, | |
93 | FLD_b40, | |
94 | FLD_scale, | |
116b6019 RS |
95 | FLD_SVE_M_4, |
96 | FLD_SVE_M_14, | |
97 | FLD_SVE_M_16, | |
e950b345 | 98 | FLD_SVE_N, |
f11ad6bc RS |
99 | FLD_SVE_Pd, |
100 | FLD_SVE_Pg3, | |
101 | FLD_SVE_Pg4_5, | |
102 | FLD_SVE_Pg4_10, | |
103 | FLD_SVE_Pg4_16, | |
104 | FLD_SVE_Pm, | |
105 | FLD_SVE_Pn, | |
106 | FLD_SVE_Pt, | |
047cd301 RS |
107 | FLD_SVE_Rm, |
108 | FLD_SVE_Rn, | |
109 | FLD_SVE_Vd, | |
110 | FLD_SVE_Vm, | |
111 | FLD_SVE_Vn, | |
f11ad6bc RS |
112 | FLD_SVE_Za_5, |
113 | FLD_SVE_Za_16, | |
114 | FLD_SVE_Zd, | |
115 | FLD_SVE_Zm_5, | |
116 | FLD_SVE_Zm_16, | |
117 | FLD_SVE_Zn, | |
118 | FLD_SVE_Zt, | |
165d4950 | 119 | FLD_SVE_i1, |
e950b345 | 120 | FLD_SVE_imm3, |
2442d846 | 121 | FLD_SVE_imm4, |
e950b345 RS |
122 | FLD_SVE_imm5, |
123 | FLD_SVE_imm5b, | |
4df068de | 124 | FLD_SVE_imm6, |
e950b345 RS |
125 | FLD_SVE_imm7, |
126 | FLD_SVE_imm8, | |
127 | FLD_SVE_imm9, | |
128 | FLD_SVE_immr, | |
129 | FLD_SVE_imms, | |
4df068de | 130 | FLD_SVE_msz, |
245d2e3f RS |
131 | FLD_SVE_pattern, |
132 | FLD_SVE_prfop, | |
116b6019 RS |
133 | FLD_SVE_sz, |
134 | FLD_SVE_tsz, | |
f11ad6bc | 135 | FLD_SVE_tszh, |
116b6019 RS |
136 | FLD_SVE_tszl_8, |
137 | FLD_SVE_tszl_19, | |
4df068de RS |
138 | FLD_SVE_xs_14, |
139 | FLD_SVE_xs_22, | |
c2c4ff8d SN |
140 | FLD_rotate1, |
141 | FLD_rotate2, | |
142 | FLD_rotate3, | |
a06ea964 NC |
143 | }; |
144 | ||
145 | /* Field description. */ | |
146 | struct aarch64_field | |
147 | { | |
148 | int lsb; | |
149 | int width; | |
150 | }; | |
151 | ||
152 | typedef struct aarch64_field aarch64_field; | |
153 | ||
154 | extern const aarch64_field fields[]; | |
155 | \f | |
156 | /* Operand description. */ | |
157 | ||
158 | struct aarch64_operand | |
159 | { | |
160 | enum aarch64_operand_class op_class; | |
161 | ||
162 | /* Name of the operand code; used mainly for the purpose of internal | |
163 | debugging. */ | |
164 | const char *name; | |
165 | ||
166 | unsigned int flags; | |
167 | ||
168 | /* The associated instruction bit-fields; no operand has more than 4 | |
169 | bit-fields */ | |
170 | enum aarch64_field_kind fields[4]; | |
171 | ||
172 | /* Brief description */ | |
173 | const char *desc; | |
174 | }; | |
175 | ||
176 | typedef struct aarch64_operand aarch64_operand; | |
177 | ||
178 | extern const aarch64_operand aarch64_operands[]; | |
179 | ||
180 | /* Operand flags. */ | |
181 | ||
182 | #define OPD_F_HAS_INSERTER 0x00000001 | |
183 | #define OPD_F_HAS_EXTRACTOR 0x00000002 | |
184 | #define OPD_F_SEXT 0x00000004 /* Require sign-extension. */ | |
185 | #define OPD_F_SHIFT_BY_2 0x00000008 /* Need to left shift the field | |
186 | value by 2 to get the value | |
187 | of an immediate operand. */ | |
188 | #define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */ | |
4df068de RS |
189 | #define OPD_F_OD_MASK 0x00000060 /* Operand-dependent data. */ |
190 | #define OPD_F_OD_LSB 5 | |
191 | #define OPD_F_NO_ZR 0x00000080 /* ZR index not allowed. */ | |
a06ea964 NC |
192 | |
193 | static inline bfd_boolean | |
194 | operand_has_inserter (const aarch64_operand *operand) | |
195 | { | |
196 | return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE; | |
197 | } | |
198 | ||
199 | static inline bfd_boolean | |
200 | operand_has_extractor (const aarch64_operand *operand) | |
201 | { | |
202 | return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE; | |
203 | } | |
204 | ||
205 | static inline bfd_boolean | |
206 | operand_need_sign_extension (const aarch64_operand *operand) | |
207 | { | |
208 | return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE; | |
209 | } | |
210 | ||
211 | static inline bfd_boolean | |
212 | operand_need_shift_by_two (const aarch64_operand *operand) | |
213 | { | |
214 | return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE; | |
215 | } | |
216 | ||
217 | static inline bfd_boolean | |
218 | operand_maybe_stack_pointer (const aarch64_operand *operand) | |
219 | { | |
220 | return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE; | |
221 | } | |
222 | ||
4df068de RS |
223 | /* Return the value of the operand-specific data field (OPD_F_OD_MASK). */ |
224 | static inline unsigned int | |
225 | get_operand_specific_data (const aarch64_operand *operand) | |
226 | { | |
227 | return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB; | |
228 | } | |
229 | ||
a06ea964 NC |
230 | /* Return the total width of the operand *OPERAND. */ |
231 | static inline unsigned | |
232 | get_operand_fields_width (const aarch64_operand *operand) | |
233 | { | |
234 | int i = 0; | |
235 | unsigned width = 0; | |
236 | while (operand->fields[i] != FLD_NIL) | |
237 | width += fields[operand->fields[i++]].width; | |
238 | assert (width > 0 && width < 32); | |
239 | return width; | |
240 | } | |
241 | ||
242 | static inline const aarch64_operand * | |
243 | get_operand_from_code (enum aarch64_opnd code) | |
244 | { | |
245 | return aarch64_operands + code; | |
246 | } | |
247 | \f | |
248 | /* Operand qualifier and operand constraint checking. */ | |
249 | ||
250 | int aarch64_match_operands_constraint (aarch64_inst *, | |
251 | aarch64_operand_error *); | |
252 | ||
253 | /* Operand qualifier related functions. */ | |
254 | const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t); | |
255 | unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t); | |
256 | aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t); | |
257 | int aarch64_find_best_match (const aarch64_inst *, | |
258 | const aarch64_opnd_qualifier_seq_t *, | |
259 | int, aarch64_opnd_qualifier_t *); | |
260 | ||
261 | static inline void | |
262 | reset_operand_qualifier (aarch64_inst *inst, int idx) | |
263 | { | |
264 | assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode)); | |
265 | inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL; | |
266 | } | |
267 | \f | |
268 | /* Inline functions operating on instruction bit-field(s). */ | |
269 | ||
270 | /* Generate a mask that has WIDTH number of consecutive 1s. */ | |
271 | ||
272 | static inline aarch64_insn | |
273 | gen_mask (int width) | |
274 | { | |
5bb3703f | 275 | return ((aarch64_insn) 1 << width) - 1; |
a06ea964 NC |
276 | } |
277 | ||
278 | /* LSB_REL is the relative location of the lsb in the sub field, starting from 0. */ | |
279 | static inline int | |
280 | gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret) | |
281 | { | |
282 | const aarch64_field *field = &fields[kind]; | |
283 | if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width) | |
284 | return 0; | |
285 | ret->lsb = field->lsb + lsb_rel; | |
286 | ret->width = width; | |
287 | return 1; | |
288 | } | |
289 | ||
290 | /* Insert VALUE into FIELD of CODE. MASK can be zero or the base mask | |
291 | of the opcode. */ | |
292 | ||
293 | static inline void | |
294 | insert_field_2 (const aarch64_field *field, aarch64_insn *code, | |
295 | aarch64_insn value, aarch64_insn mask) | |
296 | { | |
297 | assert (field->width < 32 && field->width >= 1 && field->lsb >= 0 | |
298 | && field->lsb + field->width <= 32); | |
299 | value &= gen_mask (field->width); | |
300 | value <<= field->lsb; | |
301 | /* In some opcodes, field can be part of the base opcode, e.g. the size | |
302 | field in FADD. The following helps avoid corrupt the base opcode. */ | |
303 | value &= ~mask; | |
304 | *code |= value; | |
305 | } | |
306 | ||
307 | /* Extract FIELD of CODE and return the value. MASK can be zero or the base | |
308 | mask of the opcode. */ | |
309 | ||
310 | static inline aarch64_insn | |
311 | extract_field_2 (const aarch64_field *field, aarch64_insn code, | |
312 | aarch64_insn mask) | |
313 | { | |
314 | aarch64_insn value; | |
315 | /* Clear any bit that is a part of the base opcode. */ | |
316 | code &= ~mask; | |
317 | value = (code >> field->lsb) & gen_mask (field->width); | |
318 | return value; | |
319 | } | |
320 | ||
321 | /* Insert VALUE into field KIND of CODE. MASK can be zero or the base mask | |
322 | of the opcode. */ | |
323 | ||
324 | static inline void | |
325 | insert_field (enum aarch64_field_kind kind, aarch64_insn *code, | |
326 | aarch64_insn value, aarch64_insn mask) | |
327 | { | |
328 | insert_field_2 (&fields[kind], code, value, mask); | |
329 | } | |
330 | ||
331 | /* Extract field KIND of CODE and return the value. MASK can be zero or the | |
332 | base mask of the opcode. */ | |
333 | ||
334 | static inline aarch64_insn | |
335 | extract_field (enum aarch64_field_kind kind, aarch64_insn code, | |
336 | aarch64_insn mask) | |
337 | { | |
338 | return extract_field_2 (&fields[kind], code, mask); | |
339 | } | |
c0890d26 RS |
340 | |
341 | extern aarch64_insn | |
342 | extract_fields (aarch64_insn code, aarch64_insn mask, ...); | |
a06ea964 NC |
343 | \f |
344 | /* Inline functions selecting operand to do the encoding/decoding for a | |
345 | certain instruction bit-field. */ | |
346 | ||
347 | /* Select the operand to do the encoding/decoding of the 'sf' field. | |
348 | The heuristic-based rule is that the result operand is respected more. */ | |
349 | ||
350 | static inline int | |
351 | select_operand_for_sf_field_coding (const aarch64_opcode *opcode) | |
352 | { | |
353 | int idx = -1; | |
354 | if (aarch64_get_operand_class (opcode->operands[0]) | |
355 | == AARCH64_OPND_CLASS_INT_REG) | |
356 | /* normal case. */ | |
357 | idx = 0; | |
358 | else if (aarch64_get_operand_class (opcode->operands[1]) | |
359 | == AARCH64_OPND_CLASS_INT_REG) | |
360 | /* e.g. float2fix. */ | |
361 | idx = 1; | |
362 | else | |
363 | { assert (0); abort (); } | |
364 | return idx; | |
365 | } | |
366 | ||
367 | /* Select the operand to do the encoding/decoding of the 'type' field in | |
368 | the floating-point instructions. | |
369 | The heuristic-based rule is that the source operand is respected more. */ | |
370 | ||
371 | static inline int | |
372 | select_operand_for_fptype_field_coding (const aarch64_opcode *opcode) | |
373 | { | |
374 | int idx; | |
375 | if (aarch64_get_operand_class (opcode->operands[1]) | |
376 | == AARCH64_OPND_CLASS_FP_REG) | |
377 | /* normal case. */ | |
378 | idx = 1; | |
379 | else if (aarch64_get_operand_class (opcode->operands[0]) | |
380 | == AARCH64_OPND_CLASS_FP_REG) | |
381 | /* e.g. float2fix. */ | |
382 | idx = 0; | |
383 | else | |
384 | { assert (0); abort (); } | |
385 | return idx; | |
386 | } | |
387 | ||
388 | /* Select the operand to do the encoding/decoding of the 'size' field in | |
389 | the AdvSIMD scalar instructions. | |
390 | The heuristic-based rule is that the destination operand is respected | |
391 | more. */ | |
392 | ||
393 | static inline int | |
394 | select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode) | |
395 | { | |
396 | int src_size = 0, dst_size = 0; | |
397 | if (aarch64_get_operand_class (opcode->operands[0]) | |
398 | == AARCH64_OPND_CLASS_SISD_REG) | |
399 | dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]); | |
400 | if (aarch64_get_operand_class (opcode->operands[1]) | |
401 | == AARCH64_OPND_CLASS_SISD_REG) | |
402 | src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]); | |
403 | if (src_size == dst_size && src_size == 0) | |
404 | { assert (0); abort (); } | |
405 | /* When the result is not a sisd register or it is a long operantion. */ | |
406 | if (dst_size == 0 || dst_size == src_size << 1) | |
407 | return 1; | |
408 | else | |
409 | return 0; | |
410 | } | |
411 | ||
412 | /* Select the operand to do the encoding/decoding of the 'size:Q' fields in | |
413 | the AdvSIMD instructions. */ | |
414 | ||
415 | int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *); | |
416 | \f | |
417 | /* Miscellaneous. */ | |
418 | ||
419 | aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind); | |
420 | enum aarch64_modifier_kind | |
421 | aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean); | |
422 | ||
423 | ||
424 | bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *); | |
425 | bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *); | |
426 | int aarch64_shrink_expanded_imm8 (uint64_t); | |
427 | ||
428 | /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST]. */ | |
429 | static inline void | |
430 | copy_operand_info (aarch64_inst *inst, int dst, int src) | |
431 | { | |
432 | assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM | |
433 | && src < AARCH64_MAX_OPND_NUM); | |
434 | memcpy (&inst->operands[dst], &inst->operands[src], | |
435 | sizeof (aarch64_opnd_info)); | |
436 | inst->operands[dst].idx = dst; | |
437 | } | |
438 | ||
439 | /* A primitive log caculator. */ | |
440 | ||
441 | static inline unsigned int | |
442 | get_logsz (unsigned int size) | |
443 | { | |
444 | const unsigned char ls[16] = | |
445 | {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4}; | |
446 | if (size > 16) | |
447 | { | |
448 | assert (0); | |
449 | return -1; | |
450 | } | |
451 | assert (ls[size - 1] != (unsigned char)-1); | |
452 | return ls[size - 1]; | |
453 | } | |
454 | ||
455 | #endif /* OPCODES_AARCH64_OPC_H */ |