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a06ea964 | 1 | /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c. |
6f2750fe | 2 | Copyright (C) 2012-2016 Free Software Foundation, Inc. |
a06ea964 NC |
3 | Contributed by ARM Ltd. |
4 | ||
5 | This file is part of the GNU opcodes library. | |
6 | ||
7 | This library is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11 | ||
12 | It is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; see the file COPYING3. If not, | |
19 | see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #ifndef OPCODES_AARCH64_OPC_H | |
22 | #define OPCODES_AARCH64_OPC_H | |
23 | ||
24 | #include <string.h> | |
25 | #include "opcode/aarch64.h" | |
26 | ||
27 | /* Instruction fields. | |
28 | Keep synced with fields. */ | |
29 | enum aarch64_field_kind | |
30 | { | |
31 | FLD_NIL, | |
32 | FLD_cond2, | |
33 | FLD_nzcv, | |
34 | FLD_defgh, | |
35 | FLD_abc, | |
36 | FLD_imm19, | |
37 | FLD_immhi, | |
38 | FLD_immlo, | |
39 | FLD_size, | |
40 | FLD_vldst_size, | |
41 | FLD_op, | |
42 | FLD_Q, | |
43 | FLD_Rt, | |
44 | FLD_Rd, | |
45 | FLD_Rn, | |
46 | FLD_Rt2, | |
47 | FLD_Ra, | |
48 | FLD_op2, | |
49 | FLD_CRm, | |
50 | FLD_CRn, | |
51 | FLD_op1, | |
52 | FLD_op0, | |
53 | FLD_imm3, | |
54 | FLD_cond, | |
55 | FLD_opcode, | |
56 | FLD_cmode, | |
57 | FLD_asisdlso_opcode, | |
58 | FLD_len, | |
59 | FLD_Rm, | |
60 | FLD_Rs, | |
61 | FLD_option, | |
62 | FLD_S, | |
63 | FLD_hw, | |
64 | FLD_opc, | |
65 | FLD_opc1, | |
66 | FLD_shift, | |
67 | FLD_type, | |
68 | FLD_ldst_size, | |
69 | FLD_imm6, | |
70 | FLD_imm4, | |
71 | FLD_imm5, | |
72 | FLD_imm7, | |
73 | FLD_imm8, | |
74 | FLD_imm9, | |
75 | FLD_imm12, | |
76 | FLD_imm14, | |
77 | FLD_imm16, | |
78 | FLD_imm26, | |
79 | FLD_imms, | |
80 | FLD_immr, | |
81 | FLD_immb, | |
82 | FLD_immh, | |
83 | FLD_N, | |
84 | FLD_index, | |
85 | FLD_index2, | |
86 | FLD_sf, | |
ee804238 | 87 | FLD_lse_sz, |
a06ea964 NC |
88 | FLD_H, |
89 | FLD_L, | |
90 | FLD_M, | |
91 | FLD_b5, | |
92 | FLD_b40, | |
93 | FLD_scale, | |
e950b345 | 94 | FLD_SVE_N, |
f11ad6bc RS |
95 | FLD_SVE_Pd, |
96 | FLD_SVE_Pg3, | |
97 | FLD_SVE_Pg4_5, | |
98 | FLD_SVE_Pg4_10, | |
99 | FLD_SVE_Pg4_16, | |
100 | FLD_SVE_Pm, | |
101 | FLD_SVE_Pn, | |
102 | FLD_SVE_Pt, | |
103 | FLD_SVE_Za_5, | |
104 | FLD_SVE_Za_16, | |
105 | FLD_SVE_Zd, | |
106 | FLD_SVE_Zm_5, | |
107 | FLD_SVE_Zm_16, | |
108 | FLD_SVE_Zn, | |
109 | FLD_SVE_Zt, | |
165d4950 | 110 | FLD_SVE_i1, |
e950b345 | 111 | FLD_SVE_imm3, |
2442d846 | 112 | FLD_SVE_imm4, |
e950b345 RS |
113 | FLD_SVE_imm5, |
114 | FLD_SVE_imm5b, | |
4df068de | 115 | FLD_SVE_imm6, |
e950b345 RS |
116 | FLD_SVE_imm7, |
117 | FLD_SVE_imm8, | |
118 | FLD_SVE_imm9, | |
119 | FLD_SVE_immr, | |
120 | FLD_SVE_imms, | |
4df068de | 121 | FLD_SVE_msz, |
245d2e3f RS |
122 | FLD_SVE_pattern, |
123 | FLD_SVE_prfop, | |
f11ad6bc | 124 | FLD_SVE_tszh, |
4df068de RS |
125 | FLD_SVE_xs_14, |
126 | FLD_SVE_xs_22, | |
a06ea964 NC |
127 | }; |
128 | ||
129 | /* Field description. */ | |
130 | struct aarch64_field | |
131 | { | |
132 | int lsb; | |
133 | int width; | |
134 | }; | |
135 | ||
136 | typedef struct aarch64_field aarch64_field; | |
137 | ||
138 | extern const aarch64_field fields[]; | |
139 | \f | |
140 | /* Operand description. */ | |
141 | ||
142 | struct aarch64_operand | |
143 | { | |
144 | enum aarch64_operand_class op_class; | |
145 | ||
146 | /* Name of the operand code; used mainly for the purpose of internal | |
147 | debugging. */ | |
148 | const char *name; | |
149 | ||
150 | unsigned int flags; | |
151 | ||
152 | /* The associated instruction bit-fields; no operand has more than 4 | |
153 | bit-fields */ | |
154 | enum aarch64_field_kind fields[4]; | |
155 | ||
156 | /* Brief description */ | |
157 | const char *desc; | |
158 | }; | |
159 | ||
160 | typedef struct aarch64_operand aarch64_operand; | |
161 | ||
162 | extern const aarch64_operand aarch64_operands[]; | |
163 | ||
164 | /* Operand flags. */ | |
165 | ||
166 | #define OPD_F_HAS_INSERTER 0x00000001 | |
167 | #define OPD_F_HAS_EXTRACTOR 0x00000002 | |
168 | #define OPD_F_SEXT 0x00000004 /* Require sign-extension. */ | |
169 | #define OPD_F_SHIFT_BY_2 0x00000008 /* Need to left shift the field | |
170 | value by 2 to get the value | |
171 | of an immediate operand. */ | |
172 | #define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */ | |
4df068de RS |
173 | #define OPD_F_OD_MASK 0x00000060 /* Operand-dependent data. */ |
174 | #define OPD_F_OD_LSB 5 | |
175 | #define OPD_F_NO_ZR 0x00000080 /* ZR index not allowed. */ | |
a06ea964 NC |
176 | |
177 | static inline bfd_boolean | |
178 | operand_has_inserter (const aarch64_operand *operand) | |
179 | { | |
180 | return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE; | |
181 | } | |
182 | ||
183 | static inline bfd_boolean | |
184 | operand_has_extractor (const aarch64_operand *operand) | |
185 | { | |
186 | return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE; | |
187 | } | |
188 | ||
189 | static inline bfd_boolean | |
190 | operand_need_sign_extension (const aarch64_operand *operand) | |
191 | { | |
192 | return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE; | |
193 | } | |
194 | ||
195 | static inline bfd_boolean | |
196 | operand_need_shift_by_two (const aarch64_operand *operand) | |
197 | { | |
198 | return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE; | |
199 | } | |
200 | ||
201 | static inline bfd_boolean | |
202 | operand_maybe_stack_pointer (const aarch64_operand *operand) | |
203 | { | |
204 | return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE; | |
205 | } | |
206 | ||
4df068de RS |
207 | /* Return the value of the operand-specific data field (OPD_F_OD_MASK). */ |
208 | static inline unsigned int | |
209 | get_operand_specific_data (const aarch64_operand *operand) | |
210 | { | |
211 | return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB; | |
212 | } | |
213 | ||
a06ea964 NC |
214 | /* Return the total width of the operand *OPERAND. */ |
215 | static inline unsigned | |
216 | get_operand_fields_width (const aarch64_operand *operand) | |
217 | { | |
218 | int i = 0; | |
219 | unsigned width = 0; | |
220 | while (operand->fields[i] != FLD_NIL) | |
221 | width += fields[operand->fields[i++]].width; | |
222 | assert (width > 0 && width < 32); | |
223 | return width; | |
224 | } | |
225 | ||
226 | static inline const aarch64_operand * | |
227 | get_operand_from_code (enum aarch64_opnd code) | |
228 | { | |
229 | return aarch64_operands + code; | |
230 | } | |
231 | \f | |
232 | /* Operand qualifier and operand constraint checking. */ | |
233 | ||
234 | int aarch64_match_operands_constraint (aarch64_inst *, | |
235 | aarch64_operand_error *); | |
236 | ||
237 | /* Operand qualifier related functions. */ | |
238 | const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t); | |
239 | unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t); | |
240 | aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t); | |
241 | int aarch64_find_best_match (const aarch64_inst *, | |
242 | const aarch64_opnd_qualifier_seq_t *, | |
243 | int, aarch64_opnd_qualifier_t *); | |
244 | ||
245 | static inline void | |
246 | reset_operand_qualifier (aarch64_inst *inst, int idx) | |
247 | { | |
248 | assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode)); | |
249 | inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL; | |
250 | } | |
251 | \f | |
252 | /* Inline functions operating on instruction bit-field(s). */ | |
253 | ||
254 | /* Generate a mask that has WIDTH number of consecutive 1s. */ | |
255 | ||
256 | static inline aarch64_insn | |
257 | gen_mask (int width) | |
258 | { | |
5bb3703f | 259 | return ((aarch64_insn) 1 << width) - 1; |
a06ea964 NC |
260 | } |
261 | ||
262 | /* LSB_REL is the relative location of the lsb in the sub field, starting from 0. */ | |
263 | static inline int | |
264 | gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret) | |
265 | { | |
266 | const aarch64_field *field = &fields[kind]; | |
267 | if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width) | |
268 | return 0; | |
269 | ret->lsb = field->lsb + lsb_rel; | |
270 | ret->width = width; | |
271 | return 1; | |
272 | } | |
273 | ||
274 | /* Insert VALUE into FIELD of CODE. MASK can be zero or the base mask | |
275 | of the opcode. */ | |
276 | ||
277 | static inline void | |
278 | insert_field_2 (const aarch64_field *field, aarch64_insn *code, | |
279 | aarch64_insn value, aarch64_insn mask) | |
280 | { | |
281 | assert (field->width < 32 && field->width >= 1 && field->lsb >= 0 | |
282 | && field->lsb + field->width <= 32); | |
283 | value &= gen_mask (field->width); | |
284 | value <<= field->lsb; | |
285 | /* In some opcodes, field can be part of the base opcode, e.g. the size | |
286 | field in FADD. The following helps avoid corrupt the base opcode. */ | |
287 | value &= ~mask; | |
288 | *code |= value; | |
289 | } | |
290 | ||
291 | /* Extract FIELD of CODE and return the value. MASK can be zero or the base | |
292 | mask of the opcode. */ | |
293 | ||
294 | static inline aarch64_insn | |
295 | extract_field_2 (const aarch64_field *field, aarch64_insn code, | |
296 | aarch64_insn mask) | |
297 | { | |
298 | aarch64_insn value; | |
299 | /* Clear any bit that is a part of the base opcode. */ | |
300 | code &= ~mask; | |
301 | value = (code >> field->lsb) & gen_mask (field->width); | |
302 | return value; | |
303 | } | |
304 | ||
305 | /* Insert VALUE into field KIND of CODE. MASK can be zero or the base mask | |
306 | of the opcode. */ | |
307 | ||
308 | static inline void | |
309 | insert_field (enum aarch64_field_kind kind, aarch64_insn *code, | |
310 | aarch64_insn value, aarch64_insn mask) | |
311 | { | |
312 | insert_field_2 (&fields[kind], code, value, mask); | |
313 | } | |
314 | ||
315 | /* Extract field KIND of CODE and return the value. MASK can be zero or the | |
316 | base mask of the opcode. */ | |
317 | ||
318 | static inline aarch64_insn | |
319 | extract_field (enum aarch64_field_kind kind, aarch64_insn code, | |
320 | aarch64_insn mask) | |
321 | { | |
322 | return extract_field_2 (&fields[kind], code, mask); | |
323 | } | |
324 | \f | |
325 | /* Inline functions selecting operand to do the encoding/decoding for a | |
326 | certain instruction bit-field. */ | |
327 | ||
328 | /* Select the operand to do the encoding/decoding of the 'sf' field. | |
329 | The heuristic-based rule is that the result operand is respected more. */ | |
330 | ||
331 | static inline int | |
332 | select_operand_for_sf_field_coding (const aarch64_opcode *opcode) | |
333 | { | |
334 | int idx = -1; | |
335 | if (aarch64_get_operand_class (opcode->operands[0]) | |
336 | == AARCH64_OPND_CLASS_INT_REG) | |
337 | /* normal case. */ | |
338 | idx = 0; | |
339 | else if (aarch64_get_operand_class (opcode->operands[1]) | |
340 | == AARCH64_OPND_CLASS_INT_REG) | |
341 | /* e.g. float2fix. */ | |
342 | idx = 1; | |
343 | else | |
344 | { assert (0); abort (); } | |
345 | return idx; | |
346 | } | |
347 | ||
348 | /* Select the operand to do the encoding/decoding of the 'type' field in | |
349 | the floating-point instructions. | |
350 | The heuristic-based rule is that the source operand is respected more. */ | |
351 | ||
352 | static inline int | |
353 | select_operand_for_fptype_field_coding (const aarch64_opcode *opcode) | |
354 | { | |
355 | int idx; | |
356 | if (aarch64_get_operand_class (opcode->operands[1]) | |
357 | == AARCH64_OPND_CLASS_FP_REG) | |
358 | /* normal case. */ | |
359 | idx = 1; | |
360 | else if (aarch64_get_operand_class (opcode->operands[0]) | |
361 | == AARCH64_OPND_CLASS_FP_REG) | |
362 | /* e.g. float2fix. */ | |
363 | idx = 0; | |
364 | else | |
365 | { assert (0); abort (); } | |
366 | return idx; | |
367 | } | |
368 | ||
369 | /* Select the operand to do the encoding/decoding of the 'size' field in | |
370 | the AdvSIMD scalar instructions. | |
371 | The heuristic-based rule is that the destination operand is respected | |
372 | more. */ | |
373 | ||
374 | static inline int | |
375 | select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode) | |
376 | { | |
377 | int src_size = 0, dst_size = 0; | |
378 | if (aarch64_get_operand_class (opcode->operands[0]) | |
379 | == AARCH64_OPND_CLASS_SISD_REG) | |
380 | dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]); | |
381 | if (aarch64_get_operand_class (opcode->operands[1]) | |
382 | == AARCH64_OPND_CLASS_SISD_REG) | |
383 | src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]); | |
384 | if (src_size == dst_size && src_size == 0) | |
385 | { assert (0); abort (); } | |
386 | /* When the result is not a sisd register or it is a long operantion. */ | |
387 | if (dst_size == 0 || dst_size == src_size << 1) | |
388 | return 1; | |
389 | else | |
390 | return 0; | |
391 | } | |
392 | ||
393 | /* Select the operand to do the encoding/decoding of the 'size:Q' fields in | |
394 | the AdvSIMD instructions. */ | |
395 | ||
396 | int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *); | |
397 | \f | |
398 | /* Miscellaneous. */ | |
399 | ||
400 | aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind); | |
401 | enum aarch64_modifier_kind | |
402 | aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean); | |
403 | ||
404 | ||
405 | bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *); | |
406 | bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *); | |
407 | int aarch64_shrink_expanded_imm8 (uint64_t); | |
408 | ||
409 | /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST]. */ | |
410 | static inline void | |
411 | copy_operand_info (aarch64_inst *inst, int dst, int src) | |
412 | { | |
413 | assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM | |
414 | && src < AARCH64_MAX_OPND_NUM); | |
415 | memcpy (&inst->operands[dst], &inst->operands[src], | |
416 | sizeof (aarch64_opnd_info)); | |
417 | inst->operands[dst].idx = dst; | |
418 | } | |
419 | ||
420 | /* A primitive log caculator. */ | |
421 | ||
422 | static inline unsigned int | |
423 | get_logsz (unsigned int size) | |
424 | { | |
425 | const unsigned char ls[16] = | |
426 | {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4}; | |
427 | if (size > 16) | |
428 | { | |
429 | assert (0); | |
430 | return -1; | |
431 | } | |
432 | assert (ls[size - 1] != (unsigned char)-1); | |
433 | return ls[size - 1]; | |
434 | } | |
435 | ||
436 | #endif /* OPCODES_AARCH64_OPC_H */ |