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[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.
[deliverable/binutils-gdb.git] / opcodes / aarch64-tbl.h
CommitLineData
a06ea964
NC		 1/* aarch64-tbl.h -- AArch64 opcode description table and instruction
2 operand description table.
b90efa5b 3 Copyright (C) 2012-2015 Free Software Foundation, Inc.
a06ea964
NC		 4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22#include "aarch64-opc.h"
23
24/* Operand type. */
25
26#define OPND(x) AARCH64_OPND_##x
27#define OP0() {}
28#define OP1(a) {OPND(a)}
29#define OP2(a,b) {OPND(a), OPND(b)}
30#define OP3(a,b,c) {OPND(a), OPND(b), OPND(c)}
31#define OP4(a,b,c,d) {OPND(a), OPND(b), OPND(c), OPND(d)}
32#define OP5(a,b,c,d,e) {OPND(a), OPND(b), OPND(c), OPND(d), OPND(e)}
33
34#define QLF(x) AARCH64_OPND_QLF_##x
35#define QLF1(a) {QLF(a)}
36#define QLF2(a,b) {QLF(a), QLF(b)}
37#define QLF3(a,b,c) {QLF(a), QLF(b), QLF(c)}
38#define QLF4(a,b,c,d) {QLF(a), QLF(b), QLF(c), QLF(d)}
39#define QLF5(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e)}
40
41/* Qualifiers list. */
42
43/* e.g. MSR <systemreg>, <Xt>. */
44#define QL_SRC_X \
45{ \
46 QLF2(NIL,X), \
47}
48
49/* e.g. MRS <Xt>, <systemreg>. */
50#define QL_DST_X \
51{ \
52 QLF2(X,NIL), \
53}
54
55/* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */
56#define QL_SYS \
57{ \
58 QLF5(NIL,NIL,NIL,NIL,X), \
59}
60
61/* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */
62#define QL_SYSL \
63{ \
64 QLF5(X,NIL,NIL,NIL,NIL), \
65}
66
67/* e.g. ADRP <Xd>, <label>. */
68#define QL_ADRP \
69{ \
70 QLF2(X,NIL), \
71}
72
73/* e.g. B.<cond> <label>. */
74#define QL_PCREL_NIL \
75{ \
76 QLF1(NIL), \
77}
78
79/* e.g. TBZ <Xt>, #<imm>, <label>. */
80#define QL_PCREL_14 \
81{ \
82 QLF3(X,imm_0_63,NIL), \
83}
84
85/* e.g. BL <label>. */
86#define QL_PCREL_26 \
87{ \
88 QLF1(NIL), \
89}
90
91/* e.g. LDRSW <Xt>, <label>. */
92#define QL_X_PCREL \
93{ \
94 QLF2(X,NIL), \
95}
96
97/* e.g. LDR <Wt>, <label>. */
98#define QL_R_PCREL \
99{ \
100 QLF2(W,NIL), \
101 QLF2(X,NIL), \
102}
103
104/* e.g. LDR <Dt>, <label>. */
105#define QL_FP_PCREL \
106{ \
107 QLF2(S_S,NIL), \
108 QLF2(S_D,NIL), \
109 QLF2(S_Q,NIL), \
110}
111
112/* e.g. PRFM <prfop>, <label>. */
113#define QL_PRFM_PCREL \
114{ \
115 QLF2(NIL,NIL), \
116}
117
118/* e.g. BR <Xn>. */
119#define QL_I1X \
120{ \
121 QLF1(X), \
122}
123
124/* e.g. RBIT <Wd>, <Wn>. */
125#define QL_I2SAME \
126{ \
127 QLF2(W,W), \
128 QLF2(X,X), \
129}
130
131/* e.g. CMN <Wn|WSP>, <Wm>{, <extend> {#<amount>}}. */
132#define QL_I2_EXT \
133{ \
134 QLF2(W,W), \
135 QLF2(X,W), \
136 QLF2(X,X), \
137}
138
139/* e.g. MOV <Wd|WSP>, <Wn|WSP>, at least one SP. */
140#define QL_I2SP \
141{ \
142 QLF2(WSP,W), \
143 QLF2(W,WSP), \
144 QLF2(SP,X), \
145 QLF2(X,SP), \
146}
147
148/* e.g. REV <Wd>, <Wn>. */
149#define QL_I2SAMEW \
150{ \
151 QLF2(W,W), \
152}
153
154/* e.g. REV32 <Xd>, <Xn>. */
155#define QL_I2SAMEX \
156{ \
157 QLF2(X,X), \
158}
159
160#define QL_I2SAMER \
161{ \
162 QLF2(W,W), \
163 QLF2(X,X), \
164}
165
e60bb1dd
YZ		 166/* e.g. CRC32B <Wd>, <Wn>, <Wm>. */
167#define QL_I3SAMEW \
168{ \
169 QLF3(W,W,W), \
170}
171
a06ea964
NC		 172/* e.g. SMULH <Xd>, <Xn>, <Xm>. */
173#define QL_I3SAMEX \
174{ \
175 QLF3(X,X,X), \
176}
177
e60bb1dd
YZ		 178/* e.g. CRC32X <Wd>, <Wn>, <Xm>. */
179#define QL_I3WWX \
180{ \
181 QLF3(W,W,X), \
182}
183
a06ea964
NC		 184/* e.g. UDIV <Xd>, <Xn>, <Xm>. */
185#define QL_I3SAMER \
186{ \
187 QLF3(W,W,W), \
188 QLF3(X,X,X), \
189}
190
191/* e.g. ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}. */
192#define QL_I3_EXT \
193{ \
194 QLF3(W,W,W), \
195 QLF3(X,X,W), \
196 QLF3(X,X,X), \
197}
198
199/* e.g. MADD <Xd>, <Xn>, <Xm>, <Xa>. */
200#define QL_I4SAMER \
201{ \
202 QLF4(W,W,W,W), \
203 QLF4(X,X,X,X), \
204}
205
206/* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */
207#define QL_I3SAMEL \
208{ \
209 QLF3(X,W,W), \
210}
211
212/* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */
213#define QL_I4SAMEL \
214{ \
215 QLF4(X,W,W,X), \
216}
217
218/* e.g. CSINC <Xd>, <Xn>, <Xm>, <cond>. */
219#define QL_CSEL \
220{ \
221 QLF4(W, W, W, NIL), \
222 QLF4(X, X, X, NIL), \
223}
224
225/* e.g. CSET <Wd>, <cond>. */
226#define QL_DST_R \
227{ \
228 QLF2(W, NIL), \
229 QLF2(X, NIL), \
230}
231
232/* e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>. */
233#define QL_BF \
234{ \
235 QLF4(W,W,imm_0_31,imm_0_31), \
236 QLF4(X,X,imm_0_63,imm_0_63), \
237}
238
d685192a
MW		 239/* e.g. BFC <Wd>, #<immr>, #<imms>. */
240#define QL_BF1 \
241{ \
242 QLF3 (W, imm_0_31, imm_1_32), \
243 QLF3 (X, imm_0_63, imm_1_64), \
244}
245
a06ea964
NC		 246/* e.g. UBFIZ <Wd>, <Wn>, #<lsb>, #<width>. */
247#define QL_BF2 \
248{ \
249 QLF4(W,W,imm_0_31,imm_1_32), \
250 QLF4(X,X,imm_0_63,imm_1_64), \
251}
252
253/* e.g. SCVTF <Sd>, <Xn>, #<fbits>. */
254#define QL_FIX2FP \
255{ \
256 QLF3(S_D,W,imm_1_32), \
257 QLF3(S_S,W,imm_1_32), \
258 QLF3(S_D,X,imm_1_64), \
259 QLF3(S_S,X,imm_1_64), \
260}
261
622b9eb1
MW		 262/* e.g. SCVTF <Hd>, <Xn>, #<fbits>. */
263#define QL_FIX2FP_H \
264{ \
265 QLF3 (S_H, W, imm_1_32), \
266 QLF3 (S_H, X, imm_1_64), \
267}
268
a06ea964
NC		 269/* e.g. FCVTZS <Wd>, <Dn>, #<fbits>. */
270#define QL_FP2FIX \
271{ \
272 QLF3(W,S_D,imm_1_32), \
273 QLF3(W,S_S,imm_1_32), \
274 QLF3(X,S_D,imm_1_64), \
275 QLF3(X,S_S,imm_1_64), \
276}
277
622b9eb1
MW		 278/* e.g. FCVTZS <Wd>, <Hn>, #<fbits>. */
279#define QL_FP2FIX_H \
280{ \
281 QLF3 (W, S_H, imm_1_32), \
282 QLF3 (X, S_H, imm_1_64), \
283}
284
a06ea964
NC		 285/* e.g. SCVTF <Dd>, <Wn>. */
286#define QL_INT2FP \
287{ \
288 QLF2(S_D,W), \
289 QLF2(S_S,W), \
290 QLF2(S_D,X), \
291 QLF2(S_S,X), \
292}
293
622b9eb1
MW		 294/* e.g. SCVTF <Hd>, <Wn>. */
295#define QL_INT2FP_H \
296{ \
297 QLF2 (S_H, W), \
298 QLF2 (S_H, X), \
299}
300
a06ea964
NC		 301/* e.g. FCVTNS <Xd>, <Dn>. */
302#define QL_FP2INT \
303{ \
304 QLF2(W,S_D), \
305 QLF2(W,S_S), \
306 QLF2(X,S_D), \
307 QLF2(X,S_S), \
308}
309
622b9eb1
MW		 310/* e.g. FCVTNS <Hd>, <Wn>. */
311#define QL_FP2INT_H \
312{ \
313 QLF2 (W, S_H), \
314 QLF2 (X, S_H), \
315}
316
a06ea964
NC		 317/* e.g. FMOV <Xd>, <Vn>.D[1]. */
318#define QL_XVD1 \
319{ \
320 QLF2(X,S_D), \
321}
322
323/* e.g. FMOV <Vd>.D[1], <Xn>. */
324#define QL_VD1X \
325{ \
326 QLF2(S_D,X), \
327}
328
329/* e.g. EXTR <Xd>, <Xn>, <Xm>, #<lsb>. */
330#define QL_EXTR \
331{ \
332 QLF4(W,W,W,imm_0_31), \
333 QLF4(X,X,X,imm_0_63), \
334}
335
336/* e.g. LSL <Wd>, <Wn>, #<uimm>. */
337#define QL_SHIFT \
338{ \
339 QLF3(W,W,imm_0_31), \
340 QLF3(X,X,imm_0_63), \
341}
342
343/* e.g. UXTH <Xd>, <Wn>. */
344#define QL_EXT \
345{ \
346 QLF2(W,W), \
347 QLF2(X,W), \
348}
349
350/* e.g. UXTW <Xd>, <Wn>. */
351#define QL_EXT_W \
352{ \
353 QLF2(X,W), \
354}
355
356/* e.g. SQSHL <V><d>, <V><n>, #<shift>. */
357#define QL_SSHIFT \
358{ \
359 QLF3(S_B , S_B , S_B ), \
360 QLF3(S_H , S_H , S_H ), \
361 QLF3(S_S , S_S , S_S ), \
362 QLF3(S_D , S_D , S_D ) \
363}
364
365/* e.g. SSHR <V><d>, <V><n>, #<shift>. */
366#define QL_SSHIFT_D \
367{ \
368 QLF3(S_D , S_D , S_D ) \
369}
370
371/* e.g. UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */
372#define QL_SSHIFT_SD \
373{ \
374 QLF3(S_S , S_S , S_S ), \
375 QLF3(S_D , S_D , S_D ) \
376}
377
378/* e.g. SQSHRUN <Vb><d>, <Va><n>, #<shift>. */
379#define QL_SSHIFTN \
380{ \
381 QLF3(S_B , S_H , S_B ), \
382 QLF3(S_H , S_S , S_H ), \
383 QLF3(S_S , S_D , S_S ), \
384}
385
386/* e.g. SSHR <Vd>.<T>, <Vn>.<T>, #<shift>.
387 The register operand variant qualifiers are deliberately used for the
388 immediate operand to ease the operand encoding/decoding and qualifier
389 sequence matching. */
390#define QL_VSHIFT \
391{ \
392 QLF3(V_8B , V_8B , V_8B ), \
393 QLF3(V_16B, V_16B, V_16B), \
394 QLF3(V_4H , V_4H , V_4H ), \
395 QLF3(V_8H , V_8H , V_8H ), \
396 QLF3(V_2S , V_2S , V_2S ), \
397 QLF3(V_4S , V_4S , V_4S ), \
398 QLF3(V_2D , V_2D , V_2D ) \
399}
400
401/* e.g. SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */
402#define QL_VSHIFT_SD \
403{ \
404 QLF3(V_2S , V_2S , V_2S ), \
405 QLF3(V_4S , V_4S , V_4S ), \
406 QLF3(V_2D , V_2D , V_2D ) \
407}
408
409/* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */
410#define QL_VSHIFTN \
411{ \
412 QLF3(V_8B , V_8H , V_8B ), \
413 QLF3(V_4H , V_4S , V_4H ), \
414 QLF3(V_2S , V_2D , V_2S ), \
415}
416
417/* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */
418#define QL_VSHIFTN2 \
419{ \
420 QLF3(V_16B, V_8H, V_16B), \
421 QLF3(V_8H , V_4S , V_8H ), \
422 QLF3(V_4S , V_2D , V_4S ), \
423}
424
425/* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>.
426 the 3rd qualifier is used to help the encoding. */
427#define QL_VSHIFTL \
428{ \
429 QLF3(V_8H , V_8B , V_8B ), \
430 QLF3(V_4S , V_4H , V_4H ), \
431 QLF3(V_2D , V_2S , V_2S ), \
432}
433
434/* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */
435#define QL_VSHIFTL2 \
436{ \
437 QLF3(V_8H , V_16B, V_16B), \
438 QLF3(V_4S , V_8H , V_8H ), \
439 QLF3(V_2D , V_4S , V_4S ), \
440}
441
442/* e.g. TBL. */
443#define QL_TABLE \
444{ \
445 QLF3(V_8B , V_16B, V_8B ), \
446 QLF3(V_16B, V_16B, V_16B), \
447}
448
449/* e.g. SHA1H. */
450#define QL_2SAMES \
451{ \
452 QLF2(S_S, S_S), \
453}
454
455/* e.g. ABS <V><d>, <V><n>. */
456#define QL_2SAMED \
457{ \
458 QLF2(S_D, S_D), \
459}
460
461/* e.g. CMGT <V><d>, <V><n>, #0. */
462#define QL_SISD_CMP_0 \
463{ \
464 QLF3(S_D, S_D, NIL), \
465}
466
467/* e.g. FCMEQ <V><d>, <V><n>, #0. */
468#define QL_SISD_FCMP_0 \
469{ \
470 QLF3(S_S, S_S, NIL), \
471 QLF3(S_D, S_D, NIL), \
472}
473
80776b29
MW		 474/* e.g. FCMEQ <V><d>, <V><n>, #0. */
475#define QL_SISD_FCMP_H_0 \
476{ \
477 QLF3 (S_H, S_H, NIL), \
478}
479
a06ea964
NC		 480/* e.g. FMAXNMP <V><d>, <Vn>.<T>. */
481#define QL_SISD_PAIR \
482{ \
483 QLF2(S_S, V_2S), \
484 QLF2(S_D, V_2D), \
485}
486
487/* e.g. ADDP <V><d>, <Vn>.<T>. */
488#define QL_SISD_PAIR_D \
489{ \
490 QLF2(S_D, V_2D), \
491}
492
493/* e.g. DUP <V><d>, <Vn>.<T>[<index>]. */
494#define QL_S_2SAME \
495{ \
496 QLF2(S_B, S_B), \
497 QLF2(S_H, S_H), \
498 QLF2(S_S, S_S), \
499 QLF2(S_D, S_D), \
500}
501
502/* e.g. FCVTNS <V><d>, <V><n>. */
503#define QL_S_2SAMESD \
504{ \
505 QLF2(S_S, S_S), \
506 QLF2(S_D, S_D), \
507}
508
80776b29
MW		 509/* e.g. FCVTNS <V><d>, <V><n>. */
510#define QL_S_2SAMEH \
511{ \
512 QLF2 (S_H, S_H), \
513}
514
a06ea964
NC		 515/* e.g. SQXTN <Vb><d>, <Va><n>. */
516#define QL_SISD_NARROW \
517{ \
518 QLF2(S_B, S_H), \
519 QLF2(S_H, S_S), \
520 QLF2(S_S, S_D), \
521}
522
523/* e.g. FCVTXN <Vb><d>, <Va><n>. */
524#define QL_SISD_NARROW_S \
525{ \
526 QLF2(S_S, S_D), \
527}
528
529/* e.g. FCVT. */
530#define QL_FCVT \
531{ \
532 QLF2(S_S, S_H), \
533 QLF2(S_S, S_D), \
534 QLF2(S_D, S_H), \
535 QLF2(S_D, S_S), \
536 QLF2(S_H, S_S), \
537 QLF2(S_H, S_D), \
538}
539
540/* FMOV <Dd>, <Dn>. */
541#define QL_FP2 \
542{ \
543 QLF2(S_S, S_S), \
544 QLF2(S_D, S_D), \
545}
546
622b9eb1
MW		 547/* FMOV <Hd>, <Hn>. */
548#define QL_FP2_H \
549{ \
550 QLF2 (S_H, S_H), \
551}
552
a06ea964
NC		 553/* e.g. SQADD <V><d>, <V><n>, <V><m>. */
554#define QL_S_3SAME \
555{ \
556 QLF3(S_B, S_B, S_B), \
557 QLF3(S_H, S_H, S_H), \
558 QLF3(S_S, S_S, S_S), \
559 QLF3(S_D, S_D, S_D), \
560}
561
562/* e.g. CMGE <V><d>, <V><n>, <V><m>. */
563#define QL_S_3SAMED \
564{ \
565 QLF3(S_D, S_D, S_D), \
566}
567
568/* e.g. SQDMULH <V><d>, <V><n>, <V><m>. */
569#define QL_SISD_HS \
570{ \
571 QLF3(S_H, S_H, S_H), \
572 QLF3(S_S, S_S, S_S), \
573}
574
575/* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vb><m>. */
576#define QL_SISDL_HS \
577{ \
578 QLF3(S_S, S_H, S_H), \
579 QLF3(S_D, S_S, S_S), \
580}
581
582/* FMUL <Sd>, <Sn>, <Sm>. */
583#define QL_FP3 \
584{ \
585 QLF3(S_S, S_S, S_S), \
586 QLF3(S_D, S_D, S_D), \
587}
588
622b9eb1
MW		 589/* FMUL <Hd>, <Hn>, <Hm>. */
590#define QL_FP3_H \
591{ \
592 QLF3 (S_H, S_H, S_H), \
593}
594
a06ea964
NC		 595/* FMADD <Dd>, <Dn>, <Dm>, <Da>. */
596#define QL_FP4 \
597{ \
598 QLF4(S_S, S_S, S_S, S_S), \
599 QLF4(S_D, S_D, S_D, S_D), \
600}
601
622b9eb1
MW		 602/* FMADD <Hd>, <Hn>, <Hm>, <Ha>. */
603#define QL_FP4_H \
604{ \
605 QLF4 (S_H, S_H, S_H, S_H), \
606}
607
a06ea964
NC		 608/* e.g. FCMP <Dn>, #0.0. */
609#define QL_DST_SD \
610{ \
611 QLF2(S_S, NIL), \
612 QLF2(S_D, NIL), \
613}
614
622b9eb1
MW		 615/* e.g. FCMP <Hn>, #0.0. */
616#define QL_DST_H \
617{ \
618 QLF2 (S_H, NIL), \
619}
620
a06ea964
NC		 621/* FCSEL <Sd>, <Sn>, <Sm>, <cond>. */
622#define QL_FP_COND \
623{ \
624 QLF4(S_S, S_S, S_S, NIL), \
625 QLF4(S_D, S_D, S_D, NIL), \
626}
627
622b9eb1
MW		 628/* FCSEL <Hd>, <Hn>, <Hm>, <cond>. */
629#define QL_FP_COND_H \
630{ \
631 QLF4 (S_H, S_H, S_H, NIL), \
632}
633
a06ea964
NC		 634/* e.g. CCMN <Xn>, <Xm>, #<nzcv>, <cond>. */
635#define QL_CCMP \
636{ \
637 QLF4(W, W, NIL, NIL), \
638 QLF4(X, X, NIL, NIL), \
639}
640
641/* e.g. CCMN <Xn>, #<imm>, #<nzcv>, <cond>, */
642#define QL_CCMP_IMM \
643{ \
644 QLF4(W, NIL, NIL, NIL), \
645 QLF4(X, NIL, NIL, NIL), \
646}
647
648/* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>. */
649#define QL_FCCMP \
650{ \
651 QLF4(S_S, S_S, NIL, NIL), \
652 QLF4(S_D, S_D, NIL, NIL), \
653}
654
622b9eb1
MW		 655/* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>. */
656#define QL_FCCMP_H \
657{ \
658 QLF4 (S_H, S_H, NIL, NIL), \
659}
660
a06ea964
NC		 661/* e.g. DUP <Vd>.<T>, <Vn>.<Ts>[<index>]. */
662#define QL_DUP_VX \
663{ \
664 QLF2(V_8B , S_B ), \
665 QLF2(V_16B, S_B ), \
666 QLF2(V_4H , S_H ), \
667 QLF2(V_8H , S_H ), \
668 QLF2(V_2S , S_S ), \
669 QLF2(V_4S , S_S ), \
670 QLF2(V_2D , S_D ), \
671}
672
673/* e.g. DUP <Vd>.<T>, <Wn>. */
674#define QL_DUP_VR \
675{ \
676 QLF2(V_8B , W ), \
677 QLF2(V_16B, W ), \
678 QLF2(V_4H , W ), \
679 QLF2(V_8H , W ), \
680 QLF2(V_2S , W ), \
681 QLF2(V_4S , W ), \
682 QLF2(V_2D , X ), \
683}
684
685/* e.g. INS <Vd>.<Ts>[<index>], <Wn>. */
686#define QL_INS_XR \
687{ \
688 QLF2(S_H , W ), \
689 QLF2(S_S , W ), \
690 QLF2(S_D , X ), \
691 QLF2(S_B , W ), \
692}
693
694/* e.g. SMOV <Wd>, <Vn>.<Ts>[<index>]. */
695#define QL_SMOV \
696{ \
697 QLF2(W , S_H), \
698 QLF2(X , S_H), \
699 QLF2(X , S_S), \
700 QLF2(W , S_B), \
701 QLF2(X , S_B), \
702}
703
704/* e.g. UMOV <Wd>, <Vn>.<Ts>[<index>]. */
705#define QL_UMOV \
706{ \
707 QLF2(W , S_H), \
708 QLF2(W , S_S), \
709 QLF2(X , S_D), \
710 QLF2(W , S_B), \
711}
712
713/* e.g. MOV <Wd>, <Vn>.<Ts>[<index>]. */
714#define QL_MOV \
715{ \
716 QLF2(W , S_S), \
717 QLF2(X , S_D), \
718}
719
720/* e.g. SUQADD <Vd>.<T>, <Vn>.<T>. */
721#define QL_V2SAME \
722{ \
723 QLF2(V_8B , V_8B ), \
724 QLF2(V_16B, V_16B), \
725 QLF2(V_4H , V_4H ), \
726 QLF2(V_8H , V_8H ), \
727 QLF2(V_2S , V_2S ), \
728 QLF2(V_4S , V_4S ), \
729 QLF2(V_2D , V_2D ), \
730}
731
732/* e.g. URSQRTE <Vd>.<T>, <Vn>.<T>. */
733#define QL_V2SAMES \
734{ \
735 QLF2(V_2S , V_2S ), \
736 QLF2(V_4S , V_4S ), \
737}
738
739/* e.g. REV32 <Vd>.<T>, <Vn>.<T>. */
740#define QL_V2SAMEBH \
741{ \
742 QLF2(V_8B , V_8B ), \
743 QLF2(V_16B, V_16B), \
744 QLF2(V_4H , V_4H ), \
745 QLF2(V_8H , V_8H ), \
746}
747
748/* e.g. FRINTN <Vd>.<T>, <Vn>.<T>. */
749#define QL_V2SAMESD \
750{ \
751 QLF2(V_2S , V_2S ), \
752 QLF2(V_4S , V_4S ), \
753 QLF2(V_2D , V_2D ), \
754}
755
756/* e.g. REV64 <Vd>.<T>, <Vn>.<T>. */
757#define QL_V2SAMEBHS \
758{ \
759 QLF2(V_8B , V_8B ), \
760 QLF2(V_16B, V_16B), \
761 QLF2(V_4H , V_4H ), \
762 QLF2(V_8H , V_8H ), \
763 QLF2(V_2S , V_2S ), \
764 QLF2(V_4S , V_4S ), \
765}
766
f3aa142b
MW		 767/* e.g. FCMGT <Vd>.<T>, <Vd>.<T>>, #0.0. */
768#define QL_V2SAMEH \
769{ \
770 QLF2 (V_4H, V_4H), \
771 QLF2 (V_8H, V_8H), \
772}
773
a06ea964
NC		 774/* e.g. REV16 <Vd>.<T>, <Vn>.<T>. */
775#define QL_V2SAMEB \
776{ \
777 QLF2(V_8B , V_8B ), \
778 QLF2(V_16B, V_16B), \
779}
780
781/* e.g. SADDLP <Vd>.<Ta>, <Vn>.<Tb>. */
782#define QL_V2PAIRWISELONGBHS \
783{ \
784 QLF2(V_4H , V_8B ), \
785 QLF2(V_8H , V_16B), \
786 QLF2(V_2S , V_4H ), \
787 QLF2(V_4S , V_8H ), \
788 QLF2(V_1D , V_2S ), \
789 QLF2(V_2D , V_4S ), \
790}
791
792/* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */
793#define QL_V2LONGBHS \
794{ \
795 QLF2(V_8H , V_8B ), \
796 QLF2(V_4S , V_4H ), \
797 QLF2(V_2D , V_2S ), \
798}
799
800/* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */
801#define QL_V2LONGBHS2 \
802{ \
803 QLF2(V_8H , V_16B), \
804 QLF2(V_4S , V_8H ), \
805 QLF2(V_2D , V_4S ), \
806}
807
808/* */
809#define QL_V3SAME \
810{ \
811 QLF3(V_8B , V_8B , V_8B ), \
812 QLF3(V_16B, V_16B, V_16B), \
813 QLF3(V_4H , V_4H , V_4H ), \
814 QLF3(V_8H , V_8H , V_8H ), \
815 QLF3(V_2S , V_2S , V_2S ), \
816 QLF3(V_4S , V_4S , V_4S ), \
817 QLF3(V_2D , V_2D , V_2D ) \
818}
819
820/* e.g. SHADD. */
821#define QL_V3SAMEBHS \
822{ \
823 QLF3(V_8B , V_8B , V_8B ), \
824 QLF3(V_16B, V_16B, V_16B), \
825 QLF3(V_4H , V_4H , V_4H ), \
826 QLF3(V_8H , V_8H , V_8H ), \
827 QLF3(V_2S , V_2S , V_2S ), \
828 QLF3(V_4S , V_4S , V_4S ), \
829}
830
831/* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
832#define QL_V2NARRS \
833{ \
834 QLF2(V_2S , V_2D ), \
835}
836
837/* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
838#define QL_V2NARRS2 \
839{ \
840 QLF2(V_4S , V_2D ), \
841}
842
843/* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
844#define QL_V2NARRHS \
845{ \
846 QLF2(V_4H , V_4S ), \
847 QLF2(V_2S , V_2D ), \
848}
849
850/* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
851#define QL_V2NARRHS2 \
852{ \
853 QLF2(V_8H , V_4S ), \
854 QLF2(V_4S , V_2D ), \
855}
856
857/* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
858#define QL_V2LONGHS \
859{ \
860 QLF2(V_4S , V_4H ), \
861 QLF2(V_2D , V_2S ), \
862}
863
864/* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
865#define QL_V2LONGHS2 \
866{ \
867 QLF2(V_4S , V_8H ), \
868 QLF2(V_2D , V_4S ), \
869}
870
871/* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
872#define QL_V2NARRBHS \
873{ \
874 QLF2(V_8B , V_8H ), \
875 QLF2(V_4H , V_4S ), \
876 QLF2(V_2S , V_2D ), \
877}
878
879/* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
880#define QL_V2NARRBHS2 \
881{ \
882 QLF2(V_16B, V_8H ), \
883 QLF2(V_8H , V_4S ), \
884 QLF2(V_4S , V_2D ), \
885}
886
887/* e.g. ORR. */
888#define QL_V2SAMEB \
889{ \
890 QLF2(V_8B , V_8B ), \
891 QLF2(V_16B, V_16B), \
892}
893
894/* e.g. AESE. */
895#define QL_V2SAME16B \
896{ \
897 QLF2(V_16B, V_16B), \
898}
899
900/* e.g. SHA1SU1. */
901#define QL_V2SAME4S \
902{ \
903 QLF2(V_4S, V_4S), \
904}
905
906/* e.g. SHA1SU0. */
907#define QL_V3SAME4S \
908{ \
909 QLF3(V_4S, V_4S, V_4S), \
910}
911
912/* e.g. SHADD. */
913#define QL_V3SAMEB \
914{ \
915 QLF3(V_8B , V_8B , V_8B ), \
916 QLF3(V_16B, V_16B, V_16B), \
917}
918
919/* e.g. EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index>. */
920#define QL_VEXT \
921{ \
922 QLF4(V_8B , V_8B , V_8B , imm_0_7), \
923 QLF4(V_16B, V_16B, V_16B, imm_0_15), \
924}
925
926/* e.g. . */
927#define QL_V3SAMEHS \
928{ \
929 QLF3(V_4H , V_4H , V_4H ), \
930 QLF3(V_8H , V_8H , V_8H ), \
931 QLF3(V_2S , V_2S , V_2S ), \
932 QLF3(V_4S , V_4S , V_4S ), \
933}
934
935/* */
936#define QL_V3SAMESD \
937{ \
938 QLF3(V_2S , V_2S , V_2S ), \
939 QLF3(V_4S , V_4S , V_4S ), \
940 QLF3(V_2D , V_2D , V_2D ) \
941}
942
51d543ed
MW		 943/* e.g. FMAXNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T>. */
944#define QL_V3SAMEH \
945{ \
946 QLF3 (V_4H , V_4H , V_4H ), \
947 QLF3 (V_8H , V_8H , V_8H ), \
948}
949
a06ea964
NC		 950/* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */
951#define QL_V3LONGHS \
952{ \
953 QLF3(V_4S , V_4H , V_4H ), \
954 QLF3(V_2D , V_2S , V_2S ), \
955}
956
957/* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */
958#define QL_V3LONGHS2 \
959{ \
960 QLF3(V_4S , V_8H , V_8H ), \
961 QLF3(V_2D , V_4S , V_4S ), \
962}
963
964/* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */
965#define QL_V3LONGBHS \
966{ \
967 QLF3(V_8H , V_8B , V_8B ), \
968 QLF3(V_4S , V_4H , V_4H ), \
969 QLF3(V_2D , V_2S , V_2S ), \
970}
971
972/* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */
973#define QL_V3LONGBHS2 \
974{ \
975 QLF3(V_8H , V_16B , V_16B ), \
976 QLF3(V_4S , V_8H , V_8H ), \
977 QLF3(V_2D , V_4S , V_4S ), \
978}
979
980/* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */
981#define QL_V3WIDEBHS \
982{ \
983 QLF3(V_8H , V_8H , V_8B ), \
984 QLF3(V_4S , V_4S , V_4H ), \
985 QLF3(V_2D , V_2D , V_2S ), \
986}
987
988/* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */
989#define QL_V3WIDEBHS2 \
990{ \
991 QLF3(V_8H , V_8H , V_16B ), \
992 QLF3(V_4S , V_4S , V_8H ), \
993 QLF3(V_2D , V_2D , V_4S ), \
994}
995
996/* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */
997#define QL_V3NARRBHS \
998{ \
999 QLF3(V_8B , V_8H , V_8H ), \
1000 QLF3(V_4H , V_4S , V_4S ), \
1001 QLF3(V_2S , V_2D , V_2D ), \
1002}
1003
1004/* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */
1005#define QL_V3NARRBHS2 \
1006{ \
1007 QLF3(V_16B , V_8H , V_8H ), \
1008 QLF3(V_8H , V_4S , V_4S ), \
1009 QLF3(V_4S , V_2D , V_2D ), \
1010}
1011
1012/* e.g. PMULL. */
1013#define QL_V3LONGB \
1014{ \
1015 QLF3(V_8H , V_8B , V_8B ), \
1016}
1017
1018/* e.g. PMULL crypto. */
1019#define QL_V3LONGD \
1020{ \
1021 QLF3(V_1Q , V_1D , V_1D ), \
1022}
1023
1024/* e.g. PMULL2. */
1025#define QL_V3LONGB2 \
1026{ \
1027 QLF3(V_8H , V_16B, V_16B), \
1028}
1029
1030/* e.g. PMULL2 crypto. */
1031#define QL_V3LONGD2 \
1032{ \
1033 QLF3(V_1Q , V_2D , V_2D ), \
1034}
1035
1036/* e.g. SHA1C. */
1037#define QL_SHAUPT \
1038{ \
1039 QLF3(S_Q, S_S, V_4S), \
1040}
1041
1042/* e.g. SHA256H2. */
1043#define QL_SHA256UPT \
1044{ \
1045 QLF3(S_Q, S_Q, V_4S), \
1046}
1047
1048/* e.g. LDXRB <Wt>, [<Xn|SP>{,#0}]. */
1049#define QL_W1_LDST_EXC \
1050{ \
1051 QLF2(W, NIL), \
1052}
1053
1054/* e.g. LDXR <Xt>, [<Xn|SP>{,#0}]. */
1055#define QL_R1NIL \
1056{ \
1057 QLF2(W, NIL), \
1058 QLF2(X, NIL), \
1059}
1060
1061/* e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
1062#define QL_W2_LDST_EXC \
1063{ \
1064 QLF3(W, W, NIL), \
1065}
1066
1067/* e.g. STXR <Ws>, <Xt>, [<Xn|SP>{,#0}]. */
1068#define QL_R2_LDST_EXC \
1069{ \
1070 QLF3(W, W, NIL), \
1071 QLF3(W, X, NIL), \
1072}
1073
1074/* e.g. LDXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
1075#define QL_R2NIL \
1076{ \
1077 QLF3(W, W, NIL), \
1078 QLF3(X, X, NIL), \
1079}
1080
ee804238
JW		 1081/* e.g. CASP <Xt1>, <Xt1+1>, <Xt2>, <Xt2+1>, [<Xn|SP>{,#0}]. */
1082#define QL_R4NIL \
1083{ \
1084 QLF5(W, W, W, W, NIL), \
1085 QLF5(X, X, X, X, NIL), \
1086}
1087
a06ea964
NC		 1088/* e.g. STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
1089#define QL_R3_LDST_EXC \
1090{ \
1091 QLF4(W, W, W, NIL), \
1092 QLF4(W, X, X, NIL), \
1093}
1094
1095/* e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1096#define QL_LDST_FP \
1097{ \
1098 QLF2(S_B, S_B), \
1099 QLF2(S_H, S_H), \
1100 QLF2(S_S, S_S), \
1101 QLF2(S_D, S_D), \
1102 QLF2(S_Q, S_Q), \
1103}
1104
1105/* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1106#define QL_LDST_R \
1107{ \
1108 QLF2(W, S_S), \
1109 QLF2(X, S_D), \
1110}
1111
1112/* e.g. STRB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1113#define QL_LDST_W8 \
1114{ \
1115 QLF2(W, S_B), \
1116}
1117
1118/* e.g. LDRSB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1119#define QL_LDST_R8 \
1120{ \
1121 QLF2(W, S_B), \
1122 QLF2(X, S_B), \
1123}
1124
1125/* e.g. STRH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1126#define QL_LDST_W16 \
1127{ \
1128 QLF2(W, S_H), \
1129}
1130
1131/* e.g. LDRSW <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1132#define QL_LDST_X32 \
1133{ \
1134 QLF2(X, S_S), \
1135}
1136
1137/* e.g. LDRSH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1138#define QL_LDST_R16 \
1139{ \
1140 QLF2(W, S_H), \
1141 QLF2(X, S_H), \
1142}
1143
1144/* e.g. PRFM <prfop>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1145#define QL_LDST_PRFM \
1146{ \
1147 QLF2(NIL, S_D), \
1148}
1149
1150/* e.g. LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]. */
1151#define QL_LDST_PAIR_X32 \
1152{ \
1153 QLF3(X, X, S_S), \
1154}
1155
1156/* e.g. STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!. */
1157#define QL_LDST_PAIR_R \
1158{ \
1159 QLF3(W, W, S_S), \
1160 QLF3(X, X, S_D), \
1161}
1162
1163/* e.g. STNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
1164#define QL_LDST_PAIR_FP \
1165{ \
1166 QLF3(S_S, S_S, S_S), \
1167 QLF3(S_D, S_D, S_D), \
1168 QLF3(S_Q, S_Q, S_Q), \
1169}
1170
1171/* e.g. LD3 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */
1172#define QL_SIMD_LDST \
1173{ \
1174 QLF2(V_8B, NIL), \
1175 QLF2(V_16B, NIL), \
1176 QLF2(V_4H, NIL), \
1177 QLF2(V_8H, NIL), \
1178 QLF2(V_2S, NIL), \
1179 QLF2(V_4S, NIL), \
1180 QLF2(V_2D, NIL), \
1181}
1182
1183/* e.g. LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */
1184#define QL_SIMD_LDST_ANY \
1185{ \
1186 QLF2(V_8B, NIL), \
1187 QLF2(V_16B, NIL), \
1188 QLF2(V_4H, NIL), \
1189 QLF2(V_8H, NIL), \
1190 QLF2(V_2S, NIL), \
1191 QLF2(V_4S, NIL), \
1192 QLF2(V_1D, NIL), \
1193 QLF2(V_2D, NIL), \
1194}
1195
1196/* e.g. LD4 {<Vt>.<T>, <Vt2a>.<T>, <Vt3a>.<T>, <Vt4a>.<T>}[<index>], [<Xn|SP>]. */
1197#define QL_SIMD_LDSTONE \
1198{ \
1199 QLF2(S_B, NIL), \
1200 QLF2(S_H, NIL), \
1201 QLF2(S_S, NIL), \
1202 QLF2(S_D, NIL), \
1203}
1204
1205/* e.g. ADDV <V><d>, <Vn>.<T>. */
1206#define QL_XLANES \
1207{ \
1208 QLF2(S_B, V_8B), \
1209 QLF2(S_B, V_16B), \
1210 QLF2(S_H, V_4H), \
1211 QLF2(S_H, V_8H), \
1212 QLF2(S_S, V_4S), \
1213}
1214
1215/* e.g. FMINV <V><d>, <Vn>.<T>. */
1216#define QL_XLANES_FP \
1217{ \
1218 QLF2(S_S, V_4S), \
1219}
1220
1221/* e.g. SADDLV <V><d>, <Vn>.<T>. */
1222#define QL_XLANES_L \
1223{ \
1224 QLF2(S_H, V_8B), \
1225 QLF2(S_H, V_16B), \
1226 QLF2(S_S, V_4H), \
1227 QLF2(S_S, V_8H), \
1228 QLF2(S_D, V_4S), \
1229}
1230
1231/* e.g. MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]. */
1232#define QL_ELEMENT \
1233{ \
1234 QLF3(V_4H, V_4H, S_H), \
1235 QLF3(V_8H, V_8H, S_H), \
1236 QLF3(V_2S, V_2S, S_S), \
1237 QLF3(V_4S, V_4S, S_S), \
1238}
1239
1240/* e.g. SMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */
1241#define QL_ELEMENT_L \
1242{ \
1243 QLF3(V_4S, V_4H, S_H), \
1244 QLF3(V_2D, V_2S, S_S), \
1245}
1246
1247/* e.g. SMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */
1248#define QL_ELEMENT_L2 \
1249{ \
1250 QLF3(V_4S, V_8H, S_H), \
1251 QLF3(V_2D, V_4S, S_S), \
1252}
1253
1254/* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]. */
1255#define QL_ELEMENT_FP \
1256{ \
1257 QLF3(V_2S, V_2S, S_S), \
1258 QLF3(V_4S, V_4S, S_S), \
1259 QLF3(V_2D, V_2D, S_D), \
1260}
1261
42f23f62
MW		 1262/* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]. */
1263#define QL_ELEMENT_FP_H \
1264{ \
1265 QLF3 (V_4H, V_4H, S_H), \
1266 QLF3 (V_8H, V_8H, S_H), \
1267}
1268
a06ea964
NC		 1269/* e.g. MOVI <Vd>.4S, #<imm8> {, LSL #<amount>}. */
1270#define QL_SIMD_IMM_S0W \
1271{ \
1272 QLF2(V_2S, LSL), \
1273 QLF2(V_4S, LSL), \
1274}
1275
1276/* e.g. MOVI <Vd>.4S, #<imm8>, MSL #<amount>. */
1277#define QL_SIMD_IMM_S1W \
1278{ \
1279 QLF2(V_2S, MSL), \
1280 QLF2(V_4S, MSL), \
1281}
1282
1283/* e.g. MOVI <Vd>.4H, #<imm8> {, LSL #<amount>}. */
1284#define QL_SIMD_IMM_S0H \
1285{ \
1286 QLF2(V_4H, LSL), \
1287 QLF2(V_8H, LSL), \
1288}
1289
1290/* e.g. FMOV <Vd>.<T>, #<imm>. */
1291#define QL_SIMD_IMM_S \
1292{ \
1293 QLF2(V_2S, NIL), \
1294 QLF2(V_4S, NIL), \
1295}
1296
f5555712 1297/* e.g. MOVI <Vd>.8B, #<imm8> {, LSL #<amount>}. */
a06ea964
NC		 1298#define QL_SIMD_IMM_B \
1299{ \
f5555712
YZ		 1300 QLF2(V_8B, LSL), \
1301 QLF2(V_16B, LSL), \
a06ea964
NC		 1302}
1303/* e.g. MOVI <Dd>, #<imm>. */
1304#define QL_SIMD_IMM_D \
1305{ \
1306 QLF2(S_D, NIL), \
1307}
1308
1309/* e.g. MOVI <Vd>.2D, #<imm>. */
1310#define QL_SIMD_IMM_V2D \
1311{ \
1312 QLF2(V_2D, NIL), \
1313}
1314\f
1315/* Opcode table. */
1316
1317static const aarch64_feature_set aarch64_feature_v8 =
1318 AARCH64_FEATURE (AARCH64_FEATURE_V8, 0);
1319static const aarch64_feature_set aarch64_feature_fp =
1320 AARCH64_FEATURE (AARCH64_FEATURE_FP, 0);
1321static const aarch64_feature_set aarch64_feature_simd =
1322 AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0);
1323static const aarch64_feature_set aarch64_feature_crypto =
1324 AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0);
e60bb1dd
YZ		 1325static const aarch64_feature_set aarch64_feature_crc =
1326 AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0);
ee804238
JW		 1327static const aarch64_feature_set aarch64_feature_lse =
1328 AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0);
290806fd
MW		 1329static const aarch64_feature_set aarch64_feature_lor =
1330 AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0);
9e1f0fa7
MW		 1331static const aarch64_feature_set aarch64_feature_rdma =
1332 AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0);
c8a6db6f
MW		 1333static const aarch64_feature_set aarch64_feature_ras =
1334 AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0);
d685192a
MW		 1335static const aarch64_feature_set aarch64_feature_v8_2 =
1336 AARCH64_FEATURE (AARCH64_FEATURE_V8_2, 0);
3bd894a7
MW		 1337static const aarch64_feature_set aarch64_feature_fp_f16 =
1338 AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0);
40d16a76
MW		 1339static const aarch64_feature_set aarch64_feature_simd_f16 =
1340 AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_SIMD, 0);
1e6f4800
MW		 1341static const aarch64_feature_set aarch64_feature_stat_profile =
1342 AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0);
a06ea964
NC		 1343
1344#define CORE &aarch64_feature_v8
1345#define FP &aarch64_feature_fp
1346#define SIMD &aarch64_feature_simd
1347#define CRYPTO &aarch64_feature_crypto
e60bb1dd 1348#define CRC &aarch64_feature_crc
ee804238 1349#define LSE &aarch64_feature_lse
290806fd 1350#define LOR &aarch64_feature_lor
9e1f0fa7 1351#define RDMA &aarch64_feature_rdma
3bd894a7 1352#define FP_F16 &aarch64_feature_fp_f16
40d16a76 1353#define SIMD_F16 &aarch64_feature_simd_f16
c8a6db6f 1354#define RAS &aarch64_feature_ras
1e6f4800 1355#define STAT_PROFILE &aarch64_feature_stat_profile
d685192a 1356#define ARMV8_2 &aarch64_feature_v8_2
a06ea964
NC		 1357
1358struct aarch64_opcode aarch64_opcode_table[] =
1359{
1360 /* Add/subtract (with carry). */
1361 {"adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
1362 {"adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
1363 {"sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1364 {"ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF},
1365 {"sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1366 {"ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF},
1367 /* Add/subtract (extended register). */
1368 {"add", 0x0b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF},
1369 {"adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF},
1370 {"cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, CORE, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF},
1371 {"sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF},
1372 {"subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF},
1373 {"cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, CORE, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF},
1374 /* Add/subtract (immediate). */
1375 {"add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, CORE, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
1376 {"mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, CORE, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF},
1377 {"adds", 0x31000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
1378 {"cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, CORE, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF},
1379 {"sub", 0x51000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF},
1380 {"subs", 0x71000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
1381 {"cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, CORE, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF},
1382 /* Add/subtract (shifted register). */
1383 {"add", 0xb000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
1384 {"adds", 0x2b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1385 {"cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
1386 {"sub", 0x4b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1387 {"neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
1388 {"subs", 0x6b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1389 {"cmp", 0x6b00001f, 0x7f20001f, addsub_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
1390 {"negs", 0x6b0003e0, 0x7f2003e0, addsub_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
1391 /* AdvSIMD across lanes. */
1392 {"saddlv", 0xe303800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ},
1393 {"smaxv", 0xe30a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
1394 {"sminv", 0xe31a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
1395 {"addv", 0xe31b800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
1396 {"uaddlv", 0x2e303800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ},
1397 {"umaxv", 0x2e30a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
1398 {"uminv", 0x2e31a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
1399 {"fmaxnmv", 0x2e30c800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
1400 {"fmaxv", 0x2e30f800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
1401 {"fminnmv", 0x2eb0c800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
1402 {"fminv", 0x2eb0f800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
1403 /* AdvSIMD three different. */
1404 {"saddl", 0x0e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1405 {"saddl2", 0x4e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1406 {"saddw", 0x0e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
1407 {"saddw2", 0x4e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
1408 {"ssubl", 0x0e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1409 {"ssubl2", 0x4e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1410 {"ssubw", 0x0e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
1411 {"ssubw2", 0x4e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
1412 {"addhn", 0x0e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
1413 {"addhn2", 0x4e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
1414 {"sabal", 0x0e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1415 {"sabal2", 0x4e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1416 {"subhn", 0x0e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
1417 {"subhn2", 0x4e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
1418 {"sabdl", 0x0e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1419 {"sabdl2", 0x4e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1420 {"smlal", 0x0e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1421 {"smlal2", 0x4e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1422 {"sqdmlal", 0x0e209000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ},
1423 {"sqdmlal2", 0x4e209000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ},
1424 {"smlsl", 0x0e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1425 {"smlsl2", 0x4e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1426 {"sqdmlsl", 0x0e20b000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ},
1427 {"sqdmlsl2", 0x4e20b000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ},
1428 {"smull", 0x0e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1429 {"smull2", 0x4e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1430 {"sqdmull", 0x0e20d000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ},
1431 {"sqdmull2", 0x4e20d000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ},
1432 {"pmull", 0x0e20e000, 0xffe0fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGB, 0},
1433 {"pmull", 0x0ee0e000, 0xffe0fc00, asimddiff, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3LONGD, 0},
1434 {"pmull2", 0x4e20e000, 0xffe0fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGB2, 0},
1435 {"pmull2", 0x4ee0e000, 0xffe0fc00, asimddiff, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3LONGD2, 0},
1436 {"uaddl", 0x2e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1437 {"uaddl2", 0x6e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1438 {"uaddw", 0x2e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
1439 {"uaddw2", 0x6e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
1440 {"usubl", 0x2e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1441 {"usubl2", 0x6e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1442 {"usubw", 0x2e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
1443 {"usubw2", 0x6e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
1444 {"raddhn", 0x2e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
1445 {"raddhn2", 0x6e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
1446 {"uabal", 0x2e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1447 {"uabal2", 0x6e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1448 {"rsubhn", 0x2e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
1449 {"rsubhn2", 0x6e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
1450 {"uabdl", 0x2e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1451 {"uabdl2", 0x6e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1452 {"umlal", 0x2e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1453 {"umlal2", 0x6e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1454 {"umlsl", 0x2e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1455 {"umlsl2", 0x6e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1456 {"umull", 0x2e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1457 {"umull2", 0x6e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1458 /* AdvSIMD vector x indexed element. */
1459 {"smlal", 0x0f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1460 {"smlal2", 0x4f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1461 {"sqdmlal", 0x0f003000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1462 {"sqdmlal2", 0x4f003000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1463 {"smlsl", 0x0f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1464 {"smlsl2", 0x4f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1465 {"sqdmlsl", 0x0f007000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1466 {"sqdmlsl2", 0x4f007000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1467 {"mul", 0xf008000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
1468 {"smull", 0x0f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1469 {"smull2", 0x4f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1470 {"sqdmull", 0x0f00b000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1471 {"sqdmull2", 0x4f00b000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1472 {"sqdmulh", 0xf00c000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
1473 {"sqrdmulh", 0xf00d000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
1474 {"fmla", 0xf801000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
42f23f62
MW		 1475 {"fmla", 0xf001000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
1476 OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
a06ea964 1477 {"fmls", 0xf805000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
42f23f62
MW		 1478 {"fmls", 0xf005000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
1479 OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
a06ea964 1480 {"fmul", 0xf809000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
42f23f62
MW		 1481 {"fmul", 0xf009000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
1482 OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
a06ea964
NC		 1483 {"mla", 0x2f000000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
1484 {"umlal", 0x2f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1485 {"umlal2", 0x6f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1486 {"mls", 0x2f004000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
1487 {"umlsl", 0x2f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1488 {"umlsl2", 0x6f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1489 {"umull", 0x2f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1490 {"umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1491 {"fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
42f23f62
MW		 1492 {"fmulx", 0x2f009000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
1493 OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
9e1f0fa7
MW		 1494 {"sqrdmlah", 0x2f00d000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
1495 {"sqrdmlsh", 0x2f00f000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
a06ea964 1496 /* AdvSIMD EXT. */
922c5db5 1497 {"ext", 0x2e000000, 0xbfe08400, asimdext, 0, SIMD, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ},
a06ea964
NC		 1498 /* AdvSIMD modified immediate. */
1499 {"movi", 0xf000400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
1500 {"orr", 0xf001400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
1501 {"movi", 0xf008400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
1502 {"orr", 0xf009400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
1503 {"movi", 0xf00c400, 0xbff8ec00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ},
f5555712 1504 {"movi", 0xf00e400, 0xbff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_B, F_SIZEQ},
a06ea964
NC		 1505 {"fmov", 0xf00f400, 0xbff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_S, F_SIZEQ},
1506 {"mvni", 0x2f000400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
1507 {"bic", 0x2f001400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
1508 {"mvni", 0x2f008400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
1509 {"bic", 0x2f009400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
1510 {"mvni", 0x2f00c400, 0xbff8ec00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ},
1511 {"movi", 0x2f00e400, 0xfff8fc00, asimdimm, 0, SIMD, OP2 (Sd, SIMD_IMM), QL_SIMD_IMM_D, F_SIZEQ},
1512 {"movi", 0x6f00e400, 0xfff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM), QL_SIMD_IMM_V2D, F_SIZEQ},
1513 {"fmov", 0x6f00f400, 0xfff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_V2D, F_SIZEQ},
1514 /* AdvSIMD copy. */
1515 {"dup", 0xe000400, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Vd, En), QL_DUP_VX, F_T},
1516 {"dup", 0xe000c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Vd, Rn), QL_DUP_VR, F_T},
1517 {"smov", 0xe002c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Rd, En), QL_SMOV, F_GPRSIZE_IN_Q},
1518 {"umov", 0xe003c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Rd, En), QL_UMOV, F_HAS_ALIAS | F_GPRSIZE_IN_Q},
1519 {"mov", 0xe003c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Rd, En), QL_MOV, F_ALIAS | F_GPRSIZE_IN_Q},
1520 {"ins", 0x4e001c00, 0xffe0fc00, asimdins, 0, SIMD, OP2 (Ed, Rn), QL_INS_XR, F_HAS_ALIAS},
1521 {"mov", 0x4e001c00, 0xffe0fc00, asimdins, 0, SIMD, OP2 (Ed, Rn), QL_INS_XR, F_ALIAS},
1522 {"ins", 0x6e000400, 0xffe08400, asimdins, 0, SIMD, OP2 (Ed, En), QL_S_2SAME, F_HAS_ALIAS},
1523 {"mov", 0x6e000400, 0xffe08400, asimdins, 0, SIMD, OP2 (Ed, En), QL_S_2SAME, F_ALIAS},
1524 /* AdvSIMD two-reg misc. */
1525 {"rev64", 0xe200800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ},
1526 {"rev16", 0xe201800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ},
1527 {"saddlp", 0xe202800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
1528 {"suqadd", 0xe203800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
1529 {"cls", 0xe204800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ},
1530 {"cnt", 0xe205800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ},
1531 {"sadalp", 0xe206800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
1532 {"sqabs", 0xe207800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
1533 {"cmgt", 0xe208800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
1534 {"cmeq", 0xe209800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
1535 {"cmlt", 0xe20a800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
1536 {"abs", 0xe20b800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
1537 {"xtn", 0xe212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
1538 {"xtn2", 0x4e212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
1539 {"sqxtn", 0xe214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
1540 {"sqxtn2", 0x4e214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
1541 {"fcvtn", 0xe216800, 0xffbffc00, asimdmisc, OP_FCVTN, SIMD, OP2 (Vd, Vn), QL_V2NARRHS, F_MISC},
1542 {"fcvtn2", 0x4e216800, 0xffbffc00, asimdmisc, OP_FCVTN2, SIMD, OP2 (Vd, Vn), QL_V2NARRHS2, F_MISC},
1543 {"fcvtl", 0xe217800, 0xffbffc00, asimdmisc, OP_FCVTL, SIMD, OP2 (Vd, Vn), QL_V2LONGHS, F_MISC},
1544 {"fcvtl2", 0x4e217800, 0xffbffc00, asimdmisc, OP_FCVTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGHS2, F_MISC},
1545 {"frintn", 0xe218800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1546 {"frintn", 0xe798800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1547 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1548 {"frintm", 0xe219800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1549 {"frintm", 0xe799800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1550 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1551 {"fcvtns", 0xe21a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1552 {"fcvtns", 0xe79a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1553 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1554 {"fcvtms", 0xe21b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1555 {"fcvtms", 0xe79b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1556 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1557 {"fcvtas", 0xe21c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1558 {"fcvtas", 0xe79c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1559 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1560 {"scvtf", 0xe21d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1561 {"scvtf", 0xe79d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
1562 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
f17c8bfc 1563 {"fcmgt", 0xea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1564 {"fcmgt", 0xef8c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1565 OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
f17c8bfc 1566 {"fcmeq", 0xea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1567 {"fcmeq", 0xef8d800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1568 OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
f17c8bfc 1569 {"fcmlt", 0xea0e800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1570 {"fcmlt", 0xef8e800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1571 OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
a06ea964 1572 {"fabs", 0xea0f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1573 {"fabs", 0xef8f800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1574 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1575 {"frintp", 0xea18800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1576 {"frintp", 0xef98800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1577 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1578 {"frintz", 0xea19800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1579 {"frintz", 0xef99800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1580 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1581 {"fcvtps", 0xea1a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1582 {"fcvtps", 0xef9a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1583 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1584 {"fcvtzs", 0xea1b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1585 {"fcvtzs", 0xef9b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1586 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964
NC		 1587 {"urecpe", 0xea1c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ},
1588 {"frecpe", 0xea1d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1589 {"frecpe", 0xef9d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
1590 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964
NC		 1591 {"rev32", 0x2e200800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBH, F_SIZEQ},
1592 {"uaddlp", 0x2e202800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
1593 {"usqadd", 0x2e203800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
1594 {"clz", 0x2e204800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ},
1595 {"uadalp", 0x2e206800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
1596 {"sqneg", 0x2e207800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
1597 {"cmge", 0x2e208800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
1598 {"cmle", 0x2e209800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
1599 {"neg", 0x2e20b800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
1600 {"sqxtun", 0x2e212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
1601 {"sqxtun2", 0x6e212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
1602 {"shll", 0x2e213800, 0xff3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS, F_SIZEQ},
1603 {"shll2", 0x6e213800, 0xff3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS2, F_SIZEQ},
1604 {"uqxtn", 0x2e214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
1605 {"uqxtn2", 0x6e214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
1606 {"fcvtxn", 0x2e616800, 0xfffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRS, 0},
1607 {"fcvtxn2", 0x6e616800, 0xfffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRS2, 0},
1608 {"frinta", 0x2e218800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1609 {"frinta", 0x2e798800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1610 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1611 {"frintx", 0x2e219800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1612 {"frintx", 0x2e799800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1613 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1614 {"fcvtnu", 0x2e21a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1615 {"fcvtnu", 0x2e79a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1616 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1617 {"fcvtmu", 0x2e21b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1618 {"fcvtmu", 0x2e79b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1619 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1620 {"fcvtau", 0x2e21c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1621 {"fcvtau", 0x2e79c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1622 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1623 {"ucvtf", 0x2e21d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1624 {"ucvtf", 0x2e79d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
1625 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964
NC		 1626 {"not", 0x2e205800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_HAS_ALIAS},
1627 {"mvn", 0x2e205800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_ALIAS},
1628 {"rbit", 0x2e605800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ},
f17c8bfc 1629 {"fcmge", 0x2ea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1630 {"fcmge", 0x2ef8c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1631 OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
f17c8bfc 1632 {"fcmle", 0x2ea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1633 {"fcmle", 0x2ef8d800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1634 OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
a06ea964 1635 {"fneg", 0x2ea0f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1636 {"fneg", 0x2ef8f800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1637 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1638 {"frinti", 0x2ea19800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1639 {"frinti", 0x2ef99800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1640 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1641 {"fcvtpu", 0x2ea1a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1642 {"fcvtpu", 0x2ef9a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1643 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1644 {"fcvtzu", 0x2ea1b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1645 {"fcvtzu", 0x2ef9b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1646 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964
NC		 1647 {"ursqrte", 0x2ea1c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ},
1648 {"frsqrte", 0x2ea1d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1649 {"frsqrte", 0x2ef9d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
1650 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964 1651 {"fsqrt", 0x2ea1f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
f3aa142b
MW		 1652 {"fsqrt", 0x2ef9f800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
1653 OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
a06ea964
NC		 1654 /* AdvSIMD ZIP/UZP/TRN. */
1655 {"uzp1", 0xe001800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1656 {"trn1", 0xe002800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1657 {"zip1", 0xe003800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1658 {"uzp2", 0xe005800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1659 {"trn2", 0xe006800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1660 {"zip2", 0xe007800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1661 /* AdvSIMD three same. */
1662 {"shadd", 0xe200400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1663 {"sqadd", 0xe200c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1664 {"srhadd", 0xe201400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1665 {"shsub", 0xe202400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1666 {"sqsub", 0xe202c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1667 {"cmgt", 0xe203400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1668 {"cmge", 0xe203c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1669 {"sshl", 0xe204400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1670 {"sqshl", 0xe204c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1671 {"srshl", 0xe205400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1672 {"sqrshl", 0xe205c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1673 {"smax", 0xe206400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1674 {"smin", 0xe206c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1675 {"sabd", 0xe207400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1676 {"saba", 0xe207c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1677 {"add", 0xe208400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1678 {"cmtst", 0xe208c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1679 {"mla", 0xe209400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1680 {"mul", 0xe209c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1681 {"smaxp", 0xe20a400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1682 {"sminp", 0xe20ac00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1683 {"sqdmulh", 0xe20b400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
1684 {"addp", 0xe20bc00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1685 {"fmaxnm", 0xe20c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1686 {"fmaxnm", 0xe400400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1687 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1688 {"fmla", 0xe20cc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1689 {"fmla", 0xe400c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1690 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1691 {"fadd", 0xe20d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1692 {"fadd", 0xe401400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1693 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1694 {"fmulx", 0xe20dc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1695 {"fmulx", 0xe401c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1696 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1697 {"fcmeq", 0xe20e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1698 {"fcmeq", 0xe402400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1699 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1700 {"fmax", 0xe20f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1701 {"fmax", 0xe403400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1702 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1703 {"frecps", 0xe20fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1704 {"frecps", 0xe403c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1705 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964
NC		 1706 {"and", 0xe201c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1707 {"bic", 0xe601c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1708 {"fminnm", 0xea0c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1709 {"fminnm", 0xec00400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1710 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1711 {"fmls", 0xea0cc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1712 {"fmls", 0xec00c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1713 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1714 {"fsub", 0xea0d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1715 {"fsub", 0xec01400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1716 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1717 {"fmin", 0xea0f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1718 {"fmin", 0xec03400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1719 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1720 {"frsqrts", 0xea0fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1721 {"frsqrts", 0xec03c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1722 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964
NC		 1723 {"orr", 0xea01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_HAS_ALIAS | F_SIZEQ},
1724 {"mov", 0xea01c00, 0xbfe0fc00, asimdsame, OP_MOV_V, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_ALIAS | F_CONV},
1725 {"orn", 0xee01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1726 {"uhadd", 0x2e200400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1727 {"uqadd", 0x2e200c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1728 {"urhadd", 0x2e201400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1729 {"uhsub", 0x2e202400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1730 {"uqsub", 0x2e202c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1731 {"cmhi", 0x2e203400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1732 {"cmhs", 0x2e203c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1733 {"ushl", 0x2e204400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1734 {"uqshl", 0x2e204c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1735 {"urshl", 0x2e205400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1736 {"uqrshl", 0x2e205c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1737 {"umax", 0x2e206400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1738 {"umin", 0x2e206c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1739 {"uabd", 0x2e207400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1740 {"uaba", 0x2e207c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1741 {"sub", 0x2e208400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1742 {"cmeq", 0x2e208c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1743 {"mls", 0x2e209400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1744 {"pmul", 0x2e209c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1745 {"umaxp", 0x2e20a400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1746 {"uminp", 0x2e20ac00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1747 {"sqrdmulh", 0x2e20b400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
1748 {"fmaxnmp", 0x2e20c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1749 {"fmaxnmp", 0x2e400400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1750 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1751 {"faddp", 0x2e20d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1752 {"faddp", 0x2e401400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1753 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1754 {"fmul", 0x2e20dc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1755 {"fmul", 0x2e401c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1756 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1757 {"fcmge", 0x2e20e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1758 {"fcmge", 0x2e402400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1759 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1760 {"facge", 0x2e20ec00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1761 {"facge", 0x2e402c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1762 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1763 {"fmaxp", 0x2e20f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1764 {"fmaxp", 0x2e403400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1765 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1766 {"fdiv", 0x2e20fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1767 {"fdiv", 0x2e403c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1768 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964
NC		 1769 {"eor", 0x2e201c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1770 {"bsl", 0x2e601c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1771 {"fminnmp", 0x2ea0c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1772 {"fminnmp", 0x2ec00400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1773 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1774 {"fabd", 0x2ea0d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1775 {"fabd", 0x2ec01400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1776 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1777 {"fcmgt", 0x2ea0e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1778 {"fcmgt", 0x2ec02400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1779 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1780 {"facgt", 0x2ea0ec00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1781 {"facgt", 0x2ec02c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1782 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964 1783 {"fminp", 0x2ea0f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
51d543ed
MW		 1784 {"fminp", 0x2ec03400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1785 OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
a06ea964
NC		 1786 {"bit", 0x2ea01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1787 {"bif", 0x2ee01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
9e1f0fa7
MW		 1788 /* AdvSIMD three same extension. */
1789 {"sqrdmlah", 0x2e008400, 0xbf20fe00, asimdsame, 0, RDMA, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
1790 {"sqrdmlsh", 0x2e008c00, 0xbf20fe00, asimdsame, 0, RDMA, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
a06ea964
NC		 1791 /* AdvSIMD shift by immediate. */
1792 {"sshr", 0xf000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1793 {"ssra", 0xf001400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1794 {"srshr", 0xf002400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1795 {"srsra", 0xf003400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1796 {"shl", 0xf005400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
1797 {"sqshl", 0xf007400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
1798 {"shrn", 0xf008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1799 {"shrn2", 0x4f008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1800 {"rshrn", 0xf008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1801 {"rshrn2", 0x4f008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1802 {"sqshrn", 0xf009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1803 {"sqshrn2", 0x4f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1804 {"sqrshrn", 0xf009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1805 {"sqrshrn2", 0x4f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
e30181a5
YZ		 1806 {"sshll", 0xf00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS},
1807 {"sxtl", 0xf00a400, 0xff87fc00, asimdshf, OP_SXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV},
1808 {"sshll2", 0x4f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS},
1809 {"sxtl2", 0x4f00a400, 0xff87fc00, asimdshf, OP_SXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV},
a06ea964
NC		 1810 {"scvtf", 0xf00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
1811 {"fcvtzs", 0xf00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
1812 {"ushr", 0x2f000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1813 {"usra", 0x2f001400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1814 {"urshr", 0x2f002400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1815 {"ursra", 0x2f003400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1816 {"sri", 0x2f004400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1817 {"sli", 0x2f005400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
1818 {"sqshlu", 0x2f006400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
1819 {"uqshl", 0x2f007400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
1820 {"sqshrun", 0x2f008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1821 {"sqshrun2", 0x6f008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1822 {"sqrshrun", 0x2f008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1823 {"sqrshrun2", 0x6f008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1824 {"uqshrn", 0x2f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1825 {"uqshrn2", 0x6f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1826 {"uqrshrn", 0x2f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1827 {"uqrshrn2", 0x6f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
e30181a5
YZ		 1828 {"ushll", 0x2f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS},
1829 {"uxtl", 0x2f00a400, 0xff87fc00, asimdshf, OP_UXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV},
1830 {"ushll2", 0x6f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS},
1831 {"uxtl2", 0x6f00a400, 0xff87fc00, asimdshf, OP_UXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV},
a06ea964
NC		 1832 {"ucvtf", 0x2f00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
1833 {"fcvtzu", 0x2f00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
1834 /* AdvSIMD TBL/TBX. */
1835 {"tbl", 0xe000000, 0xbfe09c00, asimdtbl, 0, SIMD, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ},
1836 {"tbx", 0xe001000, 0xbfe09c00, asimdtbl, 0, SIMD, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ},
1837 /* AdvSIMD scalar three different. */
1838 {"sqdmlal", 0x5e209000, 0xff20fc00, asisddiff, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE},
1839 {"sqdmlsl", 0x5e20b000, 0xff20fc00, asisddiff, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE},
1840 {"sqdmull", 0x5e20d000, 0xff20fc00, asisddiff, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE},
1841 /* AdvSIMD scalar x indexed element. */
1842 {"sqdmlal", 0x5f003000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE},
1843 {"sqdmlsl", 0x5f007000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE},
1844 {"sqdmull", 0x5f00b000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE},
1845 {"sqdmulh", 0x5f00c000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
1846 {"sqrdmulh", 0x5f00d000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
1847 {"fmla", 0x5f801000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
1848 {"fmls", 0x5f805000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
1849 {"fmul", 0x5f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
1850 {"fmulx", 0x7f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
9e1f0fa7
MW		 1851 {"sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem, 0, RDMA, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
1852 {"sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem, 0, RDMA, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
a06ea964
NC		 1853 /* AdvSIMD load/store multiple structures. */
1854 {"st4", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
1855 {"st1", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
1856 {"st2", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
1857 {"st3", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
1858 {"ld4", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
1859 {"ld1", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
1860 {"ld2", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
1861 {"ld3", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
1862 /* AdvSIMD load/store multiple structures (post-indexed). */
1863 {"st4", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
1864 {"st1", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
1865 {"st2", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
1866 {"st3", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
1867 {"ld4", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
1868 {"ld1", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
1869 {"ld2", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
1870 {"ld3", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
1871 /* AdvSIMD load/store single structure. */
1872 {"st1", 0xd000000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)},
1873 {"st3", 0xd002000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)},
1874 {"st2", 0xd200000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)},
1875 {"st4", 0xd202000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)},
1876 {"ld1", 0xd400000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)},
1877 {"ld3", 0xd402000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)},
1878 {"ld1r", 0xd40c000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
1879 {"ld3r", 0xd40e000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)},
1880 {"ld2", 0xd600000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)},
1881 {"ld4", 0xd602000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)},
1882 {"ld2r", 0xd60c000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)},
1883 {"ld4r", 0xd60e000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)},
1884 /* AdvSIMD load/store single structure (post-indexed). */
1885 {"st1", 0xd800000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)},
1886 {"st3", 0xd802000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)},
1887 {"st2", 0xda00000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(2)},
1888 {"st4", 0xda02000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)},
1889 {"ld1", 0xdc00000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)},
1890 {"ld3", 0xdc02000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)},
1891 {"ld1r", 0xdc0c000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
1892 {"ld3r", 0xdc0e000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)},
1893 {"ld2", 0xde00000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(2)},
1894 {"ld4", 0xde02000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)},
1895 {"ld2r", 0xde0c000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)},
1896 {"ld4r", 0xde0e000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)},
1897 /* AdvSIMD scalar two-reg misc. */
1898 {"suqadd", 0x5e203800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE},
1899 {"sqabs", 0x5e207800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE},
1900 {"cmgt", 0x5e208800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
1901 {"cmeq", 0x5e209800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
1902 {"cmlt", 0x5e20a800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
1903 {"abs", 0x5e20b800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_2SAMED, F_SSIZE},
1904 {"sqxtn", 0x5e214800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE},
1905 {"fcvtns", 0x5e21a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1906 {"fcvtns", 0x5e79a800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1907 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 1908 {"fcvtms", 0x5e21b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1909 {"fcvtms", 0x5e79b800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1910 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 1911 {"fcvtas", 0x5e21c800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1912 {"fcvtas", 0x5e79c800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1913 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 1914 {"scvtf", 0x5e21d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1915 {"scvtf", 0x5e79d800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1916 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
f17c8bfc 1917 {"fcmgt", 0x5ea0c800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
80776b29
MW		 1918 {"fcmgt", 0x5ef8c800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1919 OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE},
f17c8bfc 1920 {"fcmeq", 0x5ea0d800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
80776b29
MW		 1921 {"fcmeq", 0x5ef8d800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1922 OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE},
f17c8bfc 1923 {"fcmlt", 0x5ea0e800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
80776b29
MW		 1924 {"fcmlt", 0x5ef8e800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1925 OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE},
a06ea964 1926 {"fcvtps", 0x5ea1a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1927 {"fcvtps", 0x5ef9a800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1928 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 1929 {"fcvtzs", 0x5ea1b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1930 {"fcvtzs", 0x5ef9b800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1931 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 1932 {"frecpe", 0x5ea1d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1933 {"frecpe", 0x5ef9d800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1934 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 1935 {"frecpx", 0x5ea1f800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1936 {"frecpx", 0x5ef9f800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1937 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964
NC		 1938 {"usqadd", 0x7e203800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE},
1939 {"sqneg", 0x7e207800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE},
1940 {"cmge", 0x7e208800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
1941 {"cmle", 0x7e209800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
1942 {"neg", 0x7e20b800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_2SAMED, F_SSIZE},
1943 {"sqxtun", 0x7e212800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE},
1944 {"uqxtn", 0x7e214800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE},
1945 {"fcvtxn", 0x7e216800, 0xffbffc00, asisdmisc, OP_FCVTXN_S, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW_S, F_MISC},
1946 {"fcvtnu", 0x7e21a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1947 {"fcvtnu", 0x7e79a800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1948 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 1949 {"fcvtmu", 0x7e21b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1950 {"fcvtmu", 0x7e79b800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1951 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 1952 {"fcvtau", 0x7e21c800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1953 {"fcvtau", 0x7e79c800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1954 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 1955 {"ucvtf", 0x7e21d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1956 {"ucvtf", 0x7e79d800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1957 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
f17c8bfc 1958 {"fcmge", 0x7ea0c800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
80776b29
MW		 1959 {"fcmge", 0x7ef8c800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1960 OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE},
f17c8bfc 1961 {"fcmle", 0x7ea0d800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
80776b29
MW		 1962 {"fcmle", 0x7ef8d800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1963 OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE},
a06ea964 1964 {"fcvtpu", 0x7ea1a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1965 {"fcvtpu", 0x7ef9a800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1966 OP2 (Sd, Sn), QL_SISD_FCMP_H_0, F_SSIZE},
a06ea964 1967 {"fcvtzu", 0x7ea1b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1968 {"fcvtzu", 0x7ef9b800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1969 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964 1970 {"frsqrte", 0x7ea1d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
80776b29
MW		 1971 {"frsqrte", 0x7ef9d800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1972 OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
a06ea964
NC		 1973 /* AdvSIMD scalar copy. */
1974 {"dup", 0x5e000400, 0xffe0fc00, asisdone, 0, SIMD, OP2 (Sd, En), QL_S_2SAME, F_HAS_ALIAS},
1975 {"mov", 0x5e000400, 0xffe0fc00, asisdone, 0, SIMD, OP2 (Sd, En), QL_S_2SAME, F_ALIAS},
1976 /* AdvSIMD scalar pairwise. */
1977 {"addp", 0x5e31b800, 0xff3ffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR_D, F_SIZEQ},
1978 {"fmaxnmp", 0x7e30c800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
1979 {"faddp", 0x7e30d800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
1980 {"fmaxp", 0x7e30f800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
1981 {"fminnmp", 0x7eb0c800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
1982 {"fminp", 0x7eb0f800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
1983 /* AdvSIMD scalar three same. */
1984 {"sqadd", 0x5e200c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
1985 {"sqsub", 0x5e202c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
1986 {"sqshl", 0x5e204c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
1987 {"sqrshl", 0x5e205c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
1988 {"sqdmulh", 0x5e20b400, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
1989 {"fmulx", 0x5e20dc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
6b4680fb
MW		 1990 {"fmulx", 0x5e401c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
1991 OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
a06ea964 1992 {"fcmeq", 0x5e20e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
6b4680fb
MW		 1993 {"fcmeq", 0x5e402400, 0xffe0fc00, asisdsame, 0, SIMD_F16,
1994 OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
a06ea964 1995 {"frecps", 0x5e20fc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
6b4680fb
MW		 1996 {"frecps", 0x5e403c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
1997 OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
a06ea964 1998 {"frsqrts", 0x5ea0fc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
6b4680fb
MW		 1999 {"frsqrts", 0x5ec03c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2000 OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
a06ea964
NC		 2001 {"cmgt", 0x5ee03400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2002 {"cmge", 0x5ee03c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2003 {"sshl", 0x5ee04400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2004 {"srshl", 0x5ee05400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2005 {"add", 0x5ee08400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2006 {"cmtst", 0x5ee08c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2007 {"uqadd", 0x7e200c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2008 {"uqsub", 0x7e202c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2009 {"uqshl", 0x7e204c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2010 {"uqrshl", 0x7e205c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2011 {"sqrdmulh", 0x7e20b400, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
2012 {"fcmge", 0x7e20e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
6b4680fb
MW		 2013 {"fcmge", 0x7e402400, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2014 OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
a06ea964 2015 {"facge", 0x7e20ec00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
6b4680fb
MW		 2016 {"facge", 0x7e402c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2017 OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
a06ea964 2018 {"fabd", 0x7ea0d400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
6b4680fb
MW		 2019 {"fabd", 0x7ec01400, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2020 OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
a06ea964 2021 {"fcmgt", 0x7ea0e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
6b4680fb
MW		 2022 {"fcmgt", 0x7ec02400, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2023 OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
a06ea964 2024 {"facgt", 0x7ea0ec00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
6b4680fb
MW		 2025 {"facgt", 0x7ec02c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2026 OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
a06ea964
NC		 2027 {"cmhi", 0x7ee03400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2028 {"cmhs", 0x7ee03c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2029 {"ushl", 0x7ee04400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2030 {"urshl", 0x7ee05400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2031 {"sub", 0x7ee08400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2032 {"cmeq", 0x7ee08c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
9e1f0fa7
MW		 2033 /* AdvSIMDs scalar three same extension. */
2034 {"sqrdmlah", 0x7e008400, 0xff20fc00, asimdsame, 0, RDMA, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
2035 {"sqrdmlsh", 0x7e008c00, 0xff20fc00, asimdsame, 0, RDMA, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
a06ea964
NC		 2036 /* AdvSIMD scalar shift by immediate. */
2037 {"sshr", 0x5f000400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2038 {"ssra", 0x5f001400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2039 {"srshr", 0x5f002400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2040 {"srsra", 0x5f003400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2041 {"shl", 0x5f005400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT_D, 0},
2042 {"sqshl", 0x5f007400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0},
2043 {"sqshrn", 0x5f009400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
2044 {"sqrshrn", 0x5f009c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
2045 {"scvtf", 0x5f00e400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
2046 {"fcvtzs", 0x5f00fc00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
2047 {"ushr", 0x7f000400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2048 {"usra", 0x7f001400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2049 {"urshr", 0x7f002400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2050 {"ursra", 0x7f003400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2051 {"sri", 0x7f004400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2052 {"sli", 0x7f005400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT_D, 0},
2053 {"sqshlu", 0x7f006400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0},
2054 {"uqshl", 0x7f007400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0},
2055 {"sqshrun", 0x7f008400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
2056 {"sqrshrun", 0x7f008c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
2057 {"uqshrn", 0x7f009400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
2058 {"uqrshrn", 0x7f009c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
2059 {"ucvtf", 0x7f00e400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
2060 {"fcvtzu", 0x7f00fc00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
2061 /* Bitfield. */
2062 {"sbfm", 0x13000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N},
2063 {"sbfiz", 0x13000000, 0x7f800000, bitfield, OP_SBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
2064 {"sbfx", 0x13000000, 0x7f800000, bitfield, OP_SBFX, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
2065 {"sxtb", 0x13001c00, 0x7fbffc00, bitfield, 0, CORE, OP2 (Rd, Rn), QL_EXT, F_ALIAS | F_P3 | F_SF | F_N},
2066 {"sxth", 0x13003c00, 0x7fbffc00, bitfield, 0, CORE, OP2 (Rd, Rn), QL_EXT, F_ALIAS | F_P3 | F_SF | F_N},
2067 {"sxtw", 0x93407c00, 0xfffffc00, bitfield, 0, CORE, OP2 (Rd, Rn), QL_EXT_W, F_ALIAS | F_P3},
2068 {"asr", 0x13000000, 0x7f800000, bitfield, OP_ASR_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV},
2069 {"bfm", 0x33000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N},
2070 {"bfi", 0x33000000, 0x7f800000, bitfield, OP_BFI, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
d685192a
MW		 2071 {"bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, ARMV8_2,
2072 OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV},
a06ea964
NC		 2073 {"bfxil", 0x33000000, 0x7f800000, bitfield, OP_BFXIL, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
2074 {"ubfm", 0x53000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N},
2075 {"ubfiz", 0x53000000, 0x7f800000, bitfield, OP_UBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
2076 {"ubfx", 0x53000000, 0x7f800000, bitfield, OP_UBFX, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
2077 {"uxtb", 0x53001c00, 0xfffffc00, bitfield, OP_UXTB, CORE, OP2 (Rd, Rn), QL_I2SAMEW, F_ALIAS | F_P3},
2078 {"uxth", 0x53003c00, 0xfffffc00, bitfield, OP_UXTH, CORE, OP2 (Rd, Rn), QL_I2SAMEW, F_ALIAS | F_P3},
2079 {"lsl", 0x53000000, 0x7f800000, bitfield, OP_LSL_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV},
2080 {"lsr", 0x53000000, 0x7f800000, bitfield, OP_LSR_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV},
2081 /* Unconditional branch (immediate). */
2082 {"b", 0x14000000, 0xfc000000, branch_imm, OP_B, CORE, OP1 (ADDR_PCREL26), QL_PCREL_26, 0},
2083 {"bl", 0x94000000, 0xfc000000, branch_imm, OP_BL, CORE, OP1 (ADDR_PCREL26), QL_PCREL_26, 0},
2084 /* Unconditional branch (register). */
2085 {"br", 0xd61f0000, 0xfffffc1f, branch_reg, 0, CORE, OP1 (Rn), QL_I1X, 0},
2086 {"blr", 0xd63f0000, 0xfffffc1f, branch_reg, 0, CORE, OP1 (Rn), QL_I1X, 0},
2087 {"ret", 0xd65f0000, 0xfffffc1f, branch_reg, 0, CORE, OP1 (Rn), QL_I1X, F_OPD0_OPT | F_DEFAULT (30)},
2088 {"eret", 0xd69f03e0, 0xffffffff, branch_reg, 0, CORE, OP0 (), {}, 0},
2089 {"drps", 0xd6bf03e0, 0xffffffff, branch_reg, 0, CORE, OP0 (), {}, 0},
2090 /* Compare & branch (immediate). */
2091 {"cbz", 0x34000000, 0x7f000000, compbranch, 0, CORE, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF},
2092 {"cbnz", 0x35000000, 0x7f000000, compbranch, 0, CORE, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF},
2093 /* Conditional branch (immediate). */
2094 {"b.c", 0x54000000, 0xff000010, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_COND},
2095 /* Conditional compare (immediate). */
2096 {"ccmn", 0x3a400800, 0x7fe00c10, condcmp_imm, 0, CORE, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM, F_SF},
2097 {"ccmp", 0x7a400800, 0x7fe00c10, condcmp_imm, 0, CORE, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM, F_SF},
2098 /* Conditional compare (register). */
2099 {"ccmn", 0x3a400000, 0x7fe00c10, condcmp_reg, 0, CORE, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF},
2100 {"ccmp", 0x7a400000, 0x7fe00c10, condcmp_reg, 0, CORE, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF},
2101 /* Conditional select. */
2102 {"csel", 0x1a800000, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_SF},
2103 {"csinc", 0x1a800400, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
68a64283
YZ		 2104 {"cinc", 0x1a800400, 0x7fe00c00, condsel, OP_CINC, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV},
2105 {"cset", 0x1a9f07e0, 0x7fff0fe0, condsel, OP_CSET, CORE, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
a06ea964 2106 {"csinv", 0x5a800000, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
68a64283
YZ		 2107 {"cinv", 0x5a800000, 0x7fe00c00, condsel, OP_CINV, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV},
2108 {"csetm", 0x5a9f03e0, 0x7fff0fe0, condsel, OP_CSETM, CORE, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
a06ea964 2109 {"csneg", 0x5a800400, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
68a64283 2110 {"cneg", 0x5a800400, 0x7fe00c00, condsel, OP_CNEG, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV},
a06ea964
NC		 2111 /* Crypto AES. */
2112 {"aese", 0x4e284800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
2113 {"aesd", 0x4e285800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
2114 {"aesmc", 0x4e286800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
2115 {"aesimc", 0x4e287800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
2116 /* Crypto two-reg SHA. */
2117 {"sha1h", 0x5e280800, 0xfffffc00, cryptosha2, 0, CRYPTO, OP2 (Fd, Fn), QL_2SAMES, 0},
2118 {"sha1su1", 0x5e281800, 0xfffffc00, cryptosha2, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME4S, 0},
2119 {"sha256su0", 0x5e282800, 0xfffffc00, cryptosha2, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME4S, 0},
2120 /* Crypto three-reg SHA. */
2121 {"sha1c", 0x5e000000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0},
2122 {"sha1p", 0x5e001000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0},
2123 {"sha1m", 0x5e002000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0},
2124 {"sha1su0", 0x5e003000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0},
2125 {"sha256h", 0x5e004000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHA256UPT, 0},
2126 {"sha256h2", 0x5e005000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHA256UPT, 0},
2127 {"sha256su1", 0x5e006000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0},
2128 /* Data-processing (1 source). */
2129 {"rbit", 0x5ac00000, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
2130 {"rev16", 0x5ac00400, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
2131 {"rev", 0x5ac00800, 0xfffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAMEW, 0},
64357d2e
MW		 2132 {"rev", 0xdac00c00, 0xfffffc00, dp_1src, 0, CORE,
2133 OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_HAS_ALIAS | F_P1},
2134 {"rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, ARMV8_2,
2135 OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS},
a06ea964
NC		 2136 {"clz", 0x5ac01000, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
2137 {"cls", 0x5ac01400, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
2138 {"rev32", 0xdac00800, 0xfffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAMEX, 0},
2139 /* Data-processing (2 source). */
2140 {"udiv", 0x1ac00800, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
2141 {"sdiv", 0x1ac00c00, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
2142 {"lslv", 0x1ac02000, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS},
2143 {"lsl", 0x1ac02000, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
2144 {"lsrv", 0x1ac02400, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS},
2145 {"lsr", 0x1ac02400, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
2146 {"asrv", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS},
2147 {"asr", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
2148 {"rorv", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS},
2149 {"ror", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
e60bb1dd
YZ		 2150 /* CRC instructions. */
2151 {"crc32b", 0x1ac04000, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
2152 {"crc32h", 0x1ac04400, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
2153 {"crc32w", 0x1ac04800, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
2154 {"crc32x", 0x9ac04c00, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3WWX, 0},
2155 {"crc32cb", 0x1ac05000, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
2156 {"crc32ch", 0x1ac05400, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
2157 {"crc32cw", 0x1ac05800, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
2158 {"crc32cx", 0x9ac05c00, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3WWX, 0},
a06ea964
NC		 2159 /* Data-processing (3 source). */
2160 {"madd", 0x1b000000, 0x7fe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF},
2161 {"mul", 0x1b007c00, 0x7fe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF},
2162 {"msub", 0x1b008000, 0x7fe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF},
2163 {"mneg", 0x1b00fc00, 0x7fe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF},
2164 {"smaddl", 0x9b200000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS},
2165 {"smull", 0x9b207c00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS},
2166 {"smsubl", 0x9b208000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS},
2167 {"smnegl", 0x9b20fc00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS},
2168 {"smulh", 0x9b407c00, 0xffe08000, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEX, 0},
2169 {"umaddl", 0x9ba00000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS},
2170 {"umull", 0x9ba07c00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS},
2171 {"umsubl", 0x9ba08000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS},
2172 {"umnegl", 0x9ba0fc00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS},
2173 {"umulh", 0x9bc07c00, 0xffe08000, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEX, 0},
2174 /* Excep'n generation. */
2175 {"svc", 0xd4000001, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
2176 {"hvc", 0xd4000002, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
2177 {"smc", 0xd4000003, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
2178 {"brk", 0xd4200000, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
2179 {"hlt", 0xd4400000, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
2180 {"dcps1", 0xd4a00001, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)},
2181 {"dcps2", 0xd4a00002, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)},
2182 {"dcps3", 0xd4a00003, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)},
2183 /* Extract. */
2184 {"extr", 0x13800000, 0x7fa00000, extract, 0, CORE, OP4 (Rd, Rn, Rm, IMMS), QL_EXTR, F_HAS_ALIAS | F_SF | F_N},
2185 {"ror", 0x13800000, 0x7fa00000, extract, OP_ROR_IMM, CORE, OP3 (Rd, Rm, IMMS), QL_SHIFT, F_ALIAS | F_CONV},
2186 /* Floating-point<->fixed-point conversions. */
2187 {"scvtf", 0x1e020000, 0x7f3f0000, float2fix, 0, FP, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF},
622b9eb1
MW		 2188 {"scvtf", 0x1ec20000, 0x7f3f0000, float2fix, 0, FP_F16,
2189 OP3 (Fd, Rn, FBITS), QL_FIX2FP_H, F_FPTYPE | F_SF},
a06ea964 2190 {"ucvtf", 0x1e030000, 0x7f3f0000, float2fix, 0, FP, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF},
622b9eb1
MW		 2191 {"ucvtf", 0x1ec30000, 0x7f3f0000, float2fix, 0, FP_F16,
2192 OP3 (Fd, Rn, FBITS), QL_FIX2FP_H, F_FPTYPE | F_SF},
a06ea964 2193 {"fcvtzs", 0x1e180000, 0x7f3f0000, float2fix, 0, FP, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF},
622b9eb1
MW		 2194 {"fcvtzs", 0x1ed80000, 0x7f3f0000, float2fix, 0, FP_F16,
2195 OP3 (Rd, Fn, FBITS), QL_FP2FIX_H, F_FPTYPE | F_SF},
a06ea964 2196 {"fcvtzu", 0x1e190000, 0x7f3f0000, float2fix, 0, FP, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF},
622b9eb1
MW		 2197 {"fcvtzu", 0x1ed90000, 0x7f3f0000, float2fix, 0, FP_F16,
2198 OP3 (Rd, Fn, FBITS), QL_FP2FIX_H, F_FPTYPE | F_SF},
a06ea964
NC		 2199 /* Floating-point<->integer conversions. */
2200 {"fcvtns", 0x1e200000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2201 {"fcvtns", 0x1ee00000, 0x7f3ffc00, float2int, 0, FP_F16,
2202 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2203 {"fcvtnu", 0x1e210000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2204 {"fcvtnu", 0x1ee10000, 0x7f3ffc00, float2int, 0, FP_F16,
2205 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2206 {"scvtf", 0x1e220000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF},
622b9eb1
MW		 2207 {"scvtf", 0x1ee20000, 0x7f3ffc00, float2int, 0, FP_F16,
2208 OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF},
a06ea964 2209 {"ucvtf", 0x1e230000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF},
622b9eb1
MW		 2210 {"ucvtf", 0x1ee30000, 0x7f3ffc00, float2int, 0, FP_F16,
2211 OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF},
a06ea964 2212 {"fcvtas", 0x1e240000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2213 {"fcvtas", 0x1ee40000, 0x7f3ffc00, float2int, 0, FP_F16,
2214 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2215 {"fcvtau", 0x1e250000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2216 {"fcvtau", 0x1ee50000, 0x7f3ffc00, float2int, 0, FP_F16,
2217 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2218 {"fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2219 {"fmov", 0x1ee60000, 0x7f3ffc00, float2int, 0, FP_F16,
2220 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2221 {"fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF},
622b9eb1
MW		 2222 {"fmov", 0x1ee70000, 0x7f3ffc00, float2int, 0, FP_F16,
2223 OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF},
a06ea964 2224 {"fcvtps", 0x1e280000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2225 {"fcvtps", 0x1ee80000, 0x7f3ffc00, float2int, 0, FP_F16,
2226 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2227 {"fcvtpu", 0x1e290000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2228 {"fcvtpu", 0x1ee90000, 0x7f3ffc00, float2int, 0, FP_F16,
2229 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2230 {"fcvtms", 0x1e300000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2231 {"fcvtms", 0x1ef00000, 0x7f3ffc00, float2int, 0, FP_F16,
2232 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2233 {"fcvtmu", 0x1e310000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2234 {"fcvtmu", 0x1ef10000, 0x7f3ffc00, float2int, 0, FP_F16,
2235 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2236 {"fcvtzs", 0x1e380000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2237 {"fcvtzs", 0x1ef80000, 0x7f3ffc00, float2int, 0, FP_F16,
2238 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964 2239 {"fcvtzu", 0x1e390000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
622b9eb1
MW		 2240 {"fcvtzu", 0x1ef90000, 0x7f3ffc00, float2int, 0, FP_F16,
2241 OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
a06ea964
NC		 2242 {"fmov", 0x9eae0000, 0xfffffc00, float2int, 0, FP, OP2 (Rd, VnD1), QL_XVD1, 0},
2243 {"fmov", 0x9eaf0000, 0xfffffc00, float2int, 0, FP, OP2 (VdD1, Rn), QL_VD1X, 0},
2244 /* Floating-point conditional compare. */
2245 {"fccmp", 0x1e200400, 0xff200c10, floatccmp, 0, FP, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE},
622b9eb1
MW		 2246 {"fccmp", 0x1ee00400, 0xff200c10, floatccmp, 0, FP_F16,
2247 OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE},
a06ea964 2248 {"fccmpe", 0x1e200410, 0xff200c10, floatccmp, 0, FP, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE},
622b9eb1
MW		 2249 {"fccmpe", 0x1ee00410, 0xff200c10, floatccmp, 0, FP_F16,
2250 OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE},
a06ea964
NC		 2251 /* Floating-point compare. */
2252 {"fcmp", 0x1e202000, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, Fm), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2253 {"fcmp", 0x1ee02000, 0xff20fc1f, floatcmp, 0, FP_F16,
2254 OP2 (Fn, Fm), QL_FP2_H, F_FPTYPE},
a06ea964 2255 {"fcmpe", 0x1e202010, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, Fm), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2256 {"fcmpe", 0x1ee02010, 0xff20fc1f, floatcmp, 0, FP_F16,
2257 OP2 (Fn, Fm), QL_FP2_H, F_FPTYPE},
a06ea964 2258 {"fcmp", 0x1e202008, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, FPIMM0), QL_DST_SD, F_FPTYPE},
622b9eb1
MW		 2259 {"fcmp", 0x1ee02008, 0xff20fc1f, floatcmp, 0, FP_F16,
2260 OP2 (Fn, FPIMM0), QL_FP2_H, F_FPTYPE},
a06ea964 2261 {"fcmpe", 0x1e202018, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, FPIMM0), QL_DST_SD, F_FPTYPE},
622b9eb1
MW		 2262 {"fcmpe", 0x1ee02018, 0xff20fc1f, floatcmp, 0, FP_F16,
2263 OP2 (Fn, FPIMM0), QL_FP2_H, F_FPTYPE},
a06ea964
NC		 2264 /* Floating-point data-processing (1 source). */
2265 {"fmov", 0x1e204000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2266 {"fmov", 0x1ee04000, 0xff3ffc00, floatdp1, 0, FP_F16,
2267 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964 2268 {"fabs", 0x1e20c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2269 {"fabs", 0x1ee0c000, 0xff3ffc00, floatdp1, 0, FP_F16,
2270 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964 2271 {"fneg", 0x1e214000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2272 {"fneg", 0x1ee14000, 0xff3ffc00, floatdp1, 0, FP_F16,
2273 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964 2274 {"fsqrt", 0x1e21c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2275 {"fsqrt", 0x1ee1c000, 0xff3ffc00, floatdp1, 0, FP_F16,
2276 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964
NC		 2277 {"fcvt", 0x1e224000, 0xff3e7c00, floatdp1, OP_FCVT, FP, OP2 (Fd, Fn), QL_FCVT, F_FPTYPE | F_MISC},
2278 {"frintn", 0x1e244000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2279 {"frintn", 0x1ee44000, 0xff3ffc00, floatdp1, 0, FP_F16,
2280 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964 2281 {"frintp", 0x1e24c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2282 {"frintp", 0x1ee4c000, 0xff3ffc00, floatdp1, 0, FP_F16,
2283 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964 2284 {"frintm", 0x1e254000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2285 {"frintm", 0x1ee54000, 0xff3ffc00, floatdp1, 0, FP_F16,
2286 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964 2287 {"frintz", 0x1e25c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2288 {"frintz", 0x1ee5c000, 0xff3ffc00, floatdp1, 0, FP_F16,
2289 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964 2290 {"frinta", 0x1e264000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2291 {"frinta", 0x1ee64000, 0xff3ffc00, floatdp1, 0, FP_F16,
2292 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964 2293 {"frintx", 0x1e274000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2294 {"frintx", 0x1ee74000, 0xff3ffc00, floatdp1, 0, FP_F16,
2295 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964 2296 {"frinti", 0x1e27c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
622b9eb1
MW		 2297 {"frinti", 0x1ee7c000, 0xff3ffc00, floatdp1, 0, FP_F16,
2298 OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
a06ea964
NC		 2299 /* Floating-point data-processing (2 source). */
2300 {"fmul", 0x1e200800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
622b9eb1
MW		 2301 {"fmul", 0x1ee00800, 0xff20fc00, floatdp2, 0, FP_F16,
2302 OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
a06ea964 2303 {"fdiv", 0x1e201800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
622b9eb1
MW		 2304 {"fdiv", 0x1ee01800, 0xff20fc00, floatdp2, 0, FP_F16,
2305 OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
a06ea964 2306 {"fadd", 0x1e202800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
622b9eb1
MW		 2307 {"fadd", 0x1ee02800, 0xff20fc00, floatdp2, 0, FP_F16,
2308 OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
a06ea964 2309 {"fsub", 0x1e203800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
622b9eb1
MW		 2310 {"fsub", 0x1ee03800, 0xff20fc00, floatdp2, 0, FP_F16,
2311 OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
a06ea964 2312 {"fmax", 0x1e204800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
622b9eb1
MW		 2313 {"fmax", 0x1ee04800, 0xff20fc00, floatdp2, 0, FP_F16,
2314 OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
a06ea964 2315 {"fmin", 0x1e205800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
622b9eb1
MW		 2316 {"fmin", 0x1ee05800, 0xff20fc00, floatdp2, 0, FP_F16,
2317 OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
a06ea964 2318 {"fmaxnm", 0x1e206800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
622b9eb1
MW		 2319 {"fmaxnm", 0x1ee06800, 0xff20fc00, floatdp2, 0, FP_F16,
2320 OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
a06ea964 2321 {"fminnm", 0x1e207800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
622b9eb1
MW		 2322 {"fminnm", 0x1ee07800, 0xff20fc00, floatdp2, 0, FP_F16,
2323 OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
a06ea964 2324 {"fnmul", 0x1e208800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
622b9eb1
MW		 2325 {"fnmul", 0x1ee08800, 0xff20fc00, floatdp2, 0, FP_F16,
2326 OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
a06ea964
NC		 2327 /* Floating-point data-processing (3 source). */
2328 {"fmadd", 0x1f000000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
622b9eb1
MW		 2329 {"fmadd", 0x1fc00000, 0xff208000, floatdp3, 0, FP_F16,
2330 OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE},
a06ea964 2331 {"fmsub", 0x1f008000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
622b9eb1
MW		 2332 {"fmsub", 0x1fc08000, 0xff208000, floatdp3, 0, FP_F16,
2333 OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE},
a06ea964 2334 {"fnmadd", 0x1f200000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
622b9eb1
MW		 2335 {"fnmadd", 0x1fe00000, 0xff208000, floatdp3, 0, FP_F16,
2336 OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE},
a06ea964 2337 {"fnmsub", 0x1f208000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
622b9eb1
MW		 2338 {"fnmsub", 0x1fe08000, 0xff208000, floatdp3, 0, FP_F16,
2339 OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE},
a06ea964
NC		 2340 /* Floating-point immediate. */
2341 {"fmov", 0x1e201000, 0xff201fe0, floatimm, 0, FP, OP2 (Fd, FPIMM), QL_DST_SD, F_FPTYPE},
622b9eb1
MW		 2342 {"fmov", 0x1ee01000, 0xff201fe0, floatimm, 0, FP_F16,
2343 OP2 (Fd, FPIMM), QL_DST_H, F_FPTYPE},
a06ea964
NC		 2344 /* Floating-point conditional select. */
2345 {"fcsel", 0x1e200c00, 0xff200c00, floatsel, 0, FP, OP4 (Fd, Fn, Fm, COND), QL_FP_COND, F_FPTYPE},
622b9eb1
MW		 2346 {"fcsel", 0x1ee00c00, 0xff200c00, floatsel, 0, FP_F16,
2347 OP4 (Fd, Fn, Fm, COND), QL_FP_COND_H, F_FPTYPE},
a06ea964
NC		 2348 /* Load/store register (immediate indexed). */
2349 {"strb", 0x38000400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
2350 {"ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
2351 {"ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE},
2352 {"str", 0x3c000400, 0x3f600400, ldst_imm9, 0, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0},
2353 {"ldr", 0x3c400400, 0x3f600400, ldst_imm9, 0, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0},
2354 {"strh", 0x78000400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
2355 {"ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
2356 {"ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE},
2357 {"str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
2358 {"ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
2359 {"ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0},
2360 /* Load/store register (unsigned immediate). */
2361 {"strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0},
2362 {"ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0},
2363 {"ldrsb", 0x39800000, 0xff800000, ldst_pos, OP_LDRSB_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R8, F_LDS_SIZE},
2364 {"str", 0x3d000000, 0x3f400000, ldst_pos, OP_STRF_POS, CORE, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0},
2365 {"ldr", 0x3d400000, 0x3f400000, ldst_pos, OP_LDRF_POS, CORE, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0},
2366 {"strh", 0x79000000, 0xffc00000, ldst_pos, OP_STRH_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0},
2367 {"ldrh", 0x79400000, 0xffc00000, ldst_pos, OP_LDRH_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0},
2368 {"ldrsh", 0x79800000, 0xff800000, ldst_pos, OP_LDRSH_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R16, F_LDS_SIZE},
2369 {"str", 0xb9000000, 0xbfc00000, ldst_pos, OP_STR_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q},
2370 {"ldr", 0xb9400000, 0xbfc00000, ldst_pos, OP_LDR_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q},
2371 {"ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0},
2372 {"prfm", 0xf9800000, 0xffc00000, ldst_pos, OP_PRFM_POS, CORE, OP2 (PRFOP, ADDR_UIMM12), QL_LDST_PRFM, 0},
2373 /* Load/store register (register offset). */
2374 {"strb", 0x38200800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0},
2375 {"ldrb", 0x38600800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0},
2376 {"ldrsb", 0x38a00800, 0xffa00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R8, F_LDS_SIZE},
2377 {"str", 0x3c200800, 0x3f600c00, ldst_regoff, 0, CORE, OP2 (Ft, ADDR_REGOFF), QL_LDST_FP, 0},
2378 {"ldr", 0x3c600800, 0x3f600c00, ldst_regoff, 0, CORE, OP2 (Ft, ADDR_REGOFF), QL_LDST_FP, 0},
2379 {"strh", 0x78200800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W16, 0},
2380 {"ldrh", 0x78600800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W16, 0},
2381 {"ldrsh", 0x78a00800, 0xffa00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R16, F_LDS_SIZE},
2382 {"str", 0xb8200800, 0xbfe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R, F_GPRSIZE_IN_Q},
2383 {"ldr", 0xb8600800, 0xbfe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R, F_GPRSIZE_IN_Q},
2384 {"ldrsw", 0xb8a00800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_X32, 0},
2385 {"prfm", 0xf8a00800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (PRFOP, ADDR_REGOFF), QL_LDST_PRFM, 0},
2386 /* Load/store register (unprivileged). */
2387 {"sttrb", 0x38000800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
2388 {"ldtrb", 0x38400800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
2389 {"ldtrsb", 0x38800800, 0xffa00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE},
2390 {"sttrh", 0x78000800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
2391 {"ldtrh", 0x78400800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
2392 {"ldtrsh", 0x78800800, 0xffa00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE},
2393 {"sttr", 0xb8000800, 0xbfe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
2394 {"ldtr", 0xb8400800, 0xbfe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
2395 {"ldtrsw", 0xb8800800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0},
2396 /* Load/store register (unscaled immediate). */
c8f89a34
JW		 2397 {"sturb", 0x38000000, 0xffe00c00, ldst_unscaled, OP_STURB, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
2398 {"ldurb", 0x38400000, 0xffe00c00, ldst_unscaled, OP_LDURB, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
2399 {"ldursb", 0x38800000, 0xffa00c00, ldst_unscaled, OP_LDURSB, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE},
2400 {"stur", 0x3c000000, 0x3f600c00, ldst_unscaled, OP_STURV, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0},
2401 {"ldur", 0x3c400000, 0x3f600c00, ldst_unscaled, OP_LDURV, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0},
2402 {"sturh", 0x78000000, 0xffe00c00, ldst_unscaled, OP_STURH, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
2403 {"ldurh", 0x78400000, 0xffe00c00, ldst_unscaled, OP_LDURH, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
2404 {"ldursh", 0x78800000, 0xffa00c00, ldst_unscaled, OP_LDURSH, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE},
2405 {"stur", 0xb8000000, 0xbfe00c00, ldst_unscaled, OP_STUR, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
2406 {"ldur", 0xb8400000, 0xbfe00c00, ldst_unscaled, OP_LDUR, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
2407 {"ldursw", 0xb8800000, 0xffe00c00, ldst_unscaled, OP_LDURSW, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0},
2408 {"prfum", 0xf8800000, 0xffe00c00, ldst_unscaled, OP_PRFUM, CORE, OP2 (PRFOP, ADDR_SIMM9), QL_LDST_PRFM, 0},
a06ea964
NC		 2409 /* Load/store exclusive. */
2410 {"stxrb", 0x8007c00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2411 {"stlxrb", 0x800fc00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2412 {"ldxrb", 0x85f7c00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2413 {"ldaxrb", 0x85ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2414 {"stlrb", 0x89ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
ee804238 2415 {"ldarb", 0x8dffc00, 0xffeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
a06ea964
NC		 2416 {"stxrh", 0x48007c00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2417 {"stlxrh", 0x4800fc00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2418 {"ldxrh", 0x485f7c00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2419 {"ldaxrh", 0x485ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2420 {"stlrh", 0x489ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
ee804238 2421 {"ldarh", 0x48dffc00, 0xffeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
a06ea964
NC		 2422 {"stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q},
2423 {"stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q},
2424 {"stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, CORE, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q},
2425 {"stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, CORE, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q},
2426 {"ldxr", 0x885f7c00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
2427 {"ldaxr", 0x885ffc00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
2428 {"ldxp", 0x887f0000, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q},
2429 {"ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q},
2430 {"stlr", 0x889ffc00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
ee804238 2431 {"ldar", 0x88dffc00, 0xbfeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
290806fd
MW		 2432 /* Limited Ordering Regions load/store instructions. */
2433 {"ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
2434 {"ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2435 {"ldlarh", 0x48df7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2436 {"stllr", 0x889f7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
2437 {"stllrb", 0x089f7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2438 {"stllrh", 0x489f7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
a06ea964
NC		 2439 /* Load/store no-allocate pair (offset). */
2440 {"stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
2441 {"ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
2442 {"stnp", 0x2c000000, 0x3fc00000, ldstnapair_offs, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
2443 {"ldnp", 0x2c400000, 0x3fc00000, ldstnapair_offs, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
2444 /* Load/store register pair (offset). */
2445 {"stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
2446 {"ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
2447 {"stp", 0x2d000000, 0x3fc00000, ldstpair_off, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
2448 {"ldp", 0x2d400000, 0x3fc00000, ldstpair_off, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
2449 {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0},
2450 /* Load/store register pair (indexed). */
2451 {"stp", 0x28800000, 0x7ec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
2452 {"ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
2453 {"stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
2454 {"ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
2455 {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0},
2456 /* Load register (literal). */
2457 {"ldr", 0x18000000, 0xbf000000, loadlit, OP_LDR_LIT, CORE, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_GPRSIZE_IN_Q},
2458 {"ldr", 0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT, CORE, OP2 (Ft, ADDR_PCREL19), QL_FP_PCREL, 0},
2459 {"ldrsw", 0x98000000, 0xff000000, loadlit, OP_LDRSW_LIT, CORE, OP2 (Rt, ADDR_PCREL19), QL_X_PCREL, 0},
2460 {"prfm", 0xd8000000, 0xff000000, loadlit, OP_PRFM_LIT, CORE, OP2 (PRFOP, ADDR_PCREL19), QL_PRFM_PCREL, 0},
2461 /* Logical (immediate). */
2462 {"and", 0x12000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
2463 {"bic", 0x12000000, 0x7f800000, log_imm, OP_BIC, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_ALIAS | F_PSEUDO | F_SF},
2464 {"orr", 0x32000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
fb098a1e 2465 {"mov", 0x320003e0, 0x7f8003e0, log_imm, OP_MOV_IMM_LOG, CORE, OP2 (Rd_SP, IMM_MOV), QL_R1NIL, F_ALIAS | F_P1 | F_SF | F_CONV},
a06ea964
NC		 2466 {"eor", 0x52000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_SF},
2467 {"ands", 0x72000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
2468 {"tst", 0x7200001f, 0x7f80001f, log_imm, 0, CORE, OP2 (Rn, LIMM), QL_R1NIL, F_ALIAS | F_SF},
2469 /* Logical (shifted register). */
2470 {"and", 0xa000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
2471 {"bic", 0xa200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
2472 {"orr", 0x2a000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
2473 {"mov", 0x2a0003e0, 0x7f2003e0, log_shift, 0, CORE, OP2 (Rd, Rm), QL_I2SAMER, F_ALIAS | F_SF},
2474 {"uxtw", 0x2a0003e0, 0x7f2003e0, log_shift, OP_UXTW, CORE, OP2 (Rd, Rm), QL_I2SAMEW, F_ALIAS | F_PSEUDO},
2475 {"orn", 0x2a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
2476 {"mvn", 0x2a2003e0, 0x7f2003e0, log_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF},
2477 {"eor", 0x4a000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
2478 {"eon", 0x4a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
2479 {"ands", 0x6a000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
2480 {"tst", 0x6a00001f, 0x7f20001f, log_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF},
2481 {"bics", 0x6a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
ee804238
JW		 2482 /* LSE extension (atomic). */
2483 {"casb", 0x8a07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2484 {"cash", 0x48a07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2485 {"cas", 0x88a07c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2486 {"casab", 0x8e07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2487 {"caslb", 0x8a0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2488 {"casalb", 0x8e0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2489 {"casah", 0x48e07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2490 {"caslh", 0x48a0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2491 {"casalh", 0x48e0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2492 {"casa", 0x88e07c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2493 {"casl", 0x88a0fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2494 {"casal", 0x88e0fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2495 {"casp", 0x8207c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ},
2496 {"caspa", 0x8607c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ},
2497 {"caspl", 0x820fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ},
2498 {"caspal", 0x860fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ},
2499 {"swpb", 0x38208000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2500 {"swph", 0x78208000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2501 {"swp", 0xb8208000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2502 {"swpab", 0x38a08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2503 {"swplb", 0x38608000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2504 {"swpalb", 0x38e08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2505 {"swpah", 0x78a08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2506 {"swplh", 0x78608000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2507 {"swpalh", 0x78e08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2508 {"swpa", 0xb8a08000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2509 {"swpl", 0xb8608000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2510 {"swpal", 0xb8e08000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2511 {"ldaddb", 0x38200000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2512 {"ldaddh", 0x78200000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2513 {"ldadd", 0xb8200000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2514 {"ldaddab", 0x38a00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2515 {"ldaddlb", 0x38600000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2516 {"ldaddalb", 0x38e00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2517 {"ldaddah", 0x78a00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2518 {"ldaddlh", 0x78600000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2519 {"ldaddalh", 0x78e00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2520 {"ldadda", 0xb8a00000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2521 {"ldaddl", 0xb8600000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2522 {"ldaddal", 0xb8e00000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2523 {"ldclrb", 0x38201000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2524 {"ldclrh", 0x78201000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2525 {"ldclr", 0xb8201000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2526 {"ldclrab", 0x38a01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2527 {"ldclrlb", 0x38601000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2528 {"ldclralb", 0x38e01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2529 {"ldclrah", 0x78a01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2530 {"ldclrlh", 0x78601000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2531 {"ldclralh", 0x78e01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2532 {"ldclra", 0xb8a01000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2533 {"ldclrl", 0xb8601000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2534 {"ldclral", 0xb8e01000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2535 {"ldeorb", 0x38202000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2536 {"ldeorh", 0x78202000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2537 {"ldeor", 0xb8202000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2538 {"ldeorab", 0x38a02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2539 {"ldeorlb", 0x38602000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2540 {"ldeoralb", 0x38e02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2541 {"ldeorah", 0x78a02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2542 {"ldeorlh", 0x78602000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2543 {"ldeoralh", 0x78e02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2544 {"ldeora", 0xb8a02000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2545 {"ldeorl", 0xb8602000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2546 {"ldeoral", 0xb8e02000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2547 {"ldsetb", 0x38203000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2548 {"ldseth", 0x78203000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2549 {"ldset", 0xb8203000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2550 {"ldsetab", 0x38a03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2551 {"ldsetlb", 0x38603000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2552 {"ldsetalb", 0x38e03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2553 {"ldsetah", 0x78a03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2554 {"ldsetlh", 0x78603000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2555 {"ldsetalh", 0x78e03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2556 {"ldseta", 0xb8a03000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2557 {"ldsetl", 0xb8603000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2558 {"ldsetal", 0xb8e03000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2559 {"ldsmaxb", 0x38204000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2560 {"ldsmaxh", 0x78204000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2561 {"ldsmax", 0xb8204000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2562 {"ldsmaxab", 0x38a04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2563 {"ldsmaxlb", 0x38604000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2564 {"ldsmaxalb", 0x38e04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2565 {"ldsmaxah", 0x78a04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2566 {"ldsmaxlh", 0x78604000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2567 {"ldsmaxalh", 0x78e04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2568 {"ldsmaxa", 0xb8a04000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2569 {"ldsmaxl", 0xb8604000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2570 {"ldsmaxal", 0xb8e04000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2571 {"ldsminb", 0x38205000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2572 {"ldsminh", 0x78205000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2573 {"ldsmin", 0xb8205000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2574 {"ldsminab", 0x38a05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2575 {"ldsminlb", 0x38605000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2576 {"ldsminalb", 0x38e05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2577 {"ldsminah", 0x78a05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2578 {"ldsminlh", 0x78605000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2579 {"ldsminalh", 0x78e05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2580 {"ldsmina", 0xb8a05000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2581 {"ldsminl", 0xb8605000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2582 {"ldsminal", 0xb8e05000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2583 {"ldumaxb", 0x38206000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2584 {"ldumaxh", 0x78206000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2585 {"ldumax", 0xb8206000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2586 {"ldumaxab", 0x38a06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2587 {"ldumaxlb", 0x38606000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2588 {"ldumaxalb", 0x38e06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2589 {"ldumaxah", 0x78a06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2590 {"ldumaxlh", 0x78606000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2591 {"ldumaxalh", 0x78e06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2592 {"ldumaxa", 0xb8a06000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2593 {"ldumaxl", 0xb8606000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2594 {"ldumaxal", 0xb8e06000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2595 {"lduminb", 0x38207000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2596 {"lduminh", 0x78207000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2597 {"ldumin", 0xb8207000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2598 {"lduminab", 0x38a07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2599 {"lduminlb", 0x38607000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2600 {"lduminalb", 0x38e07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2601 {"lduminah", 0x78a07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2602 {"lduminlh", 0x78607000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2603 {"lduminalh", 0x78e07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2604 {"ldumina", 0xb8a07000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2605 {"lduminl", 0xb8607000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2606 {"lduminal", 0xb8e07000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2607 {"staddb", 0x3820001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2608 {"staddh", 0x7820001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2609 {"stadd", 0xb820001f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2610 {"staddlb", 0x3860001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2611 {"staddlh", 0x7860001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2612 {"staddl", 0xb860001f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2613 {"stclrb", 0x3820101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2614 {"stclrh", 0x7820101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2615 {"stclr", 0xb820101f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2616 {"stclrlb", 0x3860101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2617 {"stclrlh", 0x7860101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2618 {"stclrl", 0xb860101f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2619 {"steorb", 0x3820201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2620 {"steorh", 0x7820201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2621 {"steor", 0xb820201f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2622 {"steorlb", 0x3860201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2623 {"steorlh", 0x7860201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2624 {"steorl", 0xb860201f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2625 {"stsetb", 0x3820301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2626 {"stseth", 0x7820301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2627 {"stset", 0xb820301f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2628 {"stsetlb", 0x3860301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2629 {"stsetlh", 0x7860301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2630 {"stsetl", 0xb860301f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2631 {"stsmaxb", 0x3820401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2632 {"stsmaxh", 0x7820401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2633 {"stsmax", 0xb820401f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2634 {"stsmaxlb", 0x3860401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2635 {"stsmaxlh", 0x7860401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2636 {"stsmaxl", 0xb860401f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2637 {"stsminb", 0x3820501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2638 {"stsminh", 0x7820501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2639 {"stsmin", 0xb820501f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2640 {"stsminlb", 0x3860501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2641 {"stsminlh", 0x7860501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2642 {"stsminl", 0xb860501f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2643 {"stumaxb", 0x3820601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2644 {"stumaxh", 0x7820601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2645 {"stumax", 0xb820601f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2646 {"stumaxlb", 0x3860601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2647 {"stumaxlh", 0x7860601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2648 {"stumaxl", 0xb860601f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2649 {"stuminb", 0x3820701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2650 {"stuminh", 0x7820701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2651 {"stumin", 0xb820701f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2652 {"stuminlb", 0x3860701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2653 {"stuminlh", 0x7860701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2654 {"stuminl", 0xb860701f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
a06ea964
NC		 2655 /* Move wide (immediate). */
2656 {"movn", 0x12800000, 0x7f800000, movewide, OP_MOVN, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS},
fb098a1e 2657 {"mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV},
a06ea964 2658 {"movz", 0x52800000, 0x7f800000, movewide, OP_MOVZ, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS},
fb098a1e 2659 {"mov", 0x52800000, 0x7f800000, movewide, OP_MOV_IMM_WIDE, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV},
a06ea964
NC		 2660 {"movk", 0x72800000, 0x7f800000, movewide, OP_MOVK, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF},
2661 /* PC-rel. addressing. */
2662 {"adr", 0x10000000, 0x9f000000, pcreladdr, 0, CORE, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0},
2663 {"adrp", 0x90000000, 0x9f000000, pcreladdr, 0, CORE, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0},
2664 /* System. */
2665 {"msr", 0xd500401f, 0xfff8f01f, ic_system, 0, CORE, OP2 (PSTATEFIELD, UIMM4), {}, 0},
2666 {"hint", 0xd503201f, 0xfffff01f, ic_system, 0, CORE, OP1 (UIMM7), {}, F_HAS_ALIAS},
2667 {"nop", 0xd503201f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
2668 {"yield", 0xd503203f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
2669 {"wfe", 0xd503205f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
2670 {"wfi", 0xd503207f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
2671 {"sev", 0xd503209f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
2672 {"sevl", 0xd50320bf, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
c8a6db6f 2673 {"esb", 0xd503221f, 0xffffffff, ic_system, 0, RAS, OP0 (), {}, F_ALIAS},
1e6f4800
MW		 2674 {"psb", 0xd503223f, 0xffffffff, ic_system, 0, STAT_PROFILE,
2675 OP1 (BARRIER_PSB), {}, F_ALIAS },
a06ea964
NC		 2676 {"clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, CORE, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)},
2677 {"dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER), {}, 0},
2678 {"dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER), {}, 0},
2679 {"isb", 0xd50330df, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER_ISB), {}, F_OPD0_OPT | F_DEFAULT (0xF)},
2680 {"sys", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP5 (UIMM3_OP1, Cn, Cm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)},
2681 {"at", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS},
2682 {"dc", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS},
2683 {"ic", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)},
2684 {"tlbi", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)},
df7b4545 2685 {"msr", 0xd5000000, 0xffe00000, ic_system, 0, CORE, OP2 (SYSREG, Rt), QL_SRC_X, 0},
a06ea964 2686 {"sysl", 0xd5280000, 0xfff80000, ic_system, 0, CORE, OP5 (Rt, UIMM3_OP1, Cn, Cm, UIMM3_OP2), QL_SYSL, 0},
df7b4545 2687 {"mrs", 0xd5200000, 0xffe00000, ic_system, 0, CORE, OP2 (Rt, SYSREG), QL_DST_X, 0},
a06ea964
NC		 2688 /* Test & branch (immediate). */
2689 {"tbz", 0x36000000, 0x7f000000, testbranch, 0, CORE, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0},
2690 {"tbnz", 0x37000000, 0x7f000000, testbranch, 0, CORE, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0},
2691 /* The old UAL conditional branch mnemonics (to aid portability). */
2692 {"beq", 0x54000000, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2693 {"bne", 0x54000001, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2694 {"bcs", 0x54000002, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2695 {"bhs", 0x54000002, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2696 {"bcc", 0x54000003, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2697 {"blo", 0x54000003, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2698 {"bmi", 0x54000004, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2699 {"bpl", 0x54000005, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2700 {"bvs", 0x54000006, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2701 {"bvc", 0x54000007, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2702 {"bhi", 0x54000008, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2703 {"bls", 0x54000009, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2704 {"bge", 0x5400000a, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2705 {"blt", 0x5400000b, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2706 {"bgt", 0x5400000c, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2707 {"ble", 0x5400000d, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2708
2709 {0, 0, 0, 0, 0, 0, {}, {}, 0},
2710};
2711
2712#ifdef AARCH64_OPERANDS
2713#undef AARCH64_OPERANDS
2714#endif
2715
2716/* Macro-based operand decription; this will be fed into aarch64-gen for it
2717 to generate the structure aarch64_operands and the function
2718 aarch64_insert_operand and aarch64_extract_operand.
2719
2720 These inserters and extracters in the description execute the conversion
2721 between the aarch64_opnd_info and value in the operand-related instruction
2722 field(s). */
2723
2724/* Y expects arguments (left to right) to be operand class, inserter/extractor
2725 name suffix, operand name, flags, related bitfield(s) and description.
2726 X only differs from Y by having the operand inserter and extractor names
2727 listed separately. */
2728
2729#define AARCH64_OPERANDS \
2730 Y(INT_REG, regno, "Rd", 0, F(FLD_Rd), "an integer register") \
2731 Y(INT_REG, regno, "Rn", 0, F(FLD_Rn), "an integer register") \
2732 Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register") \
2733 Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register") \
2734 Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register") \
2735 Y(INT_REG, regno, "Rs", 0, F(FLD_Rs), "an integer register") \
2736 Y(INT_REG, regno, "Ra", 0, F(FLD_Ra), "an integer register") \
2737 X(INT_REG, ins_regno, ext_regrt_sysins, "Rt_SYS", 0, F(FLD_Rt), \
2738 "an integer register") \
2739 Y(INT_REG, regno, "Rd_SP", OPD_F_MAYBE_SP, F(FLD_Rd), \
2740 "an integer or stack pointer register") \
2741 Y(INT_REG, regno, "Rn_SP", OPD_F_MAYBE_SP, F(FLD_Rn), \
2742 "an integer or stack pointer register") \
ee804238
JW		 2743 X(INT_REG, 0, ext_regno_pair, "PAIRREG", 0, F(), \
2744 "the second reg of a pair") \
a06ea964
NC		 2745 Y(MODIFIED_REG, reg_extended, "Rm_EXT", 0, F(), \
2746 "an integer register with optional extension") \
2747 Y(MODIFIED_REG, reg_shifted, "Rm_SFT", 0, F(), \
2748 "an integer register with optional shift") \
2749 Y(FP_REG, regno, "Fd", 0, F(FLD_Rd), "a floating-point register") \
2750 Y(FP_REG, regno, "Fn", 0, F(FLD_Rn), "a floating-point register") \
2751 Y(FP_REG, regno, "Fm", 0, F(FLD_Rm), "a floating-point register") \
2752 Y(FP_REG, regno, "Fa", 0, F(FLD_Ra), "a floating-point register") \
2753 Y(FP_REG, ft, "Ft", 0, F(FLD_Rt), "a floating-point register") \
2754 Y(FP_REG, regno, "Ft2", 0, F(FLD_Rt2), "a floating-point register") \
2755 Y(SISD_REG, regno, "Sd", 0, F(FLD_Rd), "a SIMD scalar register") \
2756 Y(SISD_REG, regno, "Sn", 0, F(FLD_Rn), "a SIMD scalar register") \
2757 Y(SISD_REG, regno, "Sm", 0, F(FLD_Rm), "a SIMD scalar register") \
2758 Y(SIMD_REG, regno, "Vd", 0, F(FLD_Rd), "a SIMD vector register") \
2759 Y(SIMD_REG, regno, "Vn", 0, F(FLD_Rn), "a SIMD vector register") \
2760 Y(SIMD_REG, regno, "Vm", 0, F(FLD_Rm), "a SIMD vector register") \
2761 Y(FP_REG, regno, "VdD1", 0, F(FLD_Rd), \
2762 "the top half of a 128-bit FP/SIMD register") \
2763 Y(FP_REG, regno, "VnD1", 0, F(FLD_Rn), \
2764 "the top half of a 128-bit FP/SIMD register") \
2765 Y(SIMD_ELEMENT, reglane, "Ed", 0, F(FLD_Rd), \
2766 "a SIMD vector element") \
2767 Y(SIMD_ELEMENT, reglane, "En", 0, F(FLD_Rn), \
2768 "a SIMD vector element") \
2769 Y(SIMD_ELEMENT, reglane, "Em", 0, F(FLD_Rm), \
2770 "a SIMD vector element") \
2771 Y(SIMD_REGLIST, reglist, "LVn", 0, F(FLD_Rn), \
2772 "a SIMD vector register list") \
2773 Y(SIMD_REGLIST, ldst_reglist, "LVt", 0, F(), \
2774 "a SIMD vector register list") \
2775 Y(SIMD_REGLIST, ldst_reglist_r, "LVt_AL", 0, F(), \
2776 "a SIMD vector register list") \
2777 Y(SIMD_REGLIST, ldst_elemlist, "LEt", 0, F(), \
2778 "a SIMD vector element list") \
2779 Y(CP_REG, regno, "Cn", 0, F(FLD_CRn), \
2780 "a 4-bit opcode field named for historical reasons C0 - C15") \
2781 Y(CP_REG, regno, "Cm", 0, F(FLD_CRm), \
2782 "a 4-bit opcode field named for historical reasons C0 - C15") \
2783 Y(IMMEDIATE, imm, "IDX", 0, F(FLD_imm4), \
2784 "an immediate as the index of the least significant byte") \
2785 Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSL", 0, F(), \
2786 "a left shift amount for an AdvSIMD register") \
2787 Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSR", 0, F(), \
2788 "a right shift amount for an AdvSIMD register") \
2789 Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM", 0, F(), \
2790 "an immediate") \
2791 Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM_SFT", 0, F(), \
2792 "an 8-bit unsigned immediate with optional shift") \
2793 Y(IMMEDIATE, advsimd_imm_modified, "SIMD_FPIMM", 0, F(), \
2794 "an 8-bit floating-point constant") \
2795 X(IMMEDIATE, 0, ext_shll_imm, "SHLL_IMM", 0, F(), \
2796 "an immediate shift amount of 8, 16 or 32") \
2797 X(IMMEDIATE, 0, 0, "IMM0", 0, F(), "0") \
2798 X(IMMEDIATE, 0, 0, "FPIMM0", 0, F(), "0.0") \
2799 Y(IMMEDIATE, imm, "FPIMM", 0, F(FLD_imm8), \
2800 "an 8-bit floating-point constant") \
2801 Y(IMMEDIATE, imm, "IMMR", 0, F(FLD_immr), \
2802 "the right rotate amount") \
2803 Y(IMMEDIATE, imm, "IMMS", 0, F(FLD_imm6), \
2804 "the leftmost bit number to be moved from the source") \
2805 Y(IMMEDIATE, imm, "WIDTH", 0, F(FLD_imm6), \
2806 "the width of the bit-field") \
2807 Y(IMMEDIATE, imm, "IMM", 0, F(FLD_imm6), "an immediate") \
2808 Y(IMMEDIATE, imm, "UIMM3_OP1", 0, F(FLD_op1), \
2809 "a 3-bit unsigned immediate") \
2810 Y(IMMEDIATE, imm, "UIMM3_OP2", 0, F(FLD_op2), \
2811 "a 3-bit unsigned immediate") \
2812 Y(IMMEDIATE, imm, "UIMM4", 0, F(FLD_CRm), \
2813 "a 4-bit unsigned immediate") \
2814 Y(IMMEDIATE, imm, "UIMM7", 0, F(FLD_CRm, FLD_op2), \
2815 "a 7-bit unsigned immediate") \
2816 Y(IMMEDIATE, imm, "BIT_NUM", 0, F(FLD_b5, FLD_b40), \
2817 "the bit number to be tested") \
2818 Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16), \
2819 "a 16-bit unsigned immediate") \
2820 Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD_imm5), \
2821 "a 5-bit unsigned immediate") \
2822 Y(IMMEDIATE, imm, "NZCV", 0, F(FLD_nzcv), \
2823 "a flag bit specifier giving an alternative value for each flag") \
2824 Y(IMMEDIATE, limm, "LIMM", 0, F(FLD_N,FLD_immr,FLD_imms), \
2825 "Logical immediate") \
2826 Y(IMMEDIATE, aimm, "AIMM", 0, F(FLD_shift,FLD_imm12), \
2827 "a 12-bit unsigned immediate with optional left shift of 12 bits")\
2828 Y(IMMEDIATE, imm_half, "HALF", 0, F(FLD_imm16), \
2829 "a 16-bit immediate with optional left shift") \
2830 Y(IMMEDIATE, fbits, "FBITS", 0, F(FLD_scale), \
2831 "the number of bits after the binary point in the fixed-point value")\
2832 X(IMMEDIATE, 0, 0, "IMM_MOV", 0, F(), "an immediate") \
68a64283
YZ		 2833 Y(COND, cond, "COND", 0, F(), "a condition") \
2834 Y(COND, cond, "COND1", 0, F(), \
2835 "one of the standard conditions, excluding AL and NV.") \
a06ea964
NC		 2836 X(ADDRESS, 0, ext_imm, "ADDR_ADRP", OPD_F_SEXT, F(FLD_immhi, FLD_immlo),\
2837 "21-bit PC-relative address of a 4KB page") \
2838 Y(ADDRESS, imm, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \
2839 F(FLD_imm14), "14-bit PC-relative address") \
2840 Y(ADDRESS, imm, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \
2841 F(FLD_imm19), "19-bit PC-relative address") \
2842 Y(ADDRESS, imm, "ADDR_PCREL21", OPD_F_SEXT, F(FLD_immhi,FLD_immlo), \
2843 "21-bit PC-relative address") \
2844 Y(ADDRESS, imm, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \
2845 F(FLD_imm26), "26-bit PC-relative address") \
2846 Y(ADDRESS, addr_simple, "ADDR_SIMPLE", 0, F(), \
2847 "an address with base register (no offset)") \
2848 Y(ADDRESS, addr_regoff, "ADDR_REGOFF", 0, F(), \
2849 "an address with register offset") \
2850 Y(ADDRESS, addr_simm, "ADDR_SIMM7", 0, F(FLD_imm7,FLD_index2), \
2851 "an address with 7-bit signed immediate offset") \
2852 Y(ADDRESS, addr_simm, "ADDR_SIMM9", 0, F(FLD_imm9,FLD_index), \
2853 "an address with 9-bit signed immediate offset") \
2854 Y(ADDRESS, addr_simm, "ADDR_SIMM9_2", 0, F(FLD_imm9,FLD_index), \
2855 "an address with 9-bit negative or unaligned immediate offset") \
2856 Y(ADDRESS, addr_uimm12, "ADDR_UIMM12", 0, F(FLD_Rn,FLD_imm12), \
2857 "an address with scaled, unsigned immediate offset") \
2858 Y(ADDRESS, addr_simple, "SIMD_ADDR_SIMPLE", 0, F(), \
2859 "an address with base register (no offset)") \
2860 Y(ADDRESS, simd_addr_post, "SIMD_ADDR_POST", 0, F(), \
2861 "a post-indexed address with immediate or register increment") \
2862 Y(SYSTEM, sysreg, "SYSREG", 0, F(), "a system register") \
2863 Y(SYSTEM, pstatefield, "PSTATEFIELD", 0, F(), \
2864 "a PSTATE field name") \
2865 Y(SYSTEM, sysins_op, "SYSREG_AT", 0, F(), \
2866 "an address translation operation specifier") \
2867 Y(SYSTEM, sysins_op, "SYSREG_DC", 0, F(), \
2868 "a data cache maintenance operation specifier") \
2869 Y(SYSTEM, sysins_op, "SYSREG_IC", 0, F(), \
9ed608f9 2870 "an instruction cache maintenance operation specifier") \
a06ea964
NC		 2871 Y(SYSTEM, sysins_op, "SYSREG_TLBI", 0, F(), \
2872 "a TBL invalidation operation specifier") \
2873 Y(SYSTEM, barrier, "BARRIER", 0, F(), \
2874 "a barrier option name") \
2875 Y(SYSTEM, barrier, "BARRIER_ISB", 0, F(), \
2876 "the ISB option name SY or an optional 4-bit unsigned immediate") \
2877 Y(SYSTEM, prfop, "PRFOP", 0, F(), \
1e6f4800
MW		 2878 "a prefetch operation specifier") \
2879 Y (SYSTEM, hint, "BARRIER_PSB", 0, F (), \
2880 "the PSB option name CSYNC")
GDB Binutils - Deliverables
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