Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Instruction printing code for the ARC. |
0d2bcfaf | 2 | Copyright (C) 1994, 1995, 1997, 1998, 2000, 2001 Free Software Foundation, Inc. |
252b5132 RH |
3 | Contributed by Doug Evans (dje@cygnus.com). |
4 | ||
0d2bcfaf NC |
5 | This program is free software; you can redistribute it and/or modify |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
252b5132 | 9 | |
0d2bcfaf NC |
10 | This program is distributed in the hope that it will be useful, |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
252b5132 | 14 | |
0d2bcfaf NC |
15 | You should have received a copy of the GNU General Public License |
16 | along with this program; if not, write to the Free Software | |
17 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
252b5132 | 18 | |
0d2bcfaf NC |
19 | #include <ansidecl.h> |
20 | #include <libiberty.h> | |
252b5132 RH |
21 | #include "dis-asm.h" |
22 | #include "opcode/arc.h" | |
23 | #include "elf-bfd.h" | |
24 | #include "elf/arc.h" | |
0d2bcfaf | 25 | #include <string.h> |
252b5132 RH |
26 | #include "opintl.h" |
27 | ||
0d2bcfaf NC |
28 | #include <ctype.h> |
29 | #include <stdarg.h> | |
30 | #include "arc-dis.h" | |
31 | #include "arc-ext.h" | |
252b5132 | 32 | |
0d2bcfaf NC |
33 | #ifndef dbg |
34 | #define dbg (0) | |
35 | #endif | |
252b5132 | 36 | |
0d2bcfaf NC |
37 | #define BIT(word,n) ((word) & (1 << n)) |
38 | #define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e))) | |
39 | #define OPCODE(word) (BITS ((word), 27, 31)) | |
40 | #define FIELDA(word) (BITS ((word), 21, 26)) | |
41 | #define FIELDB(word) (BITS ((word), 15, 20)) | |
42 | #define FIELDC(word) (BITS ((word), 9, 14)) | |
252b5132 | 43 | |
0d2bcfaf NC |
44 | /* FIELD D is signed in all of its uses, so we make sure argument is |
45 | treated as signed for bit shifting purposes: */ | |
46 | #define FIELDD(word) (BITS (((signed int)word), 0, 8)) | |
47 | ||
48 | #define PUT_NEXT_WORD_IN(a) \ | |
49 | do \ | |
50 | { \ | |
51 | if (is_limm == 1 && !NEXT_WORD (1)) \ | |
52 | mwerror (state, _("Illegal limm reference in last instruction!\n")); \ | |
53 | a = state->words[1]; \ | |
54 | } \ | |
55 | while (0) | |
56 | ||
57 | #define CHECK_FLAG_COND_NULLIFY() \ | |
58 | do \ | |
59 | { \ | |
60 | if (is_shimm == 0) \ | |
61 | { \ | |
62 | flag = BIT (state->words[0], 8); \ | |
63 | state->nullifyMode = BITS (state->words[0], 5, 6); \ | |
64 | cond = BITS (state->words[0], 0, 4); \ | |
65 | } \ | |
66 | } \ | |
67 | while (0) | |
68 | ||
69 | #define CHECK_COND() \ | |
70 | do \ | |
71 | { \ | |
72 | if (is_shimm == 0) \ | |
73 | cond = BITS (state->words[0], 0, 4); \ | |
74 | } \ | |
75 | while (0) | |
76 | ||
77 | #define CHECK_FIELD(field) \ | |
78 | do \ | |
79 | { \ | |
80 | if (field == 62) \ | |
81 | { \ | |
82 | is_limm++; \ | |
83 | field##isReg = 0; \ | |
84 | PUT_NEXT_WORD_IN (field); \ | |
85 | limm_value = field; \ | |
86 | } \ | |
87 | else if (field > 60) \ | |
88 | { \ | |
89 | field##isReg = 0; \ | |
90 | is_shimm++; \ | |
91 | flag = (field == 61); \ | |
92 | field = FIELDD (state->words[0]); \ | |
93 | } \ | |
94 | } \ | |
95 | while (0) | |
96 | ||
97 | #define CHECK_FIELD_A() \ | |
98 | do \ | |
99 | { \ | |
100 | fieldA = FIELDA(state->words[0]); \ | |
101 | if (fieldA > 60) \ | |
102 | { \ | |
103 | fieldAisReg = 0; \ | |
104 | fieldA = 0; \ | |
105 | } \ | |
106 | } \ | |
107 | while (0) | |
108 | ||
109 | #define CHECK_FIELD_B() \ | |
110 | do \ | |
111 | { \ | |
112 | fieldB = FIELDB (state->words[0]); \ | |
113 | CHECK_FIELD (fieldB); \ | |
114 | } \ | |
115 | while (0) | |
116 | ||
117 | #define CHECK_FIELD_C() \ | |
118 | do \ | |
119 | { \ | |
120 | fieldC = FIELDC (state->words[0]); \ | |
121 | CHECK_FIELD (fieldC); \ | |
122 | } \ | |
123 | while (0) | |
124 | ||
125 | #define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257)) | |
126 | #define IS_REG(x) (field##x##isReg) | |
127 | #define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT(x,"[","]","","") | |
128 | #define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT(x,"",",[","",",[") | |
129 | #define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT(x,",","]",",","]") | |
130 | #define WRITE_FORMAT_x_RB(x) WRITE_FORMAT(x,"","]","","]") | |
131 | #define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT(x,",","",",","") | |
132 | #define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT(x,"",",","",",") | |
133 | #define WRITE_FORMAT_x(x) WRITE_FORMAT(x,"","","","") | |
134 | #define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \ | |
135 | (IS_REG (x) ? cb1"%r"ca1 : \ | |
136 | usesAuxReg ? cb"%a"ca : \ | |
137 | IS_SMALL (x) ? cb"%d"ca : cb"%h"ca)) | |
138 | #define WRITE_FORMAT_RB() strcat (formatString, "]") | |
139 | #define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str)) | |
140 | #define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop"); | |
141 | ||
142 | #define NEXT_WORD(x) (offset += 4, state->words[x]) | |
143 | ||
144 | #define add_target(x) (state->targets[state->tcnt++] = (x)) | |
145 | ||
146 | static char comment_prefix[] = "\t; "; | |
147 | ||
148 | static const char * | |
149 | core_reg_name (state, val) | |
150 | struct arcDisState * state; | |
151 | int val; | |
252b5132 | 152 | { |
0d2bcfaf NC |
153 | if (state->coreRegName) |
154 | return (*state->coreRegName)(state->_this, val); | |
155 | return 0; | |
156 | } | |
252b5132 | 157 | |
0d2bcfaf NC |
158 | static const char * |
159 | aux_reg_name (state, val) | |
160 | struct arcDisState * state; | |
161 | int val; | |
162 | { | |
163 | if (state->auxRegName) | |
164 | return (*state->auxRegName)(state->_this, val); | |
165 | return 0; | |
166 | } | |
252b5132 | 167 | |
0d2bcfaf NC |
168 | static const char * |
169 | cond_code_name (state, val) | |
170 | struct arcDisState * state; | |
171 | int val; | |
172 | { | |
173 | if (state->condCodeName) | |
174 | return (*state->condCodeName)(state->_this, val); | |
175 | return 0; | |
176 | } | |
177 | ||
178 | static const char * | |
179 | instruction_name (state, op1, op2, flags) | |
180 | struct arcDisState * state; | |
181 | int op1; | |
182 | int op2; | |
183 | int * flags; | |
184 | { | |
185 | if (state->instName) | |
186 | return (*state->instName)(state->_this, op1, op2, flags); | |
187 | return 0; | |
188 | } | |
189 | ||
190 | static void | |
191 | mwerror (state, msg) | |
192 | struct arcDisState * state; | |
193 | const char * msg; | |
194 | { | |
195 | if (state->err != 0) | |
196 | (*state->err)(state->_this, (msg)); | |
197 | } | |
198 | ||
199 | static const char * | |
200 | post_address (state, addr) | |
201 | struct arcDisState * state; | |
202 | int addr; | |
203 | { | |
204 | static char id[3 * ARRAY_SIZE (state->addresses)]; | |
205 | int j, i = state->acnt; | |
206 | ||
207 | if (i < ((int) ARRAY_SIZE (state->addresses))) | |
252b5132 | 208 | { |
0d2bcfaf NC |
209 | state->addresses[i] = addr; |
210 | ++state->acnt; | |
211 | j = i*3; | |
212 | id[j+0] = '@'; | |
213 | id[j+1] = '0'+i; | |
214 | id[j+2] = 0; | |
215 | ||
216 | return id + j; | |
252b5132 | 217 | } |
0d2bcfaf NC |
218 | return ""; |
219 | } | |
252b5132 | 220 | |
0d2bcfaf NC |
221 | static void |
222 | my_sprintf ( | |
223 | struct arcDisState * state, | |
224 | char * buf, | |
225 | const char * format, | |
226 | ...) | |
227 | { | |
228 | char *bp; | |
229 | const char *p; | |
230 | int size, leading_zero, regMap[2]; | |
231 | long auxNum; | |
232 | va_list ap; | |
233 | ||
234 | va_start (ap, format); | |
235 | ||
236 | bp = buf; | |
237 | *bp = 0; | |
238 | p = format; | |
239 | auxNum = -1; | |
240 | regMap[0] = 0; | |
241 | regMap[1] = 0; | |
242 | ||
243 | while (1) | |
244 | switch (*p++) | |
245 | { | |
246 | case 0: | |
247 | goto DOCOMM; /* (return) */ | |
248 | default: | |
249 | *bp++ = p[-1]; | |
250 | break; | |
251 | case '%': | |
252 | size = 0; | |
253 | leading_zero = 0; | |
254 | RETRY: ; | |
255 | switch (*p++) | |
256 | { | |
257 | case '0': | |
258 | case '1': | |
259 | case '2': | |
260 | case '3': | |
261 | case '4': | |
262 | case '5': | |
263 | case '6': | |
264 | case '7': | |
265 | case '8': | |
266 | case '9': | |
267 | { | |
268 | /* size. */ | |
269 | size = p[-1] - '0'; | |
270 | if (size == 0) | |
271 | leading_zero = 1; /* e.g. %08x */ | |
272 | while (*p >= '0' && *p <= '9') | |
273 | { | |
274 | size = size * 10 + *p - '0'; | |
275 | p++; | |
276 | } | |
277 | goto RETRY; | |
278 | } | |
279 | #define inc_bp() bp = bp + strlen (bp) | |
252b5132 | 280 | |
0d2bcfaf NC |
281 | case 'h': |
282 | { | |
283 | unsigned u = va_arg (ap, int); | |
252b5132 | 284 | |
0d2bcfaf NC |
285 | /* Hex. We can change the format to 0x%08x in |
286 | one place, here, if we wish. | |
287 | We add underscores for easy reading. */ | |
288 | if (u > 65536) | |
289 | sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff); | |
290 | else | |
291 | sprintf (bp, "0x%x", u); | |
292 | inc_bp (); | |
293 | } | |
294 | break; | |
295 | case 'X': case 'x': | |
296 | { | |
297 | int val = va_arg (ap, int); | |
252b5132 | 298 | |
0d2bcfaf NC |
299 | if (size != 0) |
300 | if (leading_zero) | |
301 | sprintf (bp, "%0*x", size, val); | |
302 | else | |
303 | sprintf (bp, "%*x", size, val); | |
304 | else | |
305 | sprintf (bp, "%x", val); | |
306 | inc_bp (); | |
307 | } | |
308 | break; | |
309 | case 'd': | |
252b5132 | 310 | { |
0d2bcfaf NC |
311 | int val = va_arg (ap, int); |
312 | ||
313 | if (size != 0) | |
314 | sprintf (bp, "%*d", size, val); | |
315 | else | |
316 | sprintf (bp, "%d", val); | |
317 | inc_bp (); | |
252b5132 | 318 | } |
0d2bcfaf NC |
319 | break; |
320 | case 'r': | |
321 | { | |
322 | /* Register. */ | |
323 | int val = va_arg (ap, int); | |
324 | ||
325 | #define REG2NAME(num, name) case num: sprintf (bp, ""name); \ | |
326 | regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break; | |
327 | ||
328 | switch (val) | |
329 | { | |
330 | REG2NAME (26, "gp"); | |
331 | REG2NAME (27, "fp"); | |
332 | REG2NAME (28, "sp"); | |
333 | REG2NAME (29, "ilink1"); | |
334 | REG2NAME (30, "ilink2"); | |
335 | REG2NAME (31, "blink"); | |
336 | REG2NAME (60, "lp_count"); | |
337 | default: | |
338 | { | |
339 | const char * ext; | |
340 | ||
341 | ext = core_reg_name (state, val); | |
342 | if (ext) | |
343 | sprintf (bp, "%s", ext); | |
344 | else | |
345 | sprintf (bp,"r%d",val); | |
346 | } | |
347 | break; | |
348 | } | |
349 | inc_bp (); | |
350 | } break; | |
351 | ||
352 | case 'a': | |
353 | { | |
354 | /* Aux Register. */ | |
355 | int val = va_arg (ap, int); | |
252b5132 | 356 | |
0d2bcfaf | 357 | #define AUXREG2NAME(num, name) case num: sprintf (bp,name); break; |
252b5132 | 358 | |
0d2bcfaf NC |
359 | switch (val) |
360 | { | |
361 | AUXREG2NAME (0x0, "status"); | |
362 | AUXREG2NAME (0x1, "semaphore"); | |
363 | AUXREG2NAME (0x2, "lp_start"); | |
364 | AUXREG2NAME (0x3, "lp_end"); | |
365 | AUXREG2NAME (0x4, "identity"); | |
366 | AUXREG2NAME (0x5, "debug"); | |
367 | default: | |
368 | { | |
369 | const char *ext; | |
370 | ||
371 | ext = aux_reg_name (state, val); | |
372 | if (ext) | |
373 | sprintf (bp, "%s", ext); | |
374 | else | |
375 | my_sprintf (state, bp, "%h", val); | |
376 | } | |
377 | break; | |
378 | } | |
379 | inc_bp (); | |
380 | } | |
381 | break; | |
382 | ||
383 | case 's': | |
252b5132 | 384 | { |
0d2bcfaf NC |
385 | sprintf (bp, "%s", va_arg (ap, char *)); |
386 | inc_bp (); | |
252b5132 | 387 | } |
0d2bcfaf NC |
388 | break; |
389 | ||
390 | default: | |
391 | fprintf (stderr, "?? format %c\n", p[-1]); | |
392 | break; | |
393 | } | |
394 | } | |
395 | ||
396 | DOCOMM: *bp = 0; | |
397 | } | |
398 | ||
399 | static void | |
400 | write_comments_(state, shimm, is_limm, limm_value) | |
401 | struct arcDisState * state; | |
402 | int shimm; | |
403 | int is_limm; | |
404 | long limm_value; | |
405 | { | |
406 | if (state->commentBuffer != 0) | |
407 | { | |
408 | int i; | |
409 | ||
410 | if (is_limm) | |
411 | { | |
412 | const char *name = post_address (state, limm_value + shimm); | |
413 | ||
414 | if (*name != 0) | |
415 | WRITE_COMMENT (name); | |
416 | } | |
417 | for (i = 0; i < state->commNum; i++) | |
418 | { | |
419 | if (i == 0) | |
420 | strcpy (state->commentBuffer, comment_prefix); | |
252b5132 | 421 | else |
0d2bcfaf NC |
422 | strcat (state->commentBuffer, ", "); |
423 | strncat (state->commentBuffer, state->comm[i], sizeof (state->commentBuffer)); | |
252b5132 | 424 | } |
0d2bcfaf NC |
425 | } |
426 | } | |
252b5132 | 427 | |
0d2bcfaf NC |
428 | #define write_comments2(x) write_comments_(state, x, is_limm, limm_value) |
429 | #define write_comments() write_comments2(0) | |
430 | ||
431 | static const char *condName[] = { | |
432 | /* 0..15. */ | |
433 | "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" , | |
434 | "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz" | |
435 | }; | |
436 | ||
437 | static void | |
438 | write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem) | |
439 | struct arcDisState * state; | |
440 | const char * instrName; | |
441 | int cond; | |
442 | int condCodeIsPartOfName; | |
443 | int flag; | |
444 | int signExtend; | |
445 | int addrWriteBack; | |
446 | int directMem; | |
447 | { | |
448 | strcpy (state->instrBuffer, instrName); | |
449 | ||
450 | if (cond > 0) | |
451 | { | |
452 | const char *cc = 0; | |
453 | ||
454 | if (!condCodeIsPartOfName) | |
455 | strcat (state->instrBuffer, "."); | |
456 | ||
457 | if (cond < 16) | |
458 | cc = condName[cond]; | |
459 | else | |
460 | cc = cond_code_name (state, cond); | |
461 | ||
462 | if (!cc) | |
463 | cc = "???"; | |
464 | ||
465 | strcat (state->instrBuffer, cc); | |
466 | } | |
467 | ||
468 | if (flag) | |
469 | strcat (state->instrBuffer, ".f"); | |
470 | ||
471 | switch (state->nullifyMode) | |
472 | { | |
473 | case BR_exec_always: | |
474 | strcat (state->instrBuffer, ".d"); | |
475 | break; | |
476 | case BR_exec_when_jump: | |
477 | strcat (state->instrBuffer, ".jd"); | |
478 | break; | |
479 | } | |
480 | ||
481 | if (signExtend) | |
482 | strcat (state->instrBuffer, ".x"); | |
483 | ||
484 | if (addrWriteBack) | |
485 | strcat (state->instrBuffer, ".a"); | |
486 | ||
487 | if (directMem) | |
488 | strcat (state->instrBuffer, ".di"); | |
489 | } | |
490 | ||
491 | #define write_instr_name() \ | |
492 | do \ | |
493 | { \ | |
494 | write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \ | |
495 | flag, signExtend, addrWriteBack, directMem); \ | |
496 | formatString[0] = '\0'; \ | |
497 | } \ | |
498 | while (0) | |
499 | ||
500 | enum { | |
501 | op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3, | |
502 | op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7, | |
503 | op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11, | |
504 | op_AND = 12, op_OR = 13, op_BIC = 14, op_XOR = 15 | |
505 | }; | |
506 | ||
507 | extern disassemble_info tm_print_insn_info; | |
252b5132 | 508 | |
0d2bcfaf NC |
509 | static int |
510 | dsmOneArcInst (addr, state) | |
511 | bfd_vma addr; | |
512 | struct arcDisState * state; | |
513 | { | |
514 | int condCodeIsPartOfName = 0; | |
515 | int decodingClass; | |
516 | const char * instrName; | |
517 | int repeatsOp = 0; | |
518 | int fieldAisReg = 1; | |
519 | int fieldBisReg = 1; | |
520 | int fieldCisReg = 1; | |
521 | int fieldA; | |
522 | int fieldB; | |
523 | int fieldC = 0; | |
524 | int flag = 0; | |
525 | int cond = 0; | |
526 | int is_shimm = 0; | |
527 | int is_limm = 0; | |
528 | long limm_value = 0; | |
529 | int signExtend = 0; | |
530 | int addrWriteBack = 0; | |
531 | int directMem = 0; | |
532 | int is_linked = 0; | |
533 | int offset = 0; | |
534 | int usesAuxReg = 0; | |
535 | int flags; | |
536 | int ignoreFirstOpd; | |
537 | char formatString[60]; | |
538 | ||
539 | state->instructionLen = 4; | |
540 | state->nullifyMode = BR_exec_when_no_jump; | |
541 | state->opWidth = 12; | |
542 | state->isBranch = 0; | |
543 | ||
544 | state->_mem_load = 0; | |
545 | state->_ea_present = 0; | |
546 | state->_load_len = 0; | |
547 | state->ea_reg1 = no_reg; | |
548 | state->ea_reg2 = no_reg; | |
549 | state->_offset = 0; | |
550 | ||
551 | if (! NEXT_WORD (0)) | |
552 | return 0; | |
553 | ||
554 | state->_opcode = OPCODE (state->words[0]); | |
555 | instrName = 0; | |
556 | decodingClass = 0; /* default! */ | |
557 | repeatsOp = 0; | |
558 | condCodeIsPartOfName=0; | |
559 | state->commNum = 0; | |
560 | state->tcnt = 0; | |
561 | state->acnt = 0; | |
562 | state->flow = noflow; | |
563 | ignoreFirstOpd = 0; | |
564 | ||
565 | if (state->commentBuffer) | |
566 | state->commentBuffer[0] = '\0'; | |
567 | ||
568 | switch (state->_opcode) | |
569 | { | |
570 | case op_LD0: | |
571 | switch (BITS (state->words[0],1,2)) | |
572 | { | |
573 | case 0: | |
574 | instrName = "ld"; | |
575 | state->_load_len = 4; | |
576 | break; | |
577 | case 1: | |
578 | instrName = "ldb"; | |
579 | state->_load_len = 1; | |
580 | break; | |
581 | case 2: | |
582 | instrName = "ldw"; | |
583 | state->_load_len = 2; | |
584 | break; | |
585 | default: | |
586 | instrName = "??? (0[3])"; | |
587 | state->flow = invalid_instr; | |
588 | break; | |
589 | } | |
590 | decodingClass = 5; | |
591 | break; | |
592 | ||
593 | case op_LD1: | |
594 | if (BIT (state->words[0],13)) | |
595 | { | |
596 | instrName = "lr"; | |
597 | decodingClass = 10; | |
598 | } | |
599 | else | |
600 | { | |
601 | switch (BITS (state->words[0],10,11)) | |
252b5132 | 602 | { |
0d2bcfaf NC |
603 | case 0: |
604 | instrName = "ld"; | |
605 | state->_load_len = 4; | |
606 | break; | |
607 | case 1: | |
608 | instrName = "ldb"; | |
609 | state->_load_len = 1; | |
610 | break; | |
611 | case 2: | |
612 | instrName = "ldw"; | |
613 | state->_load_len = 2; | |
614 | break; | |
615 | default: | |
616 | instrName = "??? (1[3])"; | |
617 | state->flow = invalid_instr; | |
618 | break; | |
252b5132 | 619 | } |
0d2bcfaf NC |
620 | decodingClass = 6; |
621 | } | |
622 | break; | |
623 | ||
624 | case op_ST: | |
625 | if (BIT (state->words[0],25)) | |
626 | { | |
627 | instrName = "sr"; | |
628 | decodingClass = 8; | |
629 | } | |
630 | else | |
631 | { | |
632 | switch (BITS (state->words[0],22,23)) | |
633 | { | |
634 | case 0: | |
635 | instrName = "st"; | |
636 | break; | |
637 | case 1: | |
638 | instrName = "stb"; | |
639 | break; | |
640 | case 2: | |
641 | instrName = "stw"; | |
642 | break; | |
643 | default: | |
644 | instrName = "??? (2[3])"; | |
645 | state->flow = invalid_instr; | |
646 | break; | |
647 | } | |
648 | decodingClass = 7; | |
649 | } | |
650 | break; | |
651 | ||
652 | case op_3: | |
653 | decodingClass = 1; /* default for opcode 3... */ | |
654 | switch (FIELDC (state->words[0])) | |
655 | { | |
656 | case 0: | |
657 | instrName = "flag"; | |
658 | decodingClass = 2; | |
659 | break; | |
660 | case 1: | |
661 | instrName = "asr"; | |
662 | break; | |
663 | case 2: | |
664 | instrName = "lsr"; | |
665 | break; | |
666 | case 3: | |
667 | instrName = "ror"; | |
668 | break; | |
669 | case 4: | |
670 | instrName = "rrc"; | |
671 | break; | |
672 | case 5: | |
673 | instrName = "sexb"; | |
674 | break; | |
675 | case 6: | |
676 | instrName = "sexw"; | |
677 | break; | |
678 | case 7: | |
679 | instrName = "extb"; | |
680 | break; | |
681 | case 8: | |
682 | instrName = "extw"; | |
683 | break; | |
684 | case 0x3f: | |
685 | { | |
686 | decodingClass = 9; | |
687 | switch( FIELDD (state->words[0]) ) | |
688 | { | |
689 | case 0: | |
690 | instrName = "brk"; | |
691 | break; | |
692 | case 1: | |
693 | instrName = "sleep"; | |
694 | break; | |
695 | case 2: | |
696 | instrName = "swi"; | |
697 | break; | |
698 | default: | |
699 | instrName = "???"; | |
700 | state->flow=invalid_instr; | |
701 | break; | |
702 | } | |
703 | } | |
704 | break; | |
705 | ||
706 | /* ARC Extension Library Instructions | |
707 | NOTE: We assume that extension codes are these instrs. */ | |
708 | default: | |
709 | instrName = instruction_name (state, | |
710 | state->_opcode, | |
711 | FIELDC (state->words[0]), | |
712 | & flags); | |
713 | if (!instrName) | |
252b5132 | 714 | { |
0d2bcfaf NC |
715 | instrName = "???"; |
716 | state->flow = invalid_instr; | |
252b5132 | 717 | } |
0d2bcfaf NC |
718 | if (flags & IGNORE_FIRST_OPD) |
719 | ignoreFirstOpd = 1; | |
720 | break; | |
721 | } | |
722 | break; | |
252b5132 | 723 | |
0d2bcfaf NC |
724 | case op_BC: |
725 | instrName = "b"; | |
726 | case op_BLC: | |
727 | if (!instrName) | |
728 | instrName = "bl"; | |
729 | case op_LPC: | |
730 | if (!instrName) | |
731 | instrName = "lp"; | |
732 | case op_JC: | |
733 | if (!instrName) | |
734 | { | |
735 | if (BITS (state->words[0],9,9)) | |
252b5132 | 736 | { |
0d2bcfaf NC |
737 | instrName = "jl"; |
738 | is_linked = 1; | |
252b5132 | 739 | } |
0d2bcfaf | 740 | else |
252b5132 | 741 | { |
0d2bcfaf NC |
742 | instrName = "j"; |
743 | is_linked = 0; | |
252b5132 | 744 | } |
0d2bcfaf NC |
745 | } |
746 | condCodeIsPartOfName = 1; | |
747 | decodingClass = ((state->_opcode == op_JC) ? 4 : 3); | |
748 | state->isBranch = 1; | |
749 | break; | |
750 | ||
751 | case op_ADD: | |
752 | case op_ADC: | |
753 | case op_AND: | |
754 | repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0])); | |
755 | decodingClass = 0; | |
252b5132 | 756 | |
0d2bcfaf NC |
757 | switch (state->_opcode) |
758 | { | |
759 | case op_ADD: | |
760 | instrName = (repeatsOp ? "asl" : "add"); | |
761 | break; | |
762 | case op_ADC: | |
763 | instrName = (repeatsOp ? "rlc" : "adc"); | |
764 | break; | |
765 | case op_AND: | |
766 | instrName = (repeatsOp ? "mov" : "and"); | |
767 | break; | |
768 | } | |
769 | break; | |
770 | ||
771 | case op_SUB: instrName = "sub"; | |
772 | break; | |
773 | case op_SBC: instrName = "sbc"; | |
774 | break; | |
775 | case op_OR: instrName = "or"; | |
776 | break; | |
777 | case op_BIC: instrName = "bic"; | |
778 | break; | |
252b5132 | 779 | |
0d2bcfaf NC |
780 | case op_XOR: |
781 | if (state->words[0] == 0x7fffffff) | |
782 | { | |
783 | /* nop encoded as xor -1, -1, -1 */ | |
784 | instrName = "nop"; | |
785 | decodingClass = 9; | |
786 | } | |
787 | else | |
788 | instrName = "xor"; | |
789 | break; | |
790 | ||
791 | default: | |
792 | instrName = instruction_name (state,state->_opcode,0,&flags); | |
793 | /* if (instrName) printf("FLAGS=0x%x\n", flags); */ | |
794 | if (!instrName) | |
795 | { | |
796 | instrName = "???"; | |
797 | state->flow=invalid_instr; | |
798 | } | |
799 | if (flags & IGNORE_FIRST_OPD) | |
800 | ignoreFirstOpd = 1; | |
801 | break; | |
802 | } | |
803 | ||
804 | fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now. */ | |
805 | flag = cond = is_shimm = is_limm = 0; | |
806 | state->nullifyMode = BR_exec_when_no_jump; /* 0 */ | |
807 | signExtend = addrWriteBack = directMem = 0; | |
808 | usesAuxReg = 0; | |
809 | ||
810 | switch (decodingClass) | |
811 | { | |
812 | case 0: | |
813 | CHECK_FIELD_A (); | |
814 | CHECK_FIELD_B (); | |
815 | if (!repeatsOp) | |
816 | CHECK_FIELD_C (); | |
817 | CHECK_FLAG_COND_NULLIFY (); | |
818 | ||
819 | write_instr_name (); | |
820 | if (!ignoreFirstOpd) | |
821 | { | |
822 | WRITE_FORMAT_x (A); | |
823 | WRITE_FORMAT_COMMA_x (B); | |
824 | if (!repeatsOp) | |
825 | WRITE_FORMAT_COMMA_x (C); | |
826 | WRITE_NOP_COMMENT (); | |
827 | my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); | |
828 | } | |
829 | else | |
830 | { | |
831 | WRITE_FORMAT_x (B); | |
832 | if (!repeatsOp) | |
833 | WRITE_FORMAT_COMMA_x (C); | |
834 | my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldC); | |
835 | } | |
836 | write_comments (); | |
837 | break; | |
838 | ||
839 | case 1: | |
840 | CHECK_FIELD_A (); | |
841 | CHECK_FIELD_B (); | |
842 | CHECK_FLAG_COND_NULLIFY (); | |
843 | ||
844 | write_instr_name (); | |
845 | if (!ignoreFirstOpd) | |
846 | { | |
847 | WRITE_FORMAT_x (A); | |
848 | WRITE_FORMAT_COMMA_x (B); | |
849 | WRITE_NOP_COMMENT (); | |
850 | my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB); | |
851 | } | |
852 | else | |
853 | { | |
854 | WRITE_FORMAT_x (B); | |
855 | my_sprintf (state, state->operandBuffer, formatString, fieldB); | |
856 | } | |
857 | write_comments (); | |
858 | break; | |
859 | ||
860 | case 2: | |
861 | CHECK_FIELD_B (); | |
862 | CHECK_FLAG_COND_NULLIFY (); | |
863 | flag = 0; /* this is the FLAG instruction -- it's redundant */ | |
864 | ||
865 | write_instr_name (); | |
866 | WRITE_FORMAT_x (B); | |
867 | my_sprintf (state, state->operandBuffer, formatString, fieldB); | |
868 | write_comments (); | |
869 | break; | |
870 | ||
871 | case 3: | |
872 | fieldA = BITS (state->words[0],7,26) << 2; | |
873 | fieldA = (fieldA << 10) >> 10; /* make it signed */ | |
874 | fieldA += addr + 4; | |
875 | CHECK_FLAG_COND_NULLIFY (); | |
876 | flag = 0; | |
877 | ||
878 | write_instr_name (); | |
879 | /* This address could be a label we know. Convert it. */ | |
880 | if (state->_opcode != op_LPC /* LP */) | |
881 | { | |
882 | add_target (fieldA); /* For debugger. */ | |
883 | state->flow = state->_opcode == op_BLC /* BL */ | |
884 | ? direct_call | |
885 | : direct_jump; | |
886 | /* indirect calls are achieved by "lr blink,[status]; | |
887 | lr dest<- func addr; j [dest]" */ | |
888 | } | |
889 | ||
890 | strcat (formatString, "%s"); /* address/label name */ | |
891 | my_sprintf (state, state->operandBuffer, formatString, post_address (state, fieldA)); | |
892 | write_comments (); | |
893 | break; | |
894 | ||
895 | case 4: | |
896 | /* For op_JC -- jump to address specified. | |
897 | Also covers jump and link--bit 9 of the instr. word | |
898 | selects whether linked, thus "is_linked" is set above. */ | |
899 | fieldA = 0; | |
900 | CHECK_FIELD_B (); | |
901 | CHECK_FLAG_COND_NULLIFY (); | |
902 | ||
903 | if (!fieldBisReg) | |
904 | { | |
905 | fieldAisReg = 0; | |
906 | fieldA = (fieldB >> 25) & 0x7F; /* flags */ | |
907 | fieldB = (fieldB & 0xFFFFFF) << 2; | |
908 | state->flow = is_linked ? direct_call : direct_jump; | |
909 | add_target (fieldB); | |
910 | /* screwy JLcc requires .jd mode to execute correctly | |
911 | * but we pretend it is .nd (no delay slot). */ | |
912 | if (is_linked && state->nullifyMode == BR_exec_when_jump) | |
913 | state->nullifyMode = BR_exec_when_no_jump; | |
914 | } | |
915 | else | |
916 | { | |
917 | state->flow = is_linked ? indirect_call : indirect_jump; | |
918 | /* We should also treat this as indirect call if NOT linked | |
919 | * but the preceding instruction was a "lr blink,[status]" | |
920 | * and we have a delay slot with "add blink,blink,2". | |
921 | * For now we can't detect such. */ | |
922 | state->register_for_indirect_jump = fieldB; | |
923 | } | |
924 | ||
925 | write_instr_name (); | |
926 | strcat (formatString, | |
927 | IS_REG (B) ? "[%r]" : "%s"); /* address/label name */ | |
928 | if (fieldA != 0) | |
929 | { | |
930 | fieldAisReg = 0; | |
931 | WRITE_FORMAT_COMMA_x (A); | |
932 | } | |
933 | if (IS_REG (B)) | |
934 | my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA); | |
935 | else | |
936 | my_sprintf (state, state->operandBuffer, formatString, | |
937 | post_address (state, fieldB), fieldA); | |
938 | write_comments (); | |
939 | break; | |
940 | ||
941 | case 5: | |
942 | /* LD instruction. | |
943 | B and C can be regs, or one (both?) can be limm. */ | |
944 | CHECK_FIELD_A (); | |
945 | CHECK_FIELD_B (); | |
946 | CHECK_FIELD_C (); | |
947 | if (dbg) | |
948 | printf ("5:b reg %d %d c reg %d %d \n", | |
949 | fieldBisReg,fieldB,fieldCisReg,fieldC); | |
950 | state->_offset = 0; | |
951 | state->_ea_present = 1; | |
952 | if (fieldBisReg) | |
953 | state->ea_reg1 = fieldB; | |
954 | else | |
955 | state->_offset += fieldB; | |
956 | if (fieldCisReg) | |
957 | state->ea_reg2 = fieldC; | |
958 | else | |
959 | state->_offset += fieldC; | |
960 | state->_mem_load = 1; | |
961 | ||
962 | directMem = BIT (state->words[0],5); | |
963 | addrWriteBack = BIT (state->words[0],3); | |
964 | signExtend = BIT (state->words[0],0); | |
965 | ||
966 | write_instr_name (); | |
967 | WRITE_FORMAT_x_COMMA_LB(A); | |
968 | if (fieldBisReg || fieldB != 0) | |
969 | WRITE_FORMAT_x_COMMA (B); | |
970 | else | |
971 | fieldB = fieldC; | |
972 | ||
973 | WRITE_FORMAT_x_RB (C); | |
974 | my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); | |
975 | write_comments (); | |
976 | break; | |
977 | ||
978 | case 6: | |
979 | /* LD instruction. */ | |
980 | CHECK_FIELD_B (); | |
981 | CHECK_FIELD_A (); | |
982 | fieldC = FIELDD (state->words[0]); | |
983 | ||
984 | if (dbg) | |
985 | printf ("6:b reg %d %d c 0x%x \n", | |
986 | fieldBisReg, fieldB, fieldC); | |
987 | state->_ea_present = 1; | |
988 | state->_offset = fieldC; | |
989 | state->_mem_load = 1; | |
990 | if (fieldBisReg) | |
991 | state->ea_reg1 = fieldB; | |
992 | /* field B is either a shimm (same as fieldC) or limm (different!) | |
993 | Say ea is not present, so only one of us will do the name lookup. */ | |
994 | else | |
995 | state->_offset += fieldB, state->_ea_present = 0; | |
996 | ||
997 | directMem = BIT (state->words[0],14); | |
998 | addrWriteBack = BIT (state->words[0],12); | |
999 | signExtend = BIT (state->words[0],9); | |
1000 | ||
1001 | write_instr_name (); | |
1002 | WRITE_FORMAT_x_COMMA_LB (A); | |
1003 | if (!fieldBisReg) | |
1004 | { | |
1005 | fieldB = state->_offset; | |
1006 | WRITE_FORMAT_x_RB (B); | |
1007 | } | |
1008 | else | |
1009 | { | |
1010 | WRITE_FORMAT_x (B); | |
1011 | if (fieldC != 0 && !BIT (state->words[0],13)) | |
1012 | { | |
1013 | fieldCisReg = 0; | |
1014 | WRITE_FORMAT_COMMA_x_RB (C); | |
252b5132 | 1015 | } |
252b5132 | 1016 | else |
0d2bcfaf | 1017 | WRITE_FORMAT_RB (); |
252b5132 | 1018 | } |
0d2bcfaf NC |
1019 | my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); |
1020 | write_comments (); | |
1021 | break; | |
1022 | ||
1023 | case 7: | |
1024 | /* ST instruction. */ | |
1025 | CHECK_FIELD_B(); | |
1026 | CHECK_FIELD_C(); | |
1027 | fieldA = FIELDD(state->words[0]); /* shimm */ | |
1028 | ||
1029 | /* [B,A offset] */ | |
1030 | if (dbg) printf("7:b reg %d %x off %x\n", | |
1031 | fieldBisReg,fieldB,fieldA); | |
1032 | state->_ea_present = 1; | |
1033 | state->_offset = fieldA; | |
1034 | if (fieldBisReg) | |
1035 | state->ea_reg1 = fieldB; | |
1036 | /* field B is either a shimm (same as fieldA) or limm (different!) | |
1037 | Say ea is not present, so only one of us will do the name lookup. | |
1038 | (for is_limm we do the name translation here). */ | |
1039 | else | |
1040 | state->_offset += fieldB, state->_ea_present = 0; | |
1041 | ||
1042 | directMem = BIT(state->words[0],26); | |
1043 | addrWriteBack = BIT(state->words[0],24); | |
1044 | ||
1045 | write_instr_name(); | |
1046 | WRITE_FORMAT_x_COMMA_LB(C); | |
1047 | ||
1048 | if (!fieldBisReg) | |
1049 | { | |
1050 | fieldB = state->_offset; | |
1051 | WRITE_FORMAT_x_RB(B); | |
1052 | } | |
1053 | else | |
1054 | { | |
1055 | WRITE_FORMAT_x(B); | |
1056 | if (fieldBisReg && fieldA != 0) | |
1057 | { | |
1058 | fieldAisReg = 0; | |
1059 | WRITE_FORMAT_COMMA_x_RB(A); | |
1060 | } | |
1061 | else | |
1062 | WRITE_FORMAT_RB(); | |
1063 | } | |
1064 | my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB, fieldA); | |
1065 | write_comments2(fieldA); | |
1066 | break; | |
1067 | case 8: | |
1068 | /* SR instruction */ | |
1069 | CHECK_FIELD_B(); | |
1070 | CHECK_FIELD_C(); | |
1071 | ||
1072 | write_instr_name(); | |
1073 | WRITE_FORMAT_x_COMMA_LB(C); | |
1074 | /* Try to print B as an aux reg if it is not a core reg. */ | |
1075 | usesAuxReg = 1; | |
1076 | WRITE_FORMAT_x(B); | |
1077 | WRITE_FORMAT_RB(); | |
1078 | my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB); | |
1079 | write_comments(); | |
1080 | break; | |
1081 | ||
1082 | case 9: | |
1083 | write_instr_name(); | |
1084 | state->operandBuffer[0] = '\0'; | |
1085 | break; | |
1086 | ||
1087 | case 10: | |
1088 | /* LR instruction */ | |
1089 | CHECK_FIELD_A(); | |
1090 | CHECK_FIELD_B(); | |
1091 | ||
1092 | write_instr_name(); | |
1093 | WRITE_FORMAT_x_COMMA_LB(A); | |
1094 | /* Try to print B as an aux reg if it is not a core reg. */ | |
1095 | usesAuxReg = 1; | |
1096 | WRITE_FORMAT_x(B); | |
1097 | WRITE_FORMAT_RB(); | |
1098 | my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB); | |
1099 | write_comments(); | |
1100 | break; | |
1101 | ||
1102 | case 11: | |
1103 | CHECK_COND(); | |
1104 | write_instr_name(); | |
1105 | state->operandBuffer[0] = '\0'; | |
1106 | break; | |
1107 | ||
1108 | default: | |
1109 | mwerror (state, "Bad decoding class in ARC disassembler"); | |
1110 | break; | |
252b5132 | 1111 | } |
0d2bcfaf NC |
1112 | |
1113 | state->_cond = cond; | |
1114 | return state->instructionLen = offset; | |
1115 | } | |
1116 | ||
252b5132 | 1117 | |
0d2bcfaf NC |
1118 | /* Returns the name the user specified core extension register. */ |
1119 | static const char * | |
1120 | _coreRegName(arg, regval) | |
1121 | void * arg ATTRIBUTE_UNUSED; | |
1122 | int regval; | |
1123 | { | |
1124 | return arcExtMap_coreRegName (regval); | |
252b5132 RH |
1125 | } |
1126 | ||
0d2bcfaf NC |
1127 | /* Returns the name the user specified AUX extension register. */ |
1128 | static const char * | |
1129 | _auxRegName(void *_this ATTRIBUTE_UNUSED, int regval) | |
1130 | { | |
1131 | return arcExtMap_auxRegName(regval); | |
1132 | } | |
252b5132 | 1133 | |
0d2bcfaf NC |
1134 | |
1135 | /* Returns the name the user specified condition code name. */ | |
1136 | static const char * | |
1137 | _condCodeName(void *_this ATTRIBUTE_UNUSED, int regval) | |
252b5132 | 1138 | { |
0d2bcfaf | 1139 | return arcExtMap_condCodeName(regval); |
252b5132 RH |
1140 | } |
1141 | ||
0d2bcfaf NC |
1142 | /* Returns the name the user specified extension instruction. */ |
1143 | static const char * | |
1144 | _instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags) | |
252b5132 | 1145 | { |
0d2bcfaf | 1146 | return arcExtMap_instName(majop, minop, flags); |
252b5132 RH |
1147 | } |
1148 | ||
0d2bcfaf NC |
1149 | /* Decode an instruction returning the size of the instruction |
1150 | in bytes or zero if unrecognized. */ | |
252b5132 | 1151 | static int |
0d2bcfaf NC |
1152 | decodeInstr (address, info) |
1153 | bfd_vma address; /* Address of this instruction. */ | |
1154 | disassemble_info * info; | |
1155 | { | |
1156 | int status; | |
1157 | bfd_byte buffer[4]; | |
1158 | struct arcDisState s; /* ARC Disassembler state */ | |
1159 | void *stream = info->stream; /* output stream */ | |
1160 | fprintf_ftype func = info->fprintf_func; | |
1161 | int bytes; | |
1162 | ||
1163 | memset (&s, 0, sizeof(struct arcDisState)); | |
1164 | ||
1165 | /* read first instruction */ | |
1166 | status = (*info->read_memory_func) (address, buffer, 4, info); | |
1167 | if (status != 0) | |
1168 | { | |
1169 | (*info->memory_error_func) (status, address, info); | |
1170 | return 0; | |
1171 | } | |
1172 | if (info->endian == BFD_ENDIAN_LITTLE) | |
1173 | s.words[0] = bfd_getl32(buffer); | |
1174 | else | |
1175 | s.words[0] = bfd_getb32(buffer); | |
1176 | /* always read second word in case of limm */ | |
1177 | ||
1178 | /* we ignore the result since last insn may not have a limm */ | |
1179 | status = (*info->read_memory_func) (address + 4, buffer, 4, info); | |
1180 | if (info->endian == BFD_ENDIAN_LITTLE) | |
1181 | s.words[1] = bfd_getl32(buffer); | |
1182 | else | |
1183 | s.words[1] = bfd_getb32(buffer); | |
1184 | ||
1185 | s._this = &s; | |
1186 | s.coreRegName = _coreRegName; | |
1187 | s.auxRegName = _auxRegName; | |
1188 | s.condCodeName = _condCodeName; | |
1189 | s.instName = _instName; | |
1190 | ||
1191 | /* disassemble */ | |
1192 | bytes = dsmOneArcInst(address, (void *)&s); | |
1193 | ||
1194 | /* display the disassembly instruction */ | |
1195 | (*func) (stream, "%08x ", s.words[0]); | |
1196 | (*func) (stream, " "); | |
1197 | ||
1198 | (*func) (stream, "%-10s ", s.instrBuffer); | |
1199 | ||
1200 | if (__TRANSLATION_REQUIRED(s)) | |
1201 | { | |
1202 | bfd_vma addr = s.addresses[s.operandBuffer[1] - '0']; | |
1203 | (*info->print_address_func) ((bfd_vma) addr, info); | |
1204 | (*func) (stream, "\n"); | |
1205 | } | |
1206 | else | |
1207 | (*func) (stream, "%s",s.operandBuffer); | |
1208 | return s.instructionLen; | |
1209 | } | |
1210 | ||
1211 | /* Return the print_insn function to use. | |
1212 | Side effect: load (possibly empty) extension section */ | |
1213 | ||
1214 | disassembler_ftype | |
1215 | arc_get_disassembler (void *ptr) | |
252b5132 | 1216 | { |
0d2bcfaf NC |
1217 | if (ptr) |
1218 | build_ARC_extmap (ptr); | |
1219 | return decodeInstr; | |
252b5132 | 1220 | } |