Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Opcode table for the ARC. |
b3adc24a | 2 | Copyright (C) 1994-2020 Free Software Foundation, Inc. |
886a2506 NC |
3 | |
4 | Contributed by Claudiu Zissulescu (claziss@synopsys.com) | |
bcee8eb8 | 5 | |
9b201bb5 NC |
6 | This file is part of libopcodes. |
7 | ||
8 | This library is free software; you can redistribute it and/or modify | |
252b5132 | 9 | it under the terms of the GNU General Public License as published by |
9b201bb5 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
9b201bb5 NC |
13 | It is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
252b5132 RH |
17 | |
18 | You should have received a copy of the GNU General Public License | |
0d2bcfaf | 19 | along with this program; if not, write to the Free Software Foundation, |
f4321104 | 20 | Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
252b5132 | 21 | |
5bd67f35 | 22 | #include "sysdep.h" |
252b5132 | 23 | #include <stdio.h> |
d943fe33 | 24 | #include "bfd.h" |
252b5132 | 25 | #include "opcode/arc.h" |
47b0e7ad | 26 | #include "opintl.h" |
886a2506 | 27 | #include "libiberty.h" |
252b5132 | 28 | |
e23e8ebe | 29 | /* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom |
ce440d63 | 30 | instructions. All NPS400 features are built into all ARC target builds as |
e23e8ebe AB |
31 | this reduces the chances that regressions might creep in. */ |
32 | ||
abe7c33b | 33 | /* Insert RA register into a 32-bit opcode, with checks. */ |
c0c31e91 | 34 | |
abe7c33b | 35 | static unsigned long long |
c0c31e91 RZ |
36 | insert_ra_chk (unsigned long long insn, |
37 | long long value, | |
38 | const char ** errmsg) | |
abe7c33b CZ |
39 | { |
40 | if (value == 60) | |
41 | *errmsg = _("LP_COUNT register cannot be used as destination register"); | |
42 | ||
43 | return insn | (value & 0x3F); | |
44 | } | |
c0c31e91 | 45 | |
886a2506 | 46 | /* Insert RB register into a 32-bit opcode. */ |
c0c31e91 | 47 | |
bdfe53e3 | 48 | static unsigned long long |
c0c31e91 RZ |
49 | insert_rb (unsigned long long insn, |
50 | long long value, | |
51 | const char ** errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 52 | { |
886a2506 NC |
53 | return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12); |
54 | } | |
0d2bcfaf | 55 | |
abe7c33b | 56 | /* Insert RB register with checks. */ |
c0c31e91 | 57 | |
abe7c33b | 58 | static unsigned long long |
c0c31e91 RZ |
59 | insert_rb_chk (unsigned long long insn, |
60 | long long value, | |
61 | const char ** errmsg) | |
abe7c33b CZ |
62 | { |
63 | if (value == 60) | |
64 | *errmsg = _("LP_COUNT register cannot be used as destination register"); | |
65 | ||
66 | return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12); | |
67 | } | |
68 | ||
c0c31e91 RZ |
69 | static long long |
70 | extract_rb (unsigned long long insn, | |
71 | bfd_boolean * invalid) | |
886a2506 NC |
72 | { |
73 | int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07); | |
0d2bcfaf | 74 | |
886a2506 NC |
75 | if (value == 0x3e && invalid) |
76 | *invalid = TRUE; /* A limm operand, it should be extracted in a | |
77 | different way. */ | |
252b5132 | 78 | |
886a2506 NC |
79 | return value; |
80 | } | |
252b5132 | 81 | |
bdfe53e3 | 82 | static unsigned long long |
c0c31e91 RZ |
83 | insert_rad (unsigned long long insn, |
84 | long long value, | |
85 | const char ** errmsg) | |
886a2506 NC |
86 | { |
87 | if (value & 0x01) | |
abe7c33b CZ |
88 | *errmsg = _("cannot use odd number destination register"); |
89 | if (value == 60) | |
90 | *errmsg = _("LP_COUNT register cannot be used as destination register"); | |
0d2bcfaf | 91 | |
886a2506 NC |
92 | return insn | (value & 0x3F); |
93 | } | |
0d2bcfaf | 94 | |
bdfe53e3 | 95 | static unsigned long long |
c0c31e91 RZ |
96 | insert_rcd (unsigned long long insn, |
97 | long long value, | |
98 | const char ** errmsg) | |
886a2506 NC |
99 | { |
100 | if (value & 0x01) | |
abe7c33b | 101 | *errmsg = _("cannot use odd number source register"); |
0d2bcfaf | 102 | |
886a2506 NC |
103 | return insn | ((value & 0x3F) << 6); |
104 | } | |
252b5132 | 105 | |
f337259f CZ |
106 | static unsigned long long |
107 | insert_rbd (unsigned long long insn, | |
108 | long long value, | |
109 | const char ** errmsg) | |
110 | { | |
111 | if (value & 0x01) | |
112 | *errmsg = _("cannot use odd number source register"); | |
113 | if (value == 60) | |
114 | *errmsg = _("LP_COUNT register cannot be used as destination register"); | |
115 | ||
116 | return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12); | |
117 | } | |
118 | ||
886a2506 | 119 | /* Dummy insert ZERO operand function. */ |
252b5132 | 120 | |
bdfe53e3 | 121 | static unsigned long long |
c0c31e91 RZ |
122 | insert_za (unsigned long long insn, |
123 | long long value, | |
124 | const char ** errmsg) | |
886a2506 NC |
125 | { |
126 | if (value) | |
127 | *errmsg = _("operand is not zero"); | |
128 | return insn; | |
129 | } | |
252b5132 | 130 | |
886a2506 NC |
131 | /* Insert Y-bit in bbit/br instructions. This function is called only |
132 | when solving fixups. */ | |
252b5132 | 133 | |
bdfe53e3 | 134 | static unsigned long long |
c0c31e91 RZ |
135 | insert_Ybit (unsigned long long insn, |
136 | long long value, | |
137 | const char ** errmsg ATTRIBUTE_UNUSED) | |
886a2506 NC |
138 | { |
139 | if (value > 0) | |
140 | insn |= 0x08; | |
252b5132 | 141 | |
886a2506 NC |
142 | return insn; |
143 | } | |
252b5132 | 144 | |
886a2506 NC |
145 | /* Insert Y-bit in bbit/br instructions. This function is called only |
146 | when solving fixups. */ | |
252b5132 | 147 | |
bdfe53e3 | 148 | static unsigned long long |
c0c31e91 RZ |
149 | insert_NYbit (unsigned long long insn, |
150 | long long value, | |
151 | const char ** errmsg ATTRIBUTE_UNUSED) | |
886a2506 NC |
152 | { |
153 | if (value < 0) | |
154 | insn |= 0x08; | |
0d2bcfaf | 155 | |
886a2506 NC |
156 | return insn; |
157 | } | |
252b5132 | 158 | |
886a2506 | 159 | /* Insert H register into a 16-bit opcode. */ |
252b5132 | 160 | |
bdfe53e3 | 161 | static unsigned long long |
c0c31e91 RZ |
162 | insert_rhv1 (unsigned long long insn, |
163 | long long value, | |
164 | const char ** errmsg ATTRIBUTE_UNUSED) | |
886a2506 NC |
165 | { |
166 | return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07); | |
167 | } | |
252b5132 | 168 | |
c0c31e91 RZ |
169 | static long long |
170 | extract_rhv1 (unsigned long long insn, | |
171 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
886a2506 | 172 | { |
02f3be19 | 173 | int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7); |
252b5132 | 174 | |
886a2506 NC |
175 | return value; |
176 | } | |
252b5132 | 177 | |
886a2506 | 178 | /* Insert H register into a 16-bit opcode. */ |
252b5132 | 179 | |
bdfe53e3 | 180 | static unsigned long long |
c0c31e91 RZ |
181 | insert_rhv2 (unsigned long long insn, |
182 | long long value, | |
183 | const char ** errmsg) | |
0d2bcfaf | 184 | { |
886a2506 | 185 | if (value == 0x1E) |
7cbc739c | 186 | *errmsg = _("register R30 is a limm indicator"); |
dc958481 | 187 | else if (value < 0 || value > 31) |
188 | *errmsg = _("register out of range"); | |
886a2506 NC |
189 | return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03); |
190 | } | |
252b5132 | 191 | |
c0c31e91 RZ |
192 | static long long |
193 | extract_rhv2 (unsigned long long insn, | |
194 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
886a2506 NC |
195 | { |
196 | int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3); | |
0d2bcfaf | 197 | |
886a2506 NC |
198 | return value; |
199 | } | |
0d2bcfaf | 200 | |
bdfe53e3 | 201 | static unsigned long long |
c0c31e91 RZ |
202 | insert_r0 (unsigned long long insn, |
203 | long long value, | |
204 | const char ** errmsg) | |
886a2506 NC |
205 | { |
206 | if (value != 0) | |
7cbc739c | 207 | *errmsg = _("register must be R0"); |
47b0e7ad NC |
208 | return insn; |
209 | } | |
252b5132 | 210 | |
c0c31e91 | 211 | static long long |
bdfe53e3 | 212 | extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED, |
886a2506 | 213 | bfd_boolean * invalid ATTRIBUTE_UNUSED) |
252b5132 | 214 | { |
886a2506 | 215 | return 0; |
47b0e7ad | 216 | } |
252b5132 | 217 | |
252b5132 | 218 | |
bdfe53e3 | 219 | static unsigned long long |
c0c31e91 RZ |
220 | insert_r1 (unsigned long long insn, |
221 | long long value, | |
222 | const char ** errmsg) | |
252b5132 | 223 | { |
886a2506 | 224 | if (value != 1) |
7cbc739c | 225 | *errmsg = _("register must be R1"); |
47b0e7ad | 226 | return insn; |
252b5132 RH |
227 | } |
228 | ||
c0c31e91 | 229 | static long long |
bdfe53e3 | 230 | extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED, |
886a2506 | 231 | bfd_boolean * invalid ATTRIBUTE_UNUSED) |
252b5132 | 232 | { |
886a2506 | 233 | return 1; |
252b5132 RH |
234 | } |
235 | ||
bdfe53e3 | 236 | static unsigned long long |
c0c31e91 RZ |
237 | insert_r2 (unsigned long long insn, |
238 | long long value, | |
239 | const char ** errmsg) | |
252b5132 | 240 | { |
886a2506 | 241 | if (value != 2) |
7cbc739c | 242 | *errmsg = _("register must be R2"); |
47b0e7ad | 243 | return insn; |
252b5132 RH |
244 | } |
245 | ||
c0c31e91 | 246 | static long long |
bdfe53e3 | 247 | extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED, |
886a2506 | 248 | bfd_boolean * invalid ATTRIBUTE_UNUSED) |
252b5132 | 249 | { |
886a2506 | 250 | return 2; |
252b5132 RH |
251 | } |
252 | ||
bdfe53e3 | 253 | static unsigned long long |
c0c31e91 RZ |
254 | insert_r3 (unsigned long long insn, |
255 | long long value, | |
256 | const char ** errmsg) | |
252b5132 | 257 | { |
886a2506 | 258 | if (value != 3) |
7cbc739c | 259 | *errmsg = _("register must be R3"); |
47b0e7ad | 260 | return insn; |
0d2bcfaf NC |
261 | } |
262 | ||
c0c31e91 | 263 | static long long |
bdfe53e3 | 264 | extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED, |
886a2506 | 265 | bfd_boolean * invalid ATTRIBUTE_UNUSED) |
0d2bcfaf | 266 | { |
886a2506 | 267 | return 3; |
0d2bcfaf NC |
268 | } |
269 | ||
bdfe53e3 | 270 | static unsigned long long |
c0c31e91 RZ |
271 | insert_sp (unsigned long long insn, |
272 | long long value, | |
273 | const char ** errmsg) | |
252b5132 | 274 | { |
886a2506 | 275 | if (value != 28) |
7cbc739c | 276 | *errmsg = _("register must be SP"); |
252b5132 RH |
277 | return insn; |
278 | } | |
279 | ||
c0c31e91 | 280 | static long long |
bdfe53e3 | 281 | extract_sp (unsigned long long insn ATTRIBUTE_UNUSED, |
886a2506 | 282 | bfd_boolean * invalid ATTRIBUTE_UNUSED) |
0d2bcfaf | 283 | { |
886a2506 | 284 | return 28; |
0d2bcfaf NC |
285 | } |
286 | ||
bdfe53e3 | 287 | static unsigned long long |
c0c31e91 RZ |
288 | insert_gp (unsigned long long insn, |
289 | long long value, | |
290 | const char ** errmsg) | |
0d2bcfaf | 291 | { |
886a2506 | 292 | if (value != 26) |
7cbc739c | 293 | *errmsg = _("register must be GP"); |
886a2506 | 294 | return insn; |
0d2bcfaf NC |
295 | } |
296 | ||
c0c31e91 | 297 | static long long |
bdfe53e3 | 298 | extract_gp (unsigned long long insn ATTRIBUTE_UNUSED, |
886a2506 | 299 | bfd_boolean * invalid ATTRIBUTE_UNUSED) |
0d2bcfaf | 300 | { |
886a2506 | 301 | return 26; |
0d2bcfaf NC |
302 | } |
303 | ||
bdfe53e3 | 304 | static unsigned long long |
c0c31e91 RZ |
305 | insert_pcl (unsigned long long insn, |
306 | long long value, | |
307 | const char ** errmsg) | |
252b5132 | 308 | { |
886a2506 | 309 | if (value != 63) |
7cbc739c | 310 | *errmsg = _("register must be PCL"); |
252b5132 RH |
311 | return insn; |
312 | } | |
313 | ||
c0c31e91 | 314 | static long long |
bdfe53e3 | 315 | extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED, |
886a2506 | 316 | bfd_boolean * invalid ATTRIBUTE_UNUSED) |
0d2bcfaf | 317 | { |
886a2506 | 318 | return 63; |
0d2bcfaf NC |
319 | } |
320 | ||
bdfe53e3 | 321 | static unsigned long long |
c0c31e91 RZ |
322 | insert_blink (unsigned long long insn, |
323 | long long value, | |
324 | const char ** errmsg) | |
252b5132 | 325 | { |
886a2506 | 326 | if (value != 31) |
7cbc739c | 327 | *errmsg = _("register must be BLINK"); |
252b5132 RH |
328 | return insn; |
329 | } | |
330 | ||
c0c31e91 | 331 | static long long |
bdfe53e3 | 332 | extract_blink (unsigned long long insn ATTRIBUTE_UNUSED, |
886a2506 | 333 | bfd_boolean * invalid ATTRIBUTE_UNUSED) |
252b5132 | 334 | { |
886a2506 | 335 | return 31; |
0d2bcfaf NC |
336 | } |
337 | ||
bdfe53e3 | 338 | static unsigned long long |
c0c31e91 RZ |
339 | insert_ilink1 (unsigned long long insn, |
340 | long long value, | |
341 | const char ** errmsg) | |
0d2bcfaf | 342 | { |
886a2506 | 343 | if (value != 29) |
7cbc739c | 344 | *errmsg = _("register must be ILINK1"); |
252b5132 RH |
345 | return insn; |
346 | } | |
347 | ||
c0c31e91 | 348 | static long long |
bdfe53e3 | 349 | extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED, |
886a2506 | 350 | bfd_boolean * invalid ATTRIBUTE_UNUSED) |
252b5132 | 351 | { |
886a2506 | 352 | return 29; |
252b5132 RH |
353 | } |
354 | ||
bdfe53e3 | 355 | static unsigned long long |
c0c31e91 RZ |
356 | insert_ilink2 (unsigned long long insn, |
357 | long long value, | |
358 | const char ** errmsg) | |
252b5132 | 359 | { |
886a2506 | 360 | if (value != 30) |
7cbc739c | 361 | *errmsg = _("register must be ILINK2"); |
252b5132 RH |
362 | return insn; |
363 | } | |
364 | ||
c0c31e91 | 365 | static long long |
bdfe53e3 | 366 | extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED, |
886a2506 NC |
367 | bfd_boolean * invalid ATTRIBUTE_UNUSED) |
368 | { | |
369 | return 30; | |
370 | } | |
252b5132 | 371 | |
bdfe53e3 | 372 | static unsigned long long |
c0c31e91 RZ |
373 | insert_ras (unsigned long long insn, |
374 | long long value, | |
375 | const char ** errmsg) | |
252b5132 | 376 | { |
886a2506 | 377 | switch (value) |
0d2bcfaf | 378 | { |
886a2506 NC |
379 | case 0: |
380 | case 1: | |
381 | case 2: | |
382 | case 3: | |
383 | insn |= value; | |
384 | break; | |
385 | case 12: | |
386 | case 13: | |
387 | case 14: | |
388 | case 15: | |
389 | insn |= (value - 8); | |
390 | break; | |
391 | default: | |
7cbc739c | 392 | *errmsg = _("register must be either r0-r3 or r12-r15"); |
886a2506 | 393 | break; |
0d2bcfaf | 394 | } |
252b5132 RH |
395 | return insn; |
396 | } | |
252b5132 | 397 | |
c0c31e91 RZ |
398 | static long long |
399 | extract_ras (unsigned long long insn, | |
400 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
47b0e7ad | 401 | { |
886a2506 | 402 | int value = insn & 0x07; |
c0c31e91 | 403 | |
886a2506 NC |
404 | if (value > 3) |
405 | return (value + 8); | |
406 | else | |
407 | return value; | |
47b0e7ad NC |
408 | } |
409 | ||
bdfe53e3 | 410 | static unsigned long long |
c0c31e91 RZ |
411 | insert_rbs (unsigned long long insn, |
412 | long long value, | |
413 | const char ** errmsg) | |
252b5132 | 414 | { |
886a2506 | 415 | switch (value) |
47b0e7ad | 416 | { |
886a2506 NC |
417 | case 0: |
418 | case 1: | |
419 | case 2: | |
420 | case 3: | |
421 | insn |= value << 8; | |
422 | break; | |
423 | case 12: | |
424 | case 13: | |
425 | case 14: | |
426 | case 15: | |
427 | insn |= ((value - 8)) << 8; | |
428 | break; | |
429 | default: | |
7cbc739c | 430 | *errmsg = _("register must be either r0-r3 or r12-r15"); |
886a2506 | 431 | break; |
47b0e7ad | 432 | } |
886a2506 | 433 | return insn; |
252b5132 RH |
434 | } |
435 | ||
c0c31e91 RZ |
436 | static long long |
437 | extract_rbs (unsigned long long insn, | |
438 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
252b5132 | 439 | { |
886a2506 | 440 | int value = (insn >> 8) & 0x07; |
c0c31e91 | 441 | |
886a2506 NC |
442 | if (value > 3) |
443 | return (value + 8); | |
444 | else | |
445 | return value; | |
446 | } | |
252b5132 | 447 | |
bdfe53e3 | 448 | static unsigned long long |
c0c31e91 RZ |
449 | insert_rcs (unsigned long long insn, |
450 | long long value, | |
451 | const char ** errmsg) | |
886a2506 NC |
452 | { |
453 | switch (value) | |
252b5132 | 454 | { |
886a2506 NC |
455 | case 0: |
456 | case 1: | |
457 | case 2: | |
458 | case 3: | |
459 | insn |= value << 5; | |
460 | break; | |
461 | case 12: | |
462 | case 13: | |
463 | case 14: | |
464 | case 15: | |
465 | insn |= ((value - 8)) << 5; | |
466 | break; | |
467 | default: | |
7cbc739c | 468 | *errmsg = _("register must be either r0-r3 or r12-r15"); |
886a2506 | 469 | break; |
252b5132 | 470 | } |
886a2506 NC |
471 | return insn; |
472 | } | |
47b0e7ad | 473 | |
c0c31e91 RZ |
474 | static long long |
475 | extract_rcs (unsigned long long insn, | |
476 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
886a2506 NC |
477 | { |
478 | int value = (insn >> 5) & 0x07; | |
c0c31e91 | 479 | |
886a2506 NC |
480 | if (value > 3) |
481 | return (value + 8); | |
252b5132 | 482 | else |
886a2506 NC |
483 | return value; |
484 | } | |
47b0e7ad | 485 | |
bdfe53e3 | 486 | static unsigned long long |
c0c31e91 RZ |
487 | insert_simm3s (unsigned long long insn, |
488 | long long value, | |
489 | const char ** errmsg) | |
886a2506 NC |
490 | { |
491 | int tmp = 0; | |
492 | switch (value) | |
47b0e7ad | 493 | { |
886a2506 NC |
494 | case -1: |
495 | tmp = 0x07; | |
47b0e7ad | 496 | break; |
886a2506 NC |
497 | case 0: |
498 | tmp = 0x00; | |
499 | break; | |
500 | case 1: | |
501 | tmp = 0x01; | |
47b0e7ad | 502 | break; |
886a2506 NC |
503 | case 2: |
504 | tmp = 0x02; | |
47b0e7ad | 505 | break; |
886a2506 NC |
506 | case 3: |
507 | tmp = 0x03; | |
508 | break; | |
509 | case 4: | |
510 | tmp = 0x04; | |
511 | break; | |
512 | case 5: | |
513 | tmp = 0x05; | |
514 | break; | |
515 | case 6: | |
516 | tmp = 0x06; | |
517 | break; | |
518 | default: | |
7cbc739c | 519 | *errmsg = _("accepted values are from -1 to 6"); |
47b0e7ad NC |
520 | break; |
521 | } | |
522 | ||
886a2506 NC |
523 | insn |= tmp << 8; |
524 | return insn; | |
47b0e7ad NC |
525 | } |
526 | ||
c0c31e91 RZ |
527 | static long long |
528 | extract_simm3s (unsigned long long insn, | |
529 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
47b0e7ad | 530 | { |
886a2506 | 531 | int value = (insn >> 8) & 0x07; |
c0c31e91 | 532 | |
886a2506 NC |
533 | if (value == 7) |
534 | return -1; | |
47b0e7ad | 535 | else |
886a2506 | 536 | return value; |
47b0e7ad NC |
537 | } |
538 | ||
bdfe53e3 | 539 | static unsigned long long |
c0c31e91 RZ |
540 | insert_rrange (unsigned long long insn, |
541 | long long value, | |
542 | const char ** errmsg) | |
47b0e7ad | 543 | { |
886a2506 NC |
544 | int reg1 = (value >> 16) & 0xFFFF; |
545 | int reg2 = value & 0xFFFF; | |
c0c31e91 | 546 | |
886a2506 | 547 | if (reg1 != 13) |
7cbc739c | 548 | *errmsg = _("first register of the range should be r13"); |
c0c31e91 | 549 | else if (reg2 < 13 || reg2 > 26) |
7cbc739c | 550 | *errmsg = _("last register of the range doesn't fit"); |
c0c31e91 RZ |
551 | else |
552 | insn |= ((reg2 - 12) & 0x0F) << 1; | |
886a2506 | 553 | return insn; |
47b0e7ad NC |
554 | } |
555 | ||
c0c31e91 RZ |
556 | static long long |
557 | extract_rrange (unsigned long long insn, | |
558 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
886a2506 NC |
559 | { |
560 | return (insn >> 1) & 0x0F; | |
561 | } | |
47b0e7ad | 562 | |
126124cc CZ |
563 | static unsigned long long |
564 | insert_r13el (unsigned long long insn, | |
565 | long long int value, | |
566 | const char **errmsg) | |
567 | { | |
568 | if (value != 13) | |
569 | { | |
7cbc739c | 570 | *errmsg = _("invalid register number, should be fp"); |
126124cc CZ |
571 | return insn; |
572 | } | |
573 | ||
574 | insn |= 0x02; | |
575 | return insn; | |
576 | } | |
577 | ||
bdfe53e3 | 578 | static unsigned long long |
c0c31e91 RZ |
579 | insert_fpel (unsigned long long insn, |
580 | long long value, | |
581 | const char ** errmsg) | |
47b0e7ad | 582 | { |
886a2506 NC |
583 | if (value != 27) |
584 | { | |
7cbc739c | 585 | *errmsg = _("invalid register number, should be fp"); |
886a2506 NC |
586 | return insn; |
587 | } | |
47b0e7ad | 588 | |
886a2506 NC |
589 | insn |= 0x0100; |
590 | return insn; | |
47b0e7ad NC |
591 | } |
592 | ||
c0c31e91 RZ |
593 | static long long |
594 | extract_fpel (unsigned long long insn, | |
595 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
47b0e7ad | 596 | { |
886a2506 | 597 | return (insn & 0x0100) ? 27 : -1; |
47b0e7ad NC |
598 | } |
599 | ||
bdfe53e3 | 600 | static unsigned long long |
c0c31e91 RZ |
601 | insert_blinkel (unsigned long long insn, |
602 | long long value, | |
603 | const char ** errmsg) | |
47b0e7ad | 604 | { |
886a2506 | 605 | if (value != 31) |
47b0e7ad | 606 | { |
7cbc739c | 607 | *errmsg = _("invalid register number, should be blink"); |
886a2506 | 608 | return insn; |
47b0e7ad | 609 | } |
47b0e7ad | 610 | |
886a2506 NC |
611 | insn |= 0x0200; |
612 | return insn; | |
47b0e7ad NC |
613 | } |
614 | ||
c0c31e91 RZ |
615 | static long long |
616 | extract_blinkel (unsigned long long insn, | |
617 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
47b0e7ad | 618 | { |
886a2506 NC |
619 | return (insn & 0x0200) ? 31 : -1; |
620 | } | |
47b0e7ad | 621 | |
bdfe53e3 | 622 | static unsigned long long |
c0c31e91 RZ |
623 | insert_pclel (unsigned long long insn, |
624 | long long value, | |
625 | const char ** errmsg) | |
886a2506 NC |
626 | { |
627 | if (value != 63) | |
47b0e7ad | 628 | { |
7cbc739c | 629 | *errmsg = _("invalid register number, should be pcl"); |
886a2506 | 630 | return insn; |
47b0e7ad | 631 | } |
47b0e7ad | 632 | |
886a2506 NC |
633 | insn |= 0x0400; |
634 | return insn; | |
635 | } | |
47b0e7ad | 636 | |
c0c31e91 RZ |
637 | static long long |
638 | extract_pclel (unsigned long long insn, | |
639 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
47b0e7ad | 640 | { |
886a2506 | 641 | return (insn & 0x0400) ? 63 : -1; |
47b0e7ad | 642 | } |
47b0e7ad | 643 | |
886a2506 | 644 | #define INSERT_W6 |
c0c31e91 | 645 | |
886a2506 NC |
646 | /* mask = 00000000000000000000111111000000 |
647 | insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */ | |
c0c31e91 | 648 | |
bdfe53e3 | 649 | static unsigned long long |
c0c31e91 RZ |
650 | insert_w6 (unsigned long long insn, |
651 | long long value, | |
652 | const char ** errmsg ATTRIBUTE_UNUSED) | |
47b0e7ad | 653 | { |
886a2506 | 654 | insn |= ((value >> 0) & 0x003f) << 6; |
47b0e7ad | 655 | |
886a2506 NC |
656 | return insn; |
657 | } | |
47b0e7ad | 658 | |
886a2506 | 659 | #define EXTRACT_W6 |
c0c31e91 | 660 | |
886a2506 | 661 | /* mask = 00000000000000000000111111000000. */ |
c0c31e91 RZ |
662 | |
663 | static long long | |
664 | extract_w6 (unsigned long long insn, | |
665 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
47b0e7ad | 666 | { |
04e65276 | 667 | int value = 0; |
47b0e7ad | 668 | |
886a2506 | 669 | value |= ((insn >> 6) & 0x003f) << 0; |
47b0e7ad | 670 | |
04e65276 CZ |
671 | /* Extend the sign. */ |
672 | int signbit = 1 << 5; | |
673 | value = (value ^ signbit) - signbit; | |
674 | ||
886a2506 NC |
675 | return value; |
676 | } | |
47b0e7ad | 677 | |
886a2506 | 678 | #define INSERT_G_S |
c0c31e91 | 679 | |
886a2506 NC |
680 | /* mask = 0000011100022000 |
681 | insn = 01000ggghhhGG0HH. */ | |
c0c31e91 | 682 | |
bdfe53e3 | 683 | static unsigned long long |
c0c31e91 RZ |
684 | insert_g_s (unsigned long long insn, |
685 | long long value, | |
686 | const char ** errmsg ATTRIBUTE_UNUSED) | |
47b0e7ad | 687 | { |
886a2506 NC |
688 | insn |= ((value >> 0) & 0x0007) << 8; |
689 | insn |= ((value >> 3) & 0x0003) << 3; | |
252b5132 | 690 | |
886a2506 NC |
691 | return insn; |
692 | } | |
252b5132 | 693 | |
886a2506 | 694 | #define EXTRACT_G_S |
c0c31e91 | 695 | |
886a2506 | 696 | /* mask = 0000011100022000. */ |
c0c31e91 RZ |
697 | |
698 | static long long | |
699 | extract_g_s (unsigned long long insn, | |
700 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
886a2506 NC |
701 | { |
702 | int value = 0; | |
c0c31e91 | 703 | int signbit = 1 << (6 - 1); |
252b5132 | 704 | |
886a2506 NC |
705 | value |= ((insn >> 8) & 0x0007) << 0; |
706 | value |= ((insn >> 3) & 0x0003) << 3; | |
252b5132 | 707 | |
886a2506 | 708 | /* Extend the sign. */ |
886a2506 | 709 | value = (value ^ signbit) - signbit; |
252b5132 | 710 | |
886a2506 | 711 | return value; |
252b5132 RH |
712 | } |
713 | ||
e23e8ebe | 714 | /* ARC NPS400 Support: See comment near head of file. */ |
bdfe53e3 AB |
715 | #define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \ |
716 | static unsigned long long \ | |
717 | insert_nps_3bit_reg_at_##OFFSET##_##NAME \ | |
c0c31e91 RZ |
718 | (unsigned long long insn, \ |
719 | long long value, \ | |
720 | const char ** errmsg) \ | |
bdfe53e3 AB |
721 | { \ |
722 | switch (value) \ | |
723 | { \ | |
724 | case 0: \ | |
725 | case 1: \ | |
726 | case 2: \ | |
727 | case 3: \ | |
728 | insn |= value << (OFFSET); \ | |
729 | break; \ | |
730 | case 12: \ | |
731 | case 13: \ | |
732 | case 14: \ | |
733 | case 15: \ | |
734 | insn |= (value - 8) << (OFFSET); \ | |
735 | break; \ | |
736 | default: \ | |
7cbc739c | 737 | *errmsg = _("register must be either r0-r3 or r12-r15"); \ |
bdfe53e3 AB |
738 | break; \ |
739 | } \ | |
740 | return insn; \ | |
741 | } \ | |
742 | \ | |
c0c31e91 | 743 | static long long \ |
bdfe53e3 | 744 | extract_nps_3bit_reg_at_##OFFSET##_##NAME \ |
c0c31e91 RZ |
745 | (unsigned long long insn, \ |
746 | bfd_boolean * invalid ATTRIBUTE_UNUSED) \ | |
bdfe53e3 AB |
747 | { \ |
748 | int value = (insn >> (OFFSET)) & 0x07; \ | |
749 | if (value > 3) \ | |
750 | value += 8; \ | |
751 | return value; \ | |
752 | } \ | |
753 | ||
754 | MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,8) | |
755 | MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,24) | |
756 | MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,40) | |
757 | MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,56) | |
758 | ||
759 | MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,5) | |
760 | MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,21) | |
761 | MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,37) | |
762 | MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,53) | |
763 | ||
764 | static unsigned long long | |
c0c31e91 RZ |
765 | insert_nps_bitop_size_2b (unsigned long long insn, |
766 | long long value, | |
767 | const char ** errmsg) | |
820f03ff AB |
768 | { |
769 | switch (value) | |
770 | { | |
771 | case 1: | |
772 | value = 0; | |
773 | break; | |
774 | case 2: | |
775 | value = 1; | |
776 | break; | |
777 | case 4: | |
778 | value = 2; | |
779 | break; | |
780 | case 8: | |
781 | value = 3; | |
782 | break; | |
783 | default: | |
784 | value = 0; | |
7cbc739c | 785 | *errmsg = _("invalid size, should be 1, 2, 4, or 8"); |
820f03ff AB |
786 | break; |
787 | } | |
788 | ||
789 | insn |= value << 10; | |
790 | return insn; | |
791 | } | |
792 | ||
c0c31e91 RZ |
793 | static long long |
794 | extract_nps_bitop_size_2b (unsigned long long insn, | |
795 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
820f03ff AB |
796 | { |
797 | return 1 << ((insn >> 10) & 0x3); | |
798 | } | |
799 | ||
bdfe53e3 | 800 | static unsigned long long |
c0c31e91 RZ |
801 | insert_nps_bitop_uimm8 (unsigned long long insn, |
802 | long long value, | |
803 | const char ** errmsg ATTRIBUTE_UNUSED) | |
820f03ff AB |
804 | { |
805 | insn |= ((value >> 5) & 7) << 12; | |
806 | insn |= (value & 0x1f); | |
807 | return insn; | |
808 | } | |
809 | ||
c0c31e91 RZ |
810 | static long long |
811 | extract_nps_bitop_uimm8 (unsigned long long insn, | |
812 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
820f03ff AB |
813 | { |
814 | return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f); | |
815 | } | |
816 | ||
bdfe53e3 | 817 | static unsigned long long |
c0c31e91 RZ |
818 | insert_nps_rflt_uimm6 (unsigned long long insn, |
819 | long long value, | |
820 | const char ** errmsg) | |
820f03ff AB |
821 | { |
822 | switch (value) | |
823 | { | |
824 | case 1: | |
825 | case 2: | |
826 | case 4: | |
827 | break; | |
828 | ||
829 | default: | |
830 | *errmsg = _("invalid immediate, must be 1, 2, or 4"); | |
831 | value = 0; | |
832 | } | |
833 | ||
834 | insn |= (value << 6); | |
835 | return insn; | |
836 | } | |
837 | ||
c0c31e91 RZ |
838 | static long long |
839 | extract_nps_rflt_uimm6 (unsigned long long insn, | |
840 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
820f03ff AB |
841 | { |
842 | return (insn >> 6) & 0x3f; | |
843 | } | |
844 | ||
bdfe53e3 | 845 | static unsigned long long |
c0c31e91 RZ |
846 | insert_nps_dst_pos_and_size (unsigned long long insn, |
847 | long long value, | |
848 | const char ** errmsg ATTRIBUTE_UNUSED) | |
820f03ff AB |
849 | { |
850 | insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10)); | |
851 | return insn; | |
852 | } | |
853 | ||
c0c31e91 RZ |
854 | static long long |
855 | extract_nps_dst_pos_and_size (unsigned long long insn, | |
856 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
820f03ff AB |
857 | { |
858 | return (insn & 0x1f); | |
859 | } | |
860 | ||
bdfe53e3 | 861 | static unsigned long long |
c0c31e91 RZ |
862 | insert_nps_cmem_uimm16 (unsigned long long insn, |
863 | long long value, | |
864 | const char ** errmsg) | |
4b0c052e AB |
865 | { |
866 | int top = (value >> 16) & 0xffff; | |
c0c31e91 | 867 | |
4b0c052e AB |
868 | if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE) |
869 | *errmsg = _("invalid value for CMEM ld/st immediate"); | |
870 | insn |= (value & 0xffff); | |
871 | return insn; | |
872 | } | |
873 | ||
c0c31e91 RZ |
874 | static long long |
875 | extract_nps_cmem_uimm16 (unsigned long long insn, | |
876 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
4b0c052e AB |
877 | { |
878 | return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff); | |
879 | } | |
880 | ||
c0c31e91 RZ |
881 | static unsigned long long |
882 | insert_nps_imm_offset (unsigned long long insn, | |
883 | long long value, | |
884 | const char ** errmsg) | |
645d3342 RZ |
885 | { |
886 | switch (value) | |
887 | { | |
888 | case 0: | |
889 | case 16: | |
890 | case 32: | |
891 | case 48: | |
892 | case 64: | |
893 | value = value >> 4; | |
894 | break; | |
895 | default: | |
7cbc739c | 896 | *errmsg = _("invalid position, should be 0, 16, 32, 48 or 64."); |
645d3342 RZ |
897 | value = 0; |
898 | } | |
899 | insn |= (value << 10); | |
900 | return insn; | |
901 | } | |
902 | ||
c0c31e91 RZ |
903 | static long long |
904 | extract_nps_imm_offset (unsigned long long insn, | |
905 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
645d3342 RZ |
906 | { |
907 | return ((insn >> 10) & 0x7) * 16; | |
908 | } | |
909 | ||
910 | static unsigned long long | |
c0c31e91 RZ |
911 | insert_nps_imm_entry (unsigned long long insn, |
912 | long long value, | |
913 | const char ** errmsg) | |
645d3342 RZ |
914 | { |
915 | switch (value) | |
916 | { | |
917 | case 16: | |
918 | value = 0; | |
919 | break; | |
920 | case 32: | |
921 | value = 1; | |
922 | break; | |
923 | case 64: | |
924 | value = 2; | |
925 | break; | |
926 | case 128: | |
927 | value = 3; | |
928 | break; | |
929 | default: | |
7cbc739c | 930 | *errmsg = _("invalid position, should be 16, 32, 64 or 128."); |
645d3342 RZ |
931 | value = 0; |
932 | } | |
933 | insn |= (value << 2); | |
934 | return insn; | |
935 | } | |
936 | ||
c0c31e91 RZ |
937 | static long long |
938 | extract_nps_imm_entry (unsigned long long insn, | |
939 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
645d3342 RZ |
940 | { |
941 | int imm_entry = ((insn >> 2) & 0x7); | |
942 | return (1 << (imm_entry + 4)); | |
943 | } | |
944 | ||
c0c31e91 RZ |
945 | static unsigned long long |
946 | insert_nps_size_16bit (unsigned long long insn, | |
947 | long long value, | |
948 | const char ** errmsg) | |
949 | { | |
950 | if ((value < 1) || (value > 64)) | |
951 | { | |
7cbc739c | 952 | *errmsg = _("invalid size value must be on range 1-64."); |
c0c31e91 RZ |
953 | value = 0; |
954 | } | |
955 | value = value & 0x3f; | |
956 | insn |= (value << 6); | |
957 | return insn; | |
958 | } | |
959 | ||
960 | static long long | |
961 | extract_nps_size_16bit (unsigned long long insn, | |
962 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
963 | { | |
964 | return ((insn & 0xfc0) >> 6) ? ((insn & 0xfc0) >> 6) : 64; | |
965 | } | |
966 | ||
967 | ||
968 | #define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \ | |
969 | static unsigned long long \ | |
970 | insert_nps_##NAME##_pos (unsigned long long insn, \ | |
971 | long long value, \ | |
972 | const char ** errmsg) \ | |
537aefaf AB |
973 | { \ |
974 | switch (value) \ | |
975 | { \ | |
976 | case 0: \ | |
977 | case 8: \ | |
978 | case 16: \ | |
979 | case 24: \ | |
980 | value = value / 8; \ | |
981 | break; \ | |
982 | default: \ | |
7cbc739c | 983 | *errmsg = _("invalid position, should be 0, 8, 16, or 24"); \ |
537aefaf AB |
984 | value = 0; \ |
985 | } \ | |
c0c31e91 | 986 | insn |= (value << SHIFT); \ |
537aefaf AB |
987 | return insn; \ |
988 | } \ | |
989 | \ | |
c0c31e91 RZ |
990 | static long long \ |
991 | extract_nps_##NAME##_pos (unsigned long long insn, \ | |
992 | bfd_boolean * invalid ATTRIBUTE_UNUSED) \ | |
993 | { \ | |
994 | return ((insn >> SHIFT) & 0x3) * 8; \ | |
537aefaf AB |
995 | } |
996 | ||
997 | MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12) | |
998 | MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10) | |
999 | ||
c0c31e91 RZ |
1000 | #define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT) \ |
1001 | static unsigned long long \ | |
1002 | insert_nps_##NAME (unsigned long long insn, \ | |
1003 | long long value, \ | |
1004 | const char ** errmsg) \ | |
537aefaf | 1005 | { \ |
9ba75c88 | 1006 | if (value < LOWER || value > UPPER) \ |
537aefaf | 1007 | { \ |
7cbc739c | 1008 | *errmsg = _("invalid size, value must be " \ |
537aefaf AB |
1009 | #LOWER " to " #UPPER "."); \ |
1010 | return insn; \ | |
1011 | } \ | |
1012 | value -= BIAS; \ | |
1013 | insn |= (value << SHIFT); \ | |
1014 | return insn; \ | |
1015 | } \ | |
1016 | \ | |
c0c31e91 RZ |
1017 | static long long \ |
1018 | extract_nps_##NAME (unsigned long long insn, \ | |
1019 | bfd_boolean * invalid ATTRIBUTE_UNUSED) \ | |
537aefaf AB |
1020 | { \ |
1021 | return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \ | |
1022 | } | |
1023 | ||
db18dbab GM |
1024 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5) |
1025 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5) | |
1026 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5) | |
1027 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5) | |
1028 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10) | |
1029 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9) | |
1030 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20) | |
1031 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25) | |
1032 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6) | |
1033 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2) | |
1034 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0) | |
537aefaf | 1035 | |
c0c31e91 RZ |
1036 | static long long |
1037 | extract_nps_qcmp_m3 (unsigned long long insn, | |
1038 | bfd_boolean * invalid) | |
537aefaf AB |
1039 | { |
1040 | int m3 = (insn >> 5) & 0xf; | |
1041 | if (m3 == 0xf) | |
1042 | *invalid = TRUE; | |
1043 | return m3; | |
1044 | } | |
1045 | ||
c0c31e91 RZ |
1046 | static long long |
1047 | extract_nps_qcmp_m2 (unsigned long long insn, | |
1048 | bfd_boolean * invalid) | |
537aefaf AB |
1049 | { |
1050 | bfd_boolean tmp_invalid = FALSE; | |
1051 | int m2 = (insn >> 15) & 0x1; | |
1052 | int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid); | |
1053 | ||
1054 | if (m2 == 0 && m3 == 0xf) | |
1055 | *invalid = TRUE; | |
1056 | return m2; | |
1057 | } | |
1058 | ||
c0c31e91 RZ |
1059 | static long long |
1060 | extract_nps_qcmp_m1 (unsigned long long insn, | |
1061 | bfd_boolean * invalid) | |
537aefaf AB |
1062 | { |
1063 | bfd_boolean tmp_invalid = FALSE; | |
1064 | int m1 = (insn >> 14) & 0x1; | |
1065 | int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid); | |
1066 | int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid); | |
1067 | ||
1068 | if (m1 == 0 && m2 == 0 && m3 == 0xf) | |
1069 | *invalid = TRUE; | |
1070 | return m1; | |
1071 | } | |
1072 | ||
bdfe53e3 | 1073 | static unsigned long long |
c0c31e91 RZ |
1074 | insert_nps_calc_entry_size (unsigned long long insn, |
1075 | long long value, | |
1076 | const char ** errmsg) | |
537aefaf AB |
1077 | { |
1078 | unsigned pwr; | |
1079 | ||
1080 | if (value < 1 || value > 256) | |
1081 | { | |
1082 | *errmsg = _("value out of range 1 - 256"); | |
1083 | return 0; | |
1084 | } | |
1085 | ||
1086 | for (pwr = 0; (value & 1) == 0; value >>= 1) | |
1087 | ++pwr; | |
1088 | ||
1089 | if (value != 1) | |
1090 | { | |
1091 | *errmsg = _("value must be power of 2"); | |
1092 | return 0; | |
1093 | } | |
1094 | ||
1095 | return insn | (pwr << 8); | |
1096 | } | |
1097 | ||
c0c31e91 RZ |
1098 | static long long |
1099 | extract_nps_calc_entry_size (unsigned long long insn, | |
1100 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
537aefaf AB |
1101 | { |
1102 | unsigned entry_size = (insn >> 8) & 0xf; | |
1103 | return 1 << entry_size; | |
1104 | } | |
1105 | ||
bdfe53e3 | 1106 | static unsigned long long |
c0c31e91 RZ |
1107 | insert_nps_bitop_mod4 (unsigned long long insn, |
1108 | long long value, | |
1109 | const char ** errmsg ATTRIBUTE_UNUSED) | |
4eb6f892 | 1110 | { |
bdfe53e3 | 1111 | return insn | ((value & 0x2) << 30) | ((value & 0x1) << 47); |
4eb6f892 AB |
1112 | } |
1113 | ||
c0c31e91 RZ |
1114 | static long long |
1115 | extract_nps_bitop_mod4 (unsigned long long insn, | |
1116 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
4eb6f892 | 1117 | { |
bdfe53e3 | 1118 | return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1); |
4eb6f892 AB |
1119 | } |
1120 | ||
bdfe53e3 | 1121 | static unsigned long long |
c0c31e91 RZ |
1122 | insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn, |
1123 | long long value, | |
1124 | const char ** errmsg ATTRIBUTE_UNUSED) | |
4eb6f892 | 1125 | { |
bdfe53e3 | 1126 | return insn | (value << 42) | (value << 37); |
4eb6f892 AB |
1127 | } |
1128 | ||
c0c31e91 RZ |
1129 | static long long |
1130 | extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn, | |
1131 | bfd_boolean * invalid) | |
4eb6f892 | 1132 | { |
bdfe53e3 | 1133 | if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f)) |
4eb6f892 | 1134 | *invalid = TRUE; |
bdfe53e3 | 1135 | return ((insn >> 37) & 0x1f); |
4eb6f892 AB |
1136 | } |
1137 | ||
bdfe53e3 | 1138 | static unsigned long long |
c0c31e91 RZ |
1139 | insert_nps_bitop_ins_ext (unsigned long long insn, |
1140 | long long value, | |
1141 | const char ** errmsg) | |
4eb6f892 AB |
1142 | { |
1143 | if (value < 0 || value > 28) | |
7cbc739c | 1144 | *errmsg = _("value must be in the range 0 to 28"); |
4eb6f892 AB |
1145 | return insn | (value << 20); |
1146 | } | |
1147 | ||
c0c31e91 RZ |
1148 | static long long |
1149 | extract_nps_bitop_ins_ext (unsigned long long insn, | |
1150 | bfd_boolean * invalid) | |
4eb6f892 AB |
1151 | { |
1152 | int value = (insn >> 20) & 0x1f; | |
c0c31e91 | 1153 | |
4eb6f892 AB |
1154 | if (value > 28) |
1155 | *invalid = TRUE; | |
1156 | return value; | |
1157 | } | |
1158 | ||
14053c19 | 1159 | #define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \ |
c0c31e91 RZ |
1160 | static unsigned long long \ |
1161 | insert_nps_##NAME (unsigned long long insn, \ | |
1162 | long long value, \ | |
1163 | const char ** errmsg) \ | |
14053c19 GM |
1164 | { \ |
1165 | if (value < 1 || value > UPPER) \ | |
7cbc739c | 1166 | *errmsg = _("value must be in the range 1 to " #UPPER); \ |
14053c19 GM |
1167 | if (value == UPPER) \ |
1168 | value = 0; \ | |
1169 | return insn | (value << SHIFT); \ | |
1170 | } \ | |
1171 | \ | |
c0c31e91 RZ |
1172 | static long long \ |
1173 | extract_nps_##NAME (unsigned long long insn, \ | |
1174 | bfd_boolean * invalid ATTRIBUTE_UNUSED) \ | |
14053c19 GM |
1175 | { \ |
1176 | int value = (insn >> SHIFT) & ((1 << BITS) - 1); \ | |
1177 | if (value == 0) \ | |
1178 | value = UPPER; \ | |
1179 | return value; \ | |
1180 | } | |
1181 | ||
db18dbab GM |
1182 | MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3) |
1183 | MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3) | |
1184 | MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3) | |
1185 | MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8) | |
1186 | MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3) | |
1187 | MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2) | |
5a736821 | 1188 | MAKE_1BASED_INSERT_EXTRACT_FUNCS (proto_size, 16, 64, 6) |
14053c19 | 1189 | |
bdfe53e3 | 1190 | static unsigned long long |
c0c31e91 RZ |
1191 | insert_nps_min_hofs (unsigned long long insn, |
1192 | long long value, | |
1193 | const char ** errmsg) | |
14053c19 GM |
1194 | { |
1195 | if (value < 0 || value > 240) | |
7cbc739c | 1196 | *errmsg = _("value must be in the range 0 to 240"); |
14053c19 | 1197 | if ((value % 16) != 0) |
7cbc739c | 1198 | *errmsg = _("value must be a multiple of 16"); |
14053c19 GM |
1199 | value = value / 16; |
1200 | return insn | (value << 6); | |
1201 | } | |
1202 | ||
c0c31e91 RZ |
1203 | static long long |
1204 | extract_nps_min_hofs (unsigned long long insn, | |
1205 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
14053c19 GM |
1206 | { |
1207 | int value = (insn >> 6) & 0xF; | |
1208 | return value * 16; | |
1209 | } | |
1210 | ||
c0c31e91 | 1211 | #define MAKE_INSERT_NPS_ADDRTYPE(NAME, VALUE) \ |
bdfe53e3 | 1212 | static unsigned long long \ |
c0c31e91 RZ |
1213 | insert_nps_##NAME (unsigned long long insn, \ |
1214 | long long value, \ | |
1215 | const char ** errmsg) \ | |
db18dbab GM |
1216 | { \ |
1217 | if (value != ARC_NPS400_ADDRTYPE_##VALUE) \ | |
7cbc739c | 1218 | *errmsg = _("invalid address type for operand"); \ |
db18dbab GM |
1219 | return insn; \ |
1220 | } \ | |
1221 | \ | |
c0c31e91 RZ |
1222 | static long long \ |
1223 | extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \ | |
1224 | bfd_boolean * invalid ATTRIBUTE_UNUSED) \ | |
db18dbab GM |
1225 | { \ |
1226 | return ARC_NPS400_ADDRTYPE_##VALUE; \ | |
1227 | } | |
1228 | ||
1229 | MAKE_INSERT_NPS_ADDRTYPE (bd, BD) | |
1230 | MAKE_INSERT_NPS_ADDRTYPE (jid, JID) | |
1231 | MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD) | |
1232 | MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD) | |
1233 | MAKE_INSERT_NPS_ADDRTYPE (sd, SD) | |
1234 | MAKE_INSERT_NPS_ADDRTYPE (sm, SM) | |
1235 | MAKE_INSERT_NPS_ADDRTYPE (xa, XA) | |
1236 | MAKE_INSERT_NPS_ADDRTYPE (xd, XD) | |
1237 | MAKE_INSERT_NPS_ADDRTYPE (cd, CD) | |
1238 | MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD) | |
1239 | MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID) | |
1240 | MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD) | |
1241 | MAKE_INSERT_NPS_ADDRTYPE (cm, CM) | |
1242 | MAKE_INSERT_NPS_ADDRTYPE (csd, CSD) | |
1243 | MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA) | |
1244 | MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD) | |
1245 | ||
5a736821 | 1246 | static unsigned long long |
c0c31e91 RZ |
1247 | insert_nps_rbdouble_64 (unsigned long long insn, |
1248 | long long value, | |
1249 | const char ** errmsg) | |
5a736821 GM |
1250 | { |
1251 | if (value < 0 || value > 31) | |
7cbc739c | 1252 | *errmsg = _("value must be in the range 0 to 31"); |
5a736821 GM |
1253 | return insn | (value << 43) | (value << 48); |
1254 | } | |
1255 | ||
1256 | ||
c0c31e91 RZ |
1257 | static long long |
1258 | extract_nps_rbdouble_64 (unsigned long long insn, | |
1259 | bfd_boolean * invalid) | |
5a736821 GM |
1260 | { |
1261 | int value1 = (insn >> 43) & 0x1F; | |
1262 | int value2 = (insn >> 48) & 0x1F; | |
1263 | ||
1264 | if (value1 != value2) | |
1265 | *invalid = TRUE; | |
1266 | ||
1267 | return value1; | |
1268 | } | |
1269 | ||
c0c31e91 RZ |
1270 | static unsigned long long |
1271 | insert_nps_misc_imm_offset (unsigned long long insn, | |
1272 | long long value, | |
1273 | const char ** errmsg) | |
1274 | { | |
1275 | if (value & 0x3) | |
1276 | { | |
7cbc739c | 1277 | *errmsg = _("invalid position, should be one of: 0,4,8,...124."); |
c0c31e91 RZ |
1278 | value = 0; |
1279 | } | |
1280 | insn |= (value << 6); | |
1281 | return insn; | |
1282 | } | |
1283 | ||
1284 | static long long int | |
1285 | extract_nps_misc_imm_offset (unsigned long long insn, | |
1286 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
1287 | { | |
1288 | return ((insn >> 8) & 0x1f) * 4; | |
1289 | } | |
1290 | ||
7179e0e6 CZ |
1291 | static long long int |
1292 | extract_uimm12_20 (unsigned long long insn ATTRIBUTE_UNUSED, | |
1293 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
1294 | { | |
1295 | int value = 0; | |
1296 | ||
1297 | value |= ((insn >> 6) & 0x003f) << 0; | |
1298 | value |= ((insn >> 0) & 0x003f) << 6; | |
1299 | ||
1300 | return value; | |
1301 | } | |
1302 | ||
886a2506 NC |
1303 | /* Include the generic extract/insert functions. Order is important |
1304 | as some of the functions present in the .h may be disabled via | |
1305 | defines. */ | |
1306 | #include "arc-fxi.h" | |
252b5132 | 1307 | |
886a2506 | 1308 | /* The flag operands table. |
252b5132 | 1309 | |
886a2506 NC |
1310 | The format of the table is |
1311 | NAME CODE BITS SHIFT FAVAIL. */ | |
1312 | const struct arc_flag_operand arc_flag_operands[] = | |
1313 | { | |
1314 | #define F_NULL 0 | |
1315 | { 0, 0, 0, 0, 0}, | |
1316 | #define F_ALWAYS (F_NULL + 1) | |
1317 | { "al", 0, 0, 0, 0 }, | |
1318 | #define F_RA (F_ALWAYS + 1) | |
1319 | { "ra", 0, 0, 0, 0 }, | |
1320 | #define F_EQUAL (F_RA + 1) | |
1321 | { "eq", 1, 5, 0, 1 }, | |
1322 | #define F_ZERO (F_EQUAL + 1) | |
1323 | { "z", 1, 5, 0, 0 }, | |
1324 | #define F_NOTEQUAL (F_ZERO + 1) | |
1325 | { "ne", 2, 5, 0, 1 }, | |
1326 | #define F_NOTZERO (F_NOTEQUAL + 1) | |
1327 | { "nz", 2, 5, 0, 0 }, | |
1328 | #define F_POZITIVE (F_NOTZERO + 1) | |
1329 | { "p", 3, 5, 0, 1 }, | |
1330 | #define F_PL (F_POZITIVE + 1) | |
1331 | { "pl", 3, 5, 0, 0 }, | |
1332 | #define F_NEGATIVE (F_PL + 1) | |
1333 | { "n", 4, 5, 0, 1 }, | |
1334 | #define F_MINUS (F_NEGATIVE + 1) | |
1335 | { "mi", 4, 5, 0, 0 }, | |
1336 | #define F_CARRY (F_MINUS + 1) | |
1337 | { "c", 5, 5, 0, 1 }, | |
1338 | #define F_CARRYSET (F_CARRY + 1) | |
1339 | { "cs", 5, 5, 0, 0 }, | |
1340 | #define F_LOWER (F_CARRYSET + 1) | |
1341 | { "lo", 5, 5, 0, 0 }, | |
1342 | #define F_CARRYCLR (F_LOWER + 1) | |
1343 | { "cc", 6, 5, 0, 0 }, | |
1344 | #define F_NOTCARRY (F_CARRYCLR + 1) | |
1345 | { "nc", 6, 5, 0, 1 }, | |
1346 | #define F_HIGHER (F_NOTCARRY + 1) | |
1347 | { "hs", 6, 5, 0, 0 }, | |
1348 | #define F_OVERFLOWSET (F_HIGHER + 1) | |
1349 | { "vs", 7, 5, 0, 0 }, | |
1350 | #define F_OVERFLOW (F_OVERFLOWSET + 1) | |
1351 | { "v", 7, 5, 0, 1 }, | |
1352 | #define F_NOTOVERFLOW (F_OVERFLOW + 1) | |
1353 | { "nv", 8, 5, 0, 1 }, | |
1354 | #define F_OVERFLOWCLR (F_NOTOVERFLOW + 1) | |
1355 | { "vc", 8, 5, 0, 0 }, | |
1356 | #define F_GT (F_OVERFLOWCLR + 1) | |
1357 | { "gt", 9, 5, 0, 1 }, | |
1358 | #define F_GE (F_GT + 1) | |
1359 | { "ge", 10, 5, 0, 1 }, | |
1360 | #define F_LT (F_GE + 1) | |
1361 | { "lt", 11, 5, 0, 1 }, | |
1362 | #define F_LE (F_LT + 1) | |
1363 | { "le", 12, 5, 0, 1 }, | |
1364 | #define F_HI (F_LE + 1) | |
1365 | { "hi", 13, 5, 0, 1 }, | |
1366 | #define F_LS (F_HI + 1) | |
1367 | { "ls", 14, 5, 0, 1 }, | |
1368 | #define F_PNZ (F_LS + 1) | |
1369 | { "pnz", 15, 5, 0, 1 }, | |
c0c31e91 RZ |
1370 | #define F_NJ (F_PNZ + 1) |
1371 | { "nj", 21, 5, 0, 1 }, | |
1372 | #define F_NM (F_NJ + 1) | |
1373 | { "nm", 23, 5, 0, 1 }, | |
1374 | #define F_NO_T (F_NM + 1) | |
1375 | { "nt", 24, 5, 0, 1 }, | |
886a2506 NC |
1376 | |
1377 | /* FLAG. */ | |
c0c31e91 | 1378 | #define F_FLAG (F_NO_T + 1) |
886a2506 NC |
1379 | { "f", 1, 1, 15, 1 }, |
1380 | #define F_FFAKE (F_FLAG + 1) | |
1381 | { "f", 0, 0, 0, 1 }, | |
1382 | ||
1383 | /* Delay slot. */ | |
1384 | #define F_ND (F_FFAKE + 1) | |
1385 | { "nd", 0, 1, 5, 0 }, | |
1386 | #define F_D (F_ND + 1) | |
1387 | { "d", 1, 1, 5, 1 }, | |
1388 | #define F_DFAKE (F_D + 1) | |
1389 | { "d", 0, 0, 0, 1 }, | |
2b848ebd CZ |
1390 | #define F_DNZ_ND (F_DFAKE + 1) |
1391 | { "nd", 0, 1, 16, 0 }, | |
1392 | #define F_DNZ_D (F_DNZ_ND + 1) | |
1393 | { "d", 1, 1, 16, 1 }, | |
886a2506 NC |
1394 | |
1395 | /* Data size. */ | |
2b848ebd | 1396 | #define F_SIZEB1 (F_DNZ_D + 1) |
886a2506 NC |
1397 | { "b", 1, 2, 1, 1 }, |
1398 | #define F_SIZEB7 (F_SIZEB1 + 1) | |
1399 | { "b", 1, 2, 7, 1 }, | |
1400 | #define F_SIZEB17 (F_SIZEB7 + 1) | |
1401 | { "b", 1, 2, 17, 1 }, | |
1402 | #define F_SIZEW1 (F_SIZEB17 + 1) | |
1403 | { "w", 2, 2, 1, 0 }, | |
1404 | #define F_SIZEW7 (F_SIZEW1 + 1) | |
1405 | { "w", 2, 2, 7, 0 }, | |
1406 | #define F_SIZEW17 (F_SIZEW7 + 1) | |
1407 | { "w", 2, 2, 17, 0 }, | |
1408 | ||
1409 | /* Sign extension. */ | |
1410 | #define F_SIGN6 (F_SIZEW17 + 1) | |
1411 | { "x", 1, 1, 6, 1 }, | |
1412 | #define F_SIGN16 (F_SIGN6 + 1) | |
1413 | { "x", 1, 1, 16, 1 }, | |
1414 | #define F_SIGNX (F_SIGN16 + 1) | |
1415 | { "x", 0, 0, 0, 1 }, | |
1416 | ||
1417 | /* Address write-back modes. */ | |
1418 | #define F_A3 (F_SIGNX + 1) | |
1419 | { "a", 1, 2, 3, 0 }, | |
1420 | #define F_A9 (F_A3 + 1) | |
1421 | { "a", 1, 2, 9, 0 }, | |
1422 | #define F_A22 (F_A9 + 1) | |
1423 | { "a", 1, 2, 22, 0 }, | |
1424 | #define F_AW3 (F_A22 + 1) | |
1425 | { "aw", 1, 2, 3, 1 }, | |
1426 | #define F_AW9 (F_AW3 + 1) | |
1427 | { "aw", 1, 2, 9, 1 }, | |
1428 | #define F_AW22 (F_AW9 + 1) | |
1429 | { "aw", 1, 2, 22, 1 }, | |
1430 | #define F_AB3 (F_AW22 + 1) | |
1431 | { "ab", 2, 2, 3, 1 }, | |
1432 | #define F_AB9 (F_AB3 + 1) | |
1433 | { "ab", 2, 2, 9, 1 }, | |
1434 | #define F_AB22 (F_AB9 + 1) | |
1435 | { "ab", 2, 2, 22, 1 }, | |
1436 | #define F_AS3 (F_AB22 + 1) | |
1437 | { "as", 3, 2, 3, 1 }, | |
1438 | #define F_AS9 (F_AS3 + 1) | |
1439 | { "as", 3, 2, 9, 1 }, | |
1440 | #define F_AS22 (F_AS9 + 1) | |
1441 | { "as", 3, 2, 22, 1 }, | |
1442 | #define F_ASFAKE (F_AS22 + 1) | |
1443 | { "as", 0, 0, 0, 1 }, | |
1444 | ||
1445 | /* Cache bypass. */ | |
1446 | #define F_DI5 (F_ASFAKE + 1) | |
1447 | { "di", 1, 1, 5, 1 }, | |
1448 | #define F_DI11 (F_DI5 + 1) | |
1449 | { "di", 1, 1, 11, 1 }, | |
b437d035 AB |
1450 | #define F_DI14 (F_DI11 + 1) |
1451 | { "di", 1, 1, 14, 1 }, | |
1452 | #define F_DI15 (F_DI14 + 1) | |
886a2506 NC |
1453 | { "di", 1, 1, 15, 1 }, |
1454 | ||
1455 | /* ARCv2 specific. */ | |
1456 | #define F_NT (F_DI15 + 1) | |
1457 | { "nt", 0, 1, 3, 1}, | |
1458 | #define F_T (F_NT + 1) | |
1459 | { "t", 1, 1, 3, 1}, | |
1460 | #define F_H1 (F_T + 1) | |
1461 | { "h", 2, 2, 1, 1 }, | |
1462 | #define F_H7 (F_H1 + 1) | |
1463 | { "h", 2, 2, 7, 1 }, | |
1464 | #define F_H17 (F_H7 + 1) | |
1465 | { "h", 2, 2, 17, 1 }, | |
6ec7c1ae CZ |
1466 | #define F_SIZED (F_H17 + 1) |
1467 | { "dd", 8, 0, 0, 0 }, /* Fake. */ | |
886a2506 NC |
1468 | |
1469 | /* Fake Flags. */ | |
6ec7c1ae | 1470 | #define F_NE (F_SIZED + 1) |
886a2506 | 1471 | { "ne", 0, 0, 0, 1 }, |
e23e8ebe AB |
1472 | |
1473 | /* ARC NPS400 Support: See comment near head of file. */ | |
1474 | #define F_NPS_CL (F_NE + 1) | |
1475 | { "cl", 0, 0, 0, 1 }, | |
1476 | ||
645d3342 RZ |
1477 | #define F_NPS_NA (F_NPS_CL + 1) |
1478 | { "na", 1, 1, 9, 1 }, | |
1479 | ||
c0c31e91 RZ |
1480 | #define F_NPS_SR (F_NPS_NA + 1) |
1481 | { "s", 1, 1, 13, 1 }, | |
1482 | ||
1483 | #define F_NPS_M (F_NPS_SR + 1) | |
1484 | { "m", 1, 1, 7, 1 }, | |
1485 | ||
1486 | #define F_NPS_FLAG (F_NPS_M + 1) | |
e23e8ebe | 1487 | { "f", 1, 1, 20, 1 }, |
820f03ff AB |
1488 | |
1489 | #define F_NPS_R (F_NPS_FLAG + 1) | |
1490 | { "r", 1, 1, 15, 1 }, | |
a42a4f84 AB |
1491 | |
1492 | #define F_NPS_RW (F_NPS_R + 1) | |
1493 | { "rw", 0, 1, 7, 1 }, | |
1494 | ||
1495 | #define F_NPS_RD (F_NPS_RW + 1) | |
1496 | { "rd", 1, 1, 7, 1 }, | |
1497 | ||
1498 | #define F_NPS_WFT (F_NPS_RD + 1) | |
1499 | { "wft", 0, 0, 0, 1 }, | |
1500 | ||
1501 | #define F_NPS_IE1 (F_NPS_WFT + 1) | |
1502 | { "ie1", 1, 2, 8, 1 }, | |
1503 | ||
1504 | #define F_NPS_IE2 (F_NPS_IE1 + 1) | |
1505 | { "ie2", 2, 2, 8, 1 }, | |
1506 | ||
1507 | #define F_NPS_IE12 (F_NPS_IE2 + 1) | |
1508 | { "ie12", 3, 2, 8, 1 }, | |
1509 | ||
1510 | #define F_NPS_SYNC_RD (F_NPS_IE12 + 1) | |
1511 | { "rd", 0, 1, 6, 1 }, | |
1512 | ||
1513 | #define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1) | |
1514 | { "wr", 1, 1, 6, 1 }, | |
1515 | ||
1516 | #define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1) | |
1517 | { "off", 0, 0, 0, 1 }, | |
1518 | ||
1519 | #define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1) | |
1520 | { "restore", 0, 0, 0, 1 }, | |
1521 | ||
537aefaf AB |
1522 | #define F_NPS_SX (F_NPS_HWS_RESTORE + 1) |
1523 | { "sx", 1, 1, 14, 1 }, | |
1524 | ||
1525 | #define F_NPS_AR (F_NPS_SX + 1) | |
1526 | { "ar", 0, 1, 0, 1 }, | |
1527 | ||
1528 | #define F_NPS_AL (F_NPS_AR + 1) | |
1529 | { "al", 1, 1, 0, 1 }, | |
14053c19 GM |
1530 | |
1531 | #define F_NPS_S (F_NPS_AL + 1) | |
1532 | { "s", 0, 0, 0, 1 }, | |
1533 | ||
1534 | #define F_NPS_ZNCV_RD (F_NPS_S + 1) | |
1535 | { "rd", 0, 1, 15, 1 }, | |
1536 | ||
1537 | #define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1) | |
1538 | { "wr", 1, 1, 15, 1 }, | |
9ba75c88 GM |
1539 | |
1540 | #define F_NPS_P0 (F_NPS_ZNCV_WR + 1) | |
1541 | { "p0", 0, 0, 0, 1 }, | |
1542 | ||
1543 | #define F_NPS_P1 (F_NPS_P0 + 1) | |
1544 | { "p1", 0, 0, 0, 1 }, | |
1545 | ||
1546 | #define F_NPS_P2 (F_NPS_P1 + 1) | |
1547 | { "p2", 0, 0, 0, 1 }, | |
1548 | ||
1549 | #define F_NPS_P3 (F_NPS_P2 + 1) | |
1550 | { "p3", 0, 0, 0, 1 }, | |
28215275 GM |
1551 | |
1552 | #define F_NPS_LDBIT_DI (F_NPS_P3 + 1) | |
1553 | { "di", 0, 0, 0, 1 }, | |
1554 | ||
1555 | #define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1) | |
1556 | { "cl", 1, 1, 6, 1 }, | |
1557 | ||
1558 | #define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1) | |
1559 | { "cl", 1, 1, 16, 1 }, | |
1560 | ||
1561 | #define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1) | |
1562 | { "x2", 1, 2, 9, 1 }, | |
1563 | ||
1564 | #define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1) | |
1565 | { "x2", 1, 2, 22, 1 }, | |
1566 | ||
1567 | #define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1) | |
1568 | { "x4", 2, 2, 9, 1 }, | |
1569 | ||
1570 | #define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1) | |
1571 | { "x4", 2, 2, 22, 1 }, | |
c0c31e91 RZ |
1572 | |
1573 | #define F_NPS_CORE (F_NPS_LDBIT_X4_2 + 1) | |
1574 | { "core", 1, 3, 6, 1 }, | |
1575 | ||
1576 | #define F_NPS_CLSR (F_NPS_CORE + 1) | |
1577 | { "clsr", 2, 3, 6, 1 }, | |
1578 | ||
1579 | #define F_NPS_ALL (F_NPS_CLSR + 1) | |
1580 | { "all", 3, 3, 6, 1 }, | |
1581 | ||
1582 | #define F_NPS_GIC (F_NPS_ALL + 1) | |
1583 | { "gic", 4, 3, 6, 1 }, | |
1584 | ||
1585 | #define F_NPS_RSPI_GIC (F_NPS_GIC + 1) | |
1586 | { "gic", 5, 3, 6, 1 }, | |
886a2506 | 1587 | }; |
252b5132 | 1588 | |
886a2506 | 1589 | const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands); |
252b5132 | 1590 | |
886a2506 | 1591 | /* Table of the flag classes. |
252b5132 | 1592 | |
886a2506 NC |
1593 | The format of the table is |
1594 | CLASS {FLAG_CODE}. */ | |
1595 | const struct arc_flag_class arc_flag_classes[] = | |
1596 | { | |
1597 | #define C_EMPTY 0 | |
1ae8ab47 | 1598 | { F_CLASS_NONE, { F_NULL } }, |
886a2506 | 1599 | |
6ec7c1ae CZ |
1600 | #define C_CC_EQ (C_EMPTY + 1) |
1601 | {F_CLASS_IMPLICIT | F_CLASS_COND, {F_EQUAL, F_NULL} }, | |
1602 | ||
1603 | #define C_CC_GE (C_CC_EQ + 1) | |
1604 | {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GE, F_NULL} }, | |
1605 | ||
1606 | #define C_CC_GT (C_CC_GE + 1) | |
1607 | {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GT, F_NULL} }, | |
1608 | ||
1609 | #define C_CC_HI (C_CC_GT + 1) | |
1610 | {F_CLASS_IMPLICIT | F_CLASS_COND, {F_HI, F_NULL} }, | |
1611 | ||
1612 | #define C_CC_HS (C_CC_HI + 1) | |
1613 | {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTCARRY, F_NULL} }, | |
1614 | ||
1615 | #define C_CC_LE (C_CC_HS + 1) | |
1616 | {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LE, F_NULL} }, | |
1617 | ||
1618 | #define C_CC_LO (C_CC_LE + 1) | |
1619 | {F_CLASS_IMPLICIT | F_CLASS_COND, {F_CARRY, F_NULL} }, | |
1620 | ||
1621 | #define C_CC_LS (C_CC_LO + 1) | |
1622 | {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LS, F_NULL} }, | |
1623 | ||
1624 | #define C_CC_LT (C_CC_LS + 1) | |
1625 | {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LT, F_NULL} }, | |
1626 | ||
1627 | #define C_CC_NE (C_CC_LT + 1) | |
1628 | {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTEQUAL, F_NULL} }, | |
1629 | ||
1630 | #define C_AA_AB (C_CC_NE + 1) | |
1631 | {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AB3, F_NULL} }, | |
1632 | ||
1633 | #define C_AA_AW (C_AA_AB + 1) | |
1634 | {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AW3, F_NULL} }, | |
1635 | ||
1636 | #define C_ZZ_D (C_AA_AW + 1) | |
1637 | {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZED, F_NULL} }, | |
1638 | ||
1639 | #define C_ZZ_H (C_ZZ_D + 1) | |
1640 | {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_H1, F_NULL} }, | |
1641 | ||
1642 | #define C_ZZ_B (C_ZZ_H + 1) | |
1643 | {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEB1, F_NULL} }, | |
1644 | ||
1645 | #define C_CC (C_ZZ_B + 1) | |
d9eca1df | 1646 | { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND, |
f36e33da CZ |
1647 | { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, |
1648 | F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, | |
1649 | F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
1650 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, | |
1651 | F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, | |
c0c31e91 | 1652 | F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T, F_NULL } }, |
886a2506 NC |
1653 | |
1654 | #define C_AA_ADDR3 (C_CC + 1) | |
1655 | #define C_AA27 (C_CC + 1) | |
6ec7c1ae | 1656 | { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } }, |
886a2506 NC |
1657 | #define C_AA_ADDR9 (C_AA_ADDR3 + 1) |
1658 | #define C_AA21 (C_AA_ADDR3 + 1) | |
6ec7c1ae | 1659 | { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } }, |
886a2506 NC |
1660 | #define C_AA_ADDR22 (C_AA_ADDR9 + 1) |
1661 | #define C_AA8 (C_AA_ADDR9 + 1) | |
6ec7c1ae | 1662 | { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } }, |
886a2506 NC |
1663 | |
1664 | #define C_F (C_AA_ADDR22 + 1) | |
1ae8ab47 | 1665 | { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } }, |
886a2506 | 1666 | #define C_FHARD (C_F + 1) |
1ae8ab47 | 1667 | { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } }, |
886a2506 NC |
1668 | |
1669 | #define C_T (C_FHARD + 1) | |
1ae8ab47 | 1670 | { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } }, |
886a2506 | 1671 | #define C_D (C_T + 1) |
1ae8ab47 | 1672 | { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } }, |
2b848ebd CZ |
1673 | #define C_DNZ_D (C_D + 1) |
1674 | { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } }, | |
886a2506 | 1675 | |
2b848ebd | 1676 | #define C_DHARD (C_DNZ_D + 1) |
1ae8ab47 | 1677 | { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } }, |
886a2506 NC |
1678 | |
1679 | #define C_DI20 (C_DHARD + 1) | |
1ae8ab47 | 1680 | { F_CLASS_OPTIONAL, { F_DI11, F_NULL }}, |
b437d035 AB |
1681 | #define C_DI14 (C_DI20 + 1) |
1682 | { F_CLASS_OPTIONAL, { F_DI14, F_NULL }}, | |
1683 | #define C_DI16 (C_DI14 + 1) | |
1ae8ab47 | 1684 | { F_CLASS_OPTIONAL, { F_DI15, F_NULL }}, |
886a2506 | 1685 | #define C_DI26 (C_DI16 + 1) |
1ae8ab47 | 1686 | { F_CLASS_OPTIONAL, { F_DI5, F_NULL }}, |
886a2506 NC |
1687 | |
1688 | #define C_X25 (C_DI26 + 1) | |
1ae8ab47 | 1689 | { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }}, |
886a2506 | 1690 | #define C_X15 (C_X25 + 1) |
1ae8ab47 | 1691 | { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }}, |
886a2506 NC |
1692 | #define C_XHARD (C_X15 + 1) |
1693 | #define C_X (C_X15 + 1) | |
1ae8ab47 | 1694 | { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }}, |
886a2506 NC |
1695 | |
1696 | #define C_ZZ13 (C_X + 1) | |
1ae8ab47 | 1697 | { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}}, |
886a2506 | 1698 | #define C_ZZ23 (C_ZZ13 + 1) |
1ae8ab47 | 1699 | { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}}, |
886a2506 | 1700 | #define C_ZZ29 (C_ZZ23 + 1) |
1ae8ab47 | 1701 | { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}}, |
886a2506 NC |
1702 | |
1703 | #define C_AS (C_ZZ29 + 1) | |
1ae8ab47 | 1704 | { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}}, |
886a2506 NC |
1705 | |
1706 | #define C_NE (C_AS + 1) | |
5e4f7e05 | 1707 | { F_CLASS_REQUIRED, { F_NE, F_NULL}}, |
e23e8ebe AB |
1708 | |
1709 | /* ARC NPS400 Support: See comment near head of file. */ | |
1710 | #define C_NPS_CL (C_NE + 1) | |
1711 | { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}}, | |
1712 | ||
645d3342 RZ |
1713 | #define C_NPS_NA (C_NPS_CL + 1) |
1714 | { F_CLASS_OPTIONAL, { F_NPS_NA, F_NULL}}, | |
1715 | ||
c0c31e91 RZ |
1716 | #define C_NPS_SR (C_NPS_NA + 1) |
1717 | { F_CLASS_OPTIONAL, { F_NPS_SR, F_NULL}}, | |
1718 | ||
1719 | #define C_NPS_M (C_NPS_SR + 1) | |
1720 | { F_CLASS_OPTIONAL, { F_NPS_M, F_NULL}}, | |
1721 | ||
1722 | #define C_NPS_F (C_NPS_M + 1) | |
e23e8ebe | 1723 | { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}}, |
820f03ff AB |
1724 | |
1725 | #define C_NPS_R (C_NPS_F + 1) | |
1726 | { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}}, | |
a42a4f84 AB |
1727 | |
1728 | #define C_NPS_SCHD_RW (C_NPS_R + 1) | |
1729 | { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}}, | |
1730 | ||
1731 | #define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1) | |
1732 | { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}}, | |
1733 | ||
1734 | #define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1) | |
1735 | { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}}, | |
1736 | ||
1737 | #define C_NPS_SYNC (C_NPS_SCHD_IE + 1) | |
1738 | { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}}, | |
1739 | ||
1740 | #define C_NPS_HWS_OFF (C_NPS_SYNC + 1) | |
1741 | { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}}, | |
1742 | ||
1743 | #define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1) | |
1744 | { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}}, | |
1745 | ||
537aefaf AB |
1746 | #define C_NPS_SX (C_NPS_HWS_RESTORE + 1) |
1747 | { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}}, | |
1748 | ||
1749 | #define C_NPS_AR_AL (C_NPS_SX + 1) | |
1750 | { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}}, | |
14053c19 GM |
1751 | |
1752 | #define C_NPS_S (C_NPS_AR_AL + 1) | |
1753 | { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}}, | |
1754 | ||
1755 | #define C_NPS_ZNCV (C_NPS_S + 1) | |
1756 | { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}}, | |
9ba75c88 GM |
1757 | |
1758 | #define C_NPS_P0 (C_NPS_ZNCV + 1) | |
1759 | { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }}, | |
1760 | ||
1761 | #define C_NPS_P1 (C_NPS_P0 + 1) | |
1762 | { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }}, | |
1763 | ||
1764 | #define C_NPS_P2 (C_NPS_P1 + 1) | |
1765 | { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }}, | |
1766 | ||
1767 | #define C_NPS_P3 (C_NPS_P2 + 1) | |
1768 | { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }}, | |
28215275 GM |
1769 | |
1770 | #define C_NPS_LDBIT_DI (C_NPS_P3 + 1) | |
1771 | { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }}, | |
1772 | ||
1773 | #define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1) | |
1774 | { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }}, | |
1775 | ||
1776 | #define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1) | |
1777 | { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }}, | |
1778 | ||
1779 | #define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1) | |
1780 | { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }}, | |
1781 | ||
1782 | #define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1) | |
1783 | { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }}, | |
c0c31e91 RZ |
1784 | |
1785 | #define C_NPS_CORE (C_NPS_LDBIT_X_2 + 1) | |
1786 | { F_CLASS_REQUIRED, { F_NPS_CORE, F_NULL}}, | |
1787 | ||
1788 | #define C_NPS_CLSR (C_NPS_CORE + 1) | |
1789 | { F_CLASS_REQUIRED, { F_NPS_CLSR, F_NULL}}, | |
1790 | ||
1791 | #define C_NPS_ALL (C_NPS_CLSR + 1) | |
1792 | { F_CLASS_REQUIRED, { F_NPS_ALL, F_NULL}}, | |
1793 | ||
1794 | #define C_NPS_GIC (C_NPS_ALL + 1) | |
1795 | { F_CLASS_REQUIRED, { F_NPS_GIC, F_NULL}}, | |
1796 | ||
1797 | #define C_NPS_RSPI_GIC (C_NPS_GIC + 1) | |
1798 | { F_CLASS_REQUIRED, { F_NPS_RSPI_GIC, F_NULL}}, | |
886a2506 | 1799 | }; |
252b5132 | 1800 | |
b99747ae CZ |
1801 | const unsigned char flags_none[] = { 0 }; |
1802 | const unsigned char flags_f[] = { C_F }; | |
1803 | const unsigned char flags_cc[] = { C_CC }; | |
1804 | const unsigned char flags_ccf[] = { C_CC, C_F }; | |
1805 | ||
886a2506 | 1806 | /* The operands table. |
252b5132 | 1807 | |
886a2506 | 1808 | The format of the operands table is: |
47b0e7ad | 1809 | |
886a2506 NC |
1810 | BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */ |
1811 | const struct arc_operand arc_operands[] = | |
0d2bcfaf | 1812 | { |
886a2506 NC |
1813 | /* The fields are bits, shift, insert, extract, flags. The zero |
1814 | index is used to indicate end-of-list. */ | |
1815 | #define UNUSED 0 | |
1816 | { 0, 0, 0, 0, 0, 0 }, | |
4eb6f892 AB |
1817 | |
1818 | #define IGNORED (UNUSED + 1) | |
1819 | { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 }, | |
1820 | ||
886a2506 NC |
1821 | /* The plain integer register fields. Used by 32 bit |
1822 | instructions. */ | |
4eb6f892 | 1823 | #define RA (IGNORED + 1) |
886a2506 | 1824 | { 6, 0, 0, ARC_OPERAND_IR, 0, 0 }, |
abe7c33b CZ |
1825 | #define RA_CHK (RA + 1) |
1826 | { 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0 }, | |
1827 | #define RB (RA_CHK + 1) | |
886a2506 | 1828 | { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb }, |
abe7c33b CZ |
1829 | #define RB_CHK (RB + 1) |
1830 | { 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb }, | |
1831 | #define RC (RB_CHK + 1) | |
886a2506 NC |
1832 | { 6, 6, 0, ARC_OPERAND_IR, 0, 0 }, |
1833 | #define RBdup (RC + 1) | |
1834 | { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb }, | |
1835 | ||
1836 | #define RAD (RBdup + 1) | |
1837 | { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 }, | |
7e126ba3 CZ |
1838 | #define RAD_CHK (RAD + 1) |
1839 | { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 }, | |
1840 | #define RCD (RAD_CHK + 1) | |
886a2506 | 1841 | { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 }, |
f337259f CZ |
1842 | #define RBD (RCD + 1) |
1843 | { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rbd, extract_rb }, | |
1844 | #define RBDdup (RBD + 1) | |
1845 | { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_TRUNCATE, | |
1846 | insert_rbd, extract_rb }, | |
886a2506 NC |
1847 | |
1848 | /* The plain integer register fields. Used by short | |
1849 | instructions. */ | |
f337259f CZ |
1850 | #define RA16 (RBDdup + 1) |
1851 | #define RA_S (RBDdup + 1) | |
886a2506 NC |
1852 | { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras }, |
1853 | #define RB16 (RA16 + 1) | |
1854 | #define RB_S (RA16 + 1) | |
1855 | { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs }, | |
1856 | #define RB16dup (RB16 + 1) | |
1857 | #define RB_Sdup (RB16 + 1) | |
1858 | { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs }, | |
1859 | #define RC16 (RB16dup + 1) | |
1860 | #define RC_S (RB16dup + 1) | |
1861 | { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs }, | |
1862 | #define R6H (RC16 + 1) /* 6bit register field 'h' used | |
1863 | by V1 cpus. */ | |
1864 | { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 }, | |
1865 | #define R5H (R6H + 1) /* 5bit register field 'h' used | |
1866 | by V2 cpus. */ | |
1867 | #define RH_S (R6H + 1) /* 5bit register field 'h' used | |
1868 | by V2 cpus. */ | |
1869 | { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 }, | |
1870 | #define R5Hdup (R5H + 1) | |
1871 | #define RH_Sdup (R5H + 1) | |
1872 | { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, | |
1873 | insert_rhv2, extract_rhv2 }, | |
1874 | ||
1875 | #define RG (R5Hdup + 1) | |
1876 | #define G_S (R5Hdup + 1) | |
1877 | { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s }, | |
1878 | ||
1879 | /* Fix registers. */ | |
1880 | #define R0 (RG + 1) | |
1881 | #define R0_S (RG + 1) | |
1882 | { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 }, | |
1883 | #define R1 (R0 + 1) | |
1884 | #define R1_S (R0 + 1) | |
1885 | { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 }, | |
1886 | #define R2 (R1 + 1) | |
1887 | #define R2_S (R1 + 1) | |
1888 | { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 }, | |
1889 | #define R3 (R2 + 1) | |
1890 | #define R3_S (R2 + 1) | |
1891 | { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 }, | |
8ddf6b2a | 1892 | #define RSP (R3 + 1) |
886a2506 NC |
1893 | #define SP_S (R3 + 1) |
1894 | { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp }, | |
8ddf6b2a CZ |
1895 | #define SPdup (RSP + 1) |
1896 | #define SP_Sdup (RSP + 1) | |
886a2506 NC |
1897 | { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp }, |
1898 | #define GP (SPdup + 1) | |
1899 | #define GP_S (SPdup + 1) | |
1900 | { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp }, | |
1901 | ||
1902 | #define PCL_S (GP + 1) | |
1903 | { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl }, | |
1904 | ||
1905 | #define BLINK (PCL_S + 1) | |
1906 | #define BLINK_S (PCL_S + 1) | |
1907 | { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink }, | |
1908 | ||
1909 | #define ILINK1 (BLINK + 1) | |
1910 | { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 }, | |
1911 | #define ILINK2 (ILINK1 + 1) | |
1912 | { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 }, | |
1913 | ||
1914 | /* Long immediate. */ | |
1915 | #define LIMM (ILINK2 + 1) | |
1916 | #define LIMM_S (ILINK2 + 1) | |
1917 | { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 }, | |
1918 | #define LIMMdup (LIMM + 1) | |
1919 | { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 }, | |
1920 | ||
1921 | /* Special operands. */ | |
1922 | #define ZA (LIMMdup + 1) | |
1923 | #define ZB (LIMMdup + 1) | |
1924 | #define ZA_S (LIMMdup + 1) | |
1925 | #define ZB_S (LIMMdup + 1) | |
1926 | #define ZC_S (LIMMdup + 1) | |
1927 | { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 }, | |
1928 | ||
1929 | #define RRANGE_EL (ZA + 1) | |
1930 | { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE, | |
1931 | insert_rrange, extract_rrange}, | |
126124cc CZ |
1932 | #define R13_EL (RRANGE_EL + 1) |
1933 | { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, | |
1934 | insert_r13el, extract_rrange }, | |
1935 | #define FP_EL (R13_EL + 1) | |
886a2506 NC |
1936 | { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, |
1937 | insert_fpel, extract_fpel }, | |
1938 | #define BLINK_EL (FP_EL + 1) | |
1939 | { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, | |
1940 | insert_blinkel, extract_blinkel }, | |
1941 | #define PCL_EL (BLINK_EL + 1) | |
1942 | { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, | |
1943 | insert_pclel, extract_pclel }, | |
1944 | ||
1945 | /* Fake operand to handle the T flag. */ | |
1946 | #define BRAKET (PCL_EL + 1) | |
1947 | #define BRAKETdup (PCL_EL + 1) | |
1948 | { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 }, | |
1949 | ||
1950 | /* Fake operand to handle the T flag. */ | |
1951 | #define FKT_T (BRAKET + 1) | |
1952 | { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 }, | |
1953 | /* Fake operand to handle the T flag. */ | |
1954 | #define FKT_NT (FKT_T + 1) | |
1955 | { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 }, | |
1956 | ||
1957 | /* UIMM6_20 mask = 00000000000000000000111111000000. */ | |
1958 | #define UIMM6_20 (FKT_NT + 1) | |
1959 | {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20}, | |
1960 | ||
cc07cda6 CZ |
1961 | /* Exactly like the above but used by relaxation. */ |
1962 | #define UIMM6_20R (UIMM6_20 + 1) | |
1963 | {6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, | |
1964 | insert_uimm6_20, extract_uimm6_20}, | |
1965 | ||
886a2506 | 1966 | /* SIMM12_20 mask = 00000000000000000000111111222222. */ |
cc07cda6 | 1967 | #define SIMM12_20 (UIMM6_20R + 1) |
886a2506 NC |
1968 | {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20}, |
1969 | ||
cc07cda6 CZ |
1970 | /* Exactly like the above but used by relaxation. */ |
1971 | #define SIMM12_20R (SIMM12_20 + 1) | |
1972 | {12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL, | |
1973 | insert_simm12_20, extract_simm12_20}, | |
1974 | ||
7179e0e6 CZ |
1975 | /* UIMM12_20 mask = 00000000000000000000111111222222. */ |
1976 | #define UIMM12_20 (SIMM12_20R + 1) | |
1977 | {12, 0, 0, ARC_OPERAND_UNSIGNED, insert_simm12_20, extract_uimm12_20}, | |
1978 | ||
886a2506 | 1979 | /* SIMM3_5_S mask = 0000011100000000. */ |
7179e0e6 | 1980 | #define SIMM3_5_S (UIMM12_20 + 1) |
886a2506 NC |
1981 | {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK, |
1982 | insert_simm3s, extract_simm3s}, | |
1983 | ||
1984 | /* UIMM7_A32_11_S mask = 0000000000011111. */ | |
1985 | #define UIMM7_A32_11_S (SIMM3_5_S + 1) | |
1986 | {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | |
1987 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s, | |
1988 | extract_uimm7_a32_11_s}, | |
1989 | ||
cc07cda6 CZ |
1990 | /* The same as above but used by relaxation. */ |
1991 | #define UIMM7_A32_11R_S (UIMM7_A32_11_S + 1) | |
1992 | {7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | |
1993 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL, | |
1994 | insert_uimm7_a32_11_s, extract_uimm7_a32_11_s}, | |
1995 | ||
886a2506 | 1996 | /* UIMM7_9_S mask = 0000000001111111. */ |
cc07cda6 | 1997 | #define UIMM7_9_S (UIMM7_A32_11R_S + 1) |
886a2506 NC |
1998 | {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s}, |
1999 | ||
2000 | /* UIMM3_13_S mask = 0000000000000111. */ | |
2001 | #define UIMM3_13_S (UIMM7_9_S + 1) | |
2002 | {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s}, | |
2003 | ||
cc07cda6 CZ |
2004 | /* Exactly like the above but used for relaxation. */ |
2005 | #define UIMM3_13R_S (UIMM3_13_S + 1) | |
2006 | {3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, | |
2007 | insert_uimm3_13_s, extract_uimm3_13_s}, | |
2008 | ||
886a2506 | 2009 | /* SIMM11_A32_7_S mask = 0000000111111111. */ |
cc07cda6 | 2010 | #define SIMM11_A32_7_S (UIMM3_13R_S + 1) |
886a2506 NC |
2011 | {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 |
2012 | | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s}, | |
2013 | ||
2014 | /* UIMM6_13_S mask = 0000000002220111. */ | |
2015 | #define UIMM6_13_S (SIMM11_A32_7_S + 1) | |
2016 | {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s}, | |
2017 | /* UIMM5_11_S mask = 0000000000011111. */ | |
2018 | #define UIMM5_11_S (UIMM6_13_S + 1) | |
2019 | {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s, | |
2020 | extract_uimm5_11_s}, | |
2021 | ||
2022 | /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */ | |
2023 | #define SIMM9_A16_8 (UIMM5_11_S + 1) | |
2024 | {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | |
2025 | | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8, | |
2026 | extract_simm9_a16_8}, | |
2027 | ||
2028 | /* UIMM6_8 mask = 00000000000000000000111111000000. */ | |
2029 | #define UIMM6_8 (SIMM9_A16_8 + 1) | |
2030 | {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8}, | |
2031 | ||
2032 | /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */ | |
2033 | #define SIMM21_A16_5 (UIMM6_8 + 1) | |
2034 | {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED | |
50d2740d | 2035 | | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, |
886a2506 NC |
2036 | insert_simm21_a16_5, extract_simm21_a16_5}, |
2037 | ||
2038 | /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */ | |
2039 | #define SIMM25_A16_5 (SIMM21_A16_5 + 1) | |
2040 | {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED | |
2041 | | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, | |
2042 | insert_simm25_a16_5, extract_simm25_a16_5}, | |
2043 | ||
2044 | /* SIMM10_A16_7_S mask = 0000000111111111. */ | |
2045 | #define SIMM10_A16_7_S (SIMM25_A16_5 + 1) | |
2046 | {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | |
2047 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s, | |
2048 | extract_simm10_a16_7_s}, | |
2049 | ||
2050 | #define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1) | |
2051 | {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | |
2052 | | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s}, | |
2053 | ||
2054 | /* SIMM7_A16_10_S mask = 0000000000111111. */ | |
2055 | #define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1) | |
2056 | {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | |
2057 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s, | |
2058 | extract_simm7_a16_10_s}, | |
2059 | ||
2060 | /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */ | |
2061 | #define SIMM21_A32_5 (SIMM7_A16_10_S + 1) | |
2062 | {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | |
2063 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5, | |
2064 | extract_simm21_a32_5}, | |
2065 | ||
2066 | /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */ | |
2067 | #define SIMM25_A32_5 (SIMM21_A32_5 + 1) | |
2068 | {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | |
2069 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5, | |
2070 | extract_simm25_a32_5}, | |
2071 | ||
2072 | /* SIMM13_A32_5_S mask = 0000011111111111. */ | |
2073 | #define SIMM13_A32_5_S (SIMM25_A32_5 + 1) | |
2074 | {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | |
2075 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s, | |
2076 | extract_simm13_a32_5_s}, | |
2077 | ||
2078 | /* SIMM8_A16_9_S mask = 0000000001111111. */ | |
2079 | #define SIMM8_A16_9_S (SIMM13_A32_5_S + 1) | |
2080 | {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | |
2081 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s, | |
2082 | extract_simm8_a16_9_s}, | |
2083 | ||
684d5a10 JEM |
2084 | /* UIMM10_6_S_JLIOFF mask = 0000001111111111. */ |
2085 | #define UIMM10_6_S_JLIOFF (SIMM8_A16_9_S + 1) | |
2086 | {12, 0, BFD_RELOC_ARC_JLI_SECTOFF, ARC_OPERAND_UNSIGNED | |
2087 | | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_uimm10_6_s, | |
2088 | extract_uimm10_6_s}, | |
2089 | ||
886a2506 | 2090 | /* UIMM3_23 mask = 00000000000000000000000111000000. */ |
684d5a10 | 2091 | #define UIMM3_23 (UIMM10_6_S_JLIOFF + 1) |
886a2506 NC |
2092 | {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23}, |
2093 | ||
2094 | /* UIMM10_6_S mask = 0000001111111111. */ | |
2095 | #define UIMM10_6_S (UIMM3_23 + 1) | |
2096 | {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s}, | |
2097 | ||
2098 | /* UIMM6_11_S mask = 0000002200011110. */ | |
2099 | #define UIMM6_11_S (UIMM10_6_S + 1) | |
2100 | {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s}, | |
2101 | ||
2102 | /* SIMM9_8 mask = 00000000111111112000000000000000. */ | |
2103 | #define SIMM9_8 (UIMM6_11_S + 1) | |
2104 | {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE, | |
2105 | insert_simm9_8, extract_simm9_8}, | |
2106 | ||
cc07cda6 CZ |
2107 | /* The same as above but used by relaxation. */ |
2108 | #define SIMM9_8R (SIMM9_8 + 1) | |
2109 | {9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE | |
2110 | | ARC_OPERAND_PCREL, insert_simm9_8, extract_simm9_8}, | |
2111 | ||
886a2506 | 2112 | /* UIMM10_A32_8_S mask = 0000000011111111. */ |
cc07cda6 | 2113 | #define UIMM10_A32_8_S (SIMM9_8R + 1) |
886a2506 NC |
2114 | {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 |
2115 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s, | |
2116 | extract_uimm10_a32_8_s}, | |
2117 | ||
2118 | /* SIMM9_7_S mask = 0000000111111111. */ | |
2119 | #define SIMM9_7_S (UIMM10_A32_8_S + 1) | |
2120 | {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s, | |
2121 | extract_simm9_7_s}, | |
2122 | ||
2123 | /* UIMM6_A16_11_S mask = 0000000000011111. */ | |
2124 | #define UIMM6_A16_11_S (SIMM9_7_S + 1) | |
2125 | {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | |
2126 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s, | |
2127 | extract_uimm6_a16_11_s}, | |
2128 | ||
2129 | /* UIMM5_A32_11_S mask = 0000020000011000. */ | |
2130 | #define UIMM5_A32_11_S (UIMM6_A16_11_S + 1) | |
2131 | {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | |
2132 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s, | |
2133 | extract_uimm5_a32_11_s}, | |
2134 | ||
2135 | /* SIMM11_A32_13_S mask = 0000022222200111. */ | |
2136 | #define SIMM11_A32_13_S (UIMM5_A32_11_S + 1) | |
2137 | {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | |
2138 | | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s}, | |
2139 | ||
2140 | /* UIMM7_13_S mask = 0000000022220111. */ | |
2141 | #define UIMM7_13_S (SIMM11_A32_13_S + 1) | |
2142 | {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s}, | |
2143 | ||
2144 | /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */ | |
2145 | #define UIMM6_A16_21 (UIMM7_13_S + 1) | |
2146 | {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | |
2147 | | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21}, | |
2148 | ||
2149 | /* UIMM7_11_S mask = 0000022200011110. */ | |
2150 | #define UIMM7_11_S (UIMM6_A16_21 + 1) | |
2151 | {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s}, | |
2152 | ||
2153 | /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */ | |
2154 | #define UIMM7_A16_20 (UIMM7_11_S + 1) | |
2155 | {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | |
2156 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20, | |
2157 | extract_uimm7_a16_20}, | |
2158 | ||
2159 | /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */ | |
2160 | #define SIMM13_A16_20 (UIMM7_A16_20 + 1) | |
2161 | {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | |
2162 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20, | |
2163 | extract_simm13_a16_20}, | |
2164 | ||
2165 | /* UIMM8_8_S mask = 0000000011111111. */ | |
2166 | #define UIMM8_8_S (SIMM13_A16_20 + 1) | |
2167 | {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s}, | |
2168 | ||
cc07cda6 CZ |
2169 | /* The same as above but used for relaxation. */ |
2170 | #define UIMM8_8R_S (UIMM8_8_S + 1) | |
2171 | {8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, | |
2172 | insert_uimm8_8_s, extract_uimm8_8_s}, | |
2173 | ||
886a2506 | 2174 | /* W6 mask = 00000000000000000000111111000000. */ |
cc07cda6 | 2175 | #define W6 (UIMM8_8R_S + 1) |
886a2506 NC |
2176 | {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6}, |
2177 | ||
2178 | /* UIMM6_5_S mask = 0000011111100000. */ | |
2179 | #define UIMM6_5_S (W6 + 1) | |
2180 | {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s}, | |
e23e8ebe AB |
2181 | |
2182 | /* ARC NPS400 Support: See comment near head of file. */ | |
2183 | #define NPS_R_DST_3B (UIMM6_5_S + 1) | |
c0c31e91 RZ |
2184 | { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, |
2185 | insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst }, | |
e23e8ebe AB |
2186 | |
2187 | #define NPS_R_SRC1_3B (NPS_R_DST_3B + 1) | |
c0c31e91 RZ |
2188 | { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, |
2189 | insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst }, | |
e23e8ebe AB |
2190 | |
2191 | #define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1) | |
c0c31e91 RZ |
2192 | { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, |
2193 | insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2 }, | |
e23e8ebe AB |
2194 | |
2195 | #define NPS_R_DST (NPS_R_SRC2_3B + 1) | |
2cce10e7 | 2196 | { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL }, |
e23e8ebe AB |
2197 | |
2198 | #define NPS_R_SRC1 (NPS_R_DST + 1) | |
2cce10e7 | 2199 | { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL }, |
e23e8ebe AB |
2200 | |
2201 | #define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1) | |
2202 | { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 }, | |
2203 | ||
2204 | #define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1) | |
2205 | { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 }, | |
2206 | ||
2207 | #define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1) | |
c0c31e91 RZ |
2208 | { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2209 | insert_nps_bitop_size, extract_nps_bitop_size }, | |
e23e8ebe | 2210 | |
820f03ff | 2211 | #define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1) |
c0c31e91 RZ |
2212 | { 5, 0, 0, ARC_OPERAND_UNSIGNED, |
2213 | insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size }, | |
820f03ff AB |
2214 | |
2215 | #define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1) | |
c0c31e91 RZ |
2216 | { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2217 | insert_nps_bitop_size_2b, extract_nps_bitop_size_2b }, | |
820f03ff AB |
2218 | |
2219 | #define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1) | |
c0c31e91 RZ |
2220 | { 8, 0, 0, ARC_OPERAND_UNSIGNED, |
2221 | insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 }, | |
820f03ff AB |
2222 | |
2223 | #define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1) | |
e23e8ebe | 2224 | { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, |
820f03ff | 2225 | |
14053c19 GM |
2226 | #define NPS_SIMM16 (NPS_UIMM16 + 1) |
2227 | { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL }, | |
2228 | ||
2229 | #define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1) | |
c0c31e91 RZ |
2230 | { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2231 | insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 }, | |
4b0c052e AB |
2232 | |
2233 | #define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1) | |
c0c31e91 RZ |
2234 | { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2235 | insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 }, | |
537aefaf AB |
2236 | |
2237 | #define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1) | |
c0c31e91 RZ |
2238 | { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2239 | insert_nps_src2_pos, extract_nps_src2_pos }, | |
537aefaf AB |
2240 | |
2241 | #define NPS_SRC1_POS (NPS_SRC2_POS + 1) | |
c0c31e91 RZ |
2242 | { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2243 | insert_nps_src1_pos, extract_nps_src1_pos }, | |
537aefaf AB |
2244 | |
2245 | #define NPS_ADDB_SIZE (NPS_SRC1_POS + 1) | |
c0c31e91 RZ |
2246 | { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2247 | insert_nps_addb_size, extract_nps_addb_size }, | |
537aefaf AB |
2248 | |
2249 | #define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1) | |
c0c31e91 RZ |
2250 | { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2251 | insert_nps_andb_size, extract_nps_andb_size }, | |
537aefaf AB |
2252 | |
2253 | #define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1) | |
c0c31e91 RZ |
2254 | { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2255 | insert_nps_fxorb_size, extract_nps_fxorb_size }, | |
537aefaf AB |
2256 | |
2257 | #define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1) | |
c0c31e91 RZ |
2258 | { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2259 | insert_nps_wxorb_size, extract_nps_wxorb_size }, | |
537aefaf AB |
2260 | |
2261 | #define NPS_R_XLDST (NPS_WXORB_SIZE + 1) | |
2262 | { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL }, | |
2263 | ||
2264 | #define NPS_DIV_UIMM4 (NPS_R_XLDST + 1) | |
2265 | { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2266 | ||
2267 | #define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1) | |
c0c31e91 RZ |
2268 | { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2269 | insert_nps_qcmp_size, extract_nps_qcmp_size }, | |
537aefaf AB |
2270 | |
2271 | #define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1) | |
2272 | { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 }, | |
2273 | ||
2274 | #define NPS_QCMP_M2 (NPS_QCMP_M1 + 1) | |
2275 | { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 }, | |
2276 | ||
2277 | #define NPS_QCMP_M3 (NPS_QCMP_M2 + 1) | |
2278 | { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 }, | |
2279 | ||
2280 | #define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1) | |
c0c31e91 RZ |
2281 | { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2282 | insert_nps_calc_entry_size, extract_nps_calc_entry_size }, | |
4eb6f892 AB |
2283 | |
2284 | #define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1) | |
c0c31e91 RZ |
2285 | { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, |
2286 | insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst }, | |
4eb6f892 AB |
2287 | |
2288 | #define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1) | |
c0c31e91 RZ |
2289 | { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, |
2290 | insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst }, | |
4eb6f892 AB |
2291 | |
2292 | #define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1) | |
c0c31e91 RZ |
2293 | { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, |
2294 | insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2 }, | |
4eb6f892 AB |
2295 | |
2296 | #define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1) | |
c0c31e91 RZ |
2297 | { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2298 | insert_nps_bitop2_size, extract_nps_bitop2_size }, | |
4eb6f892 AB |
2299 | |
2300 | #define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1) | |
c0c31e91 RZ |
2301 | { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2302 | insert_nps_bitop1_size, extract_nps_bitop1_size }, | |
4eb6f892 AB |
2303 | |
2304 | #define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1) | |
c0c31e91 RZ |
2305 | { 5, 0, 0, ARC_OPERAND_UNSIGNED, |
2306 | insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 }, | |
4eb6f892 AB |
2307 | |
2308 | #define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1) | |
bdfe53e3 | 2309 | { 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, |
4eb6f892 AB |
2310 | |
2311 | #define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1) | |
bdfe53e3 | 2312 | { 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, |
4eb6f892 AB |
2313 | |
2314 | #define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1) | |
2315 | { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2316 | ||
2317 | #define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1) | |
2318 | { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2319 | ||
2320 | #define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1) | |
bdfe53e3 | 2321 | { 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, |
4eb6f892 AB |
2322 | |
2323 | #define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1) | |
2324 | { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2325 | ||
2326 | #define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1) | |
2327 | { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2328 | ||
2329 | #define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1) | |
2330 | { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2331 | ||
bdfe53e3 | 2332 | #define NPS_BITOP_MOD4 (NPS_BITOP_SRC_POS1 + 1) |
c0c31e91 RZ |
2333 | { 2, 0, 0, ARC_OPERAND_UNSIGNED, |
2334 | insert_nps_bitop_mod4, extract_nps_bitop_mod4 }, | |
4eb6f892 | 2335 | |
bdfe53e3 | 2336 | #define NPS_BITOP_MOD3 (NPS_BITOP_MOD4 + 1) |
4eb6f892 AB |
2337 | { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, |
2338 | ||
2339 | #define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1) | |
2340 | { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2341 | ||
2342 | #define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1) | |
2343 | { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2344 | ||
2345 | #define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1) | |
c0c31e91 RZ |
2346 | { 5, 20, 0, ARC_OPERAND_UNSIGNED, |
2347 | insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext }, | |
14053c19 GM |
2348 | |
2349 | #define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1) | |
2350 | { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2351 | ||
2352 | #define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1) | |
c0c31e91 RZ |
2353 | { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2354 | insert_nps_field_size, extract_nps_field_size }, | |
14053c19 GM |
2355 | |
2356 | #define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1) | |
c0c31e91 RZ |
2357 | { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2358 | insert_nps_shift_factor, extract_nps_shift_factor }, | |
14053c19 GM |
2359 | |
2360 | #define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1) | |
c0c31e91 RZ |
2361 | { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2362 | insert_nps_bits_to_scramble, extract_nps_bits_to_scramble }, | |
14053c19 GM |
2363 | |
2364 | #define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1) | |
2365 | { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2366 | ||
2367 | #define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1) | |
c0c31e91 RZ |
2368 | { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2369 | insert_nps_bdlen_max_len, extract_nps_bdlen_max_len }, | |
14053c19 GM |
2370 | |
2371 | #define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1) | |
c0c31e91 RZ |
2372 | { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2373 | insert_nps_min_hofs, extract_nps_min_hofs }, | |
14053c19 GM |
2374 | |
2375 | #define NPS_PSBC (NPS_MIN_HOFS + 1) | |
2376 | { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
9ba75c88 GM |
2377 | |
2378 | #define NPS_DPI_DST (NPS_PSBC + 1) | |
2379 | { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL }, | |
2380 | ||
c0c31e91 RZ |
2381 | /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B |
2382 | but doesn't duplicate an operand. */ | |
9ba75c88 | 2383 | #define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1) |
c0c31e91 RZ |
2384 | { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, |
2385 | insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst }, | |
9ba75c88 GM |
2386 | |
2387 | #define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1) | |
c0c31e91 RZ |
2388 | { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2389 | insert_nps_hash_width, extract_nps_hash_width }, | |
9ba75c88 GM |
2390 | |
2391 | #define NPS_HASH_PERM (NPS_HASH_WIDTH + 1) | |
2392 | { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2393 | ||
2394 | #define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1) | |
2395 | { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2396 | ||
2397 | #define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1) | |
2398 | { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2399 | ||
2400 | #define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1) | |
c0c31e91 RZ |
2401 | { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2402 | insert_nps_hash_len, extract_nps_hash_len }, | |
9ba75c88 GM |
2403 | |
2404 | #define NPS_HASH_OFS (NPS_HASH_LEN + 1) | |
2405 | { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2406 | ||
2407 | #define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1) | |
2408 | { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2409 | ||
2410 | #define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1) | |
2411 | { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2412 | ||
2413 | #define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1) | |
2414 | { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2415 | ||
2416 | #define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1) | |
2417 | { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2418 | ||
2419 | #define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1) | |
c0c31e91 RZ |
2420 | { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2421 | insert_nps_index3, extract_nps_index3 }, | |
db18dbab GM |
2422 | |
2423 | #define COLON (NPS_E4BY_INDEX3 + 1) | |
2424 | { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL }, | |
2425 | ||
2426 | #define NPS_BD (COLON + 1) | |
c0c31e91 RZ |
2427 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, |
2428 | insert_nps_bd, extract_nps_bd }, | |
db18dbab GM |
2429 | |
2430 | #define NPS_JID (NPS_BD + 1) | |
c0c31e91 RZ |
2431 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, |
2432 | insert_nps_jid, extract_nps_jid }, | |
db18dbab GM |
2433 | |
2434 | #define NPS_LBD (NPS_JID + 1) | |
c0c31e91 RZ |
2435 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, |
2436 | insert_nps_lbd, extract_nps_lbd }, | |
db18dbab GM |
2437 | |
2438 | #define NPS_MBD (NPS_LBD + 1) | |
c0c31e91 RZ |
2439 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, |
2440 | insert_nps_mbd, extract_nps_mbd }, | |
db18dbab GM |
2441 | |
2442 | #define NPS_SD (NPS_MBD + 1) | |
c0c31e91 RZ |
2443 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, |
2444 | insert_nps_sd, extract_nps_sd }, | |
db18dbab GM |
2445 | |
2446 | #define NPS_SM (NPS_SD + 1) | |
c0c31e91 RZ |
2447 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, |
2448 | insert_nps_sm, extract_nps_sm }, | |
db18dbab GM |
2449 | |
2450 | #define NPS_XA (NPS_SM + 1) | |
c0c31e91 RZ |
2451 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, |
2452 | insert_nps_xa, extract_nps_xa }, | |
db18dbab GM |
2453 | |
2454 | #define NPS_XD (NPS_XA + 1) | |
c0c31e91 RZ |
2455 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, |
2456 | insert_nps_xd, extract_nps_xd }, | |
db18dbab GM |
2457 | |
2458 | #define NPS_CD (NPS_XD + 1) | |
c0c31e91 RZ |
2459 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, |
2460 | insert_nps_cd, extract_nps_cd }, | |
db18dbab GM |
2461 | |
2462 | #define NPS_CBD (NPS_CD + 1) | |
c0c31e91 RZ |
2463 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, |
2464 | insert_nps_cbd, extract_nps_cbd }, | |
db18dbab GM |
2465 | |
2466 | #define NPS_CJID (NPS_CBD + 1) | |
c0c31e91 RZ |
2467 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, |
2468 | insert_nps_cjid, extract_nps_cjid }, | |
db18dbab GM |
2469 | |
2470 | #define NPS_CLBD (NPS_CJID + 1) | |
c0c31e91 RZ |
2471 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, |
2472 | insert_nps_clbd, extract_nps_clbd }, | |
db18dbab GM |
2473 | |
2474 | #define NPS_CM (NPS_CLBD + 1) | |
c0c31e91 RZ |
2475 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, |
2476 | insert_nps_cm, extract_nps_cm }, | |
db18dbab GM |
2477 | |
2478 | #define NPS_CSD (NPS_CM + 1) | |
c0c31e91 RZ |
2479 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, |
2480 | insert_nps_csd, extract_nps_csd }, | |
db18dbab GM |
2481 | |
2482 | #define NPS_CXA (NPS_CSD + 1) | |
c0c31e91 RZ |
2483 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, |
2484 | insert_nps_cxa, extract_nps_cxa }, | |
db18dbab GM |
2485 | |
2486 | #define NPS_CXD (NPS_CXA + 1) | |
c0c31e91 RZ |
2487 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, |
2488 | insert_nps_cxd, extract_nps_cxd }, | |
db18dbab GM |
2489 | |
2490 | #define NPS_BD_TYPE (NPS_CXD + 1) | |
2491 | { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2492 | ||
2493 | #define NPS_BMU_NUM (NPS_BD_TYPE + 1) | |
c0c31e91 RZ |
2494 | { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2495 | insert_nps_bd_num_buff, extract_nps_bd_num_buff }, | |
db18dbab GM |
2496 | |
2497 | #define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1) | |
2498 | { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2499 | ||
c0c31e91 RZ |
2500 | #define NPS_WHASH_SIZE (NPS_PMU_NXT_DST + 1) |
2501 | { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, | |
2502 | insert_nps_size_16bit, extract_nps_size_16bit }, | |
2503 | ||
2504 | #define NPS_PMU_NUM_JOB (NPS_WHASH_SIZE + 1) | |
2505 | { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, | |
2506 | insert_nps_pmu_num_job, extract_nps_pmu_num_job }, | |
bdfe53e3 | 2507 | |
645d3342 | 2508 | #define NPS_DMA_IMM_ENTRY (NPS_PMU_NUM_JOB + 1) |
c0c31e91 RZ |
2509 | { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2510 | insert_nps_imm_entry, extract_nps_imm_entry }, | |
645d3342 RZ |
2511 | |
2512 | #define NPS_DMA_IMM_OFFSET (NPS_DMA_IMM_ENTRY + 1) | |
c0c31e91 RZ |
2513 | { 4, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2514 | insert_nps_imm_offset, extract_nps_imm_offset }, | |
2515 | ||
2516 | #define NPS_MISC_IMM_SIZE (NPS_DMA_IMM_OFFSET + 1) | |
2517 | { 7, 0, 0, ARC_OPERAND_UNSIGNED , NULL, NULL }, | |
2518 | ||
2519 | #define NPS_MISC_IMM_OFFSET (NPS_MISC_IMM_SIZE + 1) | |
2520 | { 5, 8, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, | |
2521 | insert_nps_misc_imm_offset, extract_nps_misc_imm_offset }, | |
645d3342 | 2522 | |
c0c31e91 RZ |
2523 | #define NPS_R_DST_3B_48 (NPS_MISC_IMM_OFFSET + 1) |
2524 | { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, | |
2525 | insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst }, | |
bdfe53e3 AB |
2526 | |
2527 | #define NPS_R_SRC1_3B_48 (NPS_R_DST_3B_48 + 1) | |
c0c31e91 RZ |
2528 | { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, |
2529 | insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst }, | |
bdfe53e3 AB |
2530 | |
2531 | #define NPS_R_SRC2_3B_48 (NPS_R_SRC1_3B_48 + 1) | |
c0c31e91 RZ |
2532 | { 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, |
2533 | insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2 }, | |
bdfe53e3 AB |
2534 | |
2535 | #define NPS_R_DST_3B_64 (NPS_R_SRC2_3B_48 + 1) | |
c0c31e91 RZ |
2536 | { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, |
2537 | insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst }, | |
bdfe53e3 AB |
2538 | |
2539 | #define NPS_R_SRC1_3B_64 (NPS_R_DST_3B_64 + 1) | |
c0c31e91 RZ |
2540 | { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, |
2541 | insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst }, | |
bdfe53e3 AB |
2542 | |
2543 | #define NPS_R_SRC2_3B_64 (NPS_R_SRC1_3B_64 + 1) | |
c0c31e91 RZ |
2544 | { 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, |
2545 | insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2 }, | |
0d2bcfaf | 2546 | |
5a736821 GM |
2547 | #define NPS_RA_64 (NPS_R_SRC2_3B_64 + 1) |
2548 | { 6, 53, 0, ARC_OPERAND_IR, NULL, NULL }, | |
2549 | ||
2550 | #define NPS_RB_64 (NPS_RA_64 + 1) | |
2551 | { 5, 48, 0, ARC_OPERAND_IR, NULL, NULL }, | |
2552 | ||
2553 | #define NPS_RBdup_64 (NPS_RB_64 + 1) | |
2554 | { 5, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL }, | |
2555 | ||
2556 | #define NPS_RBdouble_64 (NPS_RBdup_64 + 1) | |
c0c31e91 RZ |
2557 | { 10, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, |
2558 | insert_nps_rbdouble_64, extract_nps_rbdouble_64 }, | |
5a736821 GM |
2559 | |
2560 | #define NPS_RC_64 (NPS_RBdouble_64 + 1) | |
2561 | { 5, 43, 0, ARC_OPERAND_IR, NULL, NULL }, | |
2562 | ||
2563 | #define NPS_UIMM16_0_64 (NPS_RC_64 + 1) | |
2564 | { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2565 | ||
2566 | #define NPS_PROTO_SIZE (NPS_UIMM16_0_64 + 1) | |
c0c31e91 RZ |
2567 | { 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, |
2568 | insert_nps_proto_size, extract_nps_proto_size } | |
5a736821 | 2569 | }; |
886a2506 | 2570 | const unsigned arc_num_operands = ARRAY_SIZE (arc_operands); |
0d2bcfaf | 2571 | |
886a2506 NC |
2572 | const unsigned arc_Toperand = FKT_T; |
2573 | const unsigned arc_NToperand = FKT_NT; | |
47b0e7ad | 2574 | |
b99747ae CZ |
2575 | const unsigned char arg_none[] = { 0 }; |
2576 | const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC }; | |
2577 | const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC }; | |
2578 | const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC }; | |
2579 | const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 }; | |
2580 | const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 }; | |
2581 | const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 }; | |
2582 | const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 }; | |
2583 | const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC }; | |
2584 | const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM }; | |
2585 | const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC }; | |
2586 | const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM }; | |
2587 | ||
2588 | const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM }; | |
2589 | const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 }; | |
2590 | const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 }; | |
2591 | ||
2592 | const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 }; | |
2593 | const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup }; | |
2594 | const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup }; | |
2595 | ||
2596 | const unsigned char arg_32bit_rbrc[] = { RB, RC }; | |
2597 | const unsigned char arg_32bit_zarc[] = { ZA, RC }; | |
2598 | const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 }; | |
2599 | const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 }; | |
2600 | const unsigned char arg_32bit_rblimm[] = { RB, LIMM }; | |
2601 | const unsigned char arg_32bit_zalimm[] = { ZA, LIMM }; | |
2602 | ||
2603 | const unsigned char arg_32bit_limmrc[] = { LIMM, RC }; | |
2604 | const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 }; | |
2605 | const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 }; | |
2606 | const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup }; | |
2607 | ||
945e0f82 CZ |
2608 | const unsigned char arg_32bit_rc[] = { RC }; |
2609 | const unsigned char arg_32bit_u6[] = { UIMM6_20 }; | |
2610 | const unsigned char arg_32bit_limm[] = { LIMM }; | |
2611 | ||
886a2506 | 2612 | /* The opcode table. |
0d2bcfaf | 2613 | |
886a2506 | 2614 | The format of the opcode table is: |
0d2bcfaf | 2615 | |
1328504b AB |
2616 | NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }. |
2617 | ||
2618 | The table is organised such that, where possible, all instructions with | |
2619 | the same mnemonic are together in a block. When the assembler searches | |
2620 | for a suitable instruction the entries are checked in table order, so | |
2621 | more specific, or specialised cases should appear earlier in the table. | |
2622 | ||
2623 | As an example, consider two instructions 'add a,b,u6' and 'add | |
2624 | a,b,limm'. The first takes a 6-bit immediate that is encoded within the | |
2625 | 32-bit instruction, while the second takes a 32-bit immediate that is | |
2626 | encoded in a follow-on 32-bit, making the total instruction length | |
2627 | 64-bits. In this case the u6 variant must appear first in the table, as | |
2628 | all u6 immediates could also be encoded using the 'limm' extension, | |
2629 | however, we want to use the shorter instruction wherever possible. | |
2630 | ||
2631 | It is possible though to split instructions with the same mnemonic into | |
2632 | multiple groups. However, the instructions are still checked in table | |
2633 | order, even across groups. The only time that instructions with the | |
2634 | same mnemonic should be split into different groups is when different | |
2635 | variants of the instruction appear in different architectures, in which | |
2636 | case, grouping all instructions from a particular architecture together | |
2637 | might be preferable to merging the instruction into the main instruction | |
2638 | table. | |
2639 | ||
2640 | An example of this split instruction groups can be found with the 'sync' | |
2641 | instruction. The core arc architecture provides a 'sync' instruction, | |
2642 | while the nps instruction set extension provides 'sync.rd' and | |
2643 | 'sync.wr'. The rd/wr flags are instruction flags, not part of the | |
2644 | mnemonic, so we end up with two groups for the sync instruction, the | |
2645 | first within the core arc instruction table, and the second within the | |
2646 | nps extension instructions. */ | |
886a2506 | 2647 | const struct arc_opcode arc_opcodes[] = |
0d2bcfaf | 2648 | { |
886a2506 | 2649 | #include "arc-tbl.h" |
e23e8ebe | 2650 | #include "arc-nps400-tbl.h" |
f2dd8838 | 2651 | #include "arc-ext-tbl.h" |
0d2bcfaf | 2652 | |
b99747ae CZ |
2653 | { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } } |
2654 | }; | |
252b5132 | 2655 | |
886a2506 NC |
2656 | /* List with special cases instructions and the applicable flags. */ |
2657 | const struct arc_flag_special arc_flag_special_cases[] = | |
252b5132 | 2658 | { |
886a2506 NC |
2659 | { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, |
2660 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
2661 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
c0c31e91 RZ |
2662 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, |
2663 | F_NO_T, F_NULL } }, | |
886a2506 NC |
2664 | { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, |
2665 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
2666 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
2667 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
2668 | { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, | |
2669 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
2670 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
2671 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
2672 | { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, | |
2673 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
2674 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
2675 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
2676 | { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, | |
2677 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
2678 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
2679 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
2680 | { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, | |
2681 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
2682 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
2683 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
2684 | { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, | |
2685 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
2686 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
2687 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
2688 | { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } }, | |
2689 | { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } } | |
2690 | }; | |
252b5132 | 2691 | |
886a2506 | 2692 | const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases); |
252b5132 | 2693 | |
886a2506 | 2694 | /* Relocations. */ |
886a2506 NC |
2695 | const struct arc_reloc_equiv_tab arc_reloc_equiv[] = |
2696 | { | |
24b368f8 CZ |
2697 | { "sda", "ld", { F_ASFAKE, F_H1, F_NULL }, |
2698 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, | |
2699 | { "sda", "st", { F_ASFAKE, F_H1, F_NULL }, | |
2700 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, | |
2701 | { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL }, | |
2702 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, | |
2703 | { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL }, | |
2704 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, | |
2705 | ||
2706 | /* Next two entries will cover the undefined behavior ldb/stb with | |
2707 | address scaling. */ | |
2708 | { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL }, | |
2709 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST }, | |
2710 | { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL }, | |
2711 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST}, | |
2712 | ||
2713 | { "sda", "ld", { F_ASFAKE, F_NULL }, | |
2714 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 }, | |
2715 | { "sda", "st", { F_ASFAKE, F_NULL }, | |
2716 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2}, | |
2717 | { "sda", "ldd", { F_ASFAKE, F_NULL }, | |
2718 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 }, | |
2719 | { "sda", "std", { F_ASFAKE, F_NULL }, | |
2720 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2}, | |
886a2506 NC |
2721 | |
2722 | /* Short instructions. */ | |
24b368f8 CZ |
2723 | { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD }, |
2724 | { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 }, | |
2725 | { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 }, | |
2726 | { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 }, | |
2727 | ||
2728 | { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME }, | |
2729 | { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST }, | |
2730 | ||
2731 | { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL, | |
2732 | BFD_RELOC_ARC_S25H_PCREL_PLT }, | |
2733 | { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL, | |
2734 | BFD_RELOC_ARC_S21H_PCREL_PLT }, | |
2735 | { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL, | |
2736 | BFD_RELOC_ARC_S25W_PCREL_PLT }, | |
2737 | { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL, | |
2738 | BFD_RELOC_ARC_S21W_PCREL_PLT }, | |
2739 | ||
2740 | { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 } | |
886a2506 | 2741 | }; |
252b5132 | 2742 | |
886a2506 | 2743 | const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv); |
252b5132 | 2744 | |
886a2506 | 2745 | const struct arc_pseudo_insn arc_pseudo_insns[] = |
0d2bcfaf | 2746 | { |
886a2506 NC |
2747 | { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 }, |
2748 | { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 }, | |
2749 | { BRAKETdup, 1, 0, 4} } }, | |
2750 | { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 }, | |
2751 | { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 }, | |
2752 | { BRAKETdup, 1, 0, 4} } }, | |
2753 | ||
2754 | { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
2755 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2756 | { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
2757 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2758 | { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, | |
2759 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2760 | { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
2761 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2762 | { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
2763 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2764 | ||
2765 | { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
2766 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2767 | { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
2768 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2769 | { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, | |
2770 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2771 | { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
2772 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2773 | { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
2774 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2775 | ||
2776 | { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
2777 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2778 | { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
2779 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2780 | { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, | |
2781 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2782 | { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
2783 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2784 | { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
2785 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2786 | ||
2787 | { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
2788 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2789 | { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
2790 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2791 | { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, | |
2792 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2793 | { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
2794 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2795 | { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
2796 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2797 | }; | |
0d2bcfaf | 2798 | |
886a2506 NC |
2799 | const unsigned arc_num_pseudo_insn = |
2800 | sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns); | |
0d2bcfaf | 2801 | |
886a2506 | 2802 | const struct arc_aux_reg arc_aux_regs[] = |
0d2bcfaf | 2803 | { |
886a2506 | 2804 | #undef DEF |
f36e33da CZ |
2805 | #define DEF(ADDR, CPU, SUBCLASS, NAME) \ |
2806 | { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 }, | |
0d2bcfaf | 2807 | |
886a2506 | 2808 | #include "arc-regs.h" |
0d2bcfaf | 2809 | |
886a2506 NC |
2810 | #undef DEF |
2811 | }; | |
0d2bcfaf | 2812 | |
886a2506 | 2813 | const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs); |
4670103e CZ |
2814 | |
2815 | /* NOTE: The order of this array MUST be consistent with 'enum | |
2816 | arc_rlx_types' located in tc-arc.h! */ | |
2817 | const struct arc_opcode arc_relax_opcodes[] = | |
2818 | { | |
2819 | { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } }, | |
2820 | ||
2821 | /* bl_s s13 11111sssssssssss. */ | |
2822 | { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2823 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, | |
2824 | { SIMM13_A32_5_S }, { 0 }}, | |
2825 | ||
2826 | /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */ | |
2827 | { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2828 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, | |
2829 | { SIMM25_A32_5 }, { C_D }}, | |
2830 | ||
2831 | /* b_s s10 1111000sssssssss. */ | |
2832 | { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2833 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, | |
2834 | { SIMM10_A16_7_S }, { 0 }}, | |
2835 | ||
2836 | /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */ | |
2837 | { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2838 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, | |
2839 | { SIMM25_A16_5 }, { C_D }}, | |
2840 | ||
cc07cda6 | 2841 | /* add_s c,b,u3 01101bbbccc00uuu. */ |
4670103e CZ |
2842 | { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 |
2843 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, | |
cc07cda6 | 2844 | { RC_S, RB_S, UIMM3_13R_S }, { 0 }}, |
4670103e | 2845 | |
cc07cda6 | 2846 | /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */ |
4670103e CZ |
2847 | { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 |
2848 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, | |
cc07cda6 | 2849 | { RA, RB, UIMM6_20R }, { C_F }}, |
4670103e CZ |
2850 | |
2851 | /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */ | |
2852 | { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2853 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, | |
2854 | { RA, RB, LIMM }, { C_F }}, | |
2855 | ||
cc07cda6 | 2856 | /* ld_s c,b,u7 10000bbbcccuuuuu. */ |
4670103e CZ |
2857 | { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 |
2858 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, | |
cc07cda6 | 2859 | { RC_S, BRAKET, RB_S, UIMM7_A32_11R_S, BRAKETdup }, { 0 }}, |
4670103e CZ |
2860 | |
2861 | /* ld<.di><.aa><.x><zz> a,b,s9 | |
cc07cda6 | 2862 | 00010bbbssssssssSBBBDaaZZXAAAAAA. */ |
4670103e CZ |
2863 | { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 |
2864 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, | |
cc07cda6 | 2865 | { RA, BRAKET, RB, SIMM9_8R, BRAKETdup }, |
4670103e CZ |
2866 | { C_ZZ23, C_DI20, C_AA21, C_X25 }}, |
2867 | ||
2868 | /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */ | |
2869 | { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2870 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, | |
2871 | { RA, BRAKET, RB, LIMM, BRAKETdup }, | |
2872 | { C_ZZ13, C_DI16, C_AA8, C_X15 }}, | |
2873 | ||
cc07cda6 | 2874 | /* mov_s b,u8 11011bbbuuuuuuuu. */ |
4670103e CZ |
2875 | { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 |
2876 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, | |
cc07cda6 | 2877 | { RB_S, UIMM8_8R_S }, { 0 }}, |
4670103e | 2878 | |
cc07cda6 | 2879 | /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */ |
4670103e CZ |
2880 | { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 |
2881 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, | |
cc07cda6 | 2882 | { RB, SIMM12_20R }, { C_F }}, |
4670103e CZ |
2883 | |
2884 | /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */ | |
2885 | { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2886 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, | |
2887 | { RB, LIMM }, { C_F }}, | |
2888 | ||
cc07cda6 | 2889 | /* sub_s c,b,u3 01101bbbccc01uuu. */ |
4670103e CZ |
2890 | { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 |
2891 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, | |
cc07cda6 | 2892 | { RC_S, RB_S, UIMM3_13R_S }, { 0 }}, |
4670103e | 2893 | |
cc07cda6 | 2894 | /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */ |
4670103e CZ |
2895 | { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 |
2896 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, | |
cc07cda6 | 2897 | { RA, RB, UIMM6_20R }, { C_F }}, |
4670103e CZ |
2898 | |
2899 | /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */ | |
2900 | { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2901 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, | |
2902 | { RA, RB, LIMM }, { C_F }}, | |
2903 | ||
cc07cda6 | 2904 | /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */ |
4670103e | 2905 | { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM |
cc07cda6 | 2906 | | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20R }, { C_F }}, |
4670103e CZ |
2907 | |
2908 | /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */ | |
2909 | { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | |
2910 | | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }}, | |
2911 | ||
cc07cda6 | 2912 | /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */ |
4670103e CZ |
2913 | { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 |
2914 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, | |
cc07cda6 | 2915 | { RB, UIMM6_20R }, { C_F, C_CC }}, |
4670103e CZ |
2916 | |
2917 | /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */ | |
2918 | { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2919 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, | |
2920 | { RB, LIMM }, { C_F, C_CC }}, | |
2921 | ||
cc07cda6 | 2922 | /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */ |
4670103e CZ |
2923 | { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 |
2924 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, | |
cc07cda6 | 2925 | { RB, RBdup, UIMM6_20R }, { C_F, C_CC }}, |
4670103e CZ |
2926 | |
2927 | /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */ | |
2928 | { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2929 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, | |
2930 | { RB, RBdup, LIMM }, { C_F, C_CC }} | |
2931 | }; | |
2932 | ||
2933 | const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes); | |
4eb6f892 | 2934 | |
bdfe53e3 | 2935 | /* Return length of an opcode in bytes. */ |
06fe285f GM |
2936 | |
2937 | int | |
2938 | arc_opcode_len (const struct arc_opcode *opcode) | |
2939 | { | |
2940 | if (opcode->mask < 0x10000ull) | |
2941 | return 2; | |
bdfe53e3 AB |
2942 | |
2943 | if (opcode->mask < 0x100000000ull) | |
2944 | return 4; | |
2945 | ||
2946 | if (opcode->mask < 0x1000000000000ull) | |
2947 | return 6; | |
2948 | ||
2949 | return 8; | |
06fe285f | 2950 | } |