Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Opcode table for the ARC. |
6f2750fe | 2 | Copyright (C) 1994-2016 Free Software Foundation, Inc. |
886a2506 NC |
3 | |
4 | Contributed by Claudiu Zissulescu (claziss@synopsys.com) | |
bcee8eb8 | 5 | |
9b201bb5 NC |
6 | This file is part of libopcodes. |
7 | ||
8 | This library is free software; you can redistribute it and/or modify | |
252b5132 | 9 | it under the terms of the GNU General Public License as published by |
9b201bb5 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
9b201bb5 NC |
13 | It is distributed in the hope that it will be useful, but WITHOUT |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
252b5132 RH |
17 | |
18 | You should have received a copy of the GNU General Public License | |
0d2bcfaf | 19 | along with this program; if not, write to the Free Software Foundation, |
f4321104 | 20 | Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
252b5132 | 21 | |
5bd67f35 | 22 | #include "sysdep.h" |
252b5132 | 23 | #include <stdio.h> |
d943fe33 | 24 | #include "bfd.h" |
252b5132 | 25 | #include "opcode/arc.h" |
47b0e7ad | 26 | #include "opintl.h" |
886a2506 | 27 | #include "libiberty.h" |
252b5132 | 28 | |
e23e8ebe | 29 | /* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom |
ce440d63 | 30 | instructions. All NPS400 features are built into all ARC target builds as |
e23e8ebe AB |
31 | this reduces the chances that regressions might creep in. */ |
32 | ||
886a2506 NC |
33 | /* Insert RB register into a 32-bit opcode. */ |
34 | static unsigned | |
35 | insert_rb (unsigned insn, | |
36 | int value, | |
37 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 38 | { |
886a2506 NC |
39 | return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12); |
40 | } | |
0d2bcfaf | 41 | |
886a2506 NC |
42 | static int |
43 | extract_rb (unsigned insn ATTRIBUTE_UNUSED, | |
44 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
45 | { | |
46 | int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07); | |
0d2bcfaf | 47 | |
886a2506 NC |
48 | if (value == 0x3e && invalid) |
49 | *invalid = TRUE; /* A limm operand, it should be extracted in a | |
50 | different way. */ | |
252b5132 | 51 | |
886a2506 NC |
52 | return value; |
53 | } | |
252b5132 | 54 | |
886a2506 NC |
55 | static unsigned |
56 | insert_rad (unsigned insn, | |
57 | int value, | |
58 | const char **errmsg ATTRIBUTE_UNUSED) | |
59 | { | |
60 | if (value & 0x01) | |
61 | *errmsg = _("Improper register value."); | |
0d2bcfaf | 62 | |
886a2506 NC |
63 | return insn | (value & 0x3F); |
64 | } | |
0d2bcfaf | 65 | |
886a2506 NC |
66 | static unsigned |
67 | insert_rcd (unsigned insn, | |
68 | int value, | |
69 | const char **errmsg ATTRIBUTE_UNUSED) | |
70 | { | |
71 | if (value & 0x01) | |
72 | *errmsg = _("Improper register value."); | |
0d2bcfaf | 73 | |
886a2506 NC |
74 | return insn | ((value & 0x3F) << 6); |
75 | } | |
252b5132 | 76 | |
886a2506 | 77 | /* Dummy insert ZERO operand function. */ |
252b5132 | 78 | |
886a2506 NC |
79 | static unsigned |
80 | insert_za (unsigned insn, | |
81 | int value, | |
82 | const char **errmsg) | |
83 | { | |
84 | if (value) | |
85 | *errmsg = _("operand is not zero"); | |
86 | return insn; | |
87 | } | |
252b5132 | 88 | |
886a2506 NC |
89 | /* Insert Y-bit in bbit/br instructions. This function is called only |
90 | when solving fixups. */ | |
252b5132 | 91 | |
886a2506 NC |
92 | static unsigned |
93 | insert_Ybit (unsigned insn, | |
94 | int value, | |
95 | const char **errmsg ATTRIBUTE_UNUSED) | |
96 | { | |
97 | if (value > 0) | |
98 | insn |= 0x08; | |
252b5132 | 99 | |
886a2506 NC |
100 | return insn; |
101 | } | |
252b5132 | 102 | |
886a2506 NC |
103 | /* Insert Y-bit in bbit/br instructions. This function is called only |
104 | when solving fixups. */ | |
252b5132 | 105 | |
886a2506 NC |
106 | static unsigned |
107 | insert_NYbit (unsigned insn, | |
108 | int value, | |
109 | const char **errmsg ATTRIBUTE_UNUSED) | |
110 | { | |
111 | if (value < 0) | |
112 | insn |= 0x08; | |
0d2bcfaf | 113 | |
886a2506 NC |
114 | return insn; |
115 | } | |
252b5132 | 116 | |
886a2506 | 117 | /* Insert H register into a 16-bit opcode. */ |
252b5132 | 118 | |
886a2506 NC |
119 | static unsigned |
120 | insert_rhv1 (unsigned insn, | |
121 | int value, | |
122 | const char **errmsg ATTRIBUTE_UNUSED) | |
123 | { | |
124 | return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07); | |
125 | } | |
252b5132 | 126 | |
886a2506 NC |
127 | static int |
128 | extract_rhv1 (unsigned insn ATTRIBUTE_UNUSED, | |
129 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
130 | { | |
02f3be19 | 131 | int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7); |
252b5132 | 132 | |
886a2506 NC |
133 | return value; |
134 | } | |
252b5132 | 135 | |
886a2506 | 136 | /* Insert H register into a 16-bit opcode. */ |
252b5132 | 137 | |
886a2506 NC |
138 | static unsigned |
139 | insert_rhv2 (unsigned insn, | |
140 | int value, | |
141 | const char **errmsg) | |
0d2bcfaf | 142 | { |
886a2506 NC |
143 | if (value == 0x1E) |
144 | *errmsg = | |
145 | _("Register R30 is a limm indicator for this type of instruction."); | |
146 | return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03); | |
147 | } | |
252b5132 | 148 | |
886a2506 NC |
149 | static int |
150 | extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED, | |
151 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
152 | { | |
153 | int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3); | |
0d2bcfaf | 154 | |
886a2506 NC |
155 | return value; |
156 | } | |
0d2bcfaf | 157 | |
886a2506 NC |
158 | static unsigned |
159 | insert_r0 (unsigned insn, | |
160 | int value, | |
161 | const char **errmsg ATTRIBUTE_UNUSED) | |
162 | { | |
163 | if (value != 0) | |
164 | *errmsg = _("Register must be R0."); | |
47b0e7ad NC |
165 | return insn; |
166 | } | |
252b5132 | 167 | |
886a2506 NC |
168 | static int |
169 | extract_r0 (unsigned insn ATTRIBUTE_UNUSED, | |
170 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
252b5132 | 171 | { |
886a2506 | 172 | return 0; |
47b0e7ad | 173 | } |
252b5132 | 174 | |
252b5132 | 175 | |
886a2506 NC |
176 | static unsigned |
177 | insert_r1 (unsigned insn, | |
178 | int value, | |
179 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 180 | { |
886a2506 NC |
181 | if (value != 1) |
182 | *errmsg = _("Register must be R1."); | |
47b0e7ad | 183 | return insn; |
252b5132 RH |
184 | } |
185 | ||
886a2506 NC |
186 | static int |
187 | extract_r1 (unsigned insn ATTRIBUTE_UNUSED, | |
188 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
252b5132 | 189 | { |
886a2506 | 190 | return 1; |
252b5132 RH |
191 | } |
192 | ||
886a2506 NC |
193 | static unsigned |
194 | insert_r2 (unsigned insn, | |
195 | int value, | |
196 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 197 | { |
886a2506 NC |
198 | if (value != 2) |
199 | *errmsg = _("Register must be R2."); | |
47b0e7ad | 200 | return insn; |
252b5132 RH |
201 | } |
202 | ||
886a2506 NC |
203 | static int |
204 | extract_r2 (unsigned insn ATTRIBUTE_UNUSED, | |
205 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
252b5132 | 206 | { |
886a2506 | 207 | return 2; |
252b5132 RH |
208 | } |
209 | ||
886a2506 NC |
210 | static unsigned |
211 | insert_r3 (unsigned insn, | |
212 | int value, | |
213 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 214 | { |
886a2506 NC |
215 | if (value != 3) |
216 | *errmsg = _("Register must be R3."); | |
47b0e7ad | 217 | return insn; |
0d2bcfaf NC |
218 | } |
219 | ||
886a2506 NC |
220 | static int |
221 | extract_r3 (unsigned insn ATTRIBUTE_UNUSED, | |
222 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
0d2bcfaf | 223 | { |
886a2506 | 224 | return 3; |
0d2bcfaf NC |
225 | } |
226 | ||
886a2506 NC |
227 | static unsigned |
228 | insert_sp (unsigned insn, | |
229 | int value, | |
230 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 231 | { |
886a2506 NC |
232 | if (value != 28) |
233 | *errmsg = _("Register must be SP."); | |
252b5132 RH |
234 | return insn; |
235 | } | |
236 | ||
886a2506 NC |
237 | static int |
238 | extract_sp (unsigned insn ATTRIBUTE_UNUSED, | |
239 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
0d2bcfaf | 240 | { |
886a2506 | 241 | return 28; |
0d2bcfaf NC |
242 | } |
243 | ||
886a2506 NC |
244 | static unsigned |
245 | insert_gp (unsigned insn, | |
246 | int value, | |
247 | const char **errmsg ATTRIBUTE_UNUSED) | |
0d2bcfaf | 248 | { |
886a2506 NC |
249 | if (value != 26) |
250 | *errmsg = _("Register must be GP."); | |
251 | return insn; | |
0d2bcfaf NC |
252 | } |
253 | ||
886a2506 NC |
254 | static int |
255 | extract_gp (unsigned insn ATTRIBUTE_UNUSED, | |
256 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
0d2bcfaf | 257 | { |
886a2506 | 258 | return 26; |
0d2bcfaf NC |
259 | } |
260 | ||
886a2506 NC |
261 | static unsigned |
262 | insert_pcl (unsigned insn, | |
263 | int value, | |
264 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 265 | { |
886a2506 NC |
266 | if (value != 63) |
267 | *errmsg = _("Register must be PCL."); | |
252b5132 RH |
268 | return insn; |
269 | } | |
270 | ||
886a2506 NC |
271 | static int |
272 | extract_pcl (unsigned insn ATTRIBUTE_UNUSED, | |
273 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
0d2bcfaf | 274 | { |
886a2506 | 275 | return 63; |
0d2bcfaf NC |
276 | } |
277 | ||
886a2506 NC |
278 | static unsigned |
279 | insert_blink (unsigned insn, | |
280 | int value, | |
281 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 282 | { |
886a2506 NC |
283 | if (value != 31) |
284 | *errmsg = _("Register must be BLINK."); | |
252b5132 RH |
285 | return insn; |
286 | } | |
287 | ||
886a2506 NC |
288 | static int |
289 | extract_blink (unsigned insn ATTRIBUTE_UNUSED, | |
290 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
252b5132 | 291 | { |
886a2506 | 292 | return 31; |
0d2bcfaf NC |
293 | } |
294 | ||
886a2506 NC |
295 | static unsigned |
296 | insert_ilink1 (unsigned insn, | |
297 | int value, | |
298 | const char **errmsg ATTRIBUTE_UNUSED) | |
0d2bcfaf | 299 | { |
886a2506 NC |
300 | if (value != 29) |
301 | *errmsg = _("Register must be ILINK1."); | |
252b5132 RH |
302 | return insn; |
303 | } | |
304 | ||
886a2506 NC |
305 | static int |
306 | extract_ilink1 (unsigned insn ATTRIBUTE_UNUSED, | |
307 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
252b5132 | 308 | { |
886a2506 | 309 | return 29; |
252b5132 RH |
310 | } |
311 | ||
886a2506 NC |
312 | static unsigned |
313 | insert_ilink2 (unsigned insn, | |
314 | int value, | |
315 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 316 | { |
886a2506 NC |
317 | if (value != 30) |
318 | *errmsg = _("Register must be ILINK2."); | |
252b5132 RH |
319 | return insn; |
320 | } | |
321 | ||
886a2506 NC |
322 | static int |
323 | extract_ilink2 (unsigned insn ATTRIBUTE_UNUSED, | |
324 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
325 | { | |
326 | return 30; | |
327 | } | |
252b5132 | 328 | |
886a2506 NC |
329 | static unsigned |
330 | insert_ras (unsigned insn, | |
331 | int value, | |
332 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 333 | { |
886a2506 | 334 | switch (value) |
0d2bcfaf | 335 | { |
886a2506 NC |
336 | case 0: |
337 | case 1: | |
338 | case 2: | |
339 | case 3: | |
340 | insn |= value; | |
341 | break; | |
342 | case 12: | |
343 | case 13: | |
344 | case 14: | |
345 | case 15: | |
346 | insn |= (value - 8); | |
347 | break; | |
348 | default: | |
349 | *errmsg = _("Register must be either r0-r3 or r12-r15."); | |
350 | break; | |
0d2bcfaf | 351 | } |
252b5132 RH |
352 | return insn; |
353 | } | |
252b5132 | 354 | |
886a2506 NC |
355 | static int |
356 | extract_ras (unsigned insn ATTRIBUTE_UNUSED, | |
357 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
47b0e7ad | 358 | { |
886a2506 NC |
359 | int value = insn & 0x07; |
360 | if (value > 3) | |
361 | return (value + 8); | |
362 | else | |
363 | return value; | |
47b0e7ad NC |
364 | } |
365 | ||
886a2506 NC |
366 | static unsigned |
367 | insert_rbs (unsigned insn, | |
368 | int value, | |
369 | const char **errmsg ATTRIBUTE_UNUSED) | |
252b5132 | 370 | { |
886a2506 | 371 | switch (value) |
47b0e7ad | 372 | { |
886a2506 NC |
373 | case 0: |
374 | case 1: | |
375 | case 2: | |
376 | case 3: | |
377 | insn |= value << 8; | |
378 | break; | |
379 | case 12: | |
380 | case 13: | |
381 | case 14: | |
382 | case 15: | |
383 | insn |= ((value - 8)) << 8; | |
384 | break; | |
385 | default: | |
386 | *errmsg = _("Register must be either r0-r3 or r12-r15."); | |
387 | break; | |
47b0e7ad | 388 | } |
886a2506 | 389 | return insn; |
252b5132 RH |
390 | } |
391 | ||
886a2506 NC |
392 | static int |
393 | extract_rbs (unsigned insn ATTRIBUTE_UNUSED, | |
394 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
252b5132 | 395 | { |
886a2506 NC |
396 | int value = (insn >> 8) & 0x07; |
397 | if (value > 3) | |
398 | return (value + 8); | |
399 | else | |
400 | return value; | |
401 | } | |
252b5132 | 402 | |
886a2506 NC |
403 | static unsigned |
404 | insert_rcs (unsigned insn, | |
405 | int value, | |
406 | const char **errmsg ATTRIBUTE_UNUSED) | |
407 | { | |
408 | switch (value) | |
252b5132 | 409 | { |
886a2506 NC |
410 | case 0: |
411 | case 1: | |
412 | case 2: | |
413 | case 3: | |
414 | insn |= value << 5; | |
415 | break; | |
416 | case 12: | |
417 | case 13: | |
418 | case 14: | |
419 | case 15: | |
420 | insn |= ((value - 8)) << 5; | |
421 | break; | |
422 | default: | |
423 | *errmsg = _("Register must be either r0-r3 or r12-r15."); | |
424 | break; | |
252b5132 | 425 | } |
886a2506 NC |
426 | return insn; |
427 | } | |
47b0e7ad | 428 | |
886a2506 NC |
429 | static int |
430 | extract_rcs (unsigned insn ATTRIBUTE_UNUSED, | |
431 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
432 | { | |
433 | int value = (insn >> 5) & 0x07; | |
434 | if (value > 3) | |
435 | return (value + 8); | |
252b5132 | 436 | else |
886a2506 NC |
437 | return value; |
438 | } | |
47b0e7ad | 439 | |
886a2506 NC |
440 | static unsigned |
441 | insert_simm3s (unsigned insn, | |
442 | int value, | |
443 | const char **errmsg ATTRIBUTE_UNUSED) | |
444 | { | |
445 | int tmp = 0; | |
446 | switch (value) | |
47b0e7ad | 447 | { |
886a2506 NC |
448 | case -1: |
449 | tmp = 0x07; | |
47b0e7ad | 450 | break; |
886a2506 NC |
451 | case 0: |
452 | tmp = 0x00; | |
453 | break; | |
454 | case 1: | |
455 | tmp = 0x01; | |
47b0e7ad | 456 | break; |
886a2506 NC |
457 | case 2: |
458 | tmp = 0x02; | |
47b0e7ad | 459 | break; |
886a2506 NC |
460 | case 3: |
461 | tmp = 0x03; | |
462 | break; | |
463 | case 4: | |
464 | tmp = 0x04; | |
465 | break; | |
466 | case 5: | |
467 | tmp = 0x05; | |
468 | break; | |
469 | case 6: | |
470 | tmp = 0x06; | |
471 | break; | |
472 | default: | |
473 | *errmsg = _("Accepted values are from -1 to 6."); | |
47b0e7ad NC |
474 | break; |
475 | } | |
476 | ||
886a2506 NC |
477 | insn |= tmp << 8; |
478 | return insn; | |
47b0e7ad NC |
479 | } |
480 | ||
886a2506 NC |
481 | static int |
482 | extract_simm3s (unsigned insn ATTRIBUTE_UNUSED, | |
483 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
47b0e7ad | 484 | { |
886a2506 NC |
485 | int value = (insn >> 8) & 0x07; |
486 | if (value == 7) | |
487 | return -1; | |
47b0e7ad | 488 | else |
886a2506 | 489 | return value; |
47b0e7ad NC |
490 | } |
491 | ||
886a2506 NC |
492 | static unsigned |
493 | insert_rrange (unsigned insn, | |
494 | int value, | |
495 | const char **errmsg ATTRIBUTE_UNUSED) | |
47b0e7ad | 496 | { |
886a2506 NC |
497 | int reg1 = (value >> 16) & 0xFFFF; |
498 | int reg2 = value & 0xFFFF; | |
499 | if (reg1 != 13) | |
500 | { | |
501 | *errmsg = _("First register of the range should be r13."); | |
502 | return insn; | |
503 | } | |
504 | if (reg2 < 13 || reg2 > 26) | |
505 | { | |
506 | *errmsg = _("Last register of the range doesn't fit."); | |
507 | return insn; | |
508 | } | |
509 | insn |= ((reg2 - 12) & 0x0F) << 1; | |
510 | return insn; | |
47b0e7ad NC |
511 | } |
512 | ||
886a2506 NC |
513 | static int |
514 | extract_rrange (unsigned insn ATTRIBUTE_UNUSED, | |
515 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
516 | { | |
517 | return (insn >> 1) & 0x0F; | |
518 | } | |
47b0e7ad | 519 | |
886a2506 NC |
520 | static unsigned |
521 | insert_fpel (unsigned insn, | |
522 | int value, | |
523 | const char **errmsg ATTRIBUTE_UNUSED) | |
47b0e7ad | 524 | { |
886a2506 NC |
525 | if (value != 27) |
526 | { | |
527 | *errmsg = _("Invalid register number, should be fp."); | |
528 | return insn; | |
529 | } | |
47b0e7ad | 530 | |
886a2506 NC |
531 | insn |= 0x0100; |
532 | return insn; | |
47b0e7ad NC |
533 | } |
534 | ||
886a2506 NC |
535 | static int |
536 | extract_fpel (unsigned insn ATTRIBUTE_UNUSED, | |
537 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
47b0e7ad | 538 | { |
886a2506 | 539 | return (insn & 0x0100) ? 27 : -1; |
47b0e7ad NC |
540 | } |
541 | ||
886a2506 NC |
542 | static unsigned |
543 | insert_blinkel (unsigned insn, | |
544 | int value, | |
545 | const char **errmsg ATTRIBUTE_UNUSED) | |
47b0e7ad | 546 | { |
886a2506 | 547 | if (value != 31) |
47b0e7ad | 548 | { |
886a2506 NC |
549 | *errmsg = _("Invalid register number, should be blink."); |
550 | return insn; | |
47b0e7ad | 551 | } |
47b0e7ad | 552 | |
886a2506 NC |
553 | insn |= 0x0200; |
554 | return insn; | |
47b0e7ad NC |
555 | } |
556 | ||
886a2506 NC |
557 | static int |
558 | extract_blinkel (unsigned insn ATTRIBUTE_UNUSED, | |
559 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
47b0e7ad | 560 | { |
886a2506 NC |
561 | return (insn & 0x0200) ? 31 : -1; |
562 | } | |
47b0e7ad | 563 | |
886a2506 NC |
564 | static unsigned |
565 | insert_pclel (unsigned insn, | |
566 | int value, | |
567 | const char **errmsg ATTRIBUTE_UNUSED) | |
568 | { | |
569 | if (value != 63) | |
47b0e7ad | 570 | { |
886a2506 NC |
571 | *errmsg = _("Invalid register number, should be pcl."); |
572 | return insn; | |
47b0e7ad | 573 | } |
47b0e7ad | 574 | |
886a2506 NC |
575 | insn |= 0x0400; |
576 | return insn; | |
577 | } | |
47b0e7ad | 578 | |
886a2506 NC |
579 | static int |
580 | extract_pclel (unsigned insn ATTRIBUTE_UNUSED, | |
581 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
47b0e7ad | 582 | { |
886a2506 | 583 | return (insn & 0x0400) ? 63 : -1; |
47b0e7ad | 584 | } |
47b0e7ad | 585 | |
886a2506 NC |
586 | #define INSERT_W6 |
587 | /* mask = 00000000000000000000111111000000 | |
588 | insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */ | |
589 | static unsigned | |
590 | insert_w6 (unsigned insn ATTRIBUTE_UNUSED, | |
591 | int value ATTRIBUTE_UNUSED, | |
592 | const char **errmsg ATTRIBUTE_UNUSED) | |
47b0e7ad | 593 | { |
886a2506 | 594 | insn |= ((value >> 0) & 0x003f) << 6; |
47b0e7ad | 595 | |
886a2506 NC |
596 | return insn; |
597 | } | |
47b0e7ad | 598 | |
886a2506 NC |
599 | #define EXTRACT_W6 |
600 | /* mask = 00000000000000000000111111000000. */ | |
601 | static int | |
602 | extract_w6 (unsigned insn ATTRIBUTE_UNUSED, | |
603 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
47b0e7ad | 604 | { |
886a2506 | 605 | unsigned value = 0; |
47b0e7ad | 606 | |
886a2506 | 607 | value |= ((insn >> 6) & 0x003f) << 0; |
47b0e7ad | 608 | |
886a2506 NC |
609 | return value; |
610 | } | |
47b0e7ad | 611 | |
886a2506 NC |
612 | #define INSERT_G_S |
613 | /* mask = 0000011100022000 | |
614 | insn = 01000ggghhhGG0HH. */ | |
615 | static unsigned | |
616 | insert_g_s (unsigned insn ATTRIBUTE_UNUSED, | |
617 | int value ATTRIBUTE_UNUSED, | |
618 | const char **errmsg ATTRIBUTE_UNUSED) | |
47b0e7ad | 619 | { |
886a2506 NC |
620 | insn |= ((value >> 0) & 0x0007) << 8; |
621 | insn |= ((value >> 3) & 0x0003) << 3; | |
252b5132 | 622 | |
886a2506 NC |
623 | return insn; |
624 | } | |
252b5132 | 625 | |
886a2506 NC |
626 | #define EXTRACT_G_S |
627 | /* mask = 0000011100022000. */ | |
628 | static int | |
629 | extract_g_s (unsigned insn ATTRIBUTE_UNUSED, | |
630 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
631 | { | |
632 | int value = 0; | |
252b5132 | 633 | |
886a2506 NC |
634 | value |= ((insn >> 8) & 0x0007) << 0; |
635 | value |= ((insn >> 3) & 0x0003) << 3; | |
252b5132 | 636 | |
886a2506 NC |
637 | /* Extend the sign. */ |
638 | int signbit = 1 << (6 - 1); | |
639 | value = (value ^ signbit) - signbit; | |
252b5132 | 640 | |
886a2506 | 641 | return value; |
252b5132 RH |
642 | } |
643 | ||
e23e8ebe AB |
644 | /* ARC NPS400 Support: See comment near head of file. */ |
645 | static unsigned | |
646 | insert_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED, | |
647 | int value ATTRIBUTE_UNUSED, | |
648 | const char **errmsg ATTRIBUTE_UNUSED) | |
649 | { | |
650 | switch (value) | |
651 | { | |
652 | case 0: | |
653 | case 1: | |
654 | case 2: | |
655 | case 3: | |
656 | insn |= value << 24; | |
657 | break; | |
658 | case 12: | |
659 | case 13: | |
660 | case 14: | |
661 | case 15: | |
662 | insn |= (value - 8) << 24; | |
663 | break; | |
664 | default: | |
665 | *errmsg = _("Register must be either r0-r3 or r12-r15."); | |
666 | break; | |
667 | } | |
668 | return insn; | |
669 | } | |
670 | ||
671 | static int | |
672 | extract_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED, | |
673 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
674 | { | |
675 | int value = (insn >> 24) & 0x07; | |
676 | if (value > 3) | |
677 | return (value + 8); | |
678 | else | |
679 | return value; | |
680 | } | |
681 | ||
4eb6f892 AB |
682 | static unsigned |
683 | insert_nps_3bit_dst_short (unsigned insn ATTRIBUTE_UNUSED, | |
684 | int value ATTRIBUTE_UNUSED, | |
685 | const char **errmsg ATTRIBUTE_UNUSED) | |
686 | { | |
687 | switch (value) | |
688 | { | |
689 | case 0: | |
690 | case 1: | |
691 | case 2: | |
692 | case 3: | |
693 | insn |= value << 8; | |
694 | break; | |
695 | case 12: | |
696 | case 13: | |
697 | case 14: | |
698 | case 15: | |
699 | insn |= (value - 8) << 8; | |
700 | break; | |
701 | default: | |
702 | *errmsg = _("Register must be either r0-r3 or r12-r15."); | |
703 | break; | |
704 | } | |
705 | return insn; | |
706 | } | |
707 | ||
708 | static int | |
709 | extract_nps_3bit_dst_short (unsigned insn ATTRIBUTE_UNUSED, | |
710 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
711 | { | |
712 | int value = (insn >> 8) & 0x07; | |
713 | if (value > 3) | |
714 | return (value + 8); | |
715 | else | |
716 | return value; | |
717 | } | |
718 | ||
e23e8ebe AB |
719 | static unsigned |
720 | insert_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED, | |
721 | int value ATTRIBUTE_UNUSED, | |
722 | const char **errmsg ATTRIBUTE_UNUSED) | |
723 | { | |
724 | switch (value) | |
725 | { | |
726 | case 0: | |
727 | case 1: | |
728 | case 2: | |
729 | case 3: | |
730 | insn |= value << 21; | |
731 | break; | |
732 | case 12: | |
733 | case 13: | |
734 | case 14: | |
735 | case 15: | |
736 | insn |= (value - 8) << 21; | |
737 | break; | |
738 | default: | |
739 | *errmsg = _("Register must be either r0-r3 or r12-r15."); | |
740 | break; | |
741 | } | |
742 | return insn; | |
743 | } | |
744 | ||
745 | static int | |
746 | extract_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED, | |
747 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
748 | { | |
749 | int value = (insn >> 21) & 0x07; | |
750 | if (value > 3) | |
751 | return (value + 8); | |
752 | else | |
753 | return value; | |
754 | } | |
755 | ||
4eb6f892 AB |
756 | static unsigned |
757 | insert_nps_3bit_src2_short (unsigned insn ATTRIBUTE_UNUSED, | |
758 | int value ATTRIBUTE_UNUSED, | |
759 | const char **errmsg ATTRIBUTE_UNUSED) | |
760 | { | |
761 | switch (value) | |
762 | { | |
763 | case 0: | |
764 | case 1: | |
765 | case 2: | |
766 | case 3: | |
767 | insn |= value << 5; | |
768 | break; | |
769 | case 12: | |
770 | case 13: | |
771 | case 14: | |
772 | case 15: | |
773 | insn |= (value - 8) << 5; | |
774 | break; | |
775 | default: | |
776 | *errmsg = _("Register must be either r0-r3 or r12-r15."); | |
777 | break; | |
778 | } | |
779 | return insn; | |
780 | } | |
781 | ||
782 | static int | |
783 | extract_nps_3bit_src2_short (unsigned insn ATTRIBUTE_UNUSED, | |
784 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
785 | { | |
786 | int value = (insn >> 5) & 0x07; | |
787 | if (value > 3) | |
788 | return (value + 8); | |
789 | else | |
790 | return value; | |
791 | } | |
792 | ||
820f03ff AB |
793 | static unsigned |
794 | insert_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED, | |
795 | int value ATTRIBUTE_UNUSED, | |
796 | const char **errmsg ATTRIBUTE_UNUSED) | |
797 | { | |
798 | switch (value) | |
799 | { | |
800 | case 1: | |
801 | value = 0; | |
802 | break; | |
803 | case 2: | |
804 | value = 1; | |
805 | break; | |
806 | case 4: | |
807 | value = 2; | |
808 | break; | |
809 | case 8: | |
810 | value = 3; | |
811 | break; | |
812 | default: | |
813 | value = 0; | |
814 | *errmsg = _("Invalid size, should be 1, 2, 4, or 8."); | |
815 | break; | |
816 | } | |
817 | ||
818 | insn |= value << 10; | |
819 | return insn; | |
820 | } | |
821 | ||
822 | static int | |
823 | extract_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED, | |
824 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
825 | { | |
826 | return 1 << ((insn >> 10) & 0x3); | |
827 | } | |
828 | ||
829 | static unsigned | |
830 | insert_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED, | |
831 | int value ATTRIBUTE_UNUSED, | |
832 | const char **errmsg ATTRIBUTE_UNUSED) | |
833 | { | |
834 | insn |= ((value >> 5) & 7) << 12; | |
835 | insn |= (value & 0x1f); | |
836 | return insn; | |
837 | } | |
838 | ||
839 | static int | |
840 | extract_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED, | |
841 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
842 | { | |
843 | return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f); | |
844 | } | |
845 | ||
846 | static unsigned | |
847 | insert_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED, | |
848 | int value ATTRIBUTE_UNUSED, | |
849 | const char **errmsg ATTRIBUTE_UNUSED) | |
850 | { | |
851 | switch (value) | |
852 | { | |
853 | case 1: | |
854 | case 2: | |
855 | case 4: | |
856 | break; | |
857 | ||
858 | default: | |
859 | *errmsg = _("invalid immediate, must be 1, 2, or 4"); | |
860 | value = 0; | |
861 | } | |
862 | ||
863 | insn |= (value << 6); | |
864 | return insn; | |
865 | } | |
866 | ||
867 | static int | |
868 | extract_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED, | |
869 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
870 | { | |
871 | return (insn >> 6) & 0x3f; | |
872 | } | |
873 | ||
874 | static unsigned | |
875 | insert_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED, | |
876 | int value ATTRIBUTE_UNUSED, | |
877 | const char **errmsg ATTRIBUTE_UNUSED) | |
878 | { | |
879 | insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10)); | |
880 | return insn; | |
881 | } | |
882 | ||
883 | static int | |
884 | extract_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED, | |
885 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
886 | { | |
887 | return (insn & 0x1f); | |
888 | } | |
889 | ||
4b0c052e AB |
890 | static unsigned |
891 | insert_nps_cmem_uimm16 (unsigned insn ATTRIBUTE_UNUSED, | |
892 | int value ATTRIBUTE_UNUSED, | |
893 | const char **errmsg ATTRIBUTE_UNUSED) | |
894 | { | |
895 | int top = (value >> 16) & 0xffff; | |
896 | if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE) | |
897 | *errmsg = _("invalid value for CMEM ld/st immediate"); | |
898 | insn |= (value & 0xffff); | |
899 | return insn; | |
900 | } | |
901 | ||
902 | static int | |
903 | extract_nps_cmem_uimm16 (unsigned insn ATTRIBUTE_UNUSED, | |
904 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
905 | { | |
906 | return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff); | |
907 | } | |
908 | ||
537aefaf AB |
909 | #define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \ |
910 | static unsigned \ | |
911 | insert_nps_##NAME##_pos (unsigned insn ATTRIBUTE_UNUSED, \ | |
912 | int value ATTRIBUTE_UNUSED, \ | |
913 | const char **errmsg ATTRIBUTE_UNUSED) \ | |
914 | { \ | |
915 | switch (value) \ | |
916 | { \ | |
917 | case 0: \ | |
918 | case 8: \ | |
919 | case 16: \ | |
920 | case 24: \ | |
921 | value = value / 8; \ | |
922 | break; \ | |
923 | default: \ | |
924 | *errmsg = _("Invalid position, should be 0, 8, 16, or 24."); \ | |
925 | value = 0; \ | |
926 | } \ | |
927 | insn |= (value << SHIFT); \ | |
928 | return insn; \ | |
929 | } \ | |
930 | \ | |
931 | static int \ | |
932 | extract_nps_##NAME##_pos (unsigned insn ATTRIBUTE_UNUSED, \ | |
933 | bfd_boolean * invalid ATTRIBUTE_UNUSED) \ | |
934 | { \ | |
935 | return ((insn >> SHIFT) & 0x3) * 8; \ | |
936 | } | |
937 | ||
938 | MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12) | |
939 | MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10) | |
940 | ||
9ba75c88 | 941 | #define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT)\ |
537aefaf | 942 | static unsigned \ |
9ba75c88 GM |
943 | insert_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \ |
944 | int value ATTRIBUTE_UNUSED, \ | |
945 | const char **errmsg ATTRIBUTE_UNUSED) \ | |
537aefaf | 946 | { \ |
9ba75c88 | 947 | if (value < LOWER || value > UPPER) \ |
537aefaf AB |
948 | { \ |
949 | *errmsg = _("Invalid size, value must be " \ | |
950 | #LOWER " to " #UPPER "."); \ | |
951 | return insn; \ | |
952 | } \ | |
953 | value -= BIAS; \ | |
954 | insn |= (value << SHIFT); \ | |
955 | return insn; \ | |
956 | } \ | |
957 | \ | |
958 | static int \ | |
9ba75c88 GM |
959 | extract_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \ |
960 | bfd_boolean * invalid ATTRIBUTE_UNUSED) \ | |
537aefaf AB |
961 | { \ |
962 | return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \ | |
963 | } | |
964 | ||
db18dbab GM |
965 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5) |
966 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5) | |
967 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5) | |
968 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5) | |
969 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10) | |
970 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9) | |
971 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20) | |
972 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25) | |
973 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6) | |
974 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2) | |
975 | MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0) | |
537aefaf AB |
976 | |
977 | static int | |
978 | extract_nps_qcmp_m3 (unsigned insn ATTRIBUTE_UNUSED, | |
979 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
980 | { | |
981 | int m3 = (insn >> 5) & 0xf; | |
982 | if (m3 == 0xf) | |
983 | *invalid = TRUE; | |
984 | return m3; | |
985 | } | |
986 | ||
987 | static int | |
988 | extract_nps_qcmp_m2 (unsigned insn ATTRIBUTE_UNUSED, | |
989 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
990 | { | |
991 | bfd_boolean tmp_invalid = FALSE; | |
992 | int m2 = (insn >> 15) & 0x1; | |
993 | int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid); | |
994 | ||
995 | if (m2 == 0 && m3 == 0xf) | |
996 | *invalid = TRUE; | |
997 | return m2; | |
998 | } | |
999 | ||
1000 | static int | |
1001 | extract_nps_qcmp_m1 (unsigned insn ATTRIBUTE_UNUSED, | |
1002 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
1003 | { | |
1004 | bfd_boolean tmp_invalid = FALSE; | |
1005 | int m1 = (insn >> 14) & 0x1; | |
1006 | int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid); | |
1007 | int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid); | |
1008 | ||
1009 | if (m1 == 0 && m2 == 0 && m3 == 0xf) | |
1010 | *invalid = TRUE; | |
1011 | return m1; | |
1012 | } | |
1013 | ||
1014 | static unsigned | |
1015 | insert_nps_calc_entry_size (unsigned insn ATTRIBUTE_UNUSED, | |
1016 | int value ATTRIBUTE_UNUSED, | |
1017 | const char **errmsg ATTRIBUTE_UNUSED) | |
1018 | { | |
1019 | unsigned pwr; | |
1020 | ||
1021 | if (value < 1 || value > 256) | |
1022 | { | |
1023 | *errmsg = _("value out of range 1 - 256"); | |
1024 | return 0; | |
1025 | } | |
1026 | ||
1027 | for (pwr = 0; (value & 1) == 0; value >>= 1) | |
1028 | ++pwr; | |
1029 | ||
1030 | if (value != 1) | |
1031 | { | |
1032 | *errmsg = _("value must be power of 2"); | |
1033 | return 0; | |
1034 | } | |
1035 | ||
1036 | return insn | (pwr << 8); | |
1037 | } | |
1038 | ||
1039 | static int | |
1040 | extract_nps_calc_entry_size (unsigned insn ATTRIBUTE_UNUSED, | |
1041 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
1042 | { | |
1043 | unsigned entry_size = (insn >> 8) & 0xf; | |
1044 | return 1 << entry_size; | |
1045 | } | |
1046 | ||
4eb6f892 AB |
1047 | static unsigned |
1048 | insert_nps_bitop_mod4_msb (unsigned insn ATTRIBUTE_UNUSED, | |
1049 | int value ATTRIBUTE_UNUSED, | |
1050 | const char **errmsg ATTRIBUTE_UNUSED) | |
1051 | { | |
1052 | return insn | ((value & 0x2) << 30); | |
1053 | } | |
1054 | ||
1055 | static int | |
1056 | extract_nps_bitop_mod4_msb (unsigned insn ATTRIBUTE_UNUSED, | |
1057 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
1058 | { | |
1059 | return (insn >> 30) & 0x2; | |
1060 | } | |
1061 | ||
1062 | static unsigned | |
1063 | insert_nps_bitop_mod4_lsb (unsigned insn ATTRIBUTE_UNUSED, | |
1064 | int value ATTRIBUTE_UNUSED, | |
1065 | const char **errmsg ATTRIBUTE_UNUSED) | |
1066 | { | |
1067 | return insn | ((value & 0x1) << 15); | |
1068 | } | |
1069 | ||
1070 | static int | |
1071 | extract_nps_bitop_mod4_lsb (unsigned insn ATTRIBUTE_UNUSED, | |
1072 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
1073 | { | |
1074 | return (insn >> 15) & 0x1; | |
1075 | } | |
1076 | ||
1077 | static unsigned | |
1078 | insert_nps_bitop_dst_pos3_pos4 (unsigned insn ATTRIBUTE_UNUSED, | |
1079 | int value ATTRIBUTE_UNUSED, | |
1080 | const char **errmsg ATTRIBUTE_UNUSED) | |
1081 | { | |
1082 | return insn | (value << 10) | (value << 5); | |
1083 | } | |
1084 | ||
1085 | static int | |
1086 | extract_nps_bitop_dst_pos3_pos4 (unsigned insn ATTRIBUTE_UNUSED, | |
1087 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
1088 | { | |
1089 | if (((insn >> 10) & 0x1f) != ((insn >> 5) & 0x1f)) | |
1090 | *invalid = TRUE; | |
1091 | return ((insn >> 5) & 0x1f); | |
1092 | } | |
1093 | ||
1094 | static unsigned | |
1095 | insert_nps_bitop_ins_ext (unsigned insn ATTRIBUTE_UNUSED, | |
1096 | int value ATTRIBUTE_UNUSED, | |
1097 | const char **errmsg ATTRIBUTE_UNUSED) | |
1098 | { | |
1099 | if (value < 0 || value > 28) | |
1100 | *errmsg = _("Value must be in the range 0 to 28"); | |
1101 | return insn | (value << 20); | |
1102 | } | |
1103 | ||
1104 | static int | |
1105 | extract_nps_bitop_ins_ext (unsigned insn ATTRIBUTE_UNUSED, | |
1106 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
1107 | { | |
1108 | int value = (insn >> 20) & 0x1f; | |
1109 | if (value > 28) | |
1110 | *invalid = TRUE; | |
1111 | return value; | |
1112 | } | |
1113 | ||
14053c19 GM |
1114 | #define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \ |
1115 | static unsigned \ | |
1116 | insert_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \ | |
1117 | int value ATTRIBUTE_UNUSED, \ | |
1118 | const char **errmsg ATTRIBUTE_UNUSED) \ | |
1119 | { \ | |
1120 | if (value < 1 || value > UPPER) \ | |
1121 | *errmsg = _("Value must be in the range 1 to " #UPPER); \ | |
1122 | if (value == UPPER) \ | |
1123 | value = 0; \ | |
1124 | return insn | (value << SHIFT); \ | |
1125 | } \ | |
1126 | \ | |
1127 | static int \ | |
1128 | extract_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \ | |
1129 | bfd_boolean * invalid ATTRIBUTE_UNUSED) \ | |
1130 | { \ | |
1131 | int value = (insn >> SHIFT) & ((1 << BITS) - 1); \ | |
1132 | if (value == 0) \ | |
1133 | value = UPPER; \ | |
1134 | return value; \ | |
1135 | } | |
1136 | ||
db18dbab GM |
1137 | MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3) |
1138 | MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3) | |
1139 | MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3) | |
1140 | MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8) | |
1141 | MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3) | |
1142 | MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2) | |
14053c19 GM |
1143 | |
1144 | static unsigned | |
1145 | insert_nps_min_hofs (unsigned insn ATTRIBUTE_UNUSED, | |
1146 | int value ATTRIBUTE_UNUSED, | |
1147 | const char **errmsg ATTRIBUTE_UNUSED) | |
1148 | { | |
1149 | if (value < 0 || value > 240) | |
1150 | *errmsg = _("Value must be in the range 0 to 240"); | |
1151 | if ((value % 16) != 0) | |
1152 | *errmsg = _("Value must be a multiple of 16"); | |
1153 | value = value / 16; | |
1154 | return insn | (value << 6); | |
1155 | } | |
1156 | ||
1157 | static int | |
1158 | extract_nps_min_hofs (unsigned insn ATTRIBUTE_UNUSED, | |
1159 | bfd_boolean * invalid ATTRIBUTE_UNUSED) | |
1160 | { | |
1161 | int value = (insn >> 6) & 0xF; | |
1162 | return value * 16; | |
1163 | } | |
1164 | ||
db18dbab GM |
1165 | #define MAKE_INSERT_NPS_ADDRTYPE(NAME,VALUE) \ |
1166 | static unsigned \ | |
1167 | insert_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \ | |
1168 | int value ATTRIBUTE_UNUSED, \ | |
1169 | const char **errmsg ATTRIBUTE_UNUSED) \ | |
1170 | { \ | |
1171 | if (value != ARC_NPS400_ADDRTYPE_##VALUE) \ | |
1172 | *errmsg = _("Invalid address type for operand"); \ | |
1173 | return insn; \ | |
1174 | } \ | |
1175 | \ | |
1176 | static int \ | |
1177 | extract_nps_##NAME (unsigned insn ATTRIBUTE_UNUSED, \ | |
1178 | bfd_boolean * invalid ATTRIBUTE_UNUSED) \ | |
1179 | { \ | |
1180 | return ARC_NPS400_ADDRTYPE_##VALUE; \ | |
1181 | } | |
1182 | ||
1183 | MAKE_INSERT_NPS_ADDRTYPE (bd, BD) | |
1184 | MAKE_INSERT_NPS_ADDRTYPE (jid, JID) | |
1185 | MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD) | |
1186 | MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD) | |
1187 | MAKE_INSERT_NPS_ADDRTYPE (sd, SD) | |
1188 | MAKE_INSERT_NPS_ADDRTYPE (sm, SM) | |
1189 | MAKE_INSERT_NPS_ADDRTYPE (xa, XA) | |
1190 | MAKE_INSERT_NPS_ADDRTYPE (xd, XD) | |
1191 | MAKE_INSERT_NPS_ADDRTYPE (cd, CD) | |
1192 | MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD) | |
1193 | MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID) | |
1194 | MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD) | |
1195 | MAKE_INSERT_NPS_ADDRTYPE (cm, CM) | |
1196 | MAKE_INSERT_NPS_ADDRTYPE (csd, CSD) | |
1197 | MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA) | |
1198 | MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD) | |
1199 | ||
1200 | ||
886a2506 NC |
1201 | /* Include the generic extract/insert functions. Order is important |
1202 | as some of the functions present in the .h may be disabled via | |
1203 | defines. */ | |
1204 | #include "arc-fxi.h" | |
252b5132 | 1205 | |
886a2506 | 1206 | /* The flag operands table. |
252b5132 | 1207 | |
886a2506 NC |
1208 | The format of the table is |
1209 | NAME CODE BITS SHIFT FAVAIL. */ | |
1210 | const struct arc_flag_operand arc_flag_operands[] = | |
1211 | { | |
1212 | #define F_NULL 0 | |
1213 | { 0, 0, 0, 0, 0}, | |
1214 | #define F_ALWAYS (F_NULL + 1) | |
1215 | { "al", 0, 0, 0, 0 }, | |
1216 | #define F_RA (F_ALWAYS + 1) | |
1217 | { "ra", 0, 0, 0, 0 }, | |
1218 | #define F_EQUAL (F_RA + 1) | |
1219 | { "eq", 1, 5, 0, 1 }, | |
1220 | #define F_ZERO (F_EQUAL + 1) | |
1221 | { "z", 1, 5, 0, 0 }, | |
1222 | #define F_NOTEQUAL (F_ZERO + 1) | |
1223 | { "ne", 2, 5, 0, 1 }, | |
1224 | #define F_NOTZERO (F_NOTEQUAL + 1) | |
1225 | { "nz", 2, 5, 0, 0 }, | |
1226 | #define F_POZITIVE (F_NOTZERO + 1) | |
1227 | { "p", 3, 5, 0, 1 }, | |
1228 | #define F_PL (F_POZITIVE + 1) | |
1229 | { "pl", 3, 5, 0, 0 }, | |
1230 | #define F_NEGATIVE (F_PL + 1) | |
1231 | { "n", 4, 5, 0, 1 }, | |
1232 | #define F_MINUS (F_NEGATIVE + 1) | |
1233 | { "mi", 4, 5, 0, 0 }, | |
1234 | #define F_CARRY (F_MINUS + 1) | |
1235 | { "c", 5, 5, 0, 1 }, | |
1236 | #define F_CARRYSET (F_CARRY + 1) | |
1237 | { "cs", 5, 5, 0, 0 }, | |
1238 | #define F_LOWER (F_CARRYSET + 1) | |
1239 | { "lo", 5, 5, 0, 0 }, | |
1240 | #define F_CARRYCLR (F_LOWER + 1) | |
1241 | { "cc", 6, 5, 0, 0 }, | |
1242 | #define F_NOTCARRY (F_CARRYCLR + 1) | |
1243 | { "nc", 6, 5, 0, 1 }, | |
1244 | #define F_HIGHER (F_NOTCARRY + 1) | |
1245 | { "hs", 6, 5, 0, 0 }, | |
1246 | #define F_OVERFLOWSET (F_HIGHER + 1) | |
1247 | { "vs", 7, 5, 0, 0 }, | |
1248 | #define F_OVERFLOW (F_OVERFLOWSET + 1) | |
1249 | { "v", 7, 5, 0, 1 }, | |
1250 | #define F_NOTOVERFLOW (F_OVERFLOW + 1) | |
1251 | { "nv", 8, 5, 0, 1 }, | |
1252 | #define F_OVERFLOWCLR (F_NOTOVERFLOW + 1) | |
1253 | { "vc", 8, 5, 0, 0 }, | |
1254 | #define F_GT (F_OVERFLOWCLR + 1) | |
1255 | { "gt", 9, 5, 0, 1 }, | |
1256 | #define F_GE (F_GT + 1) | |
1257 | { "ge", 10, 5, 0, 1 }, | |
1258 | #define F_LT (F_GE + 1) | |
1259 | { "lt", 11, 5, 0, 1 }, | |
1260 | #define F_LE (F_LT + 1) | |
1261 | { "le", 12, 5, 0, 1 }, | |
1262 | #define F_HI (F_LE + 1) | |
1263 | { "hi", 13, 5, 0, 1 }, | |
1264 | #define F_LS (F_HI + 1) | |
1265 | { "ls", 14, 5, 0, 1 }, | |
1266 | #define F_PNZ (F_LS + 1) | |
1267 | { "pnz", 15, 5, 0, 1 }, | |
1268 | ||
1269 | /* FLAG. */ | |
1270 | #define F_FLAG (F_PNZ + 1) | |
1271 | { "f", 1, 1, 15, 1 }, | |
1272 | #define F_FFAKE (F_FLAG + 1) | |
1273 | { "f", 0, 0, 0, 1 }, | |
1274 | ||
1275 | /* Delay slot. */ | |
1276 | #define F_ND (F_FFAKE + 1) | |
1277 | { "nd", 0, 1, 5, 0 }, | |
1278 | #define F_D (F_ND + 1) | |
1279 | { "d", 1, 1, 5, 1 }, | |
1280 | #define F_DFAKE (F_D + 1) | |
1281 | { "d", 0, 0, 0, 1 }, | |
2b848ebd CZ |
1282 | #define F_DNZ_ND (F_DFAKE + 1) |
1283 | { "nd", 0, 1, 16, 0 }, | |
1284 | #define F_DNZ_D (F_DNZ_ND + 1) | |
1285 | { "d", 1, 1, 16, 1 }, | |
886a2506 NC |
1286 | |
1287 | /* Data size. */ | |
2b848ebd | 1288 | #define F_SIZEB1 (F_DNZ_D + 1) |
886a2506 NC |
1289 | { "b", 1, 2, 1, 1 }, |
1290 | #define F_SIZEB7 (F_SIZEB1 + 1) | |
1291 | { "b", 1, 2, 7, 1 }, | |
1292 | #define F_SIZEB17 (F_SIZEB7 + 1) | |
1293 | { "b", 1, 2, 17, 1 }, | |
1294 | #define F_SIZEW1 (F_SIZEB17 + 1) | |
1295 | { "w", 2, 2, 1, 0 }, | |
1296 | #define F_SIZEW7 (F_SIZEW1 + 1) | |
1297 | { "w", 2, 2, 7, 0 }, | |
1298 | #define F_SIZEW17 (F_SIZEW7 + 1) | |
1299 | { "w", 2, 2, 17, 0 }, | |
1300 | ||
1301 | /* Sign extension. */ | |
1302 | #define F_SIGN6 (F_SIZEW17 + 1) | |
1303 | { "x", 1, 1, 6, 1 }, | |
1304 | #define F_SIGN16 (F_SIGN6 + 1) | |
1305 | { "x", 1, 1, 16, 1 }, | |
1306 | #define F_SIGNX (F_SIGN16 + 1) | |
1307 | { "x", 0, 0, 0, 1 }, | |
1308 | ||
1309 | /* Address write-back modes. */ | |
1310 | #define F_A3 (F_SIGNX + 1) | |
1311 | { "a", 1, 2, 3, 0 }, | |
1312 | #define F_A9 (F_A3 + 1) | |
1313 | { "a", 1, 2, 9, 0 }, | |
1314 | #define F_A22 (F_A9 + 1) | |
1315 | { "a", 1, 2, 22, 0 }, | |
1316 | #define F_AW3 (F_A22 + 1) | |
1317 | { "aw", 1, 2, 3, 1 }, | |
1318 | #define F_AW9 (F_AW3 + 1) | |
1319 | { "aw", 1, 2, 9, 1 }, | |
1320 | #define F_AW22 (F_AW9 + 1) | |
1321 | { "aw", 1, 2, 22, 1 }, | |
1322 | #define F_AB3 (F_AW22 + 1) | |
1323 | { "ab", 2, 2, 3, 1 }, | |
1324 | #define F_AB9 (F_AB3 + 1) | |
1325 | { "ab", 2, 2, 9, 1 }, | |
1326 | #define F_AB22 (F_AB9 + 1) | |
1327 | { "ab", 2, 2, 22, 1 }, | |
1328 | #define F_AS3 (F_AB22 + 1) | |
1329 | { "as", 3, 2, 3, 1 }, | |
1330 | #define F_AS9 (F_AS3 + 1) | |
1331 | { "as", 3, 2, 9, 1 }, | |
1332 | #define F_AS22 (F_AS9 + 1) | |
1333 | { "as", 3, 2, 22, 1 }, | |
1334 | #define F_ASFAKE (F_AS22 + 1) | |
1335 | { "as", 0, 0, 0, 1 }, | |
1336 | ||
1337 | /* Cache bypass. */ | |
1338 | #define F_DI5 (F_ASFAKE + 1) | |
1339 | { "di", 1, 1, 5, 1 }, | |
1340 | #define F_DI11 (F_DI5 + 1) | |
1341 | { "di", 1, 1, 11, 1 }, | |
1342 | #define F_DI15 (F_DI11 + 1) | |
1343 | { "di", 1, 1, 15, 1 }, | |
1344 | ||
1345 | /* ARCv2 specific. */ | |
1346 | #define F_NT (F_DI15 + 1) | |
1347 | { "nt", 0, 1, 3, 1}, | |
1348 | #define F_T (F_NT + 1) | |
1349 | { "t", 1, 1, 3, 1}, | |
1350 | #define F_H1 (F_T + 1) | |
1351 | { "h", 2, 2, 1, 1 }, | |
1352 | #define F_H7 (F_H1 + 1) | |
1353 | { "h", 2, 2, 7, 1 }, | |
1354 | #define F_H17 (F_H7 + 1) | |
1355 | { "h", 2, 2, 17, 1 }, | |
1356 | ||
1357 | /* Fake Flags. */ | |
1358 | #define F_NE (F_H17 + 1) | |
1359 | { "ne", 0, 0, 0, 1 }, | |
e23e8ebe AB |
1360 | |
1361 | /* ARC NPS400 Support: See comment near head of file. */ | |
1362 | #define F_NPS_CL (F_NE + 1) | |
1363 | { "cl", 0, 0, 0, 1 }, | |
1364 | ||
1365 | #define F_NPS_FLAG (F_NPS_CL + 1) | |
1366 | { "f", 1, 1, 20, 1 }, | |
820f03ff AB |
1367 | |
1368 | #define F_NPS_R (F_NPS_FLAG + 1) | |
1369 | { "r", 1, 1, 15, 1 }, | |
a42a4f84 AB |
1370 | |
1371 | #define F_NPS_RW (F_NPS_R + 1) | |
1372 | { "rw", 0, 1, 7, 1 }, | |
1373 | ||
1374 | #define F_NPS_RD (F_NPS_RW + 1) | |
1375 | { "rd", 1, 1, 7, 1 }, | |
1376 | ||
1377 | #define F_NPS_WFT (F_NPS_RD + 1) | |
1378 | { "wft", 0, 0, 0, 1 }, | |
1379 | ||
1380 | #define F_NPS_IE1 (F_NPS_WFT + 1) | |
1381 | { "ie1", 1, 2, 8, 1 }, | |
1382 | ||
1383 | #define F_NPS_IE2 (F_NPS_IE1 + 1) | |
1384 | { "ie2", 2, 2, 8, 1 }, | |
1385 | ||
1386 | #define F_NPS_IE12 (F_NPS_IE2 + 1) | |
1387 | { "ie12", 3, 2, 8, 1 }, | |
1388 | ||
1389 | #define F_NPS_SYNC_RD (F_NPS_IE12 + 1) | |
1390 | { "rd", 0, 1, 6, 1 }, | |
1391 | ||
1392 | #define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1) | |
1393 | { "wr", 1, 1, 6, 1 }, | |
1394 | ||
1395 | #define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1) | |
1396 | { "off", 0, 0, 0, 1 }, | |
1397 | ||
1398 | #define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1) | |
1399 | { "restore", 0, 0, 0, 1 }, | |
1400 | ||
537aefaf AB |
1401 | #define F_NPS_SX (F_NPS_HWS_RESTORE + 1) |
1402 | { "sx", 1, 1, 14, 1 }, | |
1403 | ||
1404 | #define F_NPS_AR (F_NPS_SX + 1) | |
1405 | { "ar", 0, 1, 0, 1 }, | |
1406 | ||
1407 | #define F_NPS_AL (F_NPS_AR + 1) | |
1408 | { "al", 1, 1, 0, 1 }, | |
14053c19 GM |
1409 | |
1410 | #define F_NPS_S (F_NPS_AL + 1) | |
1411 | { "s", 0, 0, 0, 1 }, | |
1412 | ||
1413 | #define F_NPS_ZNCV_RD (F_NPS_S + 1) | |
1414 | { "rd", 0, 1, 15, 1 }, | |
1415 | ||
1416 | #define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1) | |
1417 | { "wr", 1, 1, 15, 1 }, | |
9ba75c88 GM |
1418 | |
1419 | #define F_NPS_P0 (F_NPS_ZNCV_WR + 1) | |
1420 | { "p0", 0, 0, 0, 1 }, | |
1421 | ||
1422 | #define F_NPS_P1 (F_NPS_P0 + 1) | |
1423 | { "p1", 0, 0, 0, 1 }, | |
1424 | ||
1425 | #define F_NPS_P2 (F_NPS_P1 + 1) | |
1426 | { "p2", 0, 0, 0, 1 }, | |
1427 | ||
1428 | #define F_NPS_P3 (F_NPS_P2 + 1) | |
1429 | { "p3", 0, 0, 0, 1 }, | |
28215275 GM |
1430 | |
1431 | #define F_NPS_LDBIT_DI (F_NPS_P3 + 1) | |
1432 | { "di", 0, 0, 0, 1 }, | |
1433 | ||
1434 | #define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1) | |
1435 | { "cl", 1, 1, 6, 1 }, | |
1436 | ||
1437 | #define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1) | |
1438 | { "cl", 1, 1, 16, 1 }, | |
1439 | ||
1440 | #define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1) | |
1441 | { "x2", 1, 2, 9, 1 }, | |
1442 | ||
1443 | #define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1) | |
1444 | { "x2", 1, 2, 22, 1 }, | |
1445 | ||
1446 | #define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1) | |
1447 | { "x4", 2, 2, 9, 1 }, | |
1448 | ||
1449 | #define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1) | |
1450 | { "x4", 2, 2, 22, 1 }, | |
886a2506 | 1451 | }; |
252b5132 | 1452 | |
886a2506 | 1453 | const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands); |
252b5132 | 1454 | |
886a2506 | 1455 | /* Table of the flag classes. |
252b5132 | 1456 | |
886a2506 NC |
1457 | The format of the table is |
1458 | CLASS {FLAG_CODE}. */ | |
1459 | const struct arc_flag_class arc_flag_classes[] = | |
1460 | { | |
1461 | #define C_EMPTY 0 | |
1ae8ab47 | 1462 | { F_CLASS_NONE, { F_NULL } }, |
886a2506 NC |
1463 | |
1464 | #define C_CC (C_EMPTY + 1) | |
d9eca1df | 1465 | { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND, |
f36e33da CZ |
1466 | { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, |
1467 | F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, | |
1468 | F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
1469 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, | |
1470 | F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, | |
1471 | F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
886a2506 NC |
1472 | |
1473 | #define C_AA_ADDR3 (C_CC + 1) | |
1474 | #define C_AA27 (C_CC + 1) | |
1ae8ab47 | 1475 | { F_CLASS_OPTIONAL, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } }, |
886a2506 NC |
1476 | #define C_AA_ADDR9 (C_AA_ADDR3 + 1) |
1477 | #define C_AA21 (C_AA_ADDR3 + 1) | |
1ae8ab47 | 1478 | { F_CLASS_OPTIONAL, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } }, |
886a2506 NC |
1479 | #define C_AA_ADDR22 (C_AA_ADDR9 + 1) |
1480 | #define C_AA8 (C_AA_ADDR9 + 1) | |
1ae8ab47 | 1481 | { F_CLASS_OPTIONAL, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } }, |
886a2506 NC |
1482 | |
1483 | #define C_F (C_AA_ADDR22 + 1) | |
1ae8ab47 | 1484 | { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } }, |
886a2506 | 1485 | #define C_FHARD (C_F + 1) |
1ae8ab47 | 1486 | { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } }, |
886a2506 NC |
1487 | |
1488 | #define C_T (C_FHARD + 1) | |
1ae8ab47 | 1489 | { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } }, |
886a2506 | 1490 | #define C_D (C_T + 1) |
1ae8ab47 | 1491 | { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } }, |
2b848ebd CZ |
1492 | #define C_DNZ_D (C_D + 1) |
1493 | { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } }, | |
886a2506 | 1494 | |
2b848ebd | 1495 | #define C_DHARD (C_DNZ_D + 1) |
1ae8ab47 | 1496 | { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } }, |
886a2506 NC |
1497 | |
1498 | #define C_DI20 (C_DHARD + 1) | |
1ae8ab47 | 1499 | { F_CLASS_OPTIONAL, { F_DI11, F_NULL }}, |
886a2506 | 1500 | #define C_DI16 (C_DI20 + 1) |
1ae8ab47 | 1501 | { F_CLASS_OPTIONAL, { F_DI15, F_NULL }}, |
886a2506 | 1502 | #define C_DI26 (C_DI16 + 1) |
1ae8ab47 | 1503 | { F_CLASS_OPTIONAL, { F_DI5, F_NULL }}, |
886a2506 NC |
1504 | |
1505 | #define C_X25 (C_DI26 + 1) | |
1ae8ab47 | 1506 | { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }}, |
886a2506 | 1507 | #define C_X15 (C_X25 + 1) |
1ae8ab47 | 1508 | { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }}, |
886a2506 NC |
1509 | #define C_XHARD (C_X15 + 1) |
1510 | #define C_X (C_X15 + 1) | |
1ae8ab47 | 1511 | { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }}, |
886a2506 NC |
1512 | |
1513 | #define C_ZZ13 (C_X + 1) | |
1ae8ab47 | 1514 | { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}}, |
886a2506 | 1515 | #define C_ZZ23 (C_ZZ13 + 1) |
1ae8ab47 | 1516 | { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}}, |
886a2506 | 1517 | #define C_ZZ29 (C_ZZ23 + 1) |
1ae8ab47 | 1518 | { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}}, |
886a2506 NC |
1519 | |
1520 | #define C_AS (C_ZZ29 + 1) | |
1ae8ab47 | 1521 | { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}}, |
886a2506 NC |
1522 | |
1523 | #define C_NE (C_AS + 1) | |
1ae8ab47 | 1524 | { F_CLASS_OPTIONAL, { F_NE, F_NULL}}, |
e23e8ebe AB |
1525 | |
1526 | /* ARC NPS400 Support: See comment near head of file. */ | |
1527 | #define C_NPS_CL (C_NE + 1) | |
1528 | { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}}, | |
1529 | ||
1530 | #define C_NPS_F (C_NPS_CL + 1) | |
1531 | { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}}, | |
820f03ff AB |
1532 | |
1533 | #define C_NPS_R (C_NPS_F + 1) | |
1534 | { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}}, | |
a42a4f84 AB |
1535 | |
1536 | #define C_NPS_SCHD_RW (C_NPS_R + 1) | |
1537 | { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}}, | |
1538 | ||
1539 | #define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1) | |
1540 | { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}}, | |
1541 | ||
1542 | #define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1) | |
1543 | { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}}, | |
1544 | ||
1545 | #define C_NPS_SYNC (C_NPS_SCHD_IE + 1) | |
1546 | { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}}, | |
1547 | ||
1548 | #define C_NPS_HWS_OFF (C_NPS_SYNC + 1) | |
1549 | { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}}, | |
1550 | ||
1551 | #define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1) | |
1552 | { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}}, | |
1553 | ||
537aefaf AB |
1554 | #define C_NPS_SX (C_NPS_HWS_RESTORE + 1) |
1555 | { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}}, | |
1556 | ||
1557 | #define C_NPS_AR_AL (C_NPS_SX + 1) | |
1558 | { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}}, | |
14053c19 GM |
1559 | |
1560 | #define C_NPS_S (C_NPS_AR_AL + 1) | |
1561 | { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}}, | |
1562 | ||
1563 | #define C_NPS_ZNCV (C_NPS_S + 1) | |
1564 | { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}}, | |
9ba75c88 GM |
1565 | |
1566 | #define C_NPS_P0 (C_NPS_ZNCV + 1) | |
1567 | { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }}, | |
1568 | ||
1569 | #define C_NPS_P1 (C_NPS_P0 + 1) | |
1570 | { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }}, | |
1571 | ||
1572 | #define C_NPS_P2 (C_NPS_P1 + 1) | |
1573 | { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }}, | |
1574 | ||
1575 | #define C_NPS_P3 (C_NPS_P2 + 1) | |
1576 | { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }}, | |
28215275 GM |
1577 | |
1578 | #define C_NPS_LDBIT_DI (C_NPS_P3 + 1) | |
1579 | { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }}, | |
1580 | ||
1581 | #define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1) | |
1582 | { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }}, | |
1583 | ||
1584 | #define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1) | |
1585 | { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }}, | |
1586 | ||
1587 | #define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1) | |
1588 | { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }}, | |
1589 | ||
1590 | #define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1) | |
1591 | { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }}, | |
886a2506 | 1592 | }; |
252b5132 | 1593 | |
b99747ae CZ |
1594 | const unsigned char flags_none[] = { 0 }; |
1595 | const unsigned char flags_f[] = { C_F }; | |
1596 | const unsigned char flags_cc[] = { C_CC }; | |
1597 | const unsigned char flags_ccf[] = { C_CC, C_F }; | |
1598 | ||
886a2506 | 1599 | /* The operands table. |
252b5132 | 1600 | |
886a2506 | 1601 | The format of the operands table is: |
47b0e7ad | 1602 | |
886a2506 NC |
1603 | BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */ |
1604 | const struct arc_operand arc_operands[] = | |
0d2bcfaf | 1605 | { |
886a2506 NC |
1606 | /* The fields are bits, shift, insert, extract, flags. The zero |
1607 | index is used to indicate end-of-list. */ | |
1608 | #define UNUSED 0 | |
1609 | { 0, 0, 0, 0, 0, 0 }, | |
4eb6f892 AB |
1610 | |
1611 | #define IGNORED (UNUSED + 1) | |
1612 | { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 }, | |
1613 | ||
886a2506 NC |
1614 | /* The plain integer register fields. Used by 32 bit |
1615 | instructions. */ | |
4eb6f892 | 1616 | #define RA (IGNORED + 1) |
886a2506 NC |
1617 | { 6, 0, 0, ARC_OPERAND_IR, 0, 0 }, |
1618 | #define RB (RA + 1) | |
1619 | { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb }, | |
1620 | #define RC (RB + 1) | |
1621 | { 6, 6, 0, ARC_OPERAND_IR, 0, 0 }, | |
1622 | #define RBdup (RC + 1) | |
1623 | { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb }, | |
1624 | ||
1625 | #define RAD (RBdup + 1) | |
1626 | { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 }, | |
1627 | #define RCD (RAD + 1) | |
1628 | { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 }, | |
1629 | ||
1630 | /* The plain integer register fields. Used by short | |
1631 | instructions. */ | |
1632 | #define RA16 (RCD + 1) | |
1633 | #define RA_S (RCD + 1) | |
1634 | { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras }, | |
1635 | #define RB16 (RA16 + 1) | |
1636 | #define RB_S (RA16 + 1) | |
1637 | { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs }, | |
1638 | #define RB16dup (RB16 + 1) | |
1639 | #define RB_Sdup (RB16 + 1) | |
1640 | { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs }, | |
1641 | #define RC16 (RB16dup + 1) | |
1642 | #define RC_S (RB16dup + 1) | |
1643 | { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs }, | |
1644 | #define R6H (RC16 + 1) /* 6bit register field 'h' used | |
1645 | by V1 cpus. */ | |
1646 | { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 }, | |
1647 | #define R5H (R6H + 1) /* 5bit register field 'h' used | |
1648 | by V2 cpus. */ | |
1649 | #define RH_S (R6H + 1) /* 5bit register field 'h' used | |
1650 | by V2 cpus. */ | |
1651 | { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 }, | |
1652 | #define R5Hdup (R5H + 1) | |
1653 | #define RH_Sdup (R5H + 1) | |
1654 | { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, | |
1655 | insert_rhv2, extract_rhv2 }, | |
1656 | ||
1657 | #define RG (R5Hdup + 1) | |
1658 | #define G_S (R5Hdup + 1) | |
1659 | { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s }, | |
1660 | ||
1661 | /* Fix registers. */ | |
1662 | #define R0 (RG + 1) | |
1663 | #define R0_S (RG + 1) | |
1664 | { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 }, | |
1665 | #define R1 (R0 + 1) | |
1666 | #define R1_S (R0 + 1) | |
1667 | { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 }, | |
1668 | #define R2 (R1 + 1) | |
1669 | #define R2_S (R1 + 1) | |
1670 | { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 }, | |
1671 | #define R3 (R2 + 1) | |
1672 | #define R3_S (R2 + 1) | |
1673 | { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 }, | |
8ddf6b2a | 1674 | #define RSP (R3 + 1) |
886a2506 NC |
1675 | #define SP_S (R3 + 1) |
1676 | { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp }, | |
8ddf6b2a CZ |
1677 | #define SPdup (RSP + 1) |
1678 | #define SP_Sdup (RSP + 1) | |
886a2506 NC |
1679 | { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp }, |
1680 | #define GP (SPdup + 1) | |
1681 | #define GP_S (SPdup + 1) | |
1682 | { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp }, | |
1683 | ||
1684 | #define PCL_S (GP + 1) | |
1685 | { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl }, | |
1686 | ||
1687 | #define BLINK (PCL_S + 1) | |
1688 | #define BLINK_S (PCL_S + 1) | |
1689 | { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink }, | |
1690 | ||
1691 | #define ILINK1 (BLINK + 1) | |
1692 | { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 }, | |
1693 | #define ILINK2 (ILINK1 + 1) | |
1694 | { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 }, | |
1695 | ||
1696 | /* Long immediate. */ | |
1697 | #define LIMM (ILINK2 + 1) | |
1698 | #define LIMM_S (ILINK2 + 1) | |
1699 | { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 }, | |
1700 | #define LIMMdup (LIMM + 1) | |
1701 | { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 }, | |
1702 | ||
1703 | /* Special operands. */ | |
1704 | #define ZA (LIMMdup + 1) | |
1705 | #define ZB (LIMMdup + 1) | |
1706 | #define ZA_S (LIMMdup + 1) | |
1707 | #define ZB_S (LIMMdup + 1) | |
1708 | #define ZC_S (LIMMdup + 1) | |
1709 | { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 }, | |
1710 | ||
1711 | #define RRANGE_EL (ZA + 1) | |
1712 | { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE, | |
1713 | insert_rrange, extract_rrange}, | |
1714 | #define FP_EL (RRANGE_EL + 1) | |
1715 | { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, | |
1716 | insert_fpel, extract_fpel }, | |
1717 | #define BLINK_EL (FP_EL + 1) | |
1718 | { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, | |
1719 | insert_blinkel, extract_blinkel }, | |
1720 | #define PCL_EL (BLINK_EL + 1) | |
1721 | { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, | |
1722 | insert_pclel, extract_pclel }, | |
1723 | ||
1724 | /* Fake operand to handle the T flag. */ | |
1725 | #define BRAKET (PCL_EL + 1) | |
1726 | #define BRAKETdup (PCL_EL + 1) | |
1727 | { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 }, | |
1728 | ||
1729 | /* Fake operand to handle the T flag. */ | |
1730 | #define FKT_T (BRAKET + 1) | |
1731 | { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 }, | |
1732 | /* Fake operand to handle the T flag. */ | |
1733 | #define FKT_NT (FKT_T + 1) | |
1734 | { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 }, | |
1735 | ||
1736 | /* UIMM6_20 mask = 00000000000000000000111111000000. */ | |
1737 | #define UIMM6_20 (FKT_NT + 1) | |
1738 | {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20}, | |
1739 | ||
1740 | /* SIMM12_20 mask = 00000000000000000000111111222222. */ | |
1741 | #define SIMM12_20 (UIMM6_20 + 1) | |
1742 | {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20}, | |
1743 | ||
1744 | /* SIMM3_5_S mask = 0000011100000000. */ | |
1745 | #define SIMM3_5_S (SIMM12_20 + 1) | |
1746 | {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK, | |
1747 | insert_simm3s, extract_simm3s}, | |
1748 | ||
1749 | /* UIMM7_A32_11_S mask = 0000000000011111. */ | |
1750 | #define UIMM7_A32_11_S (SIMM3_5_S + 1) | |
1751 | {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | |
1752 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s, | |
1753 | extract_uimm7_a32_11_s}, | |
1754 | ||
1755 | /* UIMM7_9_S mask = 0000000001111111. */ | |
1756 | #define UIMM7_9_S (UIMM7_A32_11_S + 1) | |
1757 | {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s}, | |
1758 | ||
1759 | /* UIMM3_13_S mask = 0000000000000111. */ | |
1760 | #define UIMM3_13_S (UIMM7_9_S + 1) | |
1761 | {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s}, | |
1762 | ||
1763 | /* SIMM11_A32_7_S mask = 0000000111111111. */ | |
1764 | #define SIMM11_A32_7_S (UIMM3_13_S + 1) | |
1765 | {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | |
1766 | | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s}, | |
1767 | ||
1768 | /* UIMM6_13_S mask = 0000000002220111. */ | |
1769 | #define UIMM6_13_S (SIMM11_A32_7_S + 1) | |
1770 | {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s}, | |
1771 | /* UIMM5_11_S mask = 0000000000011111. */ | |
1772 | #define UIMM5_11_S (UIMM6_13_S + 1) | |
1773 | {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s, | |
1774 | extract_uimm5_11_s}, | |
1775 | ||
1776 | /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */ | |
1777 | #define SIMM9_A16_8 (UIMM5_11_S + 1) | |
1778 | {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | |
1779 | | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8, | |
1780 | extract_simm9_a16_8}, | |
1781 | ||
1782 | /* UIMM6_8 mask = 00000000000000000000111111000000. */ | |
1783 | #define UIMM6_8 (SIMM9_A16_8 + 1) | |
1784 | {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8}, | |
1785 | ||
1786 | /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */ | |
1787 | #define SIMM21_A16_5 (UIMM6_8 + 1) | |
1788 | {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED | |
1789 | | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE, | |
1790 | insert_simm21_a16_5, extract_simm21_a16_5}, | |
1791 | ||
1792 | /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */ | |
1793 | #define SIMM25_A16_5 (SIMM21_A16_5 + 1) | |
1794 | {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED | |
1795 | | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, | |
1796 | insert_simm25_a16_5, extract_simm25_a16_5}, | |
1797 | ||
1798 | /* SIMM10_A16_7_S mask = 0000000111111111. */ | |
1799 | #define SIMM10_A16_7_S (SIMM25_A16_5 + 1) | |
1800 | {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | |
1801 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s, | |
1802 | extract_simm10_a16_7_s}, | |
1803 | ||
1804 | #define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1) | |
1805 | {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | |
1806 | | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s}, | |
1807 | ||
1808 | /* SIMM7_A16_10_S mask = 0000000000111111. */ | |
1809 | #define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1) | |
1810 | {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | |
1811 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s, | |
1812 | extract_simm7_a16_10_s}, | |
1813 | ||
1814 | /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */ | |
1815 | #define SIMM21_A32_5 (SIMM7_A16_10_S + 1) | |
1816 | {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | |
1817 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5, | |
1818 | extract_simm21_a32_5}, | |
1819 | ||
1820 | /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */ | |
1821 | #define SIMM25_A32_5 (SIMM21_A32_5 + 1) | |
1822 | {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | |
1823 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5, | |
1824 | extract_simm25_a32_5}, | |
1825 | ||
1826 | /* SIMM13_A32_5_S mask = 0000011111111111. */ | |
1827 | #define SIMM13_A32_5_S (SIMM25_A32_5 + 1) | |
1828 | {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | |
1829 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s, | |
1830 | extract_simm13_a32_5_s}, | |
1831 | ||
1832 | /* SIMM8_A16_9_S mask = 0000000001111111. */ | |
1833 | #define SIMM8_A16_9_S (SIMM13_A32_5_S + 1) | |
1834 | {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | |
1835 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s, | |
1836 | extract_simm8_a16_9_s}, | |
1837 | ||
1838 | /* UIMM3_23 mask = 00000000000000000000000111000000. */ | |
1839 | #define UIMM3_23 (SIMM8_A16_9_S + 1) | |
1840 | {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23}, | |
1841 | ||
1842 | /* UIMM10_6_S mask = 0000001111111111. */ | |
1843 | #define UIMM10_6_S (UIMM3_23 + 1) | |
1844 | {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s}, | |
1845 | ||
1846 | /* UIMM6_11_S mask = 0000002200011110. */ | |
1847 | #define UIMM6_11_S (UIMM10_6_S + 1) | |
1848 | {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s}, | |
1849 | ||
1850 | /* SIMM9_8 mask = 00000000111111112000000000000000. */ | |
1851 | #define SIMM9_8 (UIMM6_11_S + 1) | |
1852 | {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE, | |
1853 | insert_simm9_8, extract_simm9_8}, | |
1854 | ||
1855 | /* UIMM10_A32_8_S mask = 0000000011111111. */ | |
1856 | #define UIMM10_A32_8_S (SIMM9_8 + 1) | |
1857 | {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | |
1858 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s, | |
1859 | extract_uimm10_a32_8_s}, | |
1860 | ||
1861 | /* SIMM9_7_S mask = 0000000111111111. */ | |
1862 | #define SIMM9_7_S (UIMM10_A32_8_S + 1) | |
1863 | {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s, | |
1864 | extract_simm9_7_s}, | |
1865 | ||
1866 | /* UIMM6_A16_11_S mask = 0000000000011111. */ | |
1867 | #define UIMM6_A16_11_S (SIMM9_7_S + 1) | |
1868 | {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | |
1869 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s, | |
1870 | extract_uimm6_a16_11_s}, | |
1871 | ||
1872 | /* UIMM5_A32_11_S mask = 0000020000011000. */ | |
1873 | #define UIMM5_A32_11_S (UIMM6_A16_11_S + 1) | |
1874 | {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 | |
1875 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s, | |
1876 | extract_uimm5_a32_11_s}, | |
1877 | ||
1878 | /* SIMM11_A32_13_S mask = 0000022222200111. */ | |
1879 | #define SIMM11_A32_13_S (UIMM5_A32_11_S + 1) | |
1880 | {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 | |
1881 | | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s}, | |
1882 | ||
1883 | /* UIMM7_13_S mask = 0000000022220111. */ | |
1884 | #define UIMM7_13_S (SIMM11_A32_13_S + 1) | |
1885 | {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s}, | |
1886 | ||
1887 | /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */ | |
1888 | #define UIMM6_A16_21 (UIMM7_13_S + 1) | |
1889 | {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | |
1890 | | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21}, | |
1891 | ||
1892 | /* UIMM7_11_S mask = 0000022200011110. */ | |
1893 | #define UIMM7_11_S (UIMM6_A16_21 + 1) | |
1894 | {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s}, | |
1895 | ||
1896 | /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */ | |
1897 | #define UIMM7_A16_20 (UIMM7_11_S + 1) | |
1898 | {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 | |
1899 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20, | |
1900 | extract_uimm7_a16_20}, | |
1901 | ||
1902 | /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */ | |
1903 | #define SIMM13_A16_20 (UIMM7_A16_20 + 1) | |
1904 | {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 | |
1905 | | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20, | |
1906 | extract_simm13_a16_20}, | |
1907 | ||
1908 | /* UIMM8_8_S mask = 0000000011111111. */ | |
1909 | #define UIMM8_8_S (SIMM13_A16_20 + 1) | |
1910 | {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s}, | |
1911 | ||
1912 | /* W6 mask = 00000000000000000000111111000000. */ | |
1913 | #define W6 (UIMM8_8_S + 1) | |
1914 | {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6}, | |
1915 | ||
1916 | /* UIMM6_5_S mask = 0000011111100000. */ | |
1917 | #define UIMM6_5_S (W6 + 1) | |
1918 | {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s}, | |
e23e8ebe AB |
1919 | |
1920 | /* ARC NPS400 Support: See comment near head of file. */ | |
1921 | #define NPS_R_DST_3B (UIMM6_5_S + 1) | |
1922 | { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst }, | |
1923 | ||
1924 | #define NPS_R_SRC1_3B (NPS_R_DST_3B + 1) | |
1925 | { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst }, | |
1926 | ||
1927 | #define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1) | |
1928 | { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2, extract_nps_3bit_src2 }, | |
1929 | ||
1930 | #define NPS_R_DST (NPS_R_SRC2_3B + 1) | |
2cce10e7 | 1931 | { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL }, |
e23e8ebe AB |
1932 | |
1933 | #define NPS_R_SRC1 (NPS_R_DST + 1) | |
2cce10e7 | 1934 | { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL }, |
e23e8ebe AB |
1935 | |
1936 | #define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1) | |
1937 | { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 }, | |
1938 | ||
1939 | #define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1) | |
1940 | { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 }, | |
1941 | ||
1942 | #define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1) | |
820f03ff | 1943 | { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size }, |
e23e8ebe | 1944 | |
820f03ff AB |
1945 | #define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1) |
1946 | { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size }, | |
1947 | ||
1948 | #define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1) | |
1949 | { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b }, | |
1950 | ||
1951 | #define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1) | |
1952 | { 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 }, | |
1953 | ||
1954 | #define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1) | |
e23e8ebe | 1955 | { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, |
820f03ff | 1956 | |
14053c19 GM |
1957 | #define NPS_SIMM16 (NPS_UIMM16 + 1) |
1958 | { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL }, | |
1959 | ||
1960 | #define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1) | |
820f03ff | 1961 | { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 }, |
4b0c052e AB |
1962 | |
1963 | #define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1) | |
1964 | { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 }, | |
537aefaf AB |
1965 | |
1966 | #define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1) | |
1967 | { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src2_pos, extract_nps_src2_pos }, | |
1968 | ||
1969 | #define NPS_SRC1_POS (NPS_SRC2_POS + 1) | |
1970 | { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_src1_pos, extract_nps_src1_pos }, | |
1971 | ||
1972 | #define NPS_ADDB_SIZE (NPS_SRC1_POS + 1) | |
1973 | { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_addb_size, extract_nps_addb_size }, | |
1974 | ||
1975 | #define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1) | |
1976 | { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_andb_size, extract_nps_andb_size }, | |
1977 | ||
1978 | #define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1) | |
1979 | { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_fxorb_size, extract_nps_fxorb_size }, | |
1980 | ||
1981 | #define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1) | |
1982 | { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_wxorb_size, extract_nps_wxorb_size }, | |
1983 | ||
1984 | #define NPS_R_XLDST (NPS_WXORB_SIZE + 1) | |
1985 | { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL }, | |
1986 | ||
1987 | #define NPS_DIV_UIMM4 (NPS_R_XLDST + 1) | |
1988 | { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
1989 | ||
1990 | #define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1) | |
1991 | { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_qcmp_size, extract_nps_qcmp_size }, | |
1992 | ||
1993 | #define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1) | |
1994 | { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 }, | |
1995 | ||
1996 | #define NPS_QCMP_M2 (NPS_QCMP_M1 + 1) | |
1997 | { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 }, | |
1998 | ||
1999 | #define NPS_QCMP_M3 (NPS_QCMP_M2 + 1) | |
2000 | { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 }, | |
2001 | ||
2002 | #define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1) | |
2003 | { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_calc_entry_size, extract_nps_calc_entry_size }, | |
4eb6f892 AB |
2004 | |
2005 | #define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1) | |
2006 | { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst_short, extract_nps_3bit_dst_short }, | |
2007 | ||
2008 | #define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1) | |
2009 | { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst_short, extract_nps_3bit_dst_short }, | |
2010 | ||
2011 | #define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1) | |
2012 | { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2_short, extract_nps_3bit_src2_short }, | |
2013 | ||
2014 | #define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1) | |
2015 | { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop2_size, extract_nps_bitop2_size }, | |
2016 | ||
2017 | #define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1) | |
2018 | { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop1_size, extract_nps_bitop1_size }, | |
2019 | ||
2020 | #define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1) | |
2021 | { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 }, | |
2022 | ||
2023 | #define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1) | |
2024 | { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2025 | ||
2026 | #define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1) | |
2027 | { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2028 | ||
2029 | #define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1) | |
2030 | { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2031 | ||
2032 | #define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1) | |
2033 | { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2034 | ||
2035 | #define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1) | |
2036 | { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2037 | ||
2038 | #define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1) | |
2039 | { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2040 | ||
2041 | #define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1) | |
2042 | { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2043 | ||
2044 | #define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1) | |
2045 | { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2046 | ||
2047 | #define NPS_BITOP_MOD4_MSB (NPS_BITOP_SRC_POS1 + 1) | |
2048 | { 2, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_mod4_msb, extract_nps_bitop_mod4_msb }, | |
2049 | ||
2050 | #define NPS_BITOP_MOD4_LSB (NPS_BITOP_MOD4_MSB + 1) | |
2051 | { 2, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_mod4_lsb, extract_nps_bitop_mod4_lsb }, | |
2052 | ||
2053 | #define NPS_BITOP_MOD3 (NPS_BITOP_MOD4_LSB + 1) | |
2054 | { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2055 | ||
2056 | #define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1) | |
2057 | { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2058 | ||
2059 | #define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1) | |
2060 | { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2061 | ||
2062 | #define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1) | |
2063 | { 5, 20, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext }, | |
14053c19 GM |
2064 | |
2065 | #define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1) | |
2066 | { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2067 | ||
2068 | #define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1) | |
2069 | { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_field_size, extract_nps_field_size }, | |
2070 | ||
2071 | #define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1) | |
2072 | { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_shift_factor, extract_nps_shift_factor }, | |
2073 | ||
2074 | #define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1) | |
2075 | { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bits_to_scramble, extract_nps_bits_to_scramble }, | |
2076 | ||
2077 | #define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1) | |
2078 | { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2079 | ||
2080 | #define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1) | |
2081 | { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bdlen_max_len, extract_nps_bdlen_max_len }, | |
2082 | ||
2083 | #define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1) | |
2084 | { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_min_hofs, extract_nps_min_hofs }, | |
2085 | ||
2086 | #define NPS_PSBC (NPS_MIN_HOFS + 1) | |
2087 | { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
9ba75c88 GM |
2088 | |
2089 | #define NPS_DPI_DST (NPS_PSBC + 1) | |
2090 | { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL }, | |
2091 | ||
2092 | /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B but doesn't duplicate an operand */ | |
2093 | #define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1) | |
2094 | { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst }, | |
2095 | ||
2096 | #define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1) | |
2097 | { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_width, extract_nps_hash_width }, | |
2098 | ||
2099 | #define NPS_HASH_PERM (NPS_HASH_WIDTH + 1) | |
2100 | { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2101 | ||
2102 | #define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1) | |
2103 | { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2104 | ||
2105 | #define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1) | |
2106 | { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2107 | ||
2108 | #define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1) | |
2109 | { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_hash_len, extract_nps_hash_len }, | |
2110 | ||
2111 | #define NPS_HASH_OFS (NPS_HASH_LEN + 1) | |
2112 | { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2113 | ||
2114 | #define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1) | |
2115 | { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2116 | ||
2117 | #define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1) | |
2118 | { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2119 | ||
2120 | #define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1) | |
2121 | { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2122 | ||
2123 | #define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1) | |
2124 | { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2125 | ||
2126 | #define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1) | |
2127 | { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_index3, extract_nps_index3 }, | |
db18dbab GM |
2128 | |
2129 | #define COLON (NPS_E4BY_INDEX3 + 1) | |
2130 | { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL }, | |
2131 | ||
2132 | #define NPS_BD (COLON + 1) | |
2133 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_bd, extract_nps_bd }, | |
2134 | ||
2135 | #define NPS_JID (NPS_BD + 1) | |
2136 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_jid, extract_nps_jid }, | |
2137 | ||
2138 | #define NPS_LBD (NPS_JID + 1) | |
2139 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_lbd, extract_nps_lbd }, | |
2140 | ||
2141 | #define NPS_MBD (NPS_LBD + 1) | |
2142 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_mbd, extract_nps_mbd }, | |
2143 | ||
2144 | #define NPS_SD (NPS_MBD + 1) | |
2145 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sd, extract_nps_sd }, | |
2146 | ||
2147 | #define NPS_SM (NPS_SD + 1) | |
2148 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_sm, extract_nps_sm }, | |
2149 | ||
2150 | #define NPS_XA (NPS_SM + 1) | |
2151 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xa, extract_nps_xa }, | |
2152 | ||
2153 | #define NPS_XD (NPS_XA + 1) | |
2154 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_xd, extract_nps_xd }, | |
2155 | ||
2156 | #define NPS_CD (NPS_XD + 1) | |
2157 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cd, extract_nps_cd }, | |
2158 | ||
2159 | #define NPS_CBD (NPS_CD + 1) | |
2160 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cbd, extract_nps_cbd }, | |
2161 | ||
2162 | #define NPS_CJID (NPS_CBD + 1) | |
2163 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cjid, extract_nps_cjid }, | |
2164 | ||
2165 | #define NPS_CLBD (NPS_CJID + 1) | |
2166 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_clbd, extract_nps_clbd }, | |
2167 | ||
2168 | #define NPS_CM (NPS_CLBD + 1) | |
2169 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cm, extract_nps_cm }, | |
2170 | ||
2171 | #define NPS_CSD (NPS_CM + 1) | |
2172 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_csd, extract_nps_csd }, | |
2173 | ||
2174 | #define NPS_CXA (NPS_CSD + 1) | |
2175 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxa, extract_nps_cxa }, | |
2176 | ||
2177 | #define NPS_CXD (NPS_CXA + 1) | |
2178 | { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, insert_nps_cxd, extract_nps_cxd }, | |
2179 | ||
2180 | #define NPS_BD_TYPE (NPS_CXD + 1) | |
2181 | { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2182 | ||
2183 | #define NPS_BMU_NUM (NPS_BD_TYPE + 1) | |
2184 | { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bd_num_buff, extract_nps_bd_num_buff }, | |
2185 | ||
2186 | #define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1) | |
2187 | { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, | |
2188 | ||
2189 | #define NPS_PMU_NUM_JOB (NPS_PMU_NXT_DST + 1) | |
2190 | { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_pmu_num_job, extract_nps_pmu_num_job }, | |
886a2506 | 2191 | }; |
0d2bcfaf | 2192 | |
886a2506 | 2193 | const unsigned arc_num_operands = ARRAY_SIZE (arc_operands); |
0d2bcfaf | 2194 | |
886a2506 NC |
2195 | const unsigned arc_Toperand = FKT_T; |
2196 | const unsigned arc_NToperand = FKT_NT; | |
47b0e7ad | 2197 | |
b99747ae CZ |
2198 | const unsigned char arg_none[] = { 0 }; |
2199 | const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC }; | |
2200 | const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC }; | |
2201 | const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC }; | |
2202 | const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 }; | |
2203 | const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 }; | |
2204 | const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 }; | |
2205 | const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 }; | |
2206 | const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC }; | |
2207 | const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM }; | |
2208 | const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC }; | |
2209 | const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM }; | |
2210 | ||
2211 | const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM }; | |
2212 | const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 }; | |
2213 | const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 }; | |
2214 | ||
2215 | const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 }; | |
2216 | const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup }; | |
2217 | const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup }; | |
2218 | ||
2219 | const unsigned char arg_32bit_rbrc[] = { RB, RC }; | |
2220 | const unsigned char arg_32bit_zarc[] = { ZA, RC }; | |
2221 | const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 }; | |
2222 | const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 }; | |
2223 | const unsigned char arg_32bit_rblimm[] = { RB, LIMM }; | |
2224 | const unsigned char arg_32bit_zalimm[] = { ZA, LIMM }; | |
2225 | ||
2226 | const unsigned char arg_32bit_limmrc[] = { LIMM, RC }; | |
2227 | const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 }; | |
2228 | const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 }; | |
2229 | const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup }; | |
2230 | ||
945e0f82 CZ |
2231 | const unsigned char arg_32bit_rc[] = { RC }; |
2232 | const unsigned char arg_32bit_u6[] = { UIMM6_20 }; | |
2233 | const unsigned char arg_32bit_limm[] = { LIMM }; | |
2234 | ||
886a2506 | 2235 | /* The opcode table. |
0d2bcfaf | 2236 | |
886a2506 | 2237 | The format of the opcode table is: |
0d2bcfaf | 2238 | |
1328504b AB |
2239 | NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }. |
2240 | ||
2241 | The table is organised such that, where possible, all instructions with | |
2242 | the same mnemonic are together in a block. When the assembler searches | |
2243 | for a suitable instruction the entries are checked in table order, so | |
2244 | more specific, or specialised cases should appear earlier in the table. | |
2245 | ||
2246 | As an example, consider two instructions 'add a,b,u6' and 'add | |
2247 | a,b,limm'. The first takes a 6-bit immediate that is encoded within the | |
2248 | 32-bit instruction, while the second takes a 32-bit immediate that is | |
2249 | encoded in a follow-on 32-bit, making the total instruction length | |
2250 | 64-bits. In this case the u6 variant must appear first in the table, as | |
2251 | all u6 immediates could also be encoded using the 'limm' extension, | |
2252 | however, we want to use the shorter instruction wherever possible. | |
2253 | ||
2254 | It is possible though to split instructions with the same mnemonic into | |
2255 | multiple groups. However, the instructions are still checked in table | |
2256 | order, even across groups. The only time that instructions with the | |
2257 | same mnemonic should be split into different groups is when different | |
2258 | variants of the instruction appear in different architectures, in which | |
2259 | case, grouping all instructions from a particular architecture together | |
2260 | might be preferable to merging the instruction into the main instruction | |
2261 | table. | |
2262 | ||
2263 | An example of this split instruction groups can be found with the 'sync' | |
2264 | instruction. The core arc architecture provides a 'sync' instruction, | |
2265 | while the nps instruction set extension provides 'sync.rd' and | |
2266 | 'sync.wr'. The rd/wr flags are instruction flags, not part of the | |
2267 | mnemonic, so we end up with two groups for the sync instruction, the | |
2268 | first within the core arc instruction table, and the second within the | |
2269 | nps extension instructions. */ | |
886a2506 | 2270 | const struct arc_opcode arc_opcodes[] = |
0d2bcfaf | 2271 | { |
886a2506 | 2272 | #include "arc-tbl.h" |
e23e8ebe | 2273 | #include "arc-nps400-tbl.h" |
f2dd8838 | 2274 | #include "arc-ext-tbl.h" |
0d2bcfaf | 2275 | |
b99747ae CZ |
2276 | { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } } |
2277 | }; | |
252b5132 | 2278 | |
886a2506 NC |
2279 | /* List with special cases instructions and the applicable flags. */ |
2280 | const struct arc_flag_special arc_flag_special_cases[] = | |
252b5132 | 2281 | { |
886a2506 NC |
2282 | { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, |
2283 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
2284 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
2285 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
2286 | { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, | |
2287 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
2288 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
2289 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
2290 | { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, | |
2291 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
2292 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
2293 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
2294 | { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, | |
2295 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
2296 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
2297 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
2298 | { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, | |
2299 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
2300 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
2301 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
2302 | { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, | |
2303 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
2304 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
2305 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
2306 | { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, | |
2307 | F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, | |
2308 | F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, | |
2309 | F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, | |
2310 | { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } }, | |
2311 | { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } } | |
2312 | }; | |
252b5132 | 2313 | |
886a2506 | 2314 | const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases); |
252b5132 | 2315 | |
886a2506 | 2316 | /* Relocations. */ |
886a2506 NC |
2317 | const struct arc_reloc_equiv_tab arc_reloc_equiv[] = |
2318 | { | |
24b368f8 CZ |
2319 | { "sda", "ld", { F_ASFAKE, F_H1, F_NULL }, |
2320 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, | |
2321 | { "sda", "st", { F_ASFAKE, F_H1, F_NULL }, | |
2322 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, | |
2323 | { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL }, | |
2324 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, | |
2325 | { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL }, | |
2326 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, | |
2327 | ||
2328 | /* Next two entries will cover the undefined behavior ldb/stb with | |
2329 | address scaling. */ | |
2330 | { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL }, | |
2331 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST }, | |
2332 | { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL }, | |
2333 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST}, | |
2334 | ||
2335 | { "sda", "ld", { F_ASFAKE, F_NULL }, | |
2336 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 }, | |
2337 | { "sda", "st", { F_ASFAKE, F_NULL }, | |
2338 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2}, | |
2339 | { "sda", "ldd", { F_ASFAKE, F_NULL }, | |
2340 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 }, | |
2341 | { "sda", "std", { F_ASFAKE, F_NULL }, | |
2342 | BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2}, | |
886a2506 NC |
2343 | |
2344 | /* Short instructions. */ | |
24b368f8 CZ |
2345 | { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD }, |
2346 | { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 }, | |
2347 | { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 }, | |
2348 | { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 }, | |
2349 | ||
2350 | { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME }, | |
2351 | { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST }, | |
2352 | ||
2353 | { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL, | |
2354 | BFD_RELOC_ARC_S25H_PCREL_PLT }, | |
2355 | { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL, | |
2356 | BFD_RELOC_ARC_S21H_PCREL_PLT }, | |
2357 | { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL, | |
2358 | BFD_RELOC_ARC_S25W_PCREL_PLT }, | |
2359 | { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL, | |
2360 | BFD_RELOC_ARC_S21W_PCREL_PLT }, | |
2361 | ||
2362 | { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 } | |
886a2506 | 2363 | }; |
252b5132 | 2364 | |
886a2506 | 2365 | const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv); |
252b5132 | 2366 | |
886a2506 | 2367 | const struct arc_pseudo_insn arc_pseudo_insns[] = |
0d2bcfaf | 2368 | { |
886a2506 NC |
2369 | { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 }, |
2370 | { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 }, | |
2371 | { BRAKETdup, 1, 0, 4} } }, | |
2372 | { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 }, | |
2373 | { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 }, | |
2374 | { BRAKETdup, 1, 0, 4} } }, | |
2375 | ||
2376 | { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
2377 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2378 | { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
2379 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2380 | { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, | |
2381 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2382 | { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
2383 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2384 | { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
2385 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2386 | ||
2387 | { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
2388 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2389 | { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
2390 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2391 | { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, | |
2392 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2393 | { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
2394 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2395 | { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
2396 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2397 | ||
2398 | { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
2399 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2400 | { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
2401 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2402 | { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, | |
2403 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2404 | { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
2405 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2406 | { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
2407 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2408 | ||
2409 | { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
2410 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2411 | { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
2412 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2413 | { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, | |
2414 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2415 | { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, | |
2416 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2417 | { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, | |
2418 | { SIMM9_A16_8, 0, 0, 2 } } }, | |
2419 | }; | |
0d2bcfaf | 2420 | |
886a2506 NC |
2421 | const unsigned arc_num_pseudo_insn = |
2422 | sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns); | |
0d2bcfaf | 2423 | |
886a2506 | 2424 | const struct arc_aux_reg arc_aux_regs[] = |
0d2bcfaf | 2425 | { |
886a2506 | 2426 | #undef DEF |
f36e33da CZ |
2427 | #define DEF(ADDR, CPU, SUBCLASS, NAME) \ |
2428 | { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 }, | |
0d2bcfaf | 2429 | |
886a2506 | 2430 | #include "arc-regs.h" |
0d2bcfaf | 2431 | |
886a2506 NC |
2432 | #undef DEF |
2433 | }; | |
0d2bcfaf | 2434 | |
886a2506 | 2435 | const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs); |
4670103e CZ |
2436 | |
2437 | /* NOTE: The order of this array MUST be consistent with 'enum | |
2438 | arc_rlx_types' located in tc-arc.h! */ | |
2439 | const struct arc_opcode arc_relax_opcodes[] = | |
2440 | { | |
2441 | { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } }, | |
2442 | ||
2443 | /* bl_s s13 11111sssssssssss. */ | |
2444 | { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2445 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, | |
2446 | { SIMM13_A32_5_S }, { 0 }}, | |
2447 | ||
2448 | /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */ | |
2449 | { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2450 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, | |
2451 | { SIMM25_A32_5 }, { C_D }}, | |
2452 | ||
2453 | /* b_s s10 1111000sssssssss. */ | |
2454 | { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2455 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, | |
2456 | { SIMM10_A16_7_S }, { 0 }}, | |
2457 | ||
2458 | /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */ | |
2459 | { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2460 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, | |
2461 | { SIMM25_A16_5 }, { C_D }}, | |
2462 | ||
2463 | /* add_s c,b,u3 01101bbbccc00uuu. Wants UIMM3_13_S_PCREL. */ | |
2464 | { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2465 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, | |
2466 | { RC_S, RB_S, UIMM3_13_S }, { 0 }}, | |
2467 | ||
2468 | /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. Wants | |
2469 | UIMM6_20_PCREL. */ | |
2470 | { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2471 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, | |
2472 | { RA, RB, UIMM6_20 }, { C_F }}, | |
2473 | ||
2474 | /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */ | |
2475 | { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2476 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, | |
2477 | { RA, RB, LIMM }, { C_F }}, | |
2478 | ||
2479 | /* ld_s c,b,u7 10000bbbcccuuuuu. Wants UIMM7_A32_11_S_PCREL. */ | |
2480 | { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2481 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, | |
2482 | { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }}, | |
2483 | ||
2484 | /* ld<.di><.aa><.x><zz> a,b,s9 | |
2485 | 00010bbbssssssssSBBBDaaZZXAAAAAA. Wants SIMM9_8_PCREL. */ | |
2486 | { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2487 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, | |
2488 | { RA, BRAKET, RB, SIMM9_8, BRAKETdup }, | |
2489 | { C_ZZ23, C_DI20, C_AA21, C_X25 }}, | |
2490 | ||
2491 | /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */ | |
2492 | { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2493 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, | |
2494 | { RA, BRAKET, RB, LIMM, BRAKETdup }, | |
2495 | { C_ZZ13, C_DI16, C_AA8, C_X15 }}, | |
2496 | ||
2497 | /* mov_s b,u8 11011bbbuuuuuuuu. Wants UIMM8_8_S_PCREL. */ | |
2498 | { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2499 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, | |
2500 | { RB_S, UIMM8_8_S }, { 0 }}, | |
2501 | ||
2502 | /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. Wants | |
2503 | SIMM12_20_PCREL. */ | |
2504 | { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2505 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, | |
2506 | { RB, SIMM12_20 }, { C_F }}, | |
2507 | ||
2508 | /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */ | |
2509 | { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2510 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, | |
2511 | { RB, LIMM }, { C_F }}, | |
2512 | ||
2513 | /* sub_s c,b,u3 01101bbbccc01uuu. UIMM3_13_S_PCREL. */ | |
2514 | { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2515 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, | |
2516 | { RC_S, RB_S, UIMM3_13_S }, { 0 }}, | |
2517 | ||
2518 | /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. | |
2519 | UIMM6_20_PCREL. */ | |
2520 | { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2521 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, | |
2522 | { RA, RB, UIMM6_20 }, { C_F }}, | |
2523 | ||
2524 | /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */ | |
2525 | { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2526 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, | |
2527 | { RA, RB, LIMM }, { C_F }}, | |
2528 | ||
2529 | /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. | |
2530 | UIMM6_20_PCREL. */ | |
2531 | { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | |
2532 | | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }}, | |
2533 | ||
2534 | /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */ | |
2535 | { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | |
2536 | | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }}, | |
2537 | ||
2538 | /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. | |
2539 | UIMM6_20_PCREL. */ | |
2540 | { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2541 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, | |
2542 | { RB, UIMM6_20 }, { C_F, C_CC }}, | |
2543 | ||
2544 | /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */ | |
2545 | { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2546 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, | |
2547 | { RB, LIMM }, { C_F, C_CC }}, | |
2548 | ||
2549 | /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. | |
2550 | UIMM6_20_PCREL. */ | |
2551 | { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2552 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, | |
2553 | { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, | |
2554 | ||
2555 | /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */ | |
2556 | { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | |
2557 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, | |
2558 | { RB, RBdup, LIMM }, { C_F, C_CC }} | |
2559 | }; | |
2560 | ||
2561 | const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes); | |
4eb6f892 AB |
2562 | |
2563 | /* The following instructions are all either 48 or 64 bits long, and | |
2564 | require special handling in the assembler and disassembler. | |
2565 | ||
2566 | The first part of each ARC_LONG_OPCODE is the base ARC_OPCODE, this is | |
2567 | either the 16 or 32 bit base instruction, and its opcode list will | |
2568 | always end in a LIMM. | |
2569 | ||
2570 | The rest of the ARC_LONG_OPCODE describes how to build the LIMM from the | |
2571 | instruction operands. There are therefore two lists of operands for | |
2572 | each ARC_LONG_OPCODE, the second list contains operands that are merged | |
2573 | into the limm template, in the same way that a standard 32-bit | |
2574 | instruction is built. This generated limm is then added to the list of | |
2575 | tokens that is passed to the standard instruction encoder, along with | |
2576 | the first list of operands (from the base arc_opcode). | |
2577 | ||
2578 | The first list of operands then, describes how to build the base | |
2579 | instruction, and includes the 32-bit limm that was previously generated | |
2580 | as the last operand. | |
2581 | ||
2582 | In most cases operands are either encoded into the base instruction or | |
2583 | into the limm. When this happens the operand slot will be filled with | |
2584 | an operand identifier in one list, and will be IGNORED in the other | |
2585 | list, this special operand value causes the operand to be ignored, | |
2586 | without being encoded at this point. | |
2587 | ||
2588 | However, in some cases, an operand is split between the base instruction | |
2589 | and the 32-bit limm, in this case the operand slot will be filled in | |
2590 | both operand lists (see mov4b for one example of this). */ | |
2591 | const struct arc_long_opcode arc_long_opcodes[] = | |
2592 | { | |
2593 | /* mrgb - (48 bit instruction). */ | |
bdd582db | 2594 | { { "mrgb", 0x5803, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }}, |
4eb6f892 AB |
2595 | 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_SRC_POS1, NPS_BITOP_SIZE1, NPS_BITOP_DST_POS2, NPS_BITOP_SRC_POS2, NPS_BITOP_SIZE2 }}, |
2596 | ||
2597 | /* mrgb.cl - (48 bit instruction). */ | |
bdd582db | 2598 | { { "mrgb", 0x5803, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }}, |
4eb6f892 AB |
2599 | 0x80000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_SRC_POS1, NPS_BITOP_SIZE1, NPS_BITOP_DST_POS2, NPS_BITOP_SRC_POS2, NPS_BITOP_SIZE2 }}, |
2600 | ||
2601 | /* mov2b - (48 bit instruction). */ | |
bdd582db | 2602 | { { "mov2b", 0x5800, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }}, |
4eb6f892 AB |
2603 | 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2 }}, |
2604 | ||
2605 | /* mov2b.cl - (48 bit instruction). */ | |
bdd582db | 2606 | { { "mov2b", 0x5800, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }}, |
4eb6f892 AB |
2607 | 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2 }}, |
2608 | ||
2609 | /* ext4 - (48 bit instruction). */ | |
bdd582db | 2610 | { { "ext4b", 0x5801, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }}, |
4eb6f892 AB |
2611 | 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_INS_EXT, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2 }}, |
2612 | ||
2613 | /* ext4.cl - (48 bit instruction). */ | |
bdd582db | 2614 | { { "ext4b", 0x5801, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }}, |
4eb6f892 AB |
2615 | 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_INS_EXT, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2 }}, |
2616 | ||
2617 | /* ins4 - (48 bit instruction). */ | |
bdd582db | 2618 | { { "ins4b", 0x5802, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }}, |
4eb6f892 AB |
2619 | 0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_INS_EXT }}, |
2620 | ||
2621 | /* ins4.cl - (48 bit instruction). */ | |
bdd582db | 2622 | { { "ins4b", 0x5802, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }}, |
4eb6f892 AB |
2623 | 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_INS_EXT }}, |
2624 | ||
2625 | /* mov3b - (64 bit instruction). */ | |
bdd582db | 2626 | { { "mov3b", 0x58100000, 0xf81f801f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { 0 }}, |
4eb6f892 AB |
2627 | 0x80000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3 }}, |
2628 | ||
2629 | /* mov4b - (64 bit instruction). */ | |
bdd582db | 2630 | { { "mov4b", 0x58100000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { 0 }}, |
4eb6f892 AB |
2631 | 0x00000000, 0x00000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, IGNORED, NPS_BITOP_MOD4_MSB, IGNORED}}, |
2632 | ||
2633 | /* mov3bcl - (64 bit instruction). */ | |
bdd582db | 2634 | { { "mov3bcl", 0x58110000, 0xf81f801f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { 0 }}, |
4eb6f892 AB |
2635 | 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3 }}, |
2636 | ||
2637 | /* mov4bcl - (64 bit instruction). */ | |
bdd582db | 2638 | { { "mov4bcl", 0x58110000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { 0 }}, |
4eb6f892 AB |
2639 | 0x00000000, 0x00000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, IGNORED, NPS_BITOP_MOD4_MSB, IGNORED}}, |
2640 | ||
2641 | /* mov3b.cl - (64 bit instruction). */ | |
bdd582db | 2642 | { { "mov3b", 0x58110000, 0xf81f801f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { C_NPS_CL }}, |
4eb6f892 AB |
2643 | 0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3 }}, |
2644 | ||
2645 | /* mov4b.cl - (64 bit instruction). */ | |
bdd582db | 2646 | { { "mov4b", 0x58110000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { C_NPS_CL }}, |
4eb6f892 AB |
2647 | 0x00000000, 0x00000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, IGNORED, NPS_BITOP_MOD4_MSB, IGNORED}}, |
2648 | }; | |
2649 | ||
2650 | const unsigned arc_num_long_opcodes = ARRAY_SIZE (arc_long_opcodes); | |
06fe285f GM |
2651 | |
2652 | /* Return length of instruction represented by OPCODE in bytes. */ | |
2653 | ||
2654 | int | |
2655 | arc_opcode_len (const struct arc_opcode *opcode) | |
2656 | { | |
2657 | if (opcode->mask < 0x10000ull) | |
2658 | return 2; | |
2659 | return 4; | |
2660 | } |